Shift register, gate driving circuit and display apparatus

Abstract

A shift register, a gate driving circuit and a display apparatus, belonging to the technical field of display. The shift register comprises: a first input sub-circuit (11), a second input sub-circuit (12), an output sub-circuit (3), at least one pull-down control sub-circuit (41 / 42), at least one pull-down sub-circuit (51 / 52), at least one first auxiliary sub-circuit and at least one second auxiliary sub-circuit; the pull-down control sub-circuits (41 / 42) are connected to the pull-down sub-circuits (51 / 52) on a one-to-one basis, the connection nodes being pull-down nodes; a connection node between the first input sub-circuit (11), the second input sub-circuit (12) and the output sub-circuit (3) is a pull-up node (PU); each first auxiliary sub-circuit is configured to, in response to a first input signal and by means of a second scanning signal, pull down the potential of a pull-down node corresponding thereto; each second auxiliary sub-circuit is configured to, in response to a second input signal and by means of a first scanning signal, pull down the potential of a pull-down node corresponding thereto.

Description

Shift register, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit and a display device. BACKGROUND

[0002] With the continuous development of display technology, the development of display in recent years gradually presents a development trend of high integration and low cost. One of the very important technologies is the realization of mass production of GOA (Gate Driver on Array) technology. The TFT (Thin Film Transistor) gate switch circuit integrated on the array substrate of the display panel by using the GOA technology to form the scanning driving of the display panel, so that the gate driving integrated circuit part can be saved, which not only can reduce the product cost from the material cost and the manufacturing process, but also the display panel can be made to be symmetrical and narrow frame. At the same time, since the Gate direction bonding process can be saved, the production capacity and yield are also improved. The gate switch circuit integrated on the array substrate by using the GOA technology is also called GOA circuit or shift register circuit. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provide a shift register, a gate driving circuit and a display device.

[0004] The shift register provided by the present disclosure comprises a first input sub-circuit, a second input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit and at least one pull-down sub-circuit; the pull-down control sub-circuit is connected with the pull-down sub-circuit one by one, and the connection node is a pull-down node.

[0005] The first input sub-circuit is configured to pre-charge a pull-up node by a first scanning signal in response to a first input signal.

[0006] The second input sub-circuit is configured to pre-charge the pull-up node by a second scanning signal in response to a second input signal.

[0007] The output sub-circuit is configured to output a clock signal through a signal output in response to the potential of the pull-up node.

[0008] The pull-down control sub-circuit is configured to control the potential of the pull-down node corresponding thereto by a power voltage signal in response to the power voltage signal.

[0009] The pull-down sub-circuit is configured to pull down the potential of the pull-down node corresponding thereto through the non-working level signal in response to the potential of the pull-up node.

[0010] The shift register further comprises at least one first auxiliary sub-circuit and at least one second auxiliary sub-circuit, and the first auxiliary sub-circuit and the second auxiliary sub-circuit are connected to the pull-down nodes one by one.

[0011] The first auxiliary sub-circuit is configured to pull down the potential of the pull-down node corresponding thereto through the second scan signal in response to the first input signal.

[0012] The second auxiliary sub-circuit is configured to pull down the potential of the pull-down node corresponding thereto through the first scan signal in response to the second input signal.

[0013] The first auxiliary sub-circuit comprises a sixteenth transistor.

[0014] The first electrode of the sixteenth transistor is connected to the pull-down node corresponding thereto, the second electrode is connected to the second scan signal end, and the control electrode is connected to the first input signal end.

[0015] The second auxiliary sub-circuit comprises a fifteenth transistor.

[0016] The first electrode of the fifteenth transistor is connected to the pull-down node corresponding thereto, the second electrode is connected to the first scan signal end, and the control electrode is connected to the second input signal end.

[0017] The shift register further comprises a global reset sub-circuit, which is configured to globally reset the pull-up node and the signal output end through the non-working level signal in response to a global reset signal.

[0018] The global reset sub-circuit comprises a fourth transistor and a seventh transistor.

[0019] The first electrode of the fourth transistor is connected to the pull-up node, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the global reset signal end.

[0020] The first electrode of the seventh transistor is connected to the signal output end, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the global reset signal end.

[0021] The shift register further comprises at least one first noise reduction sub-circuit, and the first noise reduction sub-circuit is configured to reduce the noise of the output of the pull-up node through the non-working level signal under the control of the pull-down node corresponding thereto.

[0022] The first noise reduction sub-circuit comprises a tenth transistor.

[0023] The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to a non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

[0024] The shift register further comprises at least one second noise reduction sub-circuit, which is configured to reduce noise of the output of the signal output terminal by a non-working level signal under the control of the corresponding pull-down node.

[0025] The second noise reduction sub-circuit comprises an eleventh transistor.

[0026] The first electrode of the eleventh transistor is connected to the signal output terminal, the second electrode is connected to a non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

[0027] The shift register further comprises a cascade sub-circuit, which is configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

[0028] The cascade sub-circuit comprises a thirteenth transistor.

[0029] The first electrode of the thirteenth transistor is connected to a clock signal terminal, the second electrode is connected to a cascade signal terminal, and the control electrode is connected to the pull-up node.

[0030] The shift register further comprises at least one third noise reduction sub-circuit, which is configured to reduce noise of the output of the cascade signal terminal by a non-working level signal under the control of the corresponding pull-down node.

[0031] The third noise reduction sub-circuit comprises a twelfth transistor.

[0032] The first electrode of the twelfth transistor is connected to the cascade signal terminal, the second electrode is connected to a non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

[0033] The first input sub-circuit comprises a first transistor.

[0034] The first electrode of the first transistor is connected to a first scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to a first input signal terminal.

[0035] The second input sub-circuit comprises a second transistor.

[0036] The first electrode of the second transistor is connected to a second scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to a second input signal terminal.

[0037] The output sub-circuit comprises a third transistor and a storage capacitor.

[0038] The first electrode of the third transistor is connected to a clock signal end, the second electrode is connected to a signal output end and the second electrode of the storage capacitor, and the control electrode is connected to the first electrode of the pull-up node and the first end of the storage capacitor.

[0039] The pull-up control sub-circuit comprises a fifth transistor.

[0040] The first electrode and the control electrode of the fifth transistor are connected to a power voltage end, and the second electrode is connected to the pull-down node.

[0041] The pull-down sub-circuit comprises a sixth transistor.

[0042] The first electrode of the sixth transistor is connected to the pull-down node, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the pull-up node.

[0043] The pull-up control sub-circuit comprises a fifth transistor and a ninth transistor.

[0044] The first electrode of the fifth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor and the power voltage end, and the second electrode is connected to the pull-down node.

[0045] The pull-down sub-circuit comprises a sixth transistor and an eighth transistor.

[0046] The first electrode of the sixth transistor is connected to the pull-down node, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the pull-up node.

[0047] The first electrode of the eighth transistor is connected to the control electrode of the fifth transistor and the first electrode of the ninth transistor, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the pull-up node.

[0048] The gate drive circuit comprises a plurality of cascaded shift registers, and the shift register is any one of the above-described shift registers.

[0049] The display device comprises the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0050] FIG. 1 is a circuit diagram of an exemplary shift register.

[0051] FIG. 2 is a circuit diagram of a first exemplary shift register according to an embodiment of the present disclosure.

[0052] FIG. 3 is a timing diagram of forward scanning of the shift register of FIG. 2.

[0053] Figure 4 is a timing diagram of the reverse scan of the shift register of Figure 2.

[0054] Figure 5 is a circuit diagram of a second example of a shift register according to embodiments of the present disclosure.

[0055] Figure 6 is a circuit diagram of a third example of a shift register according to embodiments of the present disclosure.

[0056] Figure 7 is a circuit diagram of a fourth example of a shift register according to embodiments of the present disclosure.

[0057] Figure 8 is a circuit diagram of a fifth example of a shift register according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0058] In order to enable one skilled in the art to better understand the technical solutions of the present application, the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0059] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity restriction, but denote the presence of at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are only used to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0060] It should be noted that the transistor used in the embodiment of the present application can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are not distinguished. In the embodiment of the present application, one of the poles is referred to as the first pole, the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiment is described by taking the N-type transistor as an example. When the N-type transistor is used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the gate is inputted with a high level, so that the source and drain are turned on. The P-type is opposite. It is conceivable that the P-type transistor can be easily thought of by those skilled in the art without creative labor, and therefore it is also within the protection scope of the embodiment of the present application.

[0061] In the embodiment of the present application, since the transistor used is an N-type transistor, the working level signal in the embodiment of the present application refers to a high level signal, and the non-working level signal is a low level signal. Correspondingly, the working level end is a high level signal end, and the non-working level end is a low level signal end VGL.

[0062] Generally, the display panel includes a plurality of gate lines and a plurality of data lines. The gate lines and the data lines are arranged in a cross manner to define a plurality of pixel regions. Each pixel region is provided with a pixel unit. Taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example, the structure of the display panel is described. When driving the display panel to display, a gate scanning signal can be written into each gate line according to a to-be-displayed picture, and a data voltage signal can be written into each data line at the same time, so that the pixel units in the display panel are lit row by row.

[0063] The gate scanning signal is provided by a gate driving circuit, and the data voltage signal is provided by a source driving circuit. In the related art, the gate driving circuit can be integrated in a gate driving chip, and the source driving circuit can be integrated in a source driving chip. At present, in order to reduce the number of chips and realize a narrow frame or no frame, a Gate On Array (GOA) technology is provided. The gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate. Each shift register is connected to one gate line in one-to-one correspondence, and is used to provide a gate scanning signal for the gate line connected thereto.

[0064] In order to more clearly describe how the shift register outputs the gate scanning signal, the following describes a specific example of a shift register unit.

[0065] Figure 1 is a circuit diagram of an exemplary shift register; as shown in Figure 1, the shift register comprises an input sub-circuit 1, an output sub-circuit 3, a pull-up reset sub-circuit 2, a global reset sub-circuit 6, two pull-down control sub-circuits 41 / 42, two pull-down sub-circuits 51 / 52, two first noise reduction sub-circuits 71 / 72, and two second noise reduction sub-circuits 81 / 82. For ease of description, the two pull-down control sub-circuits 4 are referred to as a first pull-down control sub-circuit 41 and a second pull-down control sub-circuit 42, and the two pull-down sub-circuits 5 are referred to as a first pull-down sub-circuit 51 and a second pull-down sub-circuit 52. The first pull-down control sub-circuit 41 and the first pull-down sub-circuit 51 are connected, and the connection node therebetween is referred to as a first pull-down node PD1; the second pull-down control sub-circuit 42 and the second pull-down sub-circuit 52 are connected, and the connection node therebetween is referred to as a second pull-down node PD2.

[0066] With continued reference to Figure 1, the input sub-circuit 1 is configured to respond to an input signal and pre-charge the pull-up node PU with the input signal. The output sub-circuit 3 is configured to respond to the potential of the pull-up node PU and output a clock signal through a signal output terminal G(N). The pull-up reset sub-circuit 2 is configured to reset the pull-up node PU with a low-level signal under the control of a pull-up reset signal. The global reset sub-circuit 6 is configured to respond to a global reset signal and reset the pull-up node PU and the signal output terminal G(N) with a low-level signal. The output sub-circuit 3 is configured to respond to the potential of the pull-up node PU and output a clock signal through the signal output terminal G(N). The first pull-down control sub-circuit 41 is configured to respond to a first power voltage signal and control the potential of the first pull-down node PD1 with the first power voltage signal. The second pull-down control sub-circuit 42 is configured to respond to a second power voltage signal and control the potential of the second pull-down node PD2 with the second power voltage signal. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node PU and pull down the potential of the first pull-down node PD1 with a low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node PU and pull down the potential of the second pull-down node PD2 with a low-level signal. One of the two first noise reduction sub-circuits 71 responds to the potential of the first pull-down node PD1 and reduces the output of the pull-up node PU with a low-level signal, and the other 72 responds to the potential of the second pull-down node PD2 and reduces the output of the pull-up node PU with a low-level signal. One of the two second noise reduction sub-circuits 81 responds to the potential of the first pull-down node PD1 and reduces the output of the signal output terminal G(N) with a low-level signal, and the other 82 responds to the potential of the second pull-down node PD2 and reduces the output of the signal output terminal G(N) with a low-level signal.

[0067] Specifically, with continued reference to 1, the input sub-circuit 1 includes a first transistor M1, the pull-up reset sub-circuit 2 includes a second transistor M2, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1, the global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 each include a fifth transistor and a ninth transistor, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor and an eighth transistor, each of the first noise reduction sub-circuits includes a tenth transistor, and each of the second noise reduction sub-circuits includes an eleventh transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are denoted as M5A and M9A, respectively, the fifth transistor and the ninth transistor in the second pull-down sub-circuit 52 are denoted as M5B and M9B, respectively, the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are denoted as M6A and M8A, respectively, the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are denoted as M6B and M8B, respectively, the tenth transistor in the two first noise reduction sub-circuits are denoted as M10A and M10B, respectively, and the eleventh transistor in the two second noise reduction sub-circuits are denoted as M11A and M11B, respectively.

[0068] The source and gate of M1 are connected with a signal input end, and the drain of M1 is connected with a pull-up node PU. The source of M2 is connected with the pull-up node PU, the drain of M2 is connected with a low-level signal end VGL, and the gate of M2 is connected with a pull-up reset signal end. The source of M3 is connected with a clock signal end CLK, the drain of M3 is connected with a signal output end G(N), and the gate of M3 is connected with the pull-up node PU. The first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output end G(N). The source of M4 is connected with the pull-up node PU, the drain of M4 is connected with the low-level signal end VGL, and the gate of M4 is connected with a global reset signal end. The source of M7 is connected with the signal output end G(N), the drain of M7 is connected with the low-level signal end VGL, and the gate of M7 is connected with the global reset signal end. The source of M5A is connected with a first power voltage end VDDO, the drain of M5A is connected with a first pull-down node PD1, the gate of M5A is connected with the drain of M9A, the source and gate of M9A are connected with a second power voltage end VDDE. The source of M5B is connected with the second power voltage end VDDE, the drain of M5B is connected with a second pull-down node PD2, the gate of M5B is connected with the drain of M9B, and the source and gate of M9B are connected with the second power voltage end VDDE. The source of M6A is connected with the first pull-down node PD1, the drain of M6A is connected with the low-level signal end VGL, and the gate of M6A is connected with the pull-up node PU. The source of M8A is connected with the drain of M9A and the gate of M5A, the drain of M8A is connected with the low-level signal end VGL, and the gate of M8A is connected with the pull-up node PU. The source of M6B is connected with the second pull-down node PD2, the drain of M6B is connected with the low-level signal end VGL, and the gate of M6B is connected with the pull-up node PU. The source of M8B is connected with the drain of M9B and the gate of M5B, the drain of M8B is connected with the low-level signal end VGL, and the gate of M8B is connected with the pull-up node PU. The source of M10A is connected with the pull-up node PU, the drain of M10A is connected with the low-level signal end VGL, and the gate of M10A is connected with the first pull-down node PD1. The source of M10B is connected with the pull-up node PU, the drain of M10B is connected with the low-level signal end VGL, and the gate of M10B is connected with the second pull-down node PD2. The source of M11A is connected with the signal output end G(N), the drain of M11A is connected with the low-level signal end VGL, and the gate of M11A is connected with the first pull-down node PD1. The source of M11B is connected with the signal output end G(N), the drain of M11B is connected with the low-level signal end VGL, and the gate of M11B is connected with the second pull-down node PD2.

[0069] It should be noted that the source of M1 can also not be connected with the gate of M1, for example, the source of M1 is connected with the first signal end, the drain of M1 is connected with the pull-up node PU, and the gate of M1 is connected with the signal input end. At this time, the signal input end is written with a high-level signal, M1 is opened, and the high-level signal written by the first signal end is used to pre-charge the pull-up node PU. In the embodiments of the present disclosure, only the source and the gate of M1 are connected together as an example for description, but it should be understood that this does not constitute a limitation on the protection scope of the embodiments of the present disclosure.

[0070] When the shift register in the embodiments of the present disclosure is applied to the gate driving circuit, the signal input end of the Nth shift register is connected with the signal output end G(N-1) of the (N-1)th shift register, and the pull-up reset signal end of the Nth shift register is connected with the signal output end G(N+1) of the (N+1)th shift register, except for the last shift register. N is greater than or equal to 2, and N is an integer. The inventor finds that, as shown in FIG. 1, when the gate driving circuit is working, when G(N-1) is a high-level signal, G(N+1) and the signal input from the global reset signal end are low-level signals, M1 is opened, M2 is closed, the pull-up node PU starts to charge, when the pull-up node PU is a high-level signal, M6A / M6B / M8A / M8B are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, and it is ensured that the pull-up node PU is kept as a high level and normally output. However, when the pull-up node PU just starts to charge, the potential of the pull-up node PU has not risen to a high level, the first pull-down node PD1 and the second pull-down node PD2 are high levels, and M10A / M10B are still in an opened state. The potential of the pull-up node PU exists in the conditions of charging and discharging, and there is a competitive relationship between the pull-up node PU and the first pull-down node PD1 and the second pull-down node PD2, which affects the charging of the pull-up node PU. As shown in FIG. 1, if the pull-up node PU cannot compete with the potential of the first pull-down node PD1 and the second pull-down node PD2, the pull-up node PU cannot be charged, the shift register in this row has no output, and the interlaced display is caused.

[0071] In view of the problems in the above technical solutions, the embodiments of the present disclosure provide the following technical solutions. Before the technical solutions of the embodiments of the present disclosure are described, it should be noted that in the following technical solutions, only one or two of the pull-down control sub-circuit, the pull-down sub-circuit, the first noise reduction sub-circuit, the second noise reduction sub-circuit, and the third noise reduction sub-circuit are taken as examples. It should be understood that the number of the pull-down control sub-circuit, the pull-down sub-circuit, the first noise reduction sub-circuit, the second noise reduction sub-circuit, and the third noise reduction sub-circuit in the shift register can also be more, which are not listed one by one here.

[0072] Next, the technical solutions of the embodiments of the present disclosure are described in detail.

[0073] The first example: FIG. 2 is a circuit diagram of a shift register of the first example of the embodiment of the present disclosure; as shown in FIG. 2, the shift register comprises a first input sub-circuit 11, a second input sub-circuit 12, an output sub-circuit 3, two pull-down control sub-circuits 41 / 42, two pull-down sub-circuits 51 / 52, two first auxiliary sub-circuits and two second auxiliary sub-circuits. Among them, in order to facilitate the description, the two pull-down control sub-circuits 41 / 42 are respectively referred to as the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42, and the two pull-down sub-circuits 51 / 52 are respectively referred to as the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52. The first pull-down control sub-circuit 41 and the first pull-down sub-circuit 51 are connected, and the connection node between them is referred to as the first pull-down node PD1; the second pull-down control sub-circuit 42 and the second pull-down sub-circuit 52 are connected, and the connection node between them is referred to as the second pull-down node PD2.

[0074] For the shift register in FIG. 2, bidirectional scanning can be realized, that is, forward scanning and reverse scanning are realized. When forward scanning, the second input sub-circuit 12 is used as the pull-up reset sub-circuit 2, and when reverse scanning, the first input sub-circuit 11 is used as the pull-up reset sub-circuit 2. Among them, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU through the first scan signal in response to the first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU through the second scan signal in response to the second input signal. The output sub-circuit 3 is configured to output the clock signal through the signal output end G(N) in response to the potential of the pull-up node PU. The first pull-down control sub-circuit 41 is configured to control the potential of the first pull-down node PD1 through the first power voltage signal in response to the first power voltage signal. The second pull-down control sub-circuit 42 is configured to control the potential of the second pull-down node PD2 through the second power voltage signal in response to the second power voltage signal. The first pull-down sub-circuit 51 is configured to pull down the potential of the first pull-down node PD1 through the low-level signal in response to the potential of the pull-up node PU. The second pull-down sub-circuit 52 is configured to pull down the potential of the second pull-down node PD2 through the low-level signal in response to the potential of the pull-up node PU. One of the two first auxiliary sub-circuits is configured to pull down the potential of the first pull-down node PD1 through the second scan signal in response to the first input signal when forward scanning; the other one is configured to pull down the potential of the second pull-down node PD2 through the second scan signal in response to the first input signal. One of the two second auxiliary sub-circuits is configured to pull down the potential of the first pull-down node PD1 through the first scan signal in response to the second input signal when reverse scanning; the other one is configured to pull down the potential of the second pull-down node PD2 through the first scan signal in response to the second input signal.

[0075] In the embodiments of the present disclosure, since two first auxiliary sub-circuits and two second auxiliary sub-circuits are added, in forward scanning, the two first auxiliary sub-circuits can be controlled to work by the first input signal, and since the second scan signal is written as a low-level signal in forward scanning, the potential of the first pull-down node PD1 and the second pull-down node PD2 can be pulled down by the second scan signal at this time, so as to cancel the competitive relationship between the first pull-down node PD1 / second pull-down node PD2 and the pull-up node PU. Similarly, in reverse scanning, the two second auxiliary sub-circuits can be controlled to work by the second input signal, and since the first scan signal is written as a low-level signal in reverse scanning, the potential of the first pull-down node PD1 and the second pull-down node PD2 can be pulled down by the first scan signal at this time, so as to cancel the competitive relationship between the first pull-down node PD1 / second pull-down node PD2 and the pull-up node PU.

[0076] With continuous reference to FIG. 2, when the shift register in the embodiments of the present disclosure is applied to a gate drive circuit, the signal input end of the Nth shift register is connected to the signal output end G(N-1) of the (N-1)th shift register, and the pull-up reset signal end of the Nth shift register is connected to the signal output end G(N+1) of the (N+1)th shift register, except for the first shift register and the last shift register. N≥2, and N is an integer.

[0077] In some examples, with continuous reference to FIG. 2, two first auxiliary sub-circuits are represented as M16A and M16B respectively; the source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the second scan signal end VSD, and the gate of M16A is connected to the first input signal end; the source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the second scan signal end VSD, and the gate of M16B is connected to the first input signal end.

[0078] Specifically, when forward scanning, the second scan signal written into the second scan signal end VSD is a low-level signal, and when the first input signal end is written with a first input signal of a high-level signal, the first input sub-circuit 11 works, and the pull-up node PU is pre-charged by the first scan signal, and at the same time, since the first input signal is a high-level signal, M16A and M16B are opened, and the potential of the first pull-down node PD1 and the second pull-down node PD2 is pulled down by the low-level signal written into the second scan signal end VSD, so as to effectively avoid the competitive relationship between the pull-up node PU and the first pull-down node PD1 / second pull-down node PD2.

[0079] In some examples, continuing to refer to FIG. 2, two second auxiliary sub-circuits are denoted as M15A and M15B, respectively; the source of M15A is connected to the first pull-down node PD1, the drain of M15A is connected to the second scan signal end VSD, and the gate of M15A is connected to the first input signal end; the source of M15B is connected to the second pull-down node PD2, the drain of M15B is connected to the second scan signal end VSD, and the gate of M15B is connected to the first input signal end.

[0080] Specifically, when forward scanning, the second scan signal written by the first scan signal end VDS is a low-level signal, and when the second input signal written by the second input signal end is a high-level signal, the second input sub-circuit 12 works, pre-charges the pull-up node PU through the second scan signal, and at the same time, since the second input signal is a high-level signal, M15A and M15B are opened, and the low-level signal written by the first scan signal end VDS pulls down the potential of the first pull-down node PD1 and the second pull-down node PD2, thereby effectively avoiding the competitive relationship between the pull-up node PU and the first pull-down node PD1 / second pull-down node PD2.

[0081] In some examples, continuing to refer to FIG. 2, the shift register further includes a global reset sub-circuit 6. The global reset sub-circuit 6 is configured to reset the pull-up node PU and the signal output end G(N) through a low-level signal in response to a global reset signal.

[0082] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal end VGL, and the gate of M4 is connected to the global reset signal end Total-Rest. The source of M7 is connected to the signal output end G(N), the drain of M7 is connected to the low-level signal end VGL, and the gate of M7 is connected to the global reset signal end Total-Rest.

[0083] Specifically, in the global reset phase, the global reset signal written by the global reset signal end Total-Rest is a high-level signal, the fourth transistor M4 and the seventh transistor M7 are both opened, at this time, the low-level signal written by the low-level signal end VGL resets the pull-up node PU through the fourth transistor M4, and resets the signal output end G(N) through the seventh transistor M7.

[0084] In some examples, with reference back to FIG. 2, the shift register further comprises two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits is responsive to the potential of the first pull-down node PD1 to reduce the output of the pull-up node PU by the low-level signal, and the other is responsive to the potential of the second pull-down node PD2 to reduce the output of the pull-up node PU by the low-level signal. One of the two second noise reduction sub-circuits is responsive to the potential of the first pull-down node PD1 to reduce the output of the signal output terminal G(N) by the low-level signal, and the other is responsive to the potential of the second pull-down node PD2 to reduce the output of the signal output terminal G(N) by the low-level signal.

[0085] In some examples, with reference back to FIG. 2, the shift register further comprises two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits is responsive to the potential of the first pull-down node PD1 to reduce the output of the pull-up node PU by the low-level signal, and the other is responsive to the potential of the second pull-down node PD2 to reduce the output of the pull-up node PU by the low-level signal. One of the two second noise reduction sub-circuits is responsive to the potential of the first pull-down node PD1 to reduce the output of the signal output terminal G(N) by the low-level signal, and the other is responsive to the potential of the second pull-down node PD2 to reduce the output of the signal output terminal G(N) by the low-level signal.

[0086] In some examples, with reference back to FIG. 2, the shift register further comprises two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits is responsive to the potential of the first pull-down node PD1 to reduce the output of the pull-up node PU by the low-level signal, and the other is responsive to the potential of the second pull-down node PD2 to reduce the output of the pull-up node PU by the low-level signal. One of the two second noise reduction sub-circuits is responsive to the potential of the first pull-down node PD1 to reduce the output of the signal output terminal G(N) by the low-level signal, and the other is responsive to the potential of the second pull-down node PD2 to reduce the output of the signal output terminal G(N) by the low-level signal.

[0087] In some examples, the first input sub-circuit 11 comprises a first transistor M1, and the second input sub-circuit 12 comprises a second transistor M2. The source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0088] Specifically, when forward scanning, in the input stage, the first input signal written in the first input signal terminal is a high level signal, M1 is opened, the first scanning signal written in the first scanning signal terminal VDS is a high level signal, at this time, the pull-up node PU is pre-charged through the first scanning signal. In the pull-up reset stage, the second input signal written in the second input signal terminal is a high level signal, M2 is opened, the second scanning signal written in the second scanning signal terminal VSD is a low level signal, at this time, the pull-up node PU is discharged through the second scanning signal, so as to realize the reset of the pull-up node PU.

[0089] When reverse scanning, in the input stage, the second input signal written in the second input signal terminal is a high level signal, M2 is opened, the second scanning signal written in the second scanning signal terminal VSD is a high level signal, at this time, the pull-up node PU is pre-charged through the second scanning signal. In the pull-up reset stage, the first input signal written in the first input signal terminal is a high level signal, M1 is opened, the first scanning signal written in the first scanning signal terminal VDS is a low level signal, at this time, the pull-up node PU is discharged through the first scanning signal, so as to realize the reset of the pull-up node PU.

[0090] In some examples, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected with the clock signal terminal CLK, the drain of M3 is connected with the signal output terminal G(N), and the gate of M3 is connected with the pull-up node PU; the first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output terminal G(N).

[0091] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, the clock signal written in the clock signal terminal CLK is a high level signal at this stage, at this time, the signal output terminal G(N) outputs a high level signal.

[0092] In some examples, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 each include a fifth transistor and a ninth transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are denoted as M5A and M9A respectively, and the fifth transistor and the ninth transistor in the second pull-down control sub-circuit 42 are denoted as M5B and M9B respectively. The source of M5A is connected with the first power voltage terminal VDDO, the drain of M5A is connected with the first pull-down node PD1, the gate of M5A is connected with the drain of M9A, and the source and the gate of M9A are connected with the second power voltage terminal VDDE. The source of M5B is connected with the second power voltage terminal VDDE, the drain of M5B is connected with the second pull-down node PD2, the gate of M5B is connected with the drain of M9B, and the source and the gate of M9B are connected with the second power voltage terminal VDDE.

[0093] Specifically, when the first power voltage terminal VDDO is written with the first power voltage, M5A and M9A are both opened, the potential of the first pull-down node PD1 is pulled up to the first power voltage, i.e., at a high potential. When the second power voltage terminal VDDE is written with the second power voltage, MB5 and M9B are both opened, the potential of the second pull-down node PD2 is pulled up to the second power voltage, i.e., at a high potential. It should be noted that the first power voltage and the second power voltage can be the same power voltage. In the embodiments of the present disclosure, only the case where the first power voltage and the second power voltage are the same power voltage is described.

[0094] In some examples, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor and an eighth transistor; for the convenience of description, the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are denoted as M6A and M8A respectively, and the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are denoted as M6B and M8B respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0095] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B / M8A / M8B are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, and the pull-up node PU is ensured to be at a high level for normal output.

[0096] For a clearer structure of the shift register of the embodiments of the present disclosure, the working process of the shift register is described in detail.

[0097] For forward scanning: FIG. 3 is a timing diagram of the forward scanning of the shift register of FIG. 2; as shown in FIG. 3, the first scanning signal written into the first scanning signal terminal VDS is a continuous high-level signal, and the second scanning signal written into the second scanning signal terminal VSD is a continuous low-level signal.

[0098] Input stage: the first input signal written into the first input signal terminal is a high level signal, the first scan signal written into the first scan signal terminal VDS is a high level signal, and the second scan signal written into the second scan signal terminal VSD is a low level signal. At this time, M1, M16A and M16B are opened, the pull-up node PU is pre-charged through the first scan signal, and the first pull-down node PD1 and the second pull-down node PD2 are pulled down to a low potential by the second scan signal due to the opening of M16A and M16B, so that the potential competition between the pull-up node PU and the first pull-down node PD1 and the second pull-down node PD2 can be effectively avoided.

[0099] Output stage: the potential of the pull-up node PU is further pulled up under the bootstrap action of the storage capacitor C1, the M3 tube is fully opened, the signal output terminal G(N) outputs the high potential of the clock signal written into the clock signal terminal CLK, that is, the signal output terminal G(N) outputs a high level signal. At the same time, since the potential of the pull-up node PU is high, M6A / M6B / M8A / M8B are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, and the pull-up node PU is ensured to be high.

[0100] Reset stage: the second input signal written into the second input signal terminal is a high level signal, M2 is opened, and the second scan signal written into the second scan signal terminal VSD is a low level signal. At this time, the pull-up node PU is pulled down to a low level.

[0101] Output noise reduction stage: if the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A and M9A are both opened, the potential of the first pull-down node PD1 is pulled up to the first power supply voltage, that is, at a high potential, at this time, M10A and M11A are opened, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low level signal written into the low level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N). When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B and M9B are both opened, the potential of the second pull-down node PD2 is pulled up to the second power supply voltage, that is, at a high potential, at this time, M10B and M11B are opened, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low level signal written into the low level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N).

[0102] For reverse scanning: Fig. 4 is a timing diagram of the reverse scanning of the shift register of Fig. 2; as shown in Fig. 4, the second scan signal written into the second scan signal terminal VSD is a continuous high level signal, and the first scan signal written into the first scan signal terminal VDS is a continuous low level signal.

[0103] Input stage: the second input signal written into the second input signal terminal is a high level signal, the second scan signal written into the second scan signal terminal VSD is a high level signal, and the first scan signal written into the first scan signal terminal VDS is a low level signal. At this time, M2, M15A and M15B are opened, the pull-up node PU is pre-charged through the first scan signal, and the first pull-down node PD1 and the second pull-down node PD2 are pulled down to a low potential by the second scan signal due to the opening of M15A and M15B, so that the potential competition between the pull-up node PU and the first pull-down node PD1 and the second pull-down node PD2 can be effectively avoided.

[0104] Output stage: the potential of the pull-up node PU is further pulled up under the bootstrap action of the storage capacitor C1, the M3 tube is fully opened, the signal output terminal G(N) outputs the high potential of the clock signal written into the clock signal terminal CLK, that is, the signal output terminal G(N) outputs a high level signal. At the same time, since the potential of the pull-up node PU is high, M6A / M6B / M8A / M8B are opened, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, and the pull-up node PU is ensured to be high.

[0105] Reset stage: the first input signal written into the first input signal terminal is a high level signal, M1 is opened, and the first scan signal written into the first scan signal terminal VDS is a low level signal. At this time, the pull-up node PU is pulled down to a low level.

[0106] Output noise reduction stage: if the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A and M9A are both opened, the potential of the first pull-down node PD1 is pulled up to the first power supply voltage, that is, at a high potential. At this time, M10A and M11A are opened, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low level signal written into the low level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N). When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B and M9B are both opened, the potential of the second pull-down node PD2 is pulled up to the second power supply voltage, that is, at a high potential. At this time, M10B and M11B are opened, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low level signal written into the low level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N).

[0107] The second example: Fig. 5 is a circuit diagram of a shift register of the second example of the embodiment of the present disclosure; as shown in Fig. 5, the structure of the shift register in this example is substantially the same as that in the first example, and the only difference is that the shift register in this example adds a cascade sub-circuit to the shift register in the first example, and the cascade output sub-circuit 3 is configured to output the clock signal through the cascade signal end in response to the potential of the pull-up node PU.

[0108] In some examples, the cascade sub-circuit includes a thirteenth transistor M13, the source of M13 is connected to the clock signal end CLK, the drain of M13 is connected to the cascade signal end output_C(N), and the gate of M13 is connected to the pull-up node PU.

[0109] Specifically, in the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully open, the clock signal written by the clock signal end CLK is a high-level signal in this phase, and the cascade signal end output_C(N) outputs a high-level signal at this time.

[0110] When the shift register in the embodiment of the present disclosure is applied to a gate drive circuit, in addition to the first stage shift register, the signal input end of the Nth stage shift register is connected to the cascade signal end output_C(N-1) of the (N-1)th stage shift register; in addition to the last stage shift register, the pull-up reset signal end of the Nth stage shift register is connected to the cascade signal end output_C(N+1) of the (N+1)th stage shift register. N≥2, and N is an integer.

[0111] In some examples, the shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal end through a low-level signal in response to the potential of the first pull-down node PD1; and the other third noise reduction sub-circuit is configured to pull down the output of the cascade signal end through a low-level signal in response to the potential of the second pull-down node PD2.

[0112] Continuing to refer to Fig. 5, both third noise reduction sub-circuits can include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal end, the drain of M12A is connected to the low-level signal end VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal end, the drain of M12B is connected to the low-level signal end VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0113] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high level signal, M12A is open, and the low level signal written by the low level signal end VGL is output through M12A to pull down the cascade signal end. When the second pull-down node PD2 is a high level signal, M12B is open, and the low level signal written by the low level signal end VGL is output through M12B to pull down the cascade signal end.

[0114] The other structures of the shift register in this example can be the same as those in the first example, and thus will not be repeated here.

[0115] The third example: Fig. 6 is a circuit diagram of a shift register of the third example of the embodiment of the present disclosure; as shown in Fig. 6, the structure of the shift register of this example is substantially the same as that of the first example, and the difference is only that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the first example.

[0116] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor, and for the convenience of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B respectively. The gate and source of M5A are connected to the first power voltage end VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power voltage end VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0117] When the first power voltage end VDDO is written with the first power voltage, M5A is open, and the first pull-down node PD1 is at the potential of the first power voltage, i.e. high potential. When the second power voltage end VDDE is written with the second power voltage, M5B is open, and the second pull-down node PD2 is at the potential of the second power voltage, i.e. high potential.

[0118] In this example, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 each include a sixth transistor, and for the convenience of description, the sixth transistors in the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are represented by M6A and M6B respectively. Among them, the source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low level signal end VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low level signal end VGL, and the gate of M6B is connected to the pull-up node PU.

[0119] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, ensuring that the pull-up node PU remains high, and normal output is ensured.

[0120] The other structures of the shift register in this example can be the same as those in the first example, and thus will not be repeated here.

[0121] The fourth example: Fig. 7 is a circuit diagram of a shift register of the fourth example of the embodiment of the present disclosure; as shown in Fig. 7, the shift register includes a first input sub-circuit 11, a second input sub-circuit 12, a pull-down control sub-circuit 4, a pull-down sub-circuit 5, a first auxiliary sub-circuit and a second auxiliary sub-circuit.

[0122] The shift register in Fig. 7 can realize bidirectional scanning, that is, forward scanning and reverse scanning. When forward scanning, the second input sub-circuit 12 is used as the pull-up reset sub-circuit 2, and when reverse scanning, the first input sub-circuit 11 is used as the pull-up reset sub-circuit 2. The first input sub-circuit 11 is configured to pre-charge the pull-up node PU through the first scan signal in response to the first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU through the second scan signal in response to the second input signal. The output sub-circuit 3 is configured to output the clock signal through the signal output end G(N) in response to the potential of the pull-up node PU. The pull-down control sub-circuit 4 is configured to control the potential of the pull-down node through the power voltage signal in response to the power voltage signal. The pull-down sub-circuit 5 is configured to pull down the potential of the pull-down node PD through the low-level signal in response to the potential of the pull-up node PU. The first auxiliary sub-circuit is configured to pull down the potential of the pull-down node PD through the second scan signal in response to the first input signal when forward scanning. The second auxiliary sub-circuit is configured to pull down the potential of the pull-down node PD through the first scan signal in response to the second input signal when reverse scanning.

[0123] In the embodiment of the present disclosure, since the first auxiliary sub-circuit and the second auxiliary sub-circuit are added, when forward scanning, the first auxiliary sub-circuit can be controlled to work through the first input signal, and since the second scan signal writes a low-level signal when forward scanning, the potential of the pull-down node PD can be pulled down through the second scan signal at this time, so that the competition relationship between the pull-down node PD and the pull-up node PU can be cancelled. Similarly, when reverse scanning, the second auxiliary sub-circuit can be controlled to work through the second input signal, and since the first scan signal writes a low-level signal when reverse scanning, the potential of the pull-down node PD can be pulled down through the first scan signal at this time, so that the competition relationship between the pull-down node PD and the pull-up node PU can be cancelled.

[0124] Continuing to refer to FIG. 7, when the shift register in the embodiment of the present disclosure is applied to the gate driving circuit, the signal input end of the Nth stage shift register is connected to the signal output end G(N) of the (N-1)th stage shift register, except for the first stage shift register; and the pull-up reset signal end of the Nth stage shift register is connected to the signal output end G(N) of the (N+1)th stage shift register, except for the last stage shift register. N≥2, and N is an integer.

[0125] In some examples, continuing to refer to FIG. 2, the first auxiliary sub-circuit includes a sixteenth transistor M16; wherein the source of M16 is connected to the pull-down node PD, the drain of M16 is connected to the second scan signal end VSD, and the gate of M16 is connected to the first input signal end.

[0126] Specifically, when forward scanning, the second scan signal written into the second scan signal end VSD is a low-level signal, and when the first input signal written into the first input signal end is a high-level signal, the first input sub-circuit 11 works, pre-charges the pull-up node PU through the first scan signal, and at the same time, since the first input signal is a high-level signal, M16 is opened, and the low-level signal written into the second scan signal end VSD pulls down the potential of the pull-down node PD, thereby effectively avoiding the competitive relationship between the pull-up node PU and the pull-down node PD.

[0127] In some examples, continuing to refer to FIG. 7, the second auxiliary sub-circuit includes a fifteenth transistor M15; wherein the source of M15 is connected to the pull-down node PD, the drain of M15 is connected to the second scan signal end VSD, and the gate of M15 is connected to the first input signal end.

[0128] Specifically, when forward scanning, the second scan signal written into the second scan signal end VSD is a low-level signal, and when the first input signal written into the first input signal end is a high-level signal, the first input sub-circuit 11 works, pre-charges the pull-up node PU through the first scan signal, and at the same time, since the first input signal is a high-level signal, M16 is opened, and the low-level signal written into the second scan signal end VSD pulls down the potential of the pull-down node PD, thereby effectively avoiding the competitive relationship between the pull-up node PU and the pull-down node PD.

[0129] In some examples, continuing to refer to FIG. 7, the shift register further includes a global reset sub-circuit 6. The global reset sub-circuit 6 is configured to reset the pull-up node PU and the signal output end G(N) through a low-level signal in response to a global reset signal.

[0130] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7; a source of the M4 is connected to the pull-up node PU, a drain of the M4 is connected to the low-level signal end VGL, and a gate of the M4 is connected to the global reset signal end Total-Rest. A source of the M7 is connected to the signal output end G(N), a drain of the M7 is connected to the low-level signal end VGL, and a gate of the M7 is connected to the global reset signal end Total-Rest.

[0131] Specifically, in the global reset stage, the global reset signal written into the global reset signal end Total-Rest is a high-level signal, the fourth transistor M4 and the seventh transistor M7 are both opened, at this time, the low-level signal written into the low-level signal end VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output end G(N) through the seventh transistor M7.

[0132] In some examples, continuing to refer to FIG. 2, the shift register further includes a first noise reduction sub-circuit and a second noise reduction sub-circuit. The first noise reduction sub-circuit reduces the output of the pull-up node PU by the low-level signal in response to the potential of the pull-down node PD. The second noise reduction sub-circuit reduces the output of the signal output end G(N) by the low-level signal in response to the potential of the pull-down node PD.

[0133] The first noise reduction sub-circuit includes a tenth transistor M10, and the second noise reduction sub-circuit includes an eleventh transistor M11. A source of the M10 is connected to the pull-up node PU, a drain of the M10 is connected to the low-level signal end VGL, and a gate of the M10 is connected to the pull-down node PD. A source of the M11 is connected to the signal output end G(N), a drain of the M11 is connected to the low-level signal end VGL, and a gate of the M11 is connected to the pull-down node PD.

[0134] Specifically, in the output noise reduction stage, when the potential of the first pull-down node PD1 is a high level, the M10 and the M11 are opened, and the low-level signal written into the low-level signal end VGL pulls down the potential of the pull-up node PU and the signal output end G(N).

[0135] In some examples, the first input sub-circuit 11 includes a first transistor M1, and the second input sub-circuit 12 includes a second transistor M2; a source of the M1 is connected to the first scan signal end VDS, a drain of the M1 is connected to the pull-up node PU, and a gate of the M1 is connected to the first signal input end. A source of the M2 is connected to the second scan signal end VSD, a drain of the M2 is connected to the pull-up node PU, and a gate of the M2 is connected to the second signal input end.

[0136] Specifically, when forward scanning, in the input stage, the first input signal written into the first input signal terminal is a high level signal, M1 is opened, the first scanning signal written into the first scanning signal terminal VDS is a high level signal, at this time, the pull-up node PU is pre-charged through the first scanning signal. In the pull-up reset stage, the second input signal written into the second input signal terminal is a high level signal, M2 is opened, the second scanning signal written into the second scanning signal terminal VSD is a low level signal, at this time, the pull-up node PU is discharged through the second scanning signal, so as to realize the reset of the pull-up node PU.

[0137] When reverse scanning, in the input stage, the second input signal written into the second input signal terminal is a high level signal, M2 is opened, the second scanning signal written into the second scanning signal terminal VSD is a high level signal, at this time, the pull-up node PU is pre-charged through the second scanning signal. In the pull-up reset stage, the first input signal written into the first input signal terminal is a high level signal, M1 is opened, the first scanning signal written into the first scanning signal terminal VDS is a low level signal, at this time, the pull-up node PU is discharged through the first scanning signal, so as to realize the reset of the pull-up node PU.

[0138] In some examples, the output sub-circuit 3 comprises a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected with the clock signal terminal CLK, the drain of M3 is connected with the signal output terminal G(N), and the gate of M3 is connected with the pull-up node PU; the first end of C1 is connected with the pull-up node PU, and the second end of C1 is connected with the signal output terminal G(N).

[0139] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, the clock signal written into the clock signal terminal CLK is a high level signal at this stage, at this time, the signal output terminal G(N) outputs a high level signal.

[0140] In some examples, the pull-down control sub-circuit 4 comprises a fifth transistor and a ninth transistor. The source of M5 is connected with the first power voltage terminal VDDO, the drain of M5 is connected with the pull-down node PD, the gate of M5 is connected with the drain of M9, and the source and gate of M9 are connected with the power voltage terminal GCH.

[0141] Specifically, when the power voltage signal is written into the power voltage terminal, M5 and M9 are both opened, the potential of the pull-down node PD is pulled up to the power voltage signal, that is, at a high potential.

[0142] In some examples, the pull-down sub-circuit 5 includes a sixth transistor and an eighth transistor. The source of the sixth transistor is connected to the pull-down node PD, the drain of the sixth transistor is connected to the low-level signal terminal VGL, and the gate of the sixth transistor is connected to the pull-up node PU. The source of the eighth transistor is connected to the drain of the ninth transistor and the gate of the fifth transistor, the drain of the eighth transistor is connected to the low-level signal terminal VGL, and the gate of the eighth transistor is connected to the pull-up node PU.

[0143] Specifically, when the potential of the pull-up node PU is high, the sixth transistor is turned on, and the pull-down node PD is pulled to low, ensuring that the pull-up node PU remains high and normal output.

[0144] The fifth example is a circuit diagram of a shift register of the fifth example of the embodiment of the present disclosure. As shown in FIG. 8, the structure of the shift register in this example is substantially the same as that in the fourth example, and the difference is only that the specific structures of the pull-down control sub-circuit 4 and the pull-down sub-circuit 5 are different from those in the fourth example.

[0145] In some examples, specifically, in this example, the pull-down control sub-circuit 4 includes a fifth transistor M5; wherein the gate and the source of M5 are connected to the power voltage terminal GCH, and the drain of M5 is connected to the pull-down node PD.

[0146] When the power voltage terminal is written with the power voltage signal, the fifth transistor is turned on, and the pull-down node PD is at the potential of the power voltage signal, i.e., high potential.

[0147] In this example, the pull-down sub-circuit 5 includes a sixth transistor M6; wherein the source of M6 is connected to the pull-down node PD, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU.

[0148] Specifically, when the potential of the pull-up node PU is high, the sixth transistor is turned on, and the pull-down node PD is pulled to low, ensuring that the pull-up node PU remains high and normal output.

[0149] For other structures of the shift register in this example, they can be the same as those in the fourth example, and thus are not repeated here.

[0150] The embodiment of the present disclosure also provides a gate drive circuit including a plurality of cascaded shift registers, wherein the shift registers can adopt any one of the above-described shift registers.

[0151] The embodiment of the present disclosure provides a display device including the above-described gate drive circuit.

[0152] It is understood that the above embodiments are only exemplary for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. A shift register comprising: The first input sub-circuit, the second input sub-circuit, the output sub-circuit, at least one pull-down control sub-circuit and at least one pull-down sub-circuit; The pull-down control sub-circuit is connected with the pull-down sub-circuit one by one, and the connection node is a pull-down node; The first input sub-circuit is configured to pre-charge a pull-up node by a first scan signal in response to a first input signal; The second input sub-circuit is configured to pre-charge the pull-up node by a second scan signal in response to a second input signal; The output sub-circuit is configured to output a clock signal through a signal output in response to a potential of the pull-up node; The pull-down control sub-circuit is configured to control a potential of a corresponding pull-down node by a power voltage signal in response to the power voltage signal; The pull-down sub-circuit is configured to pull down the potential of the corresponding pull-down node by a non-working level signal in response to the potential of the pull-up node; wherein, The shift register further comprises at least one first auxiliary sub-circuit and at least one second auxiliary sub-circuit, and the first auxiliary sub-circuit and the second auxiliary sub-circuit are connected with the pull-down node one by one; The first auxiliary sub-circuit is configured to pull down the potential of the corresponding pull-down node by the second scan signal in response to the first input signal; The second auxiliary sub-circuit is configured to pull down the potential of the corresponding pull-down node by the first scan signal in response to the second input signal.

2. The shift register of claim 1, wherein, The first auxiliary sub-circuit comprises a sixteenth transistor; The first electrode of the sixteenth transistor is connected with the corresponding pull-down node, the second electrode is connected with a second scan signal end, and the control electrode is connected with a first input signal end.

3. The shift register of claim 1, wherein, The second auxiliary sub-circuit comprises a fifteenth transistor; The first electrode of the fifteenth transistor is connected with the corresponding pull-down node, the second electrode is connected with a first scan signal end, and the control electrode is connected with a second input signal end.

4. The shift register of claim 1, wherein, Further comprising a global reset sub-circuit, which is configured to globally reset the pull-up node and the signal output end by the non-working level signal in response to a global reset signal.

5. The shift register of claim 4, wherein, The global reset sub-circuit comprises a fourth transistor and a seventh transistor; The first electrode of the fourth transistor is connected with the pull-up node, the second electrode is connected with a non-working level signal end, and the control electrode is connected with a global reset signal end; The first electrode of the seventh transistor is connected with the signal output end, the second electrode is connected with a non-working level signal end, and the control electrode is connected with a global reset signal end.

6. The shift register of claim 1, wherein, Further comprising at least one first noise reduction sub-circuit; the first noise reduction sub-circuit is configured to reduce noise of the output of the pull-up node by the non-working level signal under the control of the corresponding pull-down node.

7. The shift register of claim 6, wherein, The first noise reduction sub-circuit comprises a tenth transistor; The first electrode of the tenth transistor is connected with the pull-up node, the second electrode is connected with a non-working level signal end, and the control electrode is connected with the corresponding pull-down node.

8. The shift register of claim 1, wherein, The second noise reduction sub-circuit is configured to reduce noise of the output of the signal output terminal by a non-working level signal under the control of the corresponding pull-down node.

9. The shift register of claim 8, wherein, The second noise reduction sub-circuit comprises an eleventh transistor. The first electrode of the eleventh transistor is connected to the signal output terminal, the second electrode is connected to a non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

10. The shift register of claim 1, wherein, The cascade sub-circuit is configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

11. The shift register of claim 10, wherein, The cascade sub-circuit comprises a thirteenth transistor. The first electrode of the thirteenth transistor is connected to a clock signal terminal, the second electrode is connected to a cascade signal terminal, and the control electrode is connected to the pull-up node.

12. The shift register of claim 10, wherein, The third noise reduction sub-circuit is configured to reduce noise of the output of the cascade signal terminal by a non-working level signal under the control of the corresponding pull-down node.

13. The shift register of claim 12, wherein, The third noise reduction sub-circuit comprises a twelfth transistor. The first electrode of the twelfth transistor is connected to the cascade signal terminal, the second electrode is connected to a non-working level signal terminal, and the control electrode is connected to the corresponding pull-down node.

14. The shift register of any one of claims 1-13, wherein, The first input sub-circuit comprises a first transistor. The first electrode of the first transistor is connected to a first scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to a first input signal terminal.

15. The shift register of any one of claims 1-13, wherein, The second input sub-circuit comprises a second transistor. The first electrode of the second transistor is connected to a second scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to a second input signal terminal.

16. The shift register of any one of claims 1-13, wherein, The output sub-circuit comprises a third transistor and a storage capacitor. The first electrode of the third transistor is connected to a clock signal terminal, the second electrode is connected to a signal output terminal and the second electrode of the storage capacitor, and the control electrode is connected to the first electrode of the pull-up node and the first end of the storage capacitor.

17. The shift register of any one of claims 1-13, wherein, The pull-up control sub-circuit comprises a fifth transistor. The first electrode and the control electrode of the fifth transistor are connected to a power voltage terminal, and the second electrode is connected to the pull-down node.

18. The shift register of any one of claims 1-13, wherein, The pull-down sub-circuit comprises a sixth transistor. The first electrode of the sixth transistor is connected to the pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node.

19. The shift register of any one of claims 1-13, wherein, The pull-up control sub-circuit comprises a fifth transistor and a ninth transistor. The first electrode of the fifth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor, and a power voltage terminal, and the second electrode is connected to the pull-down node.

20. The shift register of claim 19, wherein, The pull-down sub-circuit comprises a sixth transistor and an eighth transistor. The first electrode of the sixth transistor is connected to the pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node. The first electrode of the eighth transistor is connected to the control electrode of the fifth transistor and the first electrode of the ninth transistor, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node.

21. A gate drive circuit comprising a plurality of cascaded shift registers, the shift registers being according to any one of claims 1-20.

22. A display device comprising the gate driver circuit according to claim 21.

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