Shift register, scan drive circuit and display panel

Abstract

A shift register, a scan drive circuit and a display panel, which relate to the technical field of display. The shift register comprises: an input circuit (10), which is electrically connected to an input end (IN) and a pull-up node (PU), and is configured to write a signal of the input end (IN) into the pull-up node (PU) when in an on state; a first output circuit (20), which is electrically connected to the pull-up node, a first clock signal end (CK1) and a first output end (OUT1), and is configured to write a signal of the first clock signal end (CK1) into the first output end (OUT1) under the control of a signal of the pull-up node (PU); and a second output circuit (30), which is electrically connected to the pull-up node (PU), a second clock signal end (CK2) and a second output end (OUT2), and is configured to write a signal of the second clock signal end (CK2) into the second output end (OUT2) under the control of a signal of the pull-up node (PU).

Description

Shift register, scan drive circuit and display panel

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202410513454.2, filed on April 26, 2024, entitled “Shift Register, Scan Driver Circuit and Display Panel”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a shift register, a scan drive circuit, and a display panel. Background Technology

[0004] In related technologies, the wide bezels of display panels negatively impact the user experience. Summary of the Invention

[0005] Embodiments of this disclosure provide a shift register, a scan drive circuit, and a display panel.

[0006] On the one hand, a shift register is provided, including:

[0007] An input circuit is electrically connected to an input terminal and a pull-up node, and the input circuit is configured to write the signal from the input terminal to the pull-up node.

[0008] A first output circuit is electrically connected to the pull-up node, the first clock signal terminal, and the first output terminal, respectively. The first output circuit is configured to write the signal of the first clock signal terminal to the first output terminal under the signal control of the pull-up node.

[0009] The second output circuit is electrically connected to the pull-up node, the second clock signal terminal, and the second output terminal, respectively. The second output circuit is configured to write the signal of the second clock signal terminal to the second output terminal under the signal control of the pull-up node.

[0010] In some implementations, the shift register further includes:

[0011] A first isolation circuit is electrically connected between the pull-up node and the first output circuit, and is also electrically connected to a first isolation control terminal. The first isolation circuit is configured to disconnect the electrical connection between the pull-up node and the first output circuit under the signal control of the first isolation control terminal.

[0012] In some implementations, the shift register further includes:

[0013] A second isolation circuit is electrically connected between the pull-up node and the second output circuit, and is also electrically connected to a second isolation control terminal. The second isolation circuit is configured to disconnect the electrical connection between the pull-up node and the second output circuit under the signal control of the second isolation control terminal.

[0014] In some implementations, the first isolation control terminal is electrically connected to the second isolation control terminal.

[0015] In some implementations, the first isolation circuit is configured to disconnect the electrical connection between the pull-up node and the first output circuit when the first output terminal is a high-level signal; and / or, the second isolation circuit is configured to disconnect the electrical connection between the pull-up node and the second output circuit when the second output terminal is a high-level signal.

[0016] In some embodiments, the first isolation circuit includes a first isolation transistor, the first terminal of which is electrically connected to the pull-up node, the second terminal of which is electrically connected to the first output circuit, and the gate of which is electrically connected to the first isolation control terminal; and / or,

[0017] The second isolation circuit includes a second isolation transistor, the first terminal of which is electrically connected to the pull-up node, the second terminal of which is electrically connected to the second output circuit, and the gate of which is electrically connected to the second isolation control terminal.

[0018] In some implementations, the shift register further includes:

[0019] A cascaded circuit is electrically connected to a cascaded signal terminal, a pull-up node, and a cascaded output terminal, respectively. The cascaded circuit is configured to write the signal from the cascaded signal terminal to the cascaded output terminal under the signal control of the pull-up node.

[0020] In some implementations, the shift register further includes:

[0021] A third isolation circuit is electrically connected between the pull-up node and the cascaded circuit, and is also electrically connected to a third isolation control terminal. The third isolation circuit is configured to disconnect the electrical connection between the pull-up node and the cascaded circuit under the signal control of the third isolation control terminal.

[0022] In some implementations, the third isolation control terminal is electrically connected to the first isolation control terminal and the second isolation control terminal.

[0023] In some embodiments, the third isolation circuit includes a third isolation transistor, the first terminal of which is electrically connected to the pull-up node, the second terminal of which is electrically connected to the cascaded circuit, and the gate of which is electrically connected to the third isolation control terminal.

[0024] In some implementations, some or all of the transistors in the shift register are dual-gate structures.

[0025] In some embodiments, the input circuit includes a first input transistor and a second input transistor, wherein a first terminal of the first input transistor is electrically connected to the input terminal, a second terminal of the first input transistor is electrically connected to the first terminal of the second input transistor, a second terminal of the second input transistor is electrically connected to the pull-up node, and the gates of the first and second input transistors are electrically connected to the input terminal.

[0026] The shift register further includes a leakage protection circuit, which is electrically connected to a first voltage terminal, a leakage protection control terminal, and the second electrode of the first input transistor. The leakage protection circuit is configured to write the signal from the first voltage terminal to the second electrode of the first input transistor under the signal control of the leakage protection control terminal.

[0027] In some embodiments, the shift register further includes a reset circuit, which is electrically connected to a first pull-down node, a second pull-down node, a first output terminal, a second output terminal, and a second voltage terminal, respectively. The reset circuit is configured to write a signal from the second voltage terminal to the first output terminal or the second output terminal under the signal control of the first pull-down node or the second pull-down node.

[0028] On the other hand, a scan drive circuit is provided, including a plurality of the aforementioned shift registers, wherein the plurality of the aforementioned shift registers are cascaded.

[0029] In some embodiments, the plurality of shift registers includes a first shift register and a second shift register, the first shift register and the second shift register are cascaded, a first pull-down node of the first shift register is electrically connected to a first pull-down node of the second shift register, and a second pull-down node of the first shift register is electrically connected to a second pull-down node of the second shift register.

[0030] The first shift register further includes a first noise reduction circuit, which is electrically connected to the first pull-down node. The second shift register further includes a second noise reduction circuit, which is electrically connected to the second pull-down node.

[0031] On the other hand, a display panel is provided, including the shift register or the scan drive circuit.

[0032] The shift register, scan driving circuit, and display panel provided in this disclosure include a first output circuit and a second output circuit in the shift register. The first output circuit is electrically connected to one of the sub-pixel rows through a first output terminal, and the second output circuit is electrically connected to another sub-pixel row through a second output terminal. That is, one shift register can provide scan signals to multiple sub-pixel rows. With the number of sub-pixel rows in the display panel remaining unchanged, the number of shift registers in the scan driving circuit can be reduced, thereby reducing the area of ​​the non-display area in the display panel and meeting the requirements for narrow bezels in the display panel. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 is an application scenario diagram of a display panel provided in an embodiment of this disclosure;

[0035] Figure 2 is a simplified structural diagram of a display panel provided in an embodiment of this disclosure;

[0036] Figure 3 is a partial structural block diagram of a shift register provided in an embodiment of this disclosure;

[0037] Figure 4 is a partial structural diagram of a shift register provided in an embodiment of this disclosure;

[0038] Figure 5 shows a timing signal terminal of a shift register in an embodiment of this disclosure;

[0039] Figure 6 is a cascade diagram of two adjacent shift registers in the display panel provided in the embodiment of this disclosure;

[0040] Figure 7 is a partial structural block diagram of another shift register provided in an embodiment of this disclosure;

[0041] Figure 8 is a partial structural diagram of another shift register provided in an embodiment of this disclosure;

[0042] Figure 9 is a structural block diagram of another shift register provided in an embodiment of this disclosure;

[0043] Figure 10 is a circuit diagram of another shift register provided in an embodiment of this disclosure;

[0044] Figure 11 is the signal timing diagram of the shift register shown in Figure 10;

[0045] Figure 12 is a partial structural block diagram of another shift register provided in an embodiment of this disclosure;

[0046] Figure 13 is a partial structural diagram of another shift register provided in an embodiment of this disclosure;

[0047] Figure 14 is a schematic diagram of another shift register provided in an embodiment of this disclosure;

[0048] Figure 15 is a partial structural diagram of another shift register provided in an embodiment of this disclosure;

[0049] Figure 16 is a circuit diagram of another shift register provided in an embodiment of this disclosure;

[0050] Figure 17 is a timing diagram of the shift register shown in Figure 16;

[0051] Figure 18 is a circuit schematic diagram of a shift register provided in an embodiment of this disclosure;

[0052] Figure 19 is a timing signal diagram of the shift register shown in Figure 16;

[0053] Figure 20 is a circuit diagram of another shift register provided in an embodiment of this disclosure;

[0054] Figure 21 is a circuit diagram of another shift register provided in an embodiment of this disclosure;

[0055] Figure 22 is a circuit schematic diagram of another shift register provided in an embodiment of this disclosure;

[0056] Figure 23 is a circuit diagram of another shift register provided in an embodiment of this disclosure;

[0057] Figure 24 is a circuit schematic diagram of a first shift register provided in an embodiment of this disclosure;

[0058] Figure 25 is a circuit schematic diagram of a second shift register provided in an embodiment of this disclosure. Specific Implementation

[0059] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0060] In the embodiments of this disclosure, the terms "first," "second," "third," and "fourth" are used to distinguish identical or similar items with essentially the same function and effect, solely for the purpose of clearly describing the technical solutions of the embodiments of this disclosure, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0061] In embodiments of this disclosure, "a plurality of" means two or more, and "at least one" means one or more, unless otherwise expressly and specifically defined.

[0062] In the embodiments of this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0063] Embodiments of this disclosure provide a display panel that can be applied to various devices and equipment with display functions for displaying graphics. For example, the display panel can be applied to mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 is an application scenario diagram of a display panel 110 provided in an embodiment of this disclosure, illustrating the application of the display panel 110 to a mobile phone as an example.

[0064] The display panel 110 can be a liquid crystal display (LCD). When the display panel 110 is an LCD, it can be either a horizontal electric field type LCD or a vertical electric field type LCD. When the display panel 110 is a horizontal electric field type LCD, it can be an in-plane switching (IPS) LCD or an advanced super-dimensional switching (ADS) LCD.

[0065] The display panel 110 can also be an electroluminescent display panel or a photoluminescent display panel. When the display panel 110 is an electroluminescent display panel, it can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. When the display panel 110 is a photoluminescent display panel, it can be a quantum dot photoluminescent display panel. Some embodiments of this disclosure are illustrated using an organic light-emitting diode (OLED) display panel as an example.

[0066] Figure 2 is a simplified structural diagram of a display panel provided in an embodiment of this disclosure. As shown in Figure 2, the display panel includes a scan driving circuit GOA, multiple gate lines GL, multiple data lines DL, and multiple sub-pixels PX.

[0067] The display panel may have a display area AA and a non-display area NA electrically connected to the display area AA. The non-display area NA may be located on one side, two sides, or three sides of the display area AA, or the non-display area NA may be arranged around the display area AA.

[0068] Multiple sub-pixels (PX), multiple gate lines (GL), and multiple data lines (DL) can be located within the display area (AA), while the scan drive circuit (GOA) can be located within the non-display area (NA). In practical applications, to reduce the width of the non-display area (NA) of the display panel 110, a portion of the structure of the scan drive circuit (GOA) can also be located within the display area (AA).

[0069] For example, multiple subpixels PX are arranged in an array. For instance, the array arrangement of multiple subpixels PX forms multiple subpixel rows and multiple subpixel columns. The multiple subpixels PX in a subpixel row are arranged along a first direction X, and the multiple subpixels PX in a subpixel column are arranged along a second direction Y.

[0070] In this configuration, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the included angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°, etc.

[0071] The sub-pixel PX may include a pixel driving circuit P1 and a light-emitting device P2 electrically connected to the pixel driving circuit P1. When the display panel 110 is working, the light-emitting device P2 can emit light under the drive of the pixel driving circuit P1.

[0072] The pixel driving circuit P1 can have various structures, which can be flexibly selected according to actual needs. For example, the pixel driving circuit P1 can have structures such as "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C". Here, "T" represents a transistor, and the number before "T" indicates the number of transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors.

[0073] For example, a gate line GL can be electrically connected to multiple pixel driving circuits P1 in a sub-pixel row, and a data line DL can be electrically connected to multiple pixel driving circuits P1 in a sub-pixel column.

[0074] Referring again to Figure 2, the scan drive circuit GOA is electrically connected to the end of the gate line GL. It should be noted that Figure 2 only shows the scan drive circuit GOA connected to the left end of the gate line GL as an example. The scan drive circuit GOA can also be connected to the right end of the gate line GL, or both the left and right ends of the gate line GL can be electrically connected to the scan drive circuit GOA.

[0075] The scan drive circuit GOA includes multiple cascaded shift registers SR. Each shift register SR has an output terminal, which is electrically connected to the gate line GL. When the scan drive circuit GOA is working, the output terminals of the multiple cascaded shift registers SR output scan signals to the pixel drive circuit P1 step by step through the gate line GL.

[0076] In related technologies, a shift register only includes one output terminal. As the pixel density of the display panel increases, the number of sub-pixel rows in the display panel increases. Correspondingly, the number of shift registers in the scan drive circuit also increases, resulting in a larger area of ​​the non-display area of ​​the display panel, which cannot meet the user's demand for narrow bezels.

[0077] In view of this, embodiments of the present disclosure provide a shift register including multiple output terminals, which enables one shift register to provide scanning signals to multiple sub-pixels, reducing the number of shift registers in the scan driving circuit, thereby reducing the area of ​​the non-display area NA.

[0078] Figure 3 is a partial structural block diagram of a shift register provided in an embodiment of this disclosure. As shown in Figure 3, the shift register includes an input circuit 10, a first output circuit 20, and a second output circuit 30. The input circuit 10 is electrically connected to the input terminal IN and the pull-up node PU, respectively. The first output circuit 20 is electrically connected to the pull-up node PU, the first clock signal terminal CK1, and the first output terminal OUT1, respectively. The second output circuit 30 is electrically connected to the pull-up node PU, the second clock signal terminal CK2, and the second output terminal OUT2, respectively.

[0079] The input terminal IN can be electrically connected to the start signal line or to the output terminal of another shift register. For example, when the shift register is in the start position, its input terminal IN is electrically connected to the start signal line; when the shift register is in a non-start position, its input terminal IN is electrically connected to one of the output terminals of the previous shift register.

[0080] The shift register at the starting position can be the topmost shift register in Figure 2. The next-level shift register can be a shift register located above and adjacent to it. For example, the shift register at the starting position in Figure 2 is the next-level shift register of the second shift register.

[0081] The pull-up node PU is a virtual node that represents the junction where the input circuit 10, the first output circuit 20, and the second output circuit 30 are electrically connected.

[0082] The first output terminal OUT1 is electrically connected to one of the gate lines GL, and the second output terminal OUT2 is electrically connected to the other gate line GL, with the two gate lines GL being electrically connected to different sub-pixel rows respectively. For example, the multiple sub-pixel rows in the display panel 110 include adjacent first sub-pixel rows and second sub-pixel rows, with the first output terminal OUT1 electrically connected to the first sub-pixel row and the second output terminal OUT2 electrically connected to the second sub-pixel row.

[0083] The scan drive circuit also includes a first clock signal line and a second clock signal line. The first clock signal line is electrically connected to the first clock signal terminal CK1, and the second clock signal line is electrically connected to the second clock signal terminal CK2. The signals within the first clock signal line and the second clock signal line can be different.

[0084] The input circuit 10 operates in an ON state, in which it is configured to write the signal at the input terminal IN to the pull-up node PU. For example, when the signal at the input terminal IN is a high-level signal, the input circuit 10 is in the ON state and writes the high-level signal at the input terminal IN to the pull-up node PU.

[0085] The first output circuit 20 is configured to write the signal of the first clock signal terminal CK1 to the first output terminal OUT1 under the signal control of the pull-up node PU. For example, when the signal of the pull-up node PU is a high-level signal, the first output circuit 20 writes the signal of the first clock signal terminal CK1 to the first output terminal OUT1.

[0086] The second output circuit 30 is configured to write the signal of the second clock signal terminal CK2 to the second output terminal OUT2 under the signal control of the pull-up node PU. For example, when the signal of the pull-up node PU is a high-level signal, the second output circuit 30 writes the signal of the second clock signal terminal CK2 to the second output terminal OUT2.

[0087] Figure 4 is a partial structural diagram of a shift register provided in an embodiment of this disclosure. Exemplarily, as shown in Figure 4, the first output circuit 20 includes a first output transistor T3-1 and a first capacitor C1. The first terminal of the first output transistor T3-1 is electrically connected to the first clock signal terminal CK1, the second terminal of the first output transistor T3-1 is electrically connected to the first output terminal OUT1, the gate of the first output transistor T3-1 is electrically connected to the pull-up node PU, the first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the first output terminal OUT1. The second output circuit 30 includes a second output transistor T3-2 and a second capacitor C2. The first terminal of the second output transistor T3-2 is electrically connected to the second clock signal terminal CK2, the second terminal of the second output transistor T3-2 is electrically connected to the second output terminal OUT2, the gate of the second output transistor T3-2 is electrically connected to the pull-up node PU, the first plate of the second capacitor C2 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the second output terminal OUT2.

[0088] The transistors used in the embodiments of this disclosure can be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with the same characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one is referred to as the first terminal and the other as the second terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for illustration; when the gate input is high, the source and drain are conducting, while the opposite is true for P-type transistors. It is conceivable that using P-type transistors is something that those skilled in the art can easily conceive of without inventive effort, and therefore it is also within the protection scope of the embodiments of this disclosure.

[0089] Figure 5 shows a timing signal terminal of the shift register in an embodiment of this disclosure. The operation of the shift register shown in Figure 4 is described below with reference to Figure 5. During time period t1, the input terminal IN is a high-level signal, and the input circuit 10 is in a conducting state. The high-level signal of the input terminal IN is written to the pull-up node PU. Under the control of the high-level signal of the pull-up node PU, the first output circuit 20 writes the low-level signal of the first clock signal terminal CK1 to the first output terminal OUT1. Under the control of the high-level signal of the pull-up node PU, the second output circuit 30 writes the low-level signal of the second clock signal terminal CK2 to the second output terminal OUT2. During time period t2, the input terminal IN is a low-level signal, and the connection between the input terminal IN and the pull-up node PU is broken. The pull-up node PU maintains a high-level signal under the action of the first capacitor C1 and the second capacitor C2. Under the control of the high-level signal of the pull-up node PU, the first output circuit 20 writes the high-level signal of the first clock signal terminal CK1 to the first output terminal OUT1. Under the control of the high-level signal of the pull-up node PU, the second output circuit 30 writes the low-level signal of the second clock signal terminal CK2 to the second output terminal OUT2. During time period t3, the input terminal IN is a low-level signal, and the connection between the input terminal IN and the pull-up node PU is broken. The pull-up node PU maintains a high-level signal under the action of the first capacitor C1 and the second capacitor C2. Under the control of the high-level signal from the pull-up node PU, the first output circuit 20 writes the low-level signal from the first clock signal terminal CK1 to the first output terminal OUT1. Similarly, under the control of the high-level signal from the pull-up node PU, the second output circuit 30 writes the high-level signal from the second clock signal terminal CK2 to the second output terminal OUT2. That is, the first output terminal OUT1 and the second output terminal OUT2 can output high-level scan signals step by step.

[0090] The shift register provided in this embodiment includes both a first output circuit 20 and a second output circuit 30. The first output circuit 20 is electrically connected to one of the sub-pixel rows via a first output terminal OUT1, and the second output circuit 30 is electrically connected to another sub-pixel row via a second output terminal OUT2. That is, one shift register can provide scanning signals to multiple sub-pixel rows. With the number of sub-pixel rows in the display panel remaining constant, the number of shift registers in the scan driving circuit can be reduced, thereby reducing the area of ​​the non-display area in the display panel and meeting the requirements for narrow bezels in the display panel.

[0091] It should be noted that the shift register in this embodiment includes multiple output circuits, and the number of output circuits can be two, three, four, five, etc. For ease of description, this embodiment only takes the shift register including a first output circuit 20 and a second output circuit 30 as an example. In actual applications, the shift register may also include a third output circuit, a fourth output circuit, a fifth output circuit, etc. For example, the third output circuit is electrically connected to the pull-up node PU, the third clock signal terminal, and the third output terminal. The third output circuit is configured to write the signal from the third clock signal terminal to the third output terminal under the signal control of the pull-up node PU. The fourth output circuit, the fifth output circuit, etc., are similar and will not be described in detail here.

[0092] Figure 6 is a cascade diagram of two adjacent shift registers in the display panel provided in this embodiment of the present disclosure. For ease of illustration, the first clock signal terminal of the next-stage shift register is represented by CK3, the second clock signal terminal by CK4, the first output terminal by OUT3, and the second output terminal by OUT4.

[0093] As shown in Figure 6, the first output terminal OUT1 of the previous stage shift register is electrically connected to the input terminal IN of the next stage shift register. The scan drive circuit also includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, and a fourth clock signal line CLK4. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the previous stage shift register, the second clock signal line CLK2 is electrically connected to the second clock signal terminal CK2 of the previous stage shift register, the third clock signal line CLK3 is electrically connected to the first clock signal terminal CK3 of the next stage shift register, and the fourth clock signal line CLK4 is electrically connected to the second clock signal terminal CK4 of the next stage shift register.

[0094] Figure 9 is a structural block diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 9, the shift register may further include a reset circuit 70, which is electrically connected to the first pull-down node PDo, the second pull-down node PDe, the first input terminal OUT1, the second output terminal OUT2, and the second voltage terminal V2.

[0095] The reset circuit 70 is configured to write the signal of the second voltage terminal V2 to the first output terminal OUT1 or the second output terminal OUT2 under the signal control of the first pull-down node PDo or the second pull-down node PDe. For example, when the second voltage terminal V2 is electrically connected to VGL and the signal of the first pull-down node PDo or the second pull-down node PDe is a high-level signal, the reset circuit 70 writes the low-level signal of the second voltage terminal V2 to the first output terminal OUT1 or the second output terminal OUT2.

[0096] Figure 18 is a circuit schematic diagram of a shift register provided in an embodiment of this disclosure. Exemplarily, as shown in Figure 18, the input circuit 10 includes a first transistor T1, whose first terminal and gate are both electrically connected to the input terminal IN, and whose second terminal is electrically connected to the pull-up node PU.

[0097] In this design, the LVGL level is lower than the VGL level. This reduces the likelihood of the TFT Vth being negative, ensuring no leakage when the output is high, and also speeds up the output discharge process. Because the discharge path of this structure is CK1 / CK2, and CK1 / CK2 at low level corresponds to LVGL, the output can be reset to VGL more quickly. T_RST1 and T_RST2 are the global reset signals, typically low, used to reset the shift register state and output. T_RST1 resets all pull-up nodes (PU) during the blanking time, while T_RST2 resets all pull-down nodes (PDo, Pde) during power-on and power-off, initializing the shift register state and improving display reliability. VDDo / VDDe are opposite high and low power supplies, with an alternation period ranging from two frames to several seconds or longer. The switching time is generally set during the blanking time. The voltage can be a constant VGH voltage or an adjustable voltage that varies with the shift register's operating time. To prevent electrostatic discharge (ESD) damage to the structure, transistor T14 can be placed near or far from the output of the shift register.

[0098] The shift register shown in Figure 18 has fewer transistors, which reduces the area of ​​the non-display area NA in the display panel, thereby reducing the width of the display panel bezel.

[0099] Because the first output terminal OUT1 of the previous stage shift register is electrically connected to the input terminal IN of the next stage shift register, as well as to the pixel driving circuit in a sub-pixel row, the load on the first output terminal OUT1 is relatively large, which causes the signal attenuation at the input terminal IN of the next stage shift register, and the attenuation is more severe in the later shift registers.

[0100] Figure 7 is a partial structural block diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 7, the shift register also includes a cascade circuit 60, which is electrically connected to the cascade signal terminal CKc, the pull-up node PU, and the cascade output terminal Cout, respectively.

[0101] The cascade circuit 60 is configured to write the signal from the cascade signal terminal CKc to the cascade output terminal Cout under the signal control of the pull-up node PU. For example, when the cascade signal terminal CKc is a high-level signal, the cascade circuit 60 writes the high-level signal from the cascade signal terminal CKc to the cascade output terminal Cout.

[0102] When multiple shift registers are cascaded, the cascade output Cout of the previous shift register is electrically connected to the input IN of the next shift register. Since the cascade output Cout is not electrically connected to the pixel driving circuit within the sub-pixel row, the load on Cout is relatively small, and the signal input to the next shift register IN does not attenuate or experiences minimal attenuation, improving the display uniformity of the display panel. Furthermore, the signals at the cascade output Cout of each shift register are written to the cascade signal terminal CKc, thus preventing attenuation accumulation and further improving the display uniformity of the display panel.

[0103] Figure 8 is a partial structural diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 8, the cascade circuit 60 includes an eleventh transistor T11 and a third capacitor C3. The first terminal of the eleventh transistor T11 is electrically connected to the cascade signal terminal CKc, the second terminal of the eleventh transistor T11 is electrically connected to the cascade output terminal Cout, the gate of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first plate of the third capacitor C3 is electrically connected to the pull-up node PU, and the second plate of the third capacitor C3 is electrically connected to the cascade output terminal Cout.

[0104] Figure 10 is a circuit schematic diagram of another shift register provided in an embodiment of this disclosure, and Figure 11 is a signal timing diagram of the shift register shown in Figure 10. The working process of a shift register provided in an embodiment of this disclosure is described below with reference to Figures 10 and 11. Wherein, Gout(n-1) refers to the output terminal electrically connected to the (n-1)th sub-pixel row, Gout(n) refers to the output terminal electrically connected to the nth sub-pixel row, Gout(n+1) refers to the output terminal electrically connected to the (n+1)th sub-pixel row, and the signal of the second clock signal terminal CK2 is the same as the signal of the cascade signal terminal CKc. Cout(n / 2) refers to the cascaded output terminal Cout of the n / 2th shift register, Cout(n / 2-1) refers to the cascaded output terminal Cout of the previous stage shift register of the n / 2th shift register, and Cout(n / 2+1) refers to the cascaded output terminal Cout of the next stage shift register of the n / 2th shift register. CK3 is the timing signal for the first clock signal terminal CK1 in the n / 2nd shift register, and CK4 is the timing signal for the second clock signal terminal CK2 in the n / 2nd shift register. CBc refers to the timing signal for the cascading signal terminal CKc of the next stage shift register of the n / 2nd shift register. CKc refers to the timing signal for the cascading signal terminal CKc of the n / 2nd shift register.

[0105] As shown in Figures 10 and 11:

[0106] In stage t1, the input signal IN is high, transistors T1, T7o, and T7e are turned on, so the pull-up node PU is high, and transistors T3-1, T3-2, and T11 are turned on; VDDo (or VDDe) is high, and transistor T5o (or T5e) is turned on. By setting the channel width-to-length ratio of T5 / T6, the Pdo (or PDe) node is low, so transistors T8o (or T8e), T13o, T13e, T13o-2, and T13e-2 are turned off; Cout(n / 2+1) and Gout(n+2) are low, so transistors T2, T4, and T4-2 are turned off; CKc, CK1, and CK2 are low, so the outputs Cout(n / 2), Gout(n-1), and Gout(n) are low.

[0107] In stage t2, Cout(n / 2-1) goes low, transistors T1, T7o, and T7e are cut off, so the pull-up node PU remains high, and transistors T3-1, T3-2, and T11 remain on; the pull-down nodes (PDo, Pde) remain low, so transistors T8o (or T8e), T13o, T13e, T13o-2, and T13e-2 remain off; Cout(n / 2+1) and Gout(n+2) remain low, so transistors T2, T4, and T4-2 remain off; CK1 goes high, so the output Gout(n-1) goes high.

[0108] In phase t3, CK1 goes low, so the output Gout(n-1) goes low. Meanwhile, CKc and CK2 go high, so the outputs Cout(n / 2) and Gout(n) go high. The states of other nodes are the same as in phase t2.

[0109] In phase t4, CKc and CK2 go low, so the outputs Cout(n / 2) and Gout(n) go low. The states of other nodes are the same as in phase t2.

[0110] During stage t5, Cout(n / 2+1) and Gout(n+2) go high, so transistors T2, T4, and T4-2 are turned on; pull-up node PU goes low, so transistors T3-1, T3-2, T11, T6o, and T6e are turned off; T5o (or T5e) turns on, so Pdo (or Pde) goes high, and transistors T8o (or T8e), T13o (or T13e), and T13o-2 (or T13e-2) are turned on; the output remains low.

[0111] During stage t6 and thereafter, as long as Cout(n / 2-1) remains low, regardless of how CKc, CK1, and CK2 change, if the pull-up node PU remains low and the pull-down nodes (PDo, Pde) remain high, the output will remain low.

[0112] After stages t5 and t6, the outputs Cout(n / 2), Gout(n-1), and Gout(n) remain low until Cout(n / 2-1) restarts the shift register.

[0113] Referring again to Figures 4 and 10, since the voltage between the two plates of a capacitor cannot change abruptly, when the signal at the first output terminal OUT1 is high, the level of the pull-up node PU will also increase under the influence of the first capacitor C1. This increase in the level of the pull-up node PU, under the influence of the first capacitor C1, leads to an increase in the power consumption of the shift register. For example, after the level of the pull-up node PU increases, the opening degree of transistors T6o and T6e increases, resulting in an increase in leakage current through transistors T6o and T6e, thus increasing the power consumption of the shift register.

[0114] Figure 12 is a partial structural block diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 12, the shift register further includes a first isolation circuit 40, which is electrically connected between the pull-up node PU and the first output circuit 20, and is also electrically connected to the first isolation control terminal S1.

[0115] For example, the first isolation circuit 40 is electrically connected to the first plate of the first capacitor C1.

[0116] The first isolation circuit 40 is configured to disconnect the electrical connection between the pull-up node PU and the first output circuit 20 under the signal control of the first isolation control terminal S1. For example, when the first isolation control terminal S1 is a high-level signal, the first isolation circuit 40 disconnects the electrical connection between the pull-up node PU and the first plate of the first capacitor C1.

[0117] In some implementations, the first isolation circuit 40 is configured to disconnect the electrical connection between the pull-up node PU and the first output circuit 20 when the first output terminal OUT1 is a high-level signal.

[0118] In this way, when the signal at the first output terminal OUT1 is a high-level signal, the first isolation circuit 40 can disconnect the electrical connection between the pull-up node PU and the first plate of the first capacitor C1, preventing the pull-up node PU from rising under the action of the first capacitor C1 and reducing the power consumption of the shift register.

[0119] For example, the first clock signal terminal CK1 is electrically connected to the first isolation control terminal S1. This allows both the first clock signal terminal CK1 and the first isolation control terminal S1 to be high-level signals simultaneously, and reduces the number of clock signal lines in the non-display area, thereby reducing the width of the bezel.

[0120] Figure 13 is a partial structural diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 13, the first isolation circuit 40 may include a first isolation transistor T17-1. The first terminal of the first isolation transistor T17-1 is electrically connected to the pull-up node PU, the second terminal of the first isolation transistor T17-1 is electrically connected to the first output circuit 20, and the gate of the first isolation transistor T17-1 is electrically connected to the first isolation control terminal S1.

[0121] For example, the second terminal of the first isolation transistor T17-1 is electrically connected to the first plate of the first capacitor C1.

[0122] Referring again to Figures 12 and 13, the shift register may also include a second isolation circuit 50, which is electrically connected between the pull-up node PU and the second output circuit 30, and is also electrically connected to the second isolation control terminal S2.

[0123] For example, the second isolation circuit 50 is electrically connected to the first plate of the second capacitor C2.

[0124] The second isolation circuit 50 is configured to disconnect the electrical connection between the pull-up node PU and the second output circuit 30 under the signal control of the second isolation control terminal S2. For example, when the second isolation control terminal S2 is a high-level signal, the second isolation circuit 50 disconnects the electrical connection between the pull-up node PU and the first plate of the second capacitor C2.

[0125] In some implementations, the second isolation circuit 50 is configured to disconnect the electrical connection between the pull-up node PU and the second output circuit 30 when the second output terminal OUT2 is a high-level signal.

[0126] In this way, when the signal at the second output terminal OUT2 is a high-level signal, the second isolation circuit 50 can disconnect the electrical connection between the pull-up node PU and the first plate of the second capacitor C2, preventing the pull-up node PU from rising under the action of the second capacitor C2, thus reducing the power consumption of the shift register.

[0127] For example, the second clock signal terminal CK2 is electrically connected to the second isolation control terminal S2. This allows both the second clock signal terminal CK2 and the second isolation control terminal S2 to be high-level signals simultaneously, and reduces the number of clock signal lines in the non-display area, thereby reducing the width of the bezel.

[0128] As shown in Figure 13, the second isolation circuit 50 may include a second isolation transistor T17-2. The first terminal of the second isolation transistor T17-2 is electrically connected to the pull-up node PU, the second terminal of the second isolation transistor T17-2 is electrically connected to the second output circuit 30, and the gate of the second isolation transistor T17-2 is electrically connected to the second isolation control terminal S2.

[0129] For example, the second terminal of the second isolation transistor T17-2 is electrically connected to the first plate of the second capacitor C2.

[0130] Furthermore, when the shift register includes a first isolation circuit 40, a second isolation circuit 50, and a cascade circuit 60, it can improve the display uniformity of two adjacent sub-pixel rows. Specifically, when the cascade signal terminal CKc is electrically connected to the second clock signal terminal CK2, both CKc and CK2 are high. At this time, the pull-up node PU rises under the combined action of the cascade output terminal Cout and the second output terminal OUT2. However, when the first clock signal terminal CK1 is high, the pull-up node PU rises only under the action of the first output terminal OUT1, resulting in inconsistent levels of the pull-up node PU in the two time periods, thus causing poor display uniformity of two adjacent sub-pixel rows. By simultaneously setting the first isolation circuit 40 and the second isolation circuit 50, the level difference of the pull-up node PU is eliminated, improving display uniformity.

[0131] The first isolation control terminal S1 and the second isolation control terminal S2 can be electrically connected. For example, the first isolation control terminal S1 and the second isolation control terminal S2 can be electrically connected to the same clock signal line, which can reduce the number of clock signal lines, thereby further reducing the area of ​​the non-display area and achieving a narrow bezel.

[0132] The clock signal line electrically connected to the first isolation control terminal S1 and the second isolation control terminal S2 can be a separately configured clock signal line. The signal in this separately configured clock signal line satisfies the following: when the signal at the first output terminal OUT1 is a high-level signal, the signal in this clock signal line is a high-level signal, and when the signal at the second output terminal OUT2 is a high-level signal, the signal in this clock signal line is also a high-level signal.

[0133] Of course, the first isolation control terminal S1 and the second isolation control terminal S2 can also be disconnected. In this case, the signals of the first isolation control terminal S1 and the second isolation control terminal S2 can be the same or different.

[0134] The clock signal line electrically connected to the first isolation control terminal S1 or the second isolation control terminal S2 can also be a clock signal line electrically connected to the first clock signal terminal CK1 or the second clock signal terminal CK2 of other shift registers. This reduces the number of clock signal lines in the non-display area, thereby reducing the bezel width of the display panel.

[0135] Figure 14 is a schematic diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 14, when the shift register includes a cascaded circuit 60, the shift register also includes a third isolation circuit 80. The third isolation circuit 80 is electrically connected between the pull-up node PU and the cascaded circuit 60, and the third isolation circuit 80 is electrically connected to the fifth clock signal terminal.

[0136] For example, the third isolation circuit 80 is electrically connected to the first plate of the third capacitor C3.

[0137] The third isolation circuit 80 is configured to disconnect the electrical connection between the pull-up node PU and the cascaded circuit 60 under the signal control of the third isolation control terminal S3. For example, when the third isolation control terminal S3 is a high-level signal, the third isolation circuit 80 disconnects the electrical connection between the pull-up node PU and the first plate of the third capacitor C3.

[0138] In some implementations, the third isolation circuit 80 is configured to disconnect the electrical connection between the pull-up node PU and the cascade circuit 60 when the cascade output Cout is a high-level signal.

[0139] In this way, when the signal at the cascaded output terminal Cout is a high-level signal, the third isolation circuit 80 can disconnect the electrical connection between the pull-up node PU and the first plate of the third capacitor C3, preventing the pull-up node PU from rising under the action of the third capacitor C3 and reducing the power consumption of the shift register.

[0140] For example, the first clock signal terminal CK1 or the second clock signal terminal CK2 is electrically connected to the third isolation control terminal S3. This reduces the number of clock signal lines in the non-display area, thereby reducing the width of the bezel.

[0141] The third isolation control terminal S3 can be electrically connected to the first isolation control terminal S1 and the second isolation control terminal S2. This reduces the number of clock signal lines in the non-display area, thereby reducing the width of the bezel.

[0142] Figure 15 is a partial structural diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 15, the third isolation circuit 80 may include a third isolation transistor T17-3. The first terminal of the third isolation transistor T17-3 is electrically connected to the pull-up node PU, the second terminal of the third isolation transistor T17-3 is electrically connected to the cascaded circuit 60, and the gate of the third isolation transistor T17-3 is electrically connected to the third isolation control terminal S3.

[0143] For example, the second terminal of the third isolation transistor T17-3 is electrically connected to the first plate of the third capacitor C3.

[0144] Figure 16 is a circuit diagram of another shift register provided in an embodiment of this disclosure, and Figure 17 is a timing signal diagram of the shift register shown in Figure 16. As shown in Figures 16 and 17, after simultaneously setting the first isolation circuit 40, the second isolation circuit 50, and the third isolation circuit 80, the level of the pull-up node PU will not be pulled high, which helps to reduce the power consumption of the shift register and improve the display uniformity of two adjacent sub-pixel rows.

[0145] Figure 19 is a timing signal diagram of the shift register shown in Figure 16. As shown in Figure 19, the first isolation control terminal S1, the second isolation control terminal S2, and the third isolation control terminal S3 of the nth shift register can be electrically connected to a separately configured clock signal line, and the signal in this clock signal line is shown as CKc in Figure 19; the first isolation control terminal S1, the second isolation control terminal S2, and the third isolation control terminal S3 of the (n+1)th shift register can be electrically connected to a separately configured clock signal line, and the signal in this clock signal line is shown as CBc in Figure 19.

[0146] Figure 20 is a circuit diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 20, when the shift register does not have a cascaded circuit 60, a first isolation circuit 40 and a second isolation circuit 50 can also be provided.

[0147] Figure 21 is a circuit schematic of another shift register provided in an embodiment of this disclosure. Compared to the shift register shown in Figure 16, transistors T5e, T6e, T7e, T8e, T12e, T13e, T13e-2, and T16e are omitted from the shift register shown in Figure 21. This reduces the number of transistors in the shift register, thereby reducing the area of ​​the non-display area NA. At this time, under Stress conditions of 99%, the threshold voltage Vth offset of the transistors still does not exceed the design threshold (e.g., 0.1-3V).

[0148] When the threshold voltage Vth of a transistor is less than 0V, the voltage between the gate and source of the transistor is Vgs = 0V and Id is relatively large. In severe cases, this can easily cause the shift register to fail to shift normally. In milder cases, the leakage current of the shift register is large and the power consumption increases.

[0149] Figure 22 is a circuit diagram of another shift register provided in an embodiment of this disclosure. As shown in Figure 22, to improve the above-mentioned defects, at least some of the transistors in the shift register adopt a dual-gate structure, that is, two transistors are connected in series, and the gates of the two transistors connected in series are electrically connected. This can reduce node leakage current, thereby increasing the negative bias margin of the threshold voltage Vth, and can also reduce power consumption.

[0150] For example, transistors T1, T2, T8o, T15, and T17-3 in Figure 16 are replaced with a dual-gate structure. Since the pull-up node PU has a high level during the output stage, replacing T1, T2, T8o, T15, and T17-3 with a dual-gate structure can reduce leakage current.

[0151] It should be noted that, except for T1, T2, T8o, T15, and T17-3, some or all of the other transistors in Figure 16 can be replaced with a dual-gate structure.

[0152] The shift register shown in Figure 22 includes multiple output terminals, allowing one shift register to provide scan signals to multiple sub-pixel rows. This reduces the number of shift registers and increases the space available for each shift register while keeping the area of ​​the non-display area unchanged. This allows some or all transistors in the shift register to be replaced with a dual-gate structure, reducing the power consumption of the display panel and improving its reliability. In other words, without changing the area of ​​the non-display area NA, the power consumption of the display panel is reduced, and the reliability of the display panel is improved.

[0153] Figure 23 is a circuit diagram of another shift register provided in an embodiment of this disclosure. The difference between the shift register shown in Figure 23 and the shift register shown in Figure 22 is that the shift register shown in Figure 23 does not have the first isolation circuit 40, the second isolation circuit 50, and the third isolation circuit 80. When the first output terminal OUT1, the second output terminal OUT2, or the cascaded output terminal Cout outputs a high-level signal, the pull-up node PU will increase its level under the action of the capacitor, resulting in increased leakage current.

[0154] Therefore, referring to Figure 23, the input circuit 10 includes a first input transistor T1a and a second input transistor T1b. The first terminal of the first input transistor T1a is electrically connected to the input terminal IN, the second terminal of the first input transistor T1a is electrically connected to the first terminal of the second input transistor T1b, the second terminal of the second input transistor T1b is electrically connected to the pull-up node PU, and the gates of the first input transistor T1a and the second input transistor T1b are electrically connected to the input terminal IN. The shift register also includes a leakage protection circuit 80, which is electrically connected to the first voltage terminal VDD, the leakage protection control terminal, and the second terminal of the first input transistor T1a. The leakage protection circuit 80 is configured to write the signal of the first voltage terminal VDD into the second terminal of the first input transistor T1a under the signal control of the leakage protection control terminal.

[0155] For example, continuing to refer to Figure 23, the leakage protection circuit 80 includes transistors T17a and T17b, which are dual-gate structures. Their gates are electrically connected to the cascaded output Cout or Gout(n-1) of the n / 2th shift register or the pull-up node PU. One gate is electrically connected to the first voltage terminal VDD, and the other gate is connected between transistors T1a and T1b. When the pull-up node PU's voltage level increases under the influence of the capacitor, the voltage difference between the pull-up node PU and the intermediate node of the dual-gate structure decreases, reducing the leakage voltage drop of the pull-up node PU, especially when the threshold voltage Vth < 0.

[0156] Of course, the other terminal of transistor T17b can also be connected to one or more of the following locations: between T2a and T2b, between T8oa and T8ob, between T8ea and T8eb, and between T15a and T15b.

[0157] Figure 24 is a circuit diagram of a first shift register provided in an embodiment of this disclosure, and Figure 25 is a circuit diagram of a second shift register provided in an embodiment of this disclosure. The shift registers shown in Figures 24 and 25 are two cascaded shift registers.

[0158] Compared to the shift register shown in Figure 23, the second noise reduction circuit 92 is removed from the first shift register shown in Figure 24, that is, transistors T5ea, T5eb, T7ea, T7eb, T6ea, and T6eb are removed, reducing the number of transistors in the shift register and thus reducing the area of ​​the non-display area; compared to the shift register shown in Figure 23, the first noise reduction circuit 91 is removed from the second shift register shown in Figure 25, that is, transistors T5oa, T5ob, T7oa, T7ob, T6oa, and T6ob are removed, reducing the number of transistors in the shift register and thus reducing the area of ​​the non-display area.

[0159] In Figure 24, the pull-down node PDe of the first shift register is electrically connected to the pull-down node Pde of the second shift register in Figure 25, and the pull-down node PDo of the second shift register in Figure 25 is electrically connected to the pull-down node Pdo of the first shift register in Figure 24.

[0160] The shift registers shown in Figure 24 and Figure 25 share the first and second noise reduction circuits, which reduces the number of the first and second noise reduction circuits in the scan drive circuit, thereby reducing the area of ​​the non-display area.

[0161] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, include: An input circuit is electrically connected to an input terminal and a pull-up node, and the input circuit is configured to write the signal from the input terminal to the pull-up node. A first output circuit is electrically connected to the pull-up node, the first clock signal terminal, and the first output terminal, respectively. The first output circuit is configured to write the signal of the first clock signal terminal to the first output terminal under the signal control of the pull-up node. The second output circuit is electrically connected to the pull-up node, the second clock signal terminal, and the second output terminal, respectively. The second output circuit is configured to write the signal of the second clock signal terminal to the second output terminal under the signal control of the pull-up node.

2. The shift register according to claim 1, wherein, The shift register also includes: A first isolation circuit is electrically connected between the pull-up node and the first output circuit, and is also electrically connected to a first isolation control terminal. The first isolation circuit is configured to disconnect the electrical connection between the pull-up node and the first output circuit under the signal control of the first isolation control terminal.

3. The shift register according to claim 2, wherein, The shift register also includes: A second isolation circuit is electrically connected between the pull-up node and the second output circuit, and is also electrically connected to a second isolation control terminal. The second isolation circuit is configured to disconnect the electrical connection between the pull-up node and the second output circuit under the signal control of the second isolation control terminal.

4. The shift register according to claim 3, wherein, The first isolation control terminal is electrically connected to the second isolation control terminal.

5. The shift register according to claim 3, wherein, The first isolation circuit is configured to disconnect the electrical connection between the pull-up node and the first output circuit when the first output terminal is a high-level signal; and / or, the second isolation circuit is configured to disconnect the electrical connection between the pull-up node and the second output circuit when the second output terminal is a high-level signal.

6. The shift register according to claim 3, wherein, The first isolation circuit includes a first isolation transistor, the first terminal of which is electrically connected to the pull-up node, the second terminal of which is electrically connected to the first output circuit, and the gate of which is electrically connected to the first isolation control terminal; and / or, The second isolation circuit includes a second isolation transistor, the first terminal of which is electrically connected to the pull-up node, the second terminal of which is electrically connected to the second output circuit, and the gate of which is electrically connected to the second isolation control terminal.

7. The shift register according to any one of claims 1 to 6, wherein, The shift register also includes: A cascaded circuit is electrically connected to a cascaded signal terminal, a pull-up node, and a cascaded output terminal, respectively. The cascaded circuit is configured to write the signal from the cascaded signal terminal to the cascaded output terminal under the signal control of the pull-up node.

8. The shift register according to claim 7, wherein, The shift register also includes: A third isolation circuit is electrically connected between the pull-up node and the cascaded circuit, and is also electrically connected to a third isolation control terminal. The third isolation circuit is configured to disconnect the electrical connection between the pull-up node and the cascaded circuit under the signal control of the third isolation control terminal.

9. The shift register according to claim 8, wherein, The third isolation control terminal is electrically connected to the first isolation control terminal and the second isolation control terminal.

10. The shift register according to claim 8, wherein, The third isolation circuit includes a third isolation transistor, the first terminal of which is electrically connected to the pull-up node, the second terminal of which is electrically connected to the cascaded circuit, and the gate of which is electrically connected to the third isolation control terminal.

11. The shift register according to claim 1, wherein, At least some of the transistors in the shift register are dual-gate structures.

12. The shift register according to claim 11, wherein, The input circuit includes a first input transistor and a second input transistor. The first terminal of the first input transistor is electrically connected to the input terminal, the second terminal of the first input transistor is electrically connected to the first terminal of the second input transistor, the second terminal of the second input transistor is electrically connected to the pull-up node, and the gates of the first and second input transistors are electrically connected to the input terminal. The shift register further includes a leakage protection circuit, which is electrically connected to a first voltage terminal, a leakage protection control terminal, and the second electrode of the first input transistor. The leakage protection circuit is configured to write the signal from the first voltage terminal to the second electrode of the first input transistor under the signal control of the leakage protection control terminal.

13. The shift register according to claim 1, wherein, The shift register further includes a reset circuit, which is electrically connected to a first pull-down node, a second pull-down node, a first output terminal, a second output terminal, and a second voltage terminal, respectively. The reset circuit is configured to write the signal of the second voltage terminal to the first output terminal or the second output terminal under the signal control of the first pull-down node or the second pull-down node.

14. A scanning drive circuit, characterized in that, It includes a plurality of shift registers as described in any one of claims 1 to 13, wherein the plurality of shift registers are cascaded.

15. The scanning drive circuit according to claim 14, wherein, The plurality of shift registers includes a first shift register and a second shift register, the first shift register and the second shift register are cascaded, a first pull-down node of the first shift register is electrically connected to a first pull-down node of the second shift register, and a second pull-down node of the first shift register is electrically connected to a second pull-down node of the second shift register. The first shift register further includes a first noise reduction circuit, which is electrically connected to the first pull-down node. The second shift register further includes a second noise reduction circuit, which is electrically connected to the second pull-down node.

16. A display panel, characterized in that, It includes a shift register as described in any one of claims 1 to 13, or a scan drive circuit as described in claims 14 and 15.

Images