Data processing method, apparatus and system

Abstract

Disclosed in the embodiments of the present application are a data processing method, an apparatus and a system. The method specifically comprises: first acquiring p first data streams subjected to RS coding; then separately performing first data processing comprising FEC coding and first interleaving on the p first data streams, so as to obtain m second data streams, m being an integer greater than or equal to p; and further, performing second data processing comprising second interleaving, DP-16QAM symbol mapping and framing on the m second data streams, so as to obtain q first dual-polarization symbol streams, q being an integer greater than 1, and each first dual-polarization symbol stream comprising a symbol stream in a first polarization direction and a symbol stream in a second polarization direction. The method using the solution of cascaded FEC coding and multi-wavelength transmission is suitable for intra-data center transmission scenarios where the transmission rate is higher than 800 Gbps, and has the characteristics of low power consumption and low delay.

Description

Data processing method, device and system

[0001] This application claims priority to Chinese Patent Application No. 202410508847.4, filed with the State Intellectual Property Office of China on April 25, 2024, entitled “A Data Processing Method, Apparatus and System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Coherent optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and to maintain long-distance transmission, coherent optical communication systems typically employ efficient forward error correction (FEC) codes to combat optical impairments during optical transmission, ensuring a sufficiently low bit error rate over long distances.

[0004] Currently, some optical transmission network architectures support transmission rates of 400Gbps and 800Gbps. At a transmission rate of 400Gbps, the required baud rate using dual-polarization 16QAM (DP-16QAM) modulation is typically around 60Gbaud. At a transmission rate of 800Gbps, the required baud rate using DP-16QAM modulation is typically around 120Gbaud. With the growth of services, the requirements for transmission rates in internal interconnection scenarios are becoming increasingly higher. For example, transmission rates of 1.2Tbps and 1.6Tbps, using DP-16QAM modulation and single-wavelength transmission, correspond to baud rates of approximately 180Gbaud and 240Gbaud, respectively. At the same transmission rate, lower-order modulation, such as Quadrature Phase Shift Keying (QPSK), requires a higher baud rate; higher-order modulation, such as DP-32QAM or DP-64QAM, while requiring a lower baud rate, limits the transmission distance. Higher transmission rates in optical transmission networks typically require higher baud rates, resulting in higher power consumption for the devices. Currently, there are no low-power devices with baud rates exceeding 140 Gbaud. For data center interconnects, low power consumption and low latency are usually required. Therefore, current solutions are unsuitable for interconnect transmission scenarios with rates above 800 Gbps (e.g., 1.2 Tbps, 1.6 Tbps, 3.2 Tbps), a problem that urgently needs to be solved in the future. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system. Employing a cascaded FEC coding and multi-wavelength transmission scheme, it is suitable for data center internal transmission scenarios with transmission rates exceeding 800Gbps, and features low power consumption and low latency.

[0006] Firstly, embodiments of this application provide a data processing method. Specifically, firstly, p first data streams encoded using Reed-Solomon (RS) are acquired, where p is a positive integer multiple of 4 and a power of 2. Each first data stream contains a... RS The adjacent RS symbols are respectively from a RS One RS codeword, a RSThe first data stream is a power of 2 greater than or equal to 4. Then, the p first data streams are subjected to first data processing including FEC encoding and first interleaving to obtain m second data streams, where m is an integer greater than or equal to p. Next, the m second data streams are subjected to second data processing including second interleaving, dual-polarization 16-ary Quadrature Amplitude Modulation (DP-16QAM) symbol mapping, and framing to obtain q first dual-polarization symbol streams, where q is an integer greater than 1. The first dual-polarization symbol streams include symbol streams in the first polarization direction and symbol streams in the second polarization direction.

[0007] As an example, q first dual-polarization symbol streams can be carried on q optical signals, each with a different wavelength, effectively transmitting q first dual-polarization symbol streams through q wavelength channels. As another example, q first dual-polarization symbol streams can be transmitted through q optical fibers, equivalent to transmitting q first dual-polarization symbol streams through q physical channels (optical fibers). This transmission via different wavelength channels or different optical fibers eliminates the need for devices with higher baud rates, resulting in lower power consumption. Since the received p first data streams, after RS ​​encoding, are subjected to FEC encoding (also known as internal code encoding) without KP4 decoding, the overall encoding scheme exhibits low latency. Therefore, it maintains low power consumption and low latency even in scenarios with transmission rates exceeding 800Gbps.

[0008] Furthermore, in this embodiment, since a second interleaving is introduced before DP-16QAM symbol mapping and framing, it is beneficial to reduce the impact of polarization determined loss (PDL) on the X and Y polarization directions, has strong anti-burst capability, and can be applied to a wide range of transmission scenarios, especially suitable for actual coherent transmission scenarios where the channel has colored noise.

[0009] In some possible implementations, a RS =4 or 8.

[0010] In some possible implementations, performing second data processing on m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain q first dual-polarization symbol streams includes one of the following methods, enriching the implementation options of this scheme. It should be understood that the implementations provided herein all employ a combination of second interleaving with m second data streams.

[0011] Method 1: Perform second interleaving and DP-16QAM symbol mapping on m second data streams to obtain q second dual-polarized symbol streams. Insert the target symbol sequence into each of the q second dual-polarized symbol streams to obtain q first dual-polarized symbol streams. Method 2: Perform second interleaving on m second data streams to obtain q third data streams. Insert the target bit sequence into each of the q third data streams to obtain q fourth data streams. Perform DP-16QAM symbol mapping on each of the q fourth data streams to obtain q first dual-polarized symbol streams. The target bit sequence is then processed through DP-16QAM symbol mapping to obtain the target symbol sequence. Method 3: Perform a second interleaving on m second data streams to obtain 2×q third data streams. Insert the target bit sequence into each of the 2×q third data streams to obtain 2×q fourth data streams. Perform DP-16QAM symbol mapping on every two fourth data streams to obtain one first dual-polarization symbol stream, thus obtaining q first dual-polarization symbol streams. The target bit sequence is obtained by DP-16QAM symbol mapping. Method 4: Perform a second interleaving on m second data streams to obtain 4×q third data streams. Insert the I component of the target bit sequence into 2×q of the 4×q third data streams respectively, and insert the Q component of the target bit sequence into the other 2×q of the 4×q third data streams respectively to obtain 4×q fourth data streams. Perform DP-16QAM symbol mapping on every 4 fourth data streams to obtain 1 first dual-polarization symbol stream, thus obtaining q first dual-polarization symbol streams. In this method, the I component of the target bit sequence is mapped by DP-16QAM to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is mapped by DP-16QAM to obtain the Q component of the target symbol sequence.

[0012] In some possible implementations, performing second data processing on m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain q first dual-polarization symbol streams includes: obtaining one first bit set from each second data stream to obtain m first bit sets, each first bit set including N bits, where N bits are obtained by FEC encoding K information bits. Performing second interleaving on the m first bit sets to obtain q second bit sets, each second bit set including... R bits, each second bit set includes R bits from one of the first bit sets. in, This indicates a round-down operation. This indicates a rounding up operation. DP-16QAM symbol mapping is performed on each second bit set to obtain the corresponding consecutive bits in the first dual-polarization symbol stream. A dual-polarization DP-16QAM symbol. As an example, N bits in each first bit set are evenly distributed among q second bit sets, meaning each second bit set includes N / q bits from one of the first bit sets. In other words, one codeword is obtained from each second data stream to obtain a total of m codewords, and these m codewords are combined for a second interleaving to shuffle the bit order. The bit data encoded by the inner code is carried more evenly across multiple symbol data streams, which helps improve the overall concatenated code's burst resistance.

[0013] In some possible implementations, performing second data processing on m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain q first dual-polarization symbol streams includes one of the following methods, enriching the implementation options of this scheme. It should be understood that the second interleaving provided herein can also be implemented through q mutually independent sub-interleaving modules, each sub-interleaving module being used to interleave m / q of the m second data streams.

[0014] Method 1: Perform a second interleaving and DP-16QAM symbol mapping on every m / q second data streams to obtain one second dual-polarized symbol stream, resulting in q second dual-polarized symbol streams. Insert the target symbol sequence into each of the q second dual-polarized symbol streams to obtain q first dual-polarized symbol streams. Method 2: Perform a second interleaving on every m / q second data streams to obtain one third data stream, resulting in q third data streams. Insert the target bit sequence into each of the q third data streams to obtain q fourth data streams. Perform DP-16QAM symbol mapping on each of the q fourth data streams to obtain q first dual-polarized symbol streams. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain the target symbol sequence. Method 3: Perform a second interleaving on every m / q second data streams in the m second data streams to obtain 2 third data streams, resulting in 2×q third data streams. Insert the target bit sequence into each of the 2×q third data streams to obtain 2×q fourth data streams. Perform DP-16QAM symbol mapping on every 2 fourth data streams in the 2×q fourth data streams to obtain 1 first dual-polarization symbol stream, resulting in q first dual-polarization symbol streams. The target bit sequence is obtained by DP-16QAM symbol mapping to obtain the target symbol sequence. Method 4: Perform a second interleaving on every m / q second data streams from the m second data streams to obtain 4 third data streams, resulting in 4×q third data streams. Insert the I component of the target bit sequence into 2×q of the 4×q third data streams respectively, and insert the Q component of the target bit sequence into the other 2×q of the 4×q third data streams respectively to obtain 4×q fourth data streams. Perform DP-16QAM symbol mapping on every 4 fourth data streams from the 4×q fourth data streams to obtain 1 first dual-polarization symbol stream, resulting in q first dual-polarization symbol streams. Here, the I component of the target bit sequence is obtained by DP-16QAM symbol mapping to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is obtained by DP-16QAM symbol mapping to obtain the Q component of the target symbol sequence.

[0015] In some possible implementations, performing second data processing on m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain q first dual-polarization symbol streams includes: obtaining one first bit set from each of the m / q second data streams to obtain m / q first bit sets, each first bit set comprising N bits, where N bits include K information bits and NK parity bits from a codeword encoded by FEC. Performing second interleaving on the m / q first bit sets to obtain one second bit set, the second bit set comprising... One bit. Perform DP-16QAM symbol mapping on the second bit set to obtain a continuous sequence of bits in the first dual-polarization symbol stream. This involves a dual-polarization DP-16QAM symbol. In this scenario, based on q independent sub-interleaving modules for the second interleaving, m second data streams are divided into q groups, each group containing m / q second data streams. The m / q second data streams from each group are input to a corresponding sub-interleaving module for second interleaving to shuffle the bit order, thereby improving the overall concatenated code's burst resistance. It should be understood that using q independent sub-interleaving modules for the second interleaving helps reduce the complexity of the interleaving process, making the implementation of a single interleaving operation simpler.

[0016] In some possible implementations, the first dual-polarization symbol stream includes multiple dual-polarization symbol sequences, and a target symbol sequence is included at a fixed position in each dual-polarization symbol sequence. The target symbol sequence includes at least one of the following: frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0017] In some possible implementations, in scenarios where m > p, performing first data processing, including FEC encoding and first interleaving, on each of the p first data streams to obtain m second data streams includes: distributing each of the p first data streams to obtain m / p first sub-data streams, and then performing FEC encoding and first interleaving on each of the m first sub-data streams to obtain m second data streams. In this implementation, the distribution operation allows for better scalability of the data processing method, enriching the implementation of this solution. In particular, when m = 32, this data processing method is well compatible with existing 800G coherent cascaded FEC processing architectures.

[0018] In some possible implementations, each first sub-data stream obtained by distributing from a first data stream comprises K consecutive bits from the first data stream, where K is a positive integer, and K is the number of information bits involved in FEC encoding. For example, this adapts to an FEC encoding scheme where N=128 and K=120. Another example is an FEC encoding scheme where N=176 and K=160. Alternatively, each first sub-data stream obtained by distributing from a first data stream comprises K0 consecutive bits from the first data stream, where K0 is an integer multiple of 40. For example, if K is not an integer multiple of 40... in, This indicates rounding down to the nearest integer. For example, K = 110. It can adapt to FEC encoding schemes with N=126 and K=110. Multiple granularities for distributing the first data stream are provided to facilitate adaptation to different FEC encoding schemes.

[0019] In some possible implementations, performing first data processing, including FEC encoding and first interleaving, on p first data streams to obtain m second data streams includes: performing convolutional interleaving on each of the p first data streams; distributing each of the p convolutionally interleaved first data streams to obtain m / p first sub-data streams; and performing FEC encoding and first interleaving on each of the m first sub-data streams to obtain m second data streams. It should be understood that performing convolutional interleaving is beneficial for improving the performance of the cascaded FEC transmission scheme.

[0020] In some possible implementations, performing first data processing, including FEC encoding and first interleaving, on p first data streams to obtain m second data streams includes: performing convolutional interleaving on each of the p first data streams, and then performing FEC encoding and first interleaving on the convolutionally interleaved p first data streams to obtain m second data streams. In this implementation, convolutional interleaving and distribution are decoupled, enriching the implementation methods of this solution.

[0021] In some possible implementations, convolutional interleaving of a first data stream includes: delaying bits from the first data stream according to r delay lines, where r is an integer greater than 1; each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units; the difference in the number of storage units between any two adjacent delay lines is Q; each storage unit stores d bits; the input bits are sequentially input to the r delay lines according to their indices; d bits are input to each delay line at a time and d bits are output from each delay line at a time; where Q and d are both integers greater than or equal to 1. It should be understood that the aforementioned storage units are also called delay elements. In some possible implementations, the delay line with the largest indices among the r delay lines may contain 0 storage units, or the delay line with the smallest indices among the r delay lines may contain 0 storage units. Various different implementations of convolutional interleaving are provided here to facilitate adaptation to various application scenarios.

[0022] In some possible implementations, d = a RS ×10.

[0023] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, or the delay line with the smallest index among the r delay lines includes 0 memory units, p = 8, r = 3, d = 40, Q ≥ 23. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 24. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 11. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 12. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 storage units, p=4, r=3, d=40, Q≥45. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=46 or 48. Or, the delay line with the smallest sequence number among the r delay lines includes 0 storage units, p=4, r=3, d=40, Q≥46. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=46 or 48. By selecting appropriate r, d, and Q parameters and convolutional interleaving implementation methods for different p values, any 12 consecutive RS symbols in the convolutionally interleaved data stream can come from 12 different RS codewords. This can be used in FEC encoding schemes such as N=128, K=120, allowing the FEC concatenation scheme including RS encoding and internal code encoding to achieve optimal performance. Alternatively, by selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaving, any 11 consecutive RS symbols in the convolutionally interleaved data stream can come from 11 different RS codewords. This can be used in FEC encoding methods with N=126 and K=110, which can make the FEC concatenation scheme including RS encoding and internal code encoding have optimal performance.

[0024] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 34. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 35. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 8, r = 4, d = 40, and Q ≥ 17. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 18, 20, or 24. Alternatively, the delay line with the smallest sequence number among the r delay lines may have 0 memory units, p=8, r=4, d=40, Q≥18. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=18, 20, or 24. Alternatively, the delay line with the largest sequence number among the r delay lines may have 0 memory units, or the delay line with the smallest sequence number among the r delay lines may have 0 memory units, p=16, r=4, d=40, Q≥9. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=10, 12, or 16. By selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaver, any 16 consecutive RS symbols in the convolutionally interleaved data stream can come from 16 different RS codewords. This can be used in FEC encoding schemes such as N=176, K=160, allowing the FEC concatenation scheme including RS encoding and internal code encoding to achieve optimal performance.

[0025] In some possible implementations, the number of information bits involved in FEC encoding is K, each codeword after FEC encoding includes N bits, and the NK parity bits in the codeword are obtained by FEC encoding the K information bits. The first interleaving is used to cyclically shift every K information bits in the first data stream. A specific implementation of the first interleaving is provided here. By using the first interleaving to shuffle the order of the K information bits, it is beneficial to improve the burst resistance of the overall concatenated code.

[0026] In some possible implementations, p = 4, and the first interleaving is used to cyclically shift every K information bits in the first data stream i. 4 bits, 0≤i<4 Satisfy one of the following:

[0027] Alternatively, p=8, the first interleaving is used to cyclically shift every K information bits in the first data stream i. 8 bits, 0≤i<8 Satisfy one of the following:

[0028] Alternatively, p=16, the first interleaving is used to cyclically shift every K information bits in the first data stream i. 16 bits, 0≤i<16 Satisfy one of the following:

[0029] In some possible implementations, the first data processing, including FEC encoding and first interleaving, of the first data stream includes one of the following methods: Method 1: Perform first interleaving on the first data stream, and then perform FEC encoding on the first interleaved first data stream. Method 2: Perform FEC encoding on the first data stream, and then perform first interleaving on the FEC-encoded first data stream. Method 3: Perform FEC encoding on K information bits in the first data stream to obtain NK parity bits, and then perform first interleaving on the K information bits to obtain N bits including NK parity bits and the first interleaved K information bits, where K is a positive integer and N > K. Multiple implementations of the first data processing are provided here, improving the scalability of this scheme.

[0030] In some possible implementations, each codeword after FEC encoding includes K information bits and NK parity bits, for a total of N bits; N=128, K=120, or N=126, K=110, or N=176, K=160, which allows for flexible selection of the FEC encoding method according to actual needs.

[0031] In some possible implementations, m = 4, 8, 16 or 32, thus allowing for compatibility with a variety of different scenarios.

[0032] In some possible implementations, every four adjacent RS symbols in each first data stream come from four RS codewords, resulting in better resistance to colored noise.

[0033] In some possible implementations, p first data streams are obtained by processing 16 fifth data streams through a symbol-multiplexed Physical Media Attachment (PMA) layer. These 16 fifth data streams are obtained by processing the service data to be transmitted through a Physical Coding Sublayer (PCS) including RS encoding. This provides a specific implementation method for processing the service data to be transmitted to obtain p first data streams, improving the completeness of this solution.

[0034] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing, and t signals are obtained from 16 fifth data streams through 16:t PMA processing, where t is a positive integer multiple of 4. This provides a scheme for obtaining p first data streams by performing two-step PMA processing on the data streams after PCS processing, which is well compatible with the application scenario shown in Figure 2. One step of the PMA processing is performed by the sending device, and the other step is performed by the sending processing module.

[0035] In some possible implementations, p first data streams are obtained by processing 16 fifth data streams through 16:p PMA. Here, a scheme is provided to obtain p first data streams by performing a one-step PMA process on the data streams after PCS processing, which is well compatible with the application scenario shown in Figure 3. This PMA process is performed by the originating device.

[0036] In some possible implementations, the p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing. That is, for the application scenario shown in Figure 2, the sending processing module obtains the p first data streams by performing t:p PMA processing based on symbol multiplexing on t signals from the sending device, thus improving the data processing flow of the sending processing module.

[0037] In some possible implementations, t = 8, p = 8; or t = 16, p = 8; or t = 4, p = 8; or t = 8, p = 16; or t = 16, p = 16; or t = 4, p = 16; or t = 4, p = 4; or t = 8, p = 4. Several possible implementations of the t:p PMA processing are given here, improving the scalability of this solution.

[0038] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding. This provides a method to directly obtain p first data streams by PCS processing of the service data to be sent, without requiring PMA processing, allowing for flexible selection of different implementation methods according to actual needs.

[0039] In some possible implementations, the data processing method provided in this application is applied to scenarios including Ethernet, optical transport networks, and space optical communication.

[0040] Secondly, embodiments of this application provide a data processing apparatus, which includes an acquisition unit and a processing unit. The acquisition unit is used to acquire p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is an integer power of 2. Each first data stream contains a... RS The adjacent RS symbols are respectively from aRS One RS codeword, a RS The integer power of 2 is greater than or equal to 4. The processing unit is used to: perform first data processing, including forward error correction (FEC) coding and first interleaving, on p first data streams to obtain m second data streams, where m is an integer greater than or equal to p; and perform second data processing, including second interleaving, DP-16QAM symbol mapping and framing, on the m second data streams to obtain q first dual-polarization symbol streams, where q is an integer greater than 1.

[0041] In some possible implementations, the processing unit is used to perform one of the following implementations: Method 1: Perform a second interleaving and DP-16QAM symbol mapping on m second data streams to obtain q second dual-polarized symbol streams; insert target symbol sequences into each of the q second dual-polarized symbol streams to obtain q first dual-polarized symbol streams. Method 2: Perform a second interleaving on m second data streams to obtain q third data streams; insert target bit sequences into each of the q third data streams to obtain q fourth data streams; perform DP-16QAM symbol mapping on each of the q fourth data streams to obtain q first dual-polarized symbol streams, wherein the target bit sequence is processed by DP-16QAM symbol mapping to obtain the target symbol sequence. Method 3: Perform a second interleaving on m second data streams to obtain 2×q third data streams. Insert the target bit sequence into each of the 2×q third data streams to obtain 2×q fourth data streams. Perform DP-16QAM symbol mapping on every two fourth data streams to obtain one first dual-polarization symbol stream, thus obtaining q first dual-polarization symbol streams. The target bit sequence is obtained by DP-16QAM symbol mapping. Method 4: Perform a second interleaving on m second data streams to obtain 4×q third data streams. Insert the I component of the target bit sequence into 2×q of the 4×q third data streams respectively, and insert the Q component of the target bit sequence into the other 2×q of the 4×q third data streams respectively to obtain 4×q fourth data streams. Perform DP-16QAM symbol mapping on every 4 fourth data streams to obtain 1 first dual-polarization symbol stream, thus obtaining q first dual-polarization symbol streams. In this method, the I component of the target bit sequence is mapped by DP-16QAM to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is mapped by DP-16QAM to obtain the Q component of the target symbol sequence.

[0042] In some possible implementations, a RS =4 or 8.

[0043] In some possible implementations, the processing unit is specifically configured to: acquire one first bit set from each second data stream to obtain m first bit sets, each first bit set comprising N bits, where N bits are obtained by FEC encoding K information bits. Perform a second interleaving on the m first bit sets to obtain q second bit sets, each second bit set comprising... R bits, each second bit set includes R bits from one of the first bit sets. in, This indicates a round-down operation. This indicates a rounding up operation. DP-16QAM symbol mapping is performed on each second bit set to obtain the corresponding consecutive bits in the first dual-polarization symbol stream. A dual-polarization DP-16QAM symbol.

[0044] In some possible implementations, the processing unit is used to perform one of the following implementations: Method 1: Perform a second interleaving and DP-16QAM symbol mapping on every m / q second data streams in the m second data streams to obtain one second dual-polarized symbol stream, resulting in q second dual-polarized symbol streams. Insert the target symbol sequence into each of the q second dual-polarized symbol streams to obtain q first dual-polarized symbol streams. Method 2: Perform a second interleaving on every m / q second data streams in the m second data streams to obtain one third data stream, resulting in q third data streams. Insert the target bit sequence into each of the q third data streams to obtain q fourth data streams. Perform DP-16QAM symbol mapping on each of the q fourth data streams to obtain q first dual-polarized symbol streams, wherein the target bit sequence is processed by DP-16QAM symbol mapping to obtain the target symbol sequence. Method 3: Perform a second interleaving on every m / q second data streams in the m second data streams to obtain 2 third data streams, resulting in 2×q third data streams. Insert the target bit sequence into each of the 2×q third data streams to obtain 2×q fourth data streams. Perform DP-16QAM symbol mapping on every 2 fourth data streams in the 2×q fourth data streams to obtain 1 first dual-polarization symbol stream, resulting in q first dual-polarization symbol streams. The target bit sequence is obtained by DP-16QAM symbol mapping to obtain the target symbol sequence. Method 4: Perform a second interleaving on every m / q second data streams from the m second data streams to obtain 4 third data streams, resulting in 4×q third data streams. Insert the I component of the target bit sequence into 2×q of the 4×q third data streams respectively, and insert the Q component of the target bit sequence into the other 2×q of the 4×q third data streams respectively to obtain 4×q fourth data streams. Perform DP-16QAM symbol mapping on every 4 fourth data streams from the 4×q fourth data streams to obtain 1 first dual-polarization symbol stream, resulting in q first dual-polarization symbol streams. Here, the I component of the target bit sequence is obtained by DP-16QAM symbol mapping to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is obtained by DP-16QAM symbol mapping to obtain the Q component of the target symbol sequence.

[0045] In some possible implementations, the processing unit is specifically configured to: obtain one first bit set from each of the m / q second data streams to obtain m / q first bit sets, each first bit set comprising N bits, wherein the N bits include K information bits and NK check bits from the FEC-encoded codeword. The m / q first bit sets are then subjected to a second interleaving to obtain one second bit set, the second bit set comprising... One bit. Perform DP-16QAM symbol mapping on the second bit set to obtain a continuous sequence of bits in the first dual-polarization symbol stream. A dual-polarization DP-16QAM symbol.

[0046] In some possible implementations, the first dual-polarization symbol stream includes multiple dual-polarization symbol sequences, and a target symbol sequence is included at a fixed position in each dual-polarization symbol sequence. The target symbol sequence includes at least one of the following: frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0047] In some possible implementations, in the scenario where m > p, the processing unit is specifically used to: distribute each of the p first data streams to obtain m / p first sub-data streams, to obtain m first sub-data streams, and perform FEC encoding and first interleaving on the m first sub-data streams respectively to obtain m second data streams.

[0048] In some possible implementations, each first sub-data stream obtained by distributing from a first data stream comprises K consecutive bits from the first data stream, where K is a positive integer, and K is the number of information bits involved in FEC encoding. For example, this adapts to an FEC encoding scheme where N=128 and K=120. Another example is an FEC encoding scheme where N=176 and K=160. Alternatively, each first sub-data stream obtained by distributing from a first data stream comprises K0 consecutive bits from the first data stream, where K0 is an integer multiple of 40. For example, if K is not an integer multiple of 40... in, This indicates rounding down to the nearest integer. For example, K = 110. It can adapt to FEC encoding schemes with N=126 and K=110. Multiple granularities for distributing the first data stream are provided to facilitate adaptation to different FEC encoding schemes.

[0049] In some possible implementations, the processing unit is specifically used to: perform convolutional interleaving on p first data streams respectively, distribute each of the p first data streams after convolutional interleaving to obtain m / p first sub-data streams, to obtain m first sub-data streams, and perform FEC encoding and first interleaving on the m first sub-data streams respectively to obtain m second data streams.

[0050] In some possible implementations, the processing unit is specifically used to: perform convolutional interleaving on p first data streams respectively, and perform FEC encoding and first interleaving on the p first data streams after convolutional interleaving to obtain m second data streams.

[0051] In some possible implementations, the processing unit is specifically used to: delay bits from the first data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store d bits, the input bits are sequentially input to the r delay lines according to the sequence number of the r delay lines, d bits are input to each delay line at a time and d bits are output from each delay line at a time, where Q and d are both integers greater than or equal to 1.

[0052] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 storage units, or the delay line with the smallest index among the r delay lines includes 0 storage units. This provides several different implementations of convolutional interleaving to facilitate adaptation to various application scenarios.

[0053] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, or the delay line with the smallest index among the r delay lines includes 0 memory units, p = 8, r = 3, d = 40, Q ≥ 23. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 24. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 11. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 12. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the largest sequence number among the r delay lines may have 0 memory units, p=4, r=3, d=40, Q≥45. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=46 or 48. Or, the delay line with the smallest sequence number among the r delay lines may have 0 memory units, p=4, r=3, d=40, Q≥46. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=46 or 48. By selecting appropriate r, d, and Q parameters and convolutional interleaving implementation methods for different p values, any 12 consecutive RS symbols in the convolutionally interleaved data stream can come from 12 different RS codewords, which can be used in FEC encoding schemes such as N=128, K=120. Alternatively, by selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaving, any 11 consecutive RS symbols in the convolutionally interleaved data stream can come from 11 different RS codewords, which can be used in FEC encoding methods such as N=126 and K=110.

[0054] In some possible implementations, d = a RS ×10.

[0055] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 34. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 35. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 8, r = 4, d = 40, and Q ≥ 17. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 18, 20, or 24. Alternatively, the delay line with the smallest sequence number among the r delay lines can have 0 memory units, p=8, r=4, d=40, Q≥18. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=18, 20, or 24. Alternatively, the delay line with the largest sequence number among the r delay lines can have 0 memory units, or the delay line with the smallest sequence number among the r delay lines can have 0 memory units, p=16, r=4, d=40, Q≥9. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=10, 12, or 16. By selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaver, any 16 consecutive RS symbols in the convolutionally interleaved data stream can come from 16 different RS codewords, which can be used in FEC encoding schemes such as N=176, K=160.

[0056] In some possible implementations, the number of information bits involved in FEC encoding is K, each codeword after FEC encoding includes N bits, the NK parity bits in the codeword are obtained by FEC encoding the K information bits, and the first interleaving is used to cyclically shift each K information bits in the first data stream.

[0057] In some possible implementations, p = 4, and the first interleaving is used to cyclically shift every K information bits in the first data stream i. 4 bits, 0≤i<4 Satisfy one of the following:

[0058] Alternatively, p=8, the first interleaving is used to cyclically shift every K information bits in the first data stream i. 8 bits, 0≤i<8 Satisfy one of the following:

[0059] Alternatively, p=16, the first interleaving is used to cyclically shift every K information bits in the first data stream i. 16 bits, 0≤i<16 Satisfy one of the following:

[0060] In some possible implementations, the processing unit is used to perform one of the following implementations: Method 1: Perform a first interleaving on the first data stream, and then perform FEC encoding on the first interleaved first data stream. Method 2: Perform FEC encoding on the first data stream, and then perform a first interleaving on the FEC-encoded first data stream. Method 3: Perform FEC encoding on K information bits in the first data stream to obtain NK parity bits, and then perform a first interleaving on the K information bits to obtain N bits including the NK parity bits and the K information bits after the first interleaving, where K is a positive integer and N > K.

[0061] In some possible implementations, each codeword after FEC encoding includes K information bits and NK parity bits, for a total of N bits; N=128, K=120, or N=126, K=110, or N=176, K=160, which allows for flexible selection of the FEC encoding method according to actual needs.

[0062] In some possible implementations, m = 4, 8, 16 or 32, thus allowing for compatibility with a variety of different scenarios.

[0063] In some possible implementations, every four adjacent RS symbols in each first data stream come from four RS codewords, resulting in better resistance to colored noise.

[0064] In some possible implementations, p first data streams are obtained by PMA processing based on symbol multiplexing from 16 fifth data streams, and the 16 fifth data streams are obtained by PCS processing including RS encoding from the service data to be sent.

[0065] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing, and t signals are obtained from 16 fifth data streams through 16:t PMA processing, where t is a positive integer multiple of 4. This provides a scheme for obtaining p first data streams by performing two-step PMA processing on the data streams after PCS processing, which is well compatible with the application scenario shown in Figure 2. One step of the PMA processing is performed by the sending device, and the other step is performed by the sending processing module.

[0066] In some possible implementations, p first data streams are obtained by processing 16 fifth data streams through 16:p PMA. Here, a scheme is provided to obtain p first data streams by performing a one-step PMA process on the data streams after PCS processing, which is well compatible with the application scenario shown in Figure 3. This PMA process is performed by the originating device.

[0067] In some possible implementations, the p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing. That is, for the application scenario shown in Figure 2, the sending processing module obtains the p first data streams by performing t:p PMA processing based on symbol multiplexing on t signals from the sending device, thus improving the data processing flow of the sending processing module.

[0068] In some possible implementations, t = 8, p = 8; or t = 16, p = 8; or t = 4, p = 8; or t = 8, p = 16; or t = 16, p = 16; or t = 4, p = 16; or t = 4, p = 4; or t = 8, p = 4.

[0069] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding.

[0070] In some possible implementations, the data processing apparatus provided in this application is used in scenarios including Ethernet, optical transport networks, and space optical communication.

[0071] Thirdly, embodiments of this application provide a chip for performing the method as described in any of the embodiments of the first aspect.

[0072] Fourthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0073] Fifthly, embodiments of this application provide a transmitting device. The transmitting device includes a host-side device and an optical module as described in any embodiment of the fourth aspect. The optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

[0074] Sixthly, embodiments of this application provide an apparatus. The apparatus includes a processor and an interface. The processor is used to execute the method described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The apparatus may be a router, switch, server, or optical transport network equipment, etc.

[0075] In a seventh aspect, embodiments of this application provide a communication system, which includes the transmitting device and receiving device described in the fifth aspect, wherein the transmitting device is used to transmit optical signals to the receiving device.

[0076] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any embodiment of the first aspect to be implemented.

[0077] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first aspect. Attached Figure Description

[0078] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0079] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0080] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0081] Figure 4 is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0082] Figure 5(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application;

[0083] Figure 5(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application;

[0084] Figure 6(a) is a schematic diagram of one embodiment of the present application that performs internal code encoding and first interleaving;

[0085] Figure 6(b) is a schematic diagram of another implementation of the internal code encoding and first interleaving in the embodiments of this application;

[0086] Figure 7(a) is a schematic diagram of one embodiment of the second data processing in this application;

[0087] Figure 7(b) is a schematic diagram of another implementation of the second data processing in the embodiments of this application;

[0088] Figure 7(c) is a schematic diagram of another implementation of the second data processing in the embodiments of this application;

[0089] Figure 7(d) is a schematic diagram of another implementation of the second data processing in the embodiments of this application;

[0090] Figure 8(a) is a schematic diagram of another implementation of the second data processing in the embodiments of this application;

[0091] Figure 8(b) is a schematic diagram of another implementation of the second data processing in the embodiments of this application;

[0092] Figure 8(c) is a schematic diagram of another implementation of the second data processing in the embodiments of this application;

[0093] Figure 8(d) is a schematic diagram of another implementation of the second data processing in the embodiments of this application;

[0094] Figure 9(a) is a data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0095] Figure 9(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0096] Figure 9(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0097] Figure 9(d) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0098] Figure 9(e) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0099] Figure 10(a) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0100] Figure 10(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0101] Figure 10(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0102] Figure 11(a) is a schematic diagram of one embodiment of the present application that performs the first data processing and the second data processing.

[0103] Figure 11(b) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0104] Figure 12(a) is a schematic diagram of another embodiment of the first data processing and the second data processing in this application;

[0105] Figure 12(b) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0106] Figure 13 is a schematic diagram of the format of a first data stream in an embodiment of this application;

[0107] Figure 14 is a schematic diagram of one embodiment of convolutional interleaving in this application;

[0108] Figure 15 is a schematic diagram of another implementation of convolutional interleaving in the embodiments of this application;

[0109] Figure 16 is a schematic diagram of one embodiment of the internal code encoding in this application;

[0110] Figure 17 is a schematic diagram of one embodiment of the first interlacing in this application;

[0111] Figure 18 is a schematic diagram of a DSP frame structure in an embodiment of this application;

[0112] Figure 19 is a schematic diagram of an embodiment of 1:E distribution of data streams in this application;

[0113] Figure 20 is a schematic diagram of a data processing device in an embodiment of this application;

[0114] Figure 21 is a schematic diagram of a structure of an optical module in an embodiment of this application;

[0115] Figure 22 is a schematic diagram of a transmitting device in an embodiment of this application. Detailed Implementation

[0116] This application provides a data processing method, apparatus, and system. Employing a cascaded FEC coding and multi-wavelength transmission scheme, it is suitable for data center internal transmission scenarios with transmission rates exceeding 800Gbps, and features low power consumption and low latency.

[0117] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0118] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device located at the transmitting end, and the receiving device 05 is also called a client device located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The transmitting end processing module 02 and the receiving end processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a coherent optical module). Furthermore, the transmitting end device 01, transmitting end processing module 02, channel transmission medium 03, receiving end processing module 04, and receiving end device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0119] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, during the data transmission process from the transmitting device 01 to the receiving device 05, the transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to the transmitting processing module 02. The transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits the data with both external and internal code encoding to the channel transmission medium 03. The channel transmission medium 03 transmits the data with both external and internal code encoding to the receiving processing module 04. The receiving processing module 04 performs internal code decoding on the data with both external and internal code encoding and transmits the internally decoded data to the receiving device 05. The receiving device 05 performs external code decoding on the data with internal code decoding.

[0120] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external code encoding described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Hamming code for internal code encoding. Alternatively, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal code encoding. A BCH code correcting a single error is equivalent to a Hamming code. Again, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Polar code for internal code encoding.

[0121] Figure 3 is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 3, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The data after external code encoding and internal code encoding is sent to the transmission medium 03. The receiving device 05 decodes the internal code and external code of the data received from the transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device or host device located at the transmitting end, and the receiving device 05 is also called a client chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device includes a client chip and an interface. The client chip is also called a host chip. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission, which is not limited here. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In this case, the transmitting device 01 can also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0122] As business grows, the requirements for transmission rates in data center interconnect scenarios (e.g., transmissions from 100m to 10km) are increasing. For example, transmission rates of 1.2Tbps, 1.6Tbps, and 3.2Tbps, using DP-16QAM modulation and single-wavelength transmission, correspond to baud rates of approximately 180Gbaud, 240Gbaud, and 480Gbaud, respectively. At the same transmission rate, using a lower-cost modulation, such as DP-QPSK, requires a higher baud rate; using higher-order modulations, such as DP-32QAM or DP-64QAM, while requiring a lower baud rate, limits the transmission distance. The higher the required transmission rate in optical transmission networks, the higher the required baud rate, and the higher the power consumption of the corresponding devices. Currently, there are no high-baud-rate, low-power devices exceeding 140Gbaud. For interconnect scenarios, low power consumption is typically required. Therefore, the DP-16QAM modulation and single-wavelength transmission scheme is not suitable for internal interconnection scenarios of 800Gbps and above (including 1.2Tbps, 1.6Tbps, etc.).

[0123] It should be understood that baud rate, or modulation rate, refers to the rate at which the effective data signal modulates the carrier wave, that is, the number of times the carrier modulation state changes per unit time. Baud rate represents the number of symbol transmissions per unit time; it is a measure of symbol transmission rate, expressed by the number of times the carrier modulation state changes per unit time. In short, baud rate refers to the number of symbols transmitted per unit time.

[0124] It should be noted that, as shown in Figures 2 and 3, in some specific applications, the data after internal encoding is further processed by DSP framing to add at least one of the following sequences: Frame Alignment Word Sequence (FAW Sequence), Training Symbol Sequence, Reserved Symbol Sequence, and Pilot Symbol Sequence, to obtain a dual-polarization symbol sequence to be transmitted. The dual-polarization symbol sequence containing multiple dual-polarization symbols is also called a DSP frame. Optionally, the reserved symbols can also be called fixed stuff (FS), and the frame synchronization symbols can also be called a multi-frame alignment signal (MFAS).

[0125] This application provides a multi-wavelength transmission scheme that differs from the single-wavelength transmission described above. Specifically, after DSP framing, it obtains q first dual-polarization symbol streams to be transmitted, where q is an integer greater than 1. In one possible implementation, the q first dual-polarization symbol streams can be carried on q optical signals, each with a different wavelength, equivalent to transmitting the q first dual-polarization symbol streams through q wavelength channels. In another possible implementation, the q first dual-polarization symbol streams can be transmitted through q optical fibers, equivalent to transmitting the q first dual-polarization symbol streams through q physical channels (optical fibers). The above-mentioned transmission through different wavelength channels or different optical fibers eliminates the need for devices with higher baud rates, resulting in lower device power consumption.

[0126] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0127] Figure 4 is a schematic flowchart of a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied to the sending end, for example, it can be implemented by the sending end processing module 02 shown in Figure 2 above, or by the sending end device 01 shown in Figure 3 above.

[0128] 101. Obtain p first data streams after RS ​​encoding.

[0129] In this embodiment, all p first data streams are data streams encoded with external codes. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS code is counted in units of symbols. The symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, that is, the codeword of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a in each first data stream RS The adjacent RS symbols are respectively from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2. In some specific scenarios, such as 1.6T Ethernet transmission, a RS =4, meaning that every 4 adjacent RS symbols in each first data stream come from 4 RS codewords, where p is an integer multiple of 4 and p is an integer power of 2.

[0130] 102. Perform first data processing, including internal code encoding and first interleaving, on p first data streams to obtain m second data streams.

[0131] Specifically, m is an integer greater than or equal to p, for example, p = 4, 8, or 16, m = 4, 8, 16, 32, or 64. If each first data stream is not distributed, then m = p; if each first data stream is distributed, then m > p. For example, with p = 8 first data streams, if each first data stream is not distributed, then after first data processing, m = 8 second data streams are obtained. With p = 4 first data streams, if each first data stream is not distributed, then after first data processing, m = 4 second data streams are obtained. With p = 4 first data streams, if each first data stream is distributed in a 1:2 ratio, then after first data processing, m = 8 second data streams are obtained. With p = 4 first data streams, if each first data stream is distributed in a 1:4 ratio, then after first data processing, m = 16 second data streams are obtained. Taking p = 4 first data streams as an example, if each first data stream is distributed in a 1:8 ratio, then m = 32 second data streams are obtained after first data processing. Taking p = 8 first data streams as an example, if each first data stream is distributed in a 1:2 ratio, then m = 16 second data streams are obtained after first data processing. Taking p = 8 first data streams as an example, if each first data stream is distributed in a 1:4 ratio, then m = 32 second data streams are obtained after first data processing.

[0132] The following uses a single data stream as an example to illustrate the internal code encoding method. Specifically, every K information bits in the first data stream are internally encoded to generate NK check bits, thus obtaining an internal codeword consisting of N bits, where 1 < K < N. For example, the internal code encoding uses a linear block code with N = 126 and K = 110, such as BCH(126, 110). Another example is using a linear block code with N = 128 and K = 120, such as BCH(128, 120). Yet another example is using a linear block code with N = 176 and K = 160, such as BCH(176, 160).

[0133] In some scenarios, considering that K is a multiple of 10, and that the K information bits in each inner codeword correspond to K / 10 outer code RS symbols, and that the corresponding K / 10 outer code RS symbols come from K / 10 different outer code RS codewords, the FEC concatenation scheme including RS encoding and inner code encoding can achieve optimal performance. For example, the inner code encoding uses BCH(126,110), where K=110 information bits in each inner codeword correspond to K / 10=11 outer code symbols, and that the corresponding K / 10=11 outer code symbols come from K / 10=11 different outer code RS codewords. Another example is the inner code encoding using a linear block code of N=128 and K=120, where K=120 information bits in each inner codeword correspond to K / 10=12 outer code symbols, and that the corresponding K / 10=12 outer code symbols come from K / 10=12 different outer code RS codewords. For example, the internal code encoding uses a linear block code with N=176 and K=160. Each internal codeword contains K=160 information bits, corresponding to K / 10=16 external code symbols, and these K / 10=16 external code symbols come from K / 10=16 different external code RS codewords. In some possible scenarios, to ensure that the K information bits in each internal codeword correspond to K / 10 different external code RS codewords, the first data stream undergoes convolutional interleaving before internal code encoding. The convolutional interleaving process will be described in detail below.

[0134] Specifically, the convolutional interleaver (CIE) performing the convolutional interleaving process includes r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage unit stores d bits, where d is an integer greater than or equal to 1. The bits in the input data stream of the CIE are sequentially input to the r delay lines according to their numbers, with d bits input and output from each delay line at a time. In some applications, the CIE outputs d bits at a time. In other applications, the CIE outputs r × d bits at a time, where r × d bits come from the r delay lines and include the d bits output from each delay line. The consecutive r × d bits in the output data stream of the CIE include the d bits output from each delay line.

[0135] It should be understood that the r delay lines each comprise 0, Q, 2Q, ..., (r-1)Q storage units, with each unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) of that delay line to the data stream. It should be understood that when a delay line contains no storage units, the delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0136] Figure 5(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application. As shown in Figure 5(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 5(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application. As shown in Figure 5(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units.

[0137] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0138] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving process in Figure 5(a) and the convolutional interleaving process in Figure 5(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5(a).

[0139] Typically, the number of bits stored in each memory cell is d = a. RS ×10. For example, in a 1.6T Ethernet transmission scenario, a RS =4, d=a RS ×10=40. It should be noted that each a in each of the first data streams... RS The adjacent RS symbols are respectively from a RS A different external code RS codeword, when a RS When the size of the outer code is larger, in order to achieve K / 10 different outer code RS codewords corresponding to K information bits in each inner codeword, the total number of bits in the storage units (also called delay units) of the convolutional interleaver is smaller, which means the latency and complexity of the convolutional interleaver are lower. The first interleaving included in the first data processing described above is described in detail below. The first interleaving is used to interleave every K information bits in the first data stream to shuffle their order, thereby improving the overall concatenated code's burst resistance performance. The first interleaving is also called bit shuffling or permutation. In some possible scenarios, the first interleaving is performed before the inner code encoding; that is, the first data stream is first interleaved, and then the first interleaved first data stream is encoded with the inner code.

[0140] Figure 6(a) is a schematic diagram of one embodiment of the internal code encoding and first interleaving in this application. As shown in Figure 6(a), in some other possible scenarios, the first interleaving is performed after the internal code encoding. That is, the first data stream is first internally encoded, and then the first data stream after internal code encoding is interleaved. Specifically, the K information bits are represented by U. First, internal code encoding is performed to obtain the corresponding internal code codeword (U,V). The NK parity bits generated by the internal code encoding are represented by V. Then, the K information bits U in the codeword (U,V) are first interleaved to obtain N bits (W,V), where W is the K bits obtained by first interleaving the K information bits U.

[0141] Figure 6(b) is a schematic diagram of another implementation of the internal code encoding and first interleaving in the embodiments of this application. As shown in Figure 6(b), in some possible scenarios, considering that the first interleaving is only used to interleave K information bits to shuffle their order, and the parity bits do not participate in the first interleaving, the first interleaving and internal code encoding can also be processed in parallel. Specifically, the K information bits are represented by U, and internal code encoding is performed to obtain the corresponding internal code codeword (U,V), where the NK parity bits generated by the internal code encoding are represented by V. After the first interleaving of the K information bits U in the codeword (U,V), N bits (W,V) are obtained, where the K bits obtained by the first interleaving of the K information bits U are represented by W. This is equivalent to the internal code encoding and the first interleaving being processed in parallel, that is, the K information bits U are internally encoded to obtain NK parity bits V, and the K bits W obtained by the first interleaving of the K information bits U are combined with V to obtain N bits (W,V) after internal code encoding and first interleaving. For simplicity, the N bits (W,V) are also called the codeword interleaving sequence.

[0142] In some specific applications, the first interleaving is used to perform a right circular shift of K information bits. bits, where the integer In other specific applications, the first interleaving is used to cyclically shift K information bits to the left by δ bits. In this case, the first interleaving is also called a circular shift. It should be noted that a right circular shift of K information bits... Each bit is equivalent to a left circular shift of K information bits. The following description of the circular shift operation uses a right circular shift as an example. Typically, the number of bits used in a right circular shift for the first interleaving of m data streams is... Not exactly the same, among which, The number of bits to circularly shift to the right of the i-th data stream out of m data streams. For example, K is an integer multiple of 10. It is an integer multiple of 10. The first interleaving can further improve the overall scheme's resistance to colored noise.

[0143] It should be noted that for scenarios where m > p, the aforementioned first data processing also includes a distribution operation. Each of the p first data streams is distributed to obtain m / p first sub-data streams, resulting in a total of p × (m / p) = m first sub-data streams. These m first sub-data streams are then subjected to internal code encoding and first interleaving to obtain m second data streams. It should be understood that distribution and convolutional interleaving are decoupled; for example, only convolutional interleaving can be performed; or only distribution can be performed; or convolutional interleaving can be performed first, followed by distribution.

[0144] In some possible scenarios, distribution is performed at a granularity of K bits. Taking a first data stream distributed into m / p first sub-data streams as an example, the (m / p) × K consecutive bits in the first data stream are distributed to the corresponding m / p sub-data streams. Each sub-data stream contains K consecutive bits from the (m / p) × K bits. In this case, the distribution is also called 1:(m / p)K-bit block distribution. The distribution operation can also be called de-muxing.

[0145] In other possible scenarios, distribution is performed in granularity of K0 bits. A consecutive (m / p) × K0 bits from one first data stream is distributed to its corresponding m / p first sub-data streams. Each first sub-data stream contains a consecutive K0 bits from the (m / p) × K0 bits, where K0 is an integer multiple of 40. As another example, K may not be an integer multiple of 40. in This indicates rounding down to the nearest integer. For example, K = 110.

[0146] 103. Perform second data processing on m second data streams, including second interleaving, dual polarization symbol mapping and framing, to obtain q first dual polarization symbol streams.

[0147] One inner codeword is obtained from each of the m second data streams, resulting in a total of m inner codewords with m×N bits. The second interleaving is used to shuffle the m×N bits of the m inner codewords, improving the burst resistance and colored noise resistance of the cascaded FEC coding scheme. The second interleaving can also be called codeword interleaving. As an example, the second interleaving here can be divided into two steps: first, a multiplexing operation to obtain the m inner codewords, and then interleaving the m inner codewords. As another example, the second interleaving here can be implemented in one step, achieving the same effect as the two-step implementation described above.

[0148] The multiple data streams after the second interleaving are subjected to dual-polarization symbol mapping and framing to obtain q first dual-polarization symbol streams to be transmitted. This framing can also be called DSP framing. The following description uses DP-16QAM symbol mapping as an example. DP-16QAM symbol mapping maps every 8 bits in the data stream after the second interleaving to one dual-polarization 16QAM (DP-16QAM) symbol. Each DP-16QAM symbol includes one 16QAM symbol in the X-polarization direction and one 16QAM symbol in the Y-polarization direction, where the X-polarization and Y-polarization directions are orthogonal. Furthermore, the 16QAM symbol in the X-polarization direction includes an in-phase component and a quadrature-phase component in the X-polarization direction, and the 16QAM symbol in the Y-polarization direction includes an in-phase component and a quadrature-phase component in the Y-polarization direction. It should be understood that dual-polarization symbol mapping is also called DP-16QAM symbol mapping, or 16QAM symbol mapping and polarization distribution. Specifically, the DP-16QAM symbol stream to be transmitted contains multiple DP-16QAM symbol sequences. DSP framing is used to insert target symbol sequences at fixed positions in each DP-16QAM symbol sequence. The DP-16QAM symbol sequence is also called a DSP frame.

[0149] The following describes several implementations of the second data processing, including second interleaving, dual polarization symbol mapping, and framing.

[0150] Figure 7(a) is a schematic diagram of one implementation of the second data processing in this application. As shown in Figure 7(a), DSP framing is performed after DP-16QAM symbol mapping. DSP framing is an operation performed on symbols. m second data streams undergo second interleaving and DP-16QAM symbol mapping to obtain q second dual-polarization symbol streams (also called pre-framing symbol streams). Next, DSP framing is performed on the q second dual-polarization symbol streams. Specifically, target symbol sequences are inserted into the symbol streams in the X-polarization and Y-polarization directions of each second dual-polarization symbol stream to obtain one first dual-polarization symbol stream to be transmitted, resulting in a total of q first dual-polarization symbol streams. The first dual-polarization symbol stream to be transmitted contains multiple DSP frames. It should be understood that the values ​​of the target symbol sequences inserted in the X-polarization direction and the target symbol sequences inserted in the Y-polarization direction may not be exactly the same; they are collectively referred to as target symbol sequences here without specific distinction. For example, the target symbol sequence includes at least one of the following: Frame Alignment Word Sequence (FAW Sequence), Training Symbol Sequence, Reserved Symbol Sequence, and Pilot Symbol Sequence. Optionally, reserved symbols may also be referred to as fixed stuff (FS), and frame alignment symbols may also be referred to as multi-frame alignment signal (MFAS).

[0151] In one possible scenario, the target symbol sequence is a pilot symbol sequence. In either the X-polarization or Y-polarization direction, each N in the DSP frame... G One symbol at a fixed position among the symbols is the pilot symbol. As an example, every N... G The first symbol in the set is the pilot symbol. Typically, N G =32, 64, 96, or 128, etc. In the X-polarization or Y-polarization direction, each pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j. Here, j is the imaginary unit of a complex number. That is, each pilot symbol uses one of the outermost four symbols in the 16QAM constellation diagram.

[0152] In some specific applications, the DSP framing operation adds one pilot symbol to every 63 DP-16QAM symbols in every 96 × 63 = 6048 pre-framing DP-16QAM symbols, resulting in 96 × 64 = 6144 DP-16QAM symbols to be transmitted. These 6144 DP-16QAM symbols are called a DSP frame. It should be understood that, in the X-polarization direction or the Y-polarization direction, every N... G =The first symbol in the 64 symbols is the pilot symbol. The 96×63=6048 pre-framing DP-16QAM symbols are obtained by mapping 6048×8=48384 bits in the data stream obtained after the second interleaving through DP-16QAM.

[0153] Figure 7(b) is a schematic diagram of another implementation of the second data processing in this application. As shown in Figure 7(b), DSP framing is performed before DP-16QAM symbol mapping, and DSP framing is performed on a bit-by-bit basis. Specifically, m second data streams are interleaved to obtain q third data streams, target bit sequences are inserted into the q third data streams to obtain q fourth data streams, and DP-16QAM symbol mapping is performed on the q fourth data streams to obtain q first dual-polarization symbol streams. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain the target symbol sequence.

[0154] Figure 7(c) is a schematic diagram of another implementation of the second data processing in this application. As shown in Figure 7(c), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on bits, and the data after the second interleaving is represented by 2×q data streams. Specifically, the m second data streams are interleaved to obtain 2×q third data streams. Target bit sequence X and target bit sequence Y are inserted into every two third data streams to obtain two fourth data streams, resulting in a total of 2×q fourth data streams. DP-16QAM symbol mapping is performed on every two fourth data streams to obtain one first dual-polarization symbol stream, thus obtaining a total of q first dual-polarization symbol streams. Specifically, the target bit sequence X is mapped by DP-16QAM to obtain a target symbol sequence in the X polarization direction, and the target bit sequence Y is mapped by DP-16QAM to obtain a target symbol sequence in the Y polarization direction.

[0155] Figure 7(d) is a schematic diagram of another implementation of the second data processing in this application. As shown in Figure 7(d), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on a bit-by-bit basis, and the data after the second interleaving is represented by 4×q data streams. Specifically, the m second data streams are second-interleaved to obtain 4×q third data streams, and the target bit sequence X is inserted into every 4 third data streams. I Target bit sequence X Q Target bit sequence Y I Target bit sequence Y Q Four fourth data streams are obtained, resulting in a total of 4×q fourth data streams. DP-16QAM symbol mapping is performed on every four fourth data streams to obtain one first dual-polarization symbol stream, thus obtaining a total of q first dual-polarization symbol streams. The target bit sequence X... I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the X polarization direction is obtained, and the target bit sequence X is obtained. Q After DP-16QAM symbol mapping, the Q component of the target symbol sequence in the X-polarization direction is obtained, and the target bit sequence Y is obtained. I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the Y polarization direction is obtained, and the target bit sequence Y... Q The Q component of the target symbol sequence in the Y polarization direction is obtained by DP-16QAM symbol mapping.

[0156] In some specific scenarios, the first dual-polarization symbol stream to be transmitted is described by two symbol streams: one is the symbol stream of the first dual-polarization symbol stream in the X-polarization direction, and the other is the symbol stream of the first dual-polarization symbol stream to be transmitted in the Y-polarization direction. In other specific scenarios, the first dual-polarization symbol stream is described by four data streams: the first is the data stream of the I-path component corresponding to the first dual-polarization symbol stream in the X-polarization direction (referred to as X...). I The second data stream is the Q-path data stream in the X-polarization direction corresponding to the first dual-polarization symbol stream (abbreviated as X). Q The third data stream is the data stream of the I-path component in the Y-polarization direction corresponding to the first dual-polarization symbol stream (abbreviated as Y). I The fourth data stream is the data stream of the Q-path component in the Y-polarization direction corresponding to the first dual-polarization symbol stream (abbreviated as Y). Q (Data flow).

[0157] It should be noted that Figures 7(a)-7(d) above all employ an implementation method that combines m second data streams for second interleaving. Based on this, a specific rule for second interleaving is further introduced. Specifically, one first bit set is obtained from each of the m second data streams to obtain m first bit sets, each first bit set including N bits from an internal codeword. Then, the m first bit sets are second-interleaved to obtain q second bit sets, each second bit set including... Each second bit set is then subjected to DP-16QAM symbol mapping to obtain a continuous sequence of bits in the first dual-polarization symbol stream. There are DP-16QAM symbols. Each second bit set includes R bits from one of the first bit sets. As an example, the N bits in each first bit set are evenly distributed among q second bit sets, meaning that each second bit set includes N / q bits from one of the first bit sets.

[0158] It should be noted that, in addition to the implementation method of combining m second data streams for second interleaving shown in Figures 7(a)-7(d) above, in some possible scenarios, the second interleaving can also be implemented by q mutually independent sub-interleaving modules. Each sub-interleaving module is used to interleave m / q second data streams out of m second data streams. The following describes this scenario in detail with several implementation methods.

[0159] Figure 8(a) is a schematic diagram of another implementation of the second data processing in this application. As shown in Figure 8(a), DSP framing is performed after DP-16QAM symbol mapping, and DSP framing is an operation performed on symbols. Specifically, for each m / q second data stream in the m second data streams, a second interleaving and DP-16QAM symbol mapping are performed to obtain one second dual-polarization symbol stream, thereby obtaining q second dual-polarization symbol streams. Then, DSP framing is performed on the q second dual-polarization symbol streams. Specifically, the target symbol sequence is inserted into the symbol streams in the X-polarization direction and the Y-polarization direction of each second dual-polarization symbol stream, thereby obtaining one first dual-polarization symbol stream to be transmitted, resulting in a total of q first dual-polarization symbol streams.

[0160] Figure 8(b) is a schematic diagram of another implementation of the second data processing in this application. As shown in Figure 8(b), DSP framing is performed before DP-16QAM symbol mapping, and DSP framing is performed on a bit-by-bit basis. Specifically, every m / q second data streams in m second data streams undergo a second interleaving to obtain one third data stream, thereby obtaining q third data streams. Target bit sequences are inserted into the q third data streams to obtain q fourth data streams, and DP-16QAM symbol mapping is performed on the q fourth data streams to obtain q first dual-polarization symbol streams. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain the target symbol sequence.

[0161] Figure 8(c) is a schematic diagram of another implementation of the second data processing in this application. As shown in Figure 8(c), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on bits, and the data after the second interleaving is represented by 2×q data streams. Specifically, every m / q second data streams in the m second data streams are second-interleaved to obtain 2 third data streams, thus obtaining 2×q third data streams. Target bit sequence X and target bit sequence Y are inserted into every 2 third data streams to obtain 2 fourth data streams, thus obtaining a total of 2×q fourth data streams. DP-16QAM symbol mapping is performed on every 2 fourth data streams to obtain 1 first dual-polarization symbol stream, thus obtaining a total of q first dual-polarization symbol streams. Specifically, the target bit sequence X is mapped by DP-16QAM to obtain the target symbol sequence in the X polarization direction, and the target bit sequence Y is mapped by DP-16QAM to obtain the target symbol sequence in the Y polarization direction.

[0162] Figure 8(d) is a schematic diagram of another implementation of the second data processing in this application. As shown in Figure 8(d), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on a bit-by-bit basis, and the data after the second interleaving is represented by 4×q data streams. Specifically, every m / q second data streams in the m second data streams are second-interleaved to obtain 4 third data streams, thus obtaining 4×q third data streams. The target bit sequence X is inserted into every 4 third data streams in the 4×q third data streams. I Target bit sequence X Q Target bit sequence Y I Target bit sequence Y QFour fourth data streams are obtained, resulting in a total of 4×q fourth data streams. DP-16QAM symbol mapping is performed on every four fourth data streams to obtain one first dual-polarization symbol stream, thus obtaining a total of q first dual-polarization symbol streams. The target bit sequence X... I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the X polarization direction is obtained, and the target bit sequence X is obtained. Q After DP-16QAM symbol mapping, the Q component of the target symbol sequence in the X-polarization direction is obtained, and the target bit sequence Y is obtained. I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the Y polarization direction is obtained, and the target bit sequence Y... Q The Q component of the target symbol sequence in the Y polarization direction is obtained by DP-16QAM symbol mapping.

[0163] It should be noted that the second interleaving shown in Figures 8(a)-8(d) is implemented through q independent sub-interleaving modules. Based on this, a specific rule for the second interleaving is further introduced. Specifically, taking m / q of the m second data streams as an example, one first bit set is obtained from each of the m / q second data streams to obtain m / q first bit sets. Each first bit set includes N bits from an internal codeword. Then, the m / q first bit sets are subjected to second interleaving to obtain a second bit set, which includes... One bit. Then, a dual-polarization symbol mapping is performed on the second bit set to obtain a continuous sequence of bits from the first dual-polarization symbol stream. There are DP-16QAM symbols. That is, in this scenario, based on q independent sub-interleaving modules of the second interleaving, m second data streams are divided into q groups, each group including m / q second data streams, and the m / q second data streams of each group are input to the corresponding sub-interleaving module for second interleaving.

[0164] Considering the service transmission of 1.6T Ethernet (1.6Terabit Ethernet, 1.6TE), the total bit rate of p first data streams is 106.25 × 2 × 8 = 1700 Gbits per second. It should also be understood that the bit rates in this application are nominal rates; in practical applications, the bit rate will have a certain offset range, for example, a ±V0 (ppm) error, where V0 can be 20, 25, 50, or 100, etc. Each first data stream contains four consecutive RS symbols derived from four different RS codewords; each first data stream is also called a 4-symbol-quartet stream. In some specific applications, the first data streams are further processed by a Physical Media Attachment (PMA) layer based on symbol multiplexing. More specifically, the first data streams are obtained through PMA processing based on 4-symbol-quartet multiplexing. It should be noted that, in the embodiments of this application, m0:m1PMA represents the symbol multiplexing of m0 input data streams to obtain m1 output data streams. In some other specific applications, the first data stream also undergoes processing by a Physical Coding Sublayer (PCS).

[0165] Figure 9(a) is a data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 9(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. Specifically, the 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are then subjected to symbol distribution and interleave to obtain 16 PCS Lanes. Among them, the symbol distribution is granular with 10 bits. Each of the 4 adjacent RS symbols in the 16 PCS Lanes comes from 4 different RS codewords. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. Each of the eight 1.6T AUI-8 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation. The corresponding baud rate (also known as symbol rate) is 106.25 GBaud, meaning the total bit rate of the eight 1.6T AUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, the 1.6T PCS is also called 1.6T BASE-RPCS, and the 1.6T 16:8PMA is also called 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the eight 1.6T AUI-8 signals. These eight signals first undergo 1.6T 8:8PMA to obtain p = eight first data streams, which are then processed by first and second data processing to obtain two first dual-polarization symbol streams to be transmitted.

[0166] Figure 9(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 9(b), 16 PCS lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 53.125 G Baud, that is, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T AUI-16 signals, first processes them through 1.6T 16:8PMA to obtain p=8 first data streams, and then performs first data processing and second data processing to obtain 2 first dual-polarization symbol streams to be transmitted.

[0167] Figure 9(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 9(c), 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain p=8 first data streams, and then undergo first data processing and second data processing to obtain 2 first dual-polarization symbol streams to be sent. The 1.6T PCS processing, 1.6T 16:8PMA, first data processing and second data processing are implemented in the transmitting device 01.

[0168] Figure 10(a) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 10(a), 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The bit rate of each of the 8 1.6T AUI-8 signals is 212.5 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 106.25 GBaud, that is, the total bit rate of the 8 1.6T AUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, 1.6T PCS is also called 1.6T BASE-R PCS, and 1.6T 16:8PMA is also called 1.6T BASE-R 16:8PMA. 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 8 1.6T AUI-8 signals, first processes them through 1.6T 8:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 2 first dual-polarization symbol streams to be transmitted.

[0169] Figure 10(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 10(b), 16 PCS lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 53.125 G Baud, that is, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T AUI-16 signals, first processes them through 1.6T 16:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 2 first dual-polarization symbol streams to be transmitted.

[0170] Figure 10(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 10(c), the total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes serve as p = 16 first data streams, and undergo first data processing and second data processing to obtain two first dual-polarization symbol streams to be transmitted. The 1.6T PCS processing, the first data processing, and the second data processing are implemented in the transmitting device 01.

[0171] It should be noted that in the scenarios for 1.6T services shown in Figures 9(a), 9(b), and 9(c), p = 8 first data streams participate in the first and second data processing. In the scenarios for 1.6T services shown in Figures 10(a), 10(b), and 10(c), p = 16 first data streams participate in the first and second data processing. The p = 8 first data streams participating in the first and second data processing is applicable not only to the 1.6T service scenarios described above but also to other service scenarios with a total rate of 1.6T, such as two 800G services or four 400G services.

[0172] Figure 9(d) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 9(d), consider two 800G service scenarios, where each 800G service data is processed by 800G PCS to obtain 32 PCS Lanes. Specifically, each 800G PCS process includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units are then symbol-distributed and interleaved to obtain 32 PCS Lanes. The symbol distribution is granular with 10 bits. The 32 PCS Lanes are processed by 800G 32:4PMA based on 4-symbol multiplexing to obtain four 800G AUI-4 signals. The two 800G service data are processed by the above 800G PCS and 800G 32:4PMA to obtain a total of two sets of 800G AUI-4 signals, totaling eight signal streams. Each of the two 800G AUI-4 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the two 800G AUI-4 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the two 800G AUI-4 signals. Each 800G AUI-4 signal is processed by 800G 4:4 PMA to obtain four first data streams, resulting in a total of p = eight first data streams. These eight first data streams then undergo first data processing and second data processing to obtain two first dual-polarization symbol streams to be transmitted.

[0173] Figure 9(e) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 9(e), consider four 400G service scenarios, where each 400G service data is processed by 400G PCS to obtain 16 PCS Lanes. Specifically, each 400G PCS process includes two RS encoding processing units. For example, the 400G PCS process in the figure may include RS-A and RS-B, and the 400G PCS process may also include RS-C and RS-D. The encoded data streams obtained after the two RS encoding processing units are then symbol-distributed and interleaved to obtain 16 PCS Lanes. The symbol distribution is granular with 10 bits. The 16 PCS Lanes are processed by 400G 16:2PMA based on 4-symbol multiplexing to obtain two 400G AUI-2 signals. The four 400G service data are processed by the above 400G PCS and 400G 16:2PMA to obtain a total of four sets of 400G AUI-2 signals, totaling eight signal streams. Each of the four 400G AUI-2 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation, with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the four 400G AUI-2 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the four 400G AUI-2 signals. Each 400G AUI-2 signal is processed by 400G 2:2 PMA to obtain two first data streams, resulting in a total of p = 8 first data streams. These 8 first data streams then undergo first data processing and second data processing to obtain two first dual-polarization symbol streams to be transmitted.

[0174] In some possible implementations, the following describes several possible implementations using the scenario of obtaining p=4 first data streams as an example.

[0175] As an example, the 16 PCS lanes processed by 1.6T PCS are then processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-16 signals. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 8 1.6T AUI-16 signals, first processes them through 1.6T 8:4PMA to obtain p=4 first data streams, and then performs first data processing and second data processing to obtain 2 first dual-polarization symbol streams to be transmitted.

[0176] As another example, the 16 PCS lanes processed by 1.6T PCS are then processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain p=4 first data streams. First data processing and second data processing are then performed to obtain 2 first dual-polarization symbol streams to be transmitted. The 1.6T PCS processing, 1.6T 16:4PMA, first data processing, and second data processing are implemented in the transmitting device 01.

[0177] In some possible implementations, several possible implementations are introduced for the next-generation 1.6T AUI-4 scenario.

[0178] As an example, the 16 PCS lanes processed by 1.6T PCS are then processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain 4 1.6T AUI-4 signals. Each of the 4 1.6T AUI-4 signals has a bit rate of 425 Gbits per second, uses PAM4 modulation, and has a corresponding baud rate (also known as symbol rate) of 212.5 G Baud. The 1.6T PCS processing and 1.6T 16:4PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 4 1.6T AUI-4 signals, first processes them through 1.6T 4:8PMA to obtain p=8 first data streams, and then performs first data processing and second data processing to obtain 2 first dual-polarization symbol streams to be transmitted.

[0179] As an example, the 16 PCS lanes processed by 1.6T PCS are then processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain 4 1.6T AUI-4 signals. Each of the 4 1.6T AUI-4 signals has a bit rate of 425 Gbits per second, uses PAM4 modulation, and has a corresponding baud rate (also known as symbol rate) of 212.5 G Baud. The 1.6T PCS processing and 1.6T 16:4PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 4 1.6T AUI-4 signals, first processes them through 1.6T 4:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 2 first dual-polarization symbol streams to be transmitted.

[0180] As another example, the 16 PCS lanes processed by 1.6T PCS are then processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain four 1.6T AUI-4 signals. Each of the four 1.6T AUI-4 signals has a bit rate of 425 Gbits per second, uses PAM4 modulation, and has a corresponding baud rate (also known as symbol rate) of 212.5 G Baud. The 1.6T PCS processing and 1.6T 16:4PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the four 1.6T AUI-4 signals, first processes them through 1.6T 4:4PMA to obtain p=4 first data streams, and then performs first data processing and second data processing to obtain two first dual-polarization symbol streams to be transmitted.

[0181] The following section further introduces several specific operations of the first and second data processing.

[0182] Figure 11(a) is a schematic diagram of one embodiment of the first and second data processing in this application. As shown in Figure 11(a), for the scenario where m=p, p first data streams are processed by convolutional interleaving, internal code encoding, and first interleaving to obtain p second data streams. Then, the p second data streams are processed by second interleaving, DP-16QAM symbol mapping, and DSP framing to obtain q first dual-polarization symbol streams to be transmitted. It can be seen that in the embodiment shown in Figure 11(a), each first data stream after convolutional interleaving is first encoded by internal code and then interleaved by first interleaving.

[0183] Figure 11(b) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figure 11(a), as shown in Figure 11(b), each first data stream after convolutional interleaving is first interleaved and then encoded using internal codes.

[0184] It should be noted that, for the implementation methods shown in Figures 11(a) and 11(b) above, in some scenarios requiring low latency, the convolutional interleaving process can be bypassed, which has the advantages of low latency and low power consumption.

[0185] Figure 12(a) is a schematic diagram of another implementation of the first and second data processing in this application. As shown in Figure 12(a), for the scenario where m > p, p first data streams are convolved and interleaved to obtain p convolved and interleaved data streams. Each convolved and interleaved data stream is distributed to obtain h = m / p first sub-data streams. The h = m / p first sub-data streams are encoded using internal code and interleaved using the first method to obtain h = m / p second data streams. The p convolved and interleaved data streams are distributed, encoded using internal code, and interleaved using the first method to obtain m second data streams. Then, the m second data streams are subjected to second interleaving, DP-16QAM symbol mapping, and DSP framing to obtain q first dual-polarization symbol streams to be transmitted. It can be seen that in the implementation shown in Figure 12(a), each first data stream after convolved and interleaved is first encoded using internal code and then interleaved using the first method.

[0186] Figure 12(b) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figure 12(a), as shown in Figure 12(b), each first data stream after convolutional interleaving is first interleaved and then encoded with internal code.

[0187] It should be noted that, for the implementation methods shown in Figures 12(a) and 12(b) above, in some scenarios requiring low latency, the convolutional interleaving process can be bypassed, which has the advantages of low latency and low power consumption.

[0188] Based on the above description of the first and second data processing methods, several specific implementation examples are given below.

[0189] Example 1

[0190] This embodiment 1 provides a specific implementation scheme for the first data processing and the second data processing shown in Figure 11(a) when the transmitting device 01 transmits 1.6T service, where p = 8 and m = 8.

[0191] In this embodiment, eight first data streams are obtained from either the 1.6T 8:8PMA shown in Figure 9(a), or the 1.6T 16:8PMA shown in Figures 9(b) and 9(c). Figure 13 is a schematic diagram of the format of one first data stream in this embodiment. Combining 1.6T PCS processing and 1.6T PMA processing, each first data stream satisfies the format shown in Figure 13. Every four consecutive RS symbols come from four different RS codewords, namely from the aforementioned RS-A, RS-B, RS-C, and RS-D encoders. The four adjacent RS symbols are represented as RS-FEC symbol-quartet. Using A... i(t) represents the t-th RS-FEC-symbol-quartet in the i-th first data stream, where 0≤i<8 and t is an integer. Then, 8 convolutional interleavers perform convolutional interleaving on the 8 first data streams respectively.

[0192] Figure 14 is a schematic diagram of one implementation of convolutional interleaving in this application. As shown in Figure 14, each convolutional interleaver contains r = 3 delay lines, and each delay unit contains d = 40 bits, i.e., 4 RS symbols. Delay line 0 has 2Q delay units, delay line 1 has Q delay units, and delay line 2 has no delay units. Figure 15 is a schematic diagram of another implementation of convolutional interleaving in this application. As shown in Figure 15, each convolutional interleaver contains r = 3 delay lines, and each delay unit stores d = 40 bits, i.e., 4 RS symbols. Delay line 0 has 0 delay units, delay line 1 has Q delay units, and delay line 2 contains 2Q delay units.

[0193] For ease of description, let's use A. i (a) represents the a-th RS-FEC symbol-quartet in the first data stream i, A′ i (a) represents the a-th RS-FEC symbol-quartet in the output data stream of convolutional interleaver i, which consists of four RS symbols output by one delay line of the convolutional interleaver, where a is an integer greater than or equal to 0, and 0 ≤ i < 8. The specific implementation of convolutional interleaver is as follows: the first data is polled and input to delay lines 0, 1, and 2, with each input to each delay line resulting in one RS-FEC symbol-quartet; delay lines 0, 1, and 2 then poll and output data, with each delay line outputting one RS-FEC symbol-quartet at a time. This can be understood as... i (3t) Input to delay line 0, and delay line 0 outputs A′. i (3t); then A i (3t+1) is input to delay line 1, and delay line 1 outputs A′. i (3t+1); then A i (3t+2) is input to delay line 2, and delay line 2 outputs A′. i (3t+2); then A i (3t+3) is input to delay line 0, and delay line 0 outputs A′. i (3t+3); and so on. When Q≥23, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i(3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, let Q be a multiple of 2, 4, or 8, such as Q = 24, 26, 28, 32, etc. Where t is an integer greater than or equal to 0.

[0194] Then, the data stream output from each convolutional interleaver is encoded using internal code. The internal code employs extended BCH(126,110), which is obtained by shortening the T=2 BCH(127,113) constructed based on the GF(2^7) field by 3 bits to obtain BCH(124,110). Then, odd-bit parity and even-bit parity are added to BCH(124,110) to finally obtain BCH(126,110). Its corresponding generator polynomial is: g(x) = M1(x)·M3(x)·(x... 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1)=x 16 +x 14 +x 11 + x 10 +x 9 +x 7 +x 5 +x 3 +x+1.

[0195] Figure 16 is a schematic diagram of one implementation of the internal code encoding in this application. As shown in Figure 16, the 3 delay lines of the convolutional interleaver are polled 11 times to output 33 consecutive RS-FEC symbol-quartets (i.e., 132 RS symbols), which is represented as {A′ i (3t),A′ i (3t+1),A′ i (3t+2),A′ i (3t+3),A′ i (3t+4),A′ i (3t+5),…,A′ i (3t+30),A′ i (3t+31),A′ i (3t+32)} is divided into 12 information bit sequences U. j Each information bit sequence contains 110 bits, represented by (u0, u1, ..., u...). 108 ,u 109 ) represents, and the information bit sequence U jThis includes bits 110×j to 110×j+109 of the 33 RS-FEC symbol-quartets shown. For each information bit block U... j BCH(126,110) encoding with 16 parity bits results in a codeword C containing 126 internal code bits. j The 16 parity bits are represented as (v0, v1, ..., v 14 ,v 15 Then the internal codeword C j The 126 bits are represented as (u0, u1, ..., u 108 ,u 109, v0,v1,…,v 14 ,v 15 ), where 0≤j<12. Then the data stream i output by the internal code encoder i is processed by the first interleaver i to obtain the second data stream i, where 0≤i<8.

[0196] Figure 17 is a schematic diagram of one implementation of the first interleaving in this application. As shown in Figure 17, performing the first interleaving i on data stream i involves performing the first interleaving process on each BCH(126,110) codeword C in data stream i to obtain the codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C. 108 ,u 109 Perform a left circular shift of (i*δ)%110 bits to obtain a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ), where w j = u(j+(i*δ)%110)%110, 0≤i<8, 0≤j<110, while the codeword C has 16 parity bits (v0,v1,…,v 14 ,v 15 The position of ) remains unchanged. Alternatively, the 110 information bits (u0, u1, ..., u) of each BCH(126, 110) codeword C in the data stream i are kept unchanged. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 8, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific loop shifts corresponding to the first interlacing 0 to the first interlacing 7. The specific values ​​of are shown in Table 1-a.

[0197] Table 1-a

[0198] In some specific embodiments, the specific cyclic shifts corresponding to the first interleaving 0 to the first interleaving 7 are... The values ​​of are shown in Table 1-b.

[0199] Table 1-b

[0200] Then, the eight second data streams undergo second data processing to obtain two first dual-polarization symbol streams, namely first dual-polarization symbol stream 0 and first dual-polarization symbol stream 1. One specific implementation involves obtaining one codeword interleaving sequence C′ from each second data stream, totaling 8 × 126 bits. Each interleaving sequence C′ is called a first bit set. The eight first bit sets undergo second interleaving processing to obtain two second bit sets, namely second bit set 0 and second bit set 1, with each second bit set containing 4 × 126 bits. Then, through DP-16QAM symbol mapping, second bit set 0 is mapped to 63 consecutive DP-16QAM symbols in first dual-polarization symbol stream 0, and second bit set 1 is mapped to 63 consecutive DP-16QAM symbols in first dual-polarization symbol stream 1. For ease of description, we use... This represents the j-th (0≤j≤126) bit in the codeword interleaved sequence C′ obtained from the second data stream i (0≤i≤7); using Let represent the (8i+j)th bit of the second bit set q, where 0 ≤ i < 63, 0 ≤ j < 8, and 0 ≤ q < 2. Then, a specific embodiment of the second interleaving is:

[0201] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0202] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0203] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0204] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0205] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0206] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0207] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0208] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0209] Another implementation of the second interleaving and DP-16QAM symbol mapping is as follows: Second interleaving and DP-16QAM symbol mapping are performed on second data streams 0 to 3 to obtain a first dual-polarization symbol stream 0; second interleaving and DP-16QAM symbol mapping are performed on second data streams 4 to 7 to obtain a first dual-polarization symbol stream 1. A specific embodiment of the second interleaving is then as follows:

[0210] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0211] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0212] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0213] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0214] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0215] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0216] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0217] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0218] Then, DP-16QAM is performed on each second bit set to obtain 63 DP-16QAM symbols, specifically by taking 8 consecutive bits of the second bit set q. Mapped to a DP-16QAM symbol S of the first dual-polarization symbol stream q i,q Where 0≤i<63, 0≤q<2, the specific mapping method is as follows: Mapped to DP-16QAM symbol S i,q The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i,q The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i,q The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i,q The Q-path component in the Y-polarization direction.

[0219] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner codeword is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0220] Figure 18 is a schematic diagram of a DSP frame structure in an embodiment of this application. As shown in Figure 18, the 6048 DP-16QAM symbols obtained by the second interleaving and DP-16QAM symbol mapping for 96 consecutive times are finally encapsulated by inserting a pilot symbol every 63 DP-16QAM symbols to obtain a DSP frame as shown in Figure 18. This frame contains 96 subframes, each containing 64 DP-16QAM symbols. The first symbol of each subframe is the inserted pilot symbol, and the remaining 63 symbols are DP-16QAM symbols obtained by mapping the second bit set. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, and -3-3j, where j is the imaginary unit of a complex number.

[0221] Example 2: This Example 2 is a specific scheme based on Example 1, which first performs the first interleaving and then performs the corresponding internal code encoding.

[0222] In this embodiment 2, the eight first data streams are convolutionally interleaved according to the convolutional interleaving scheme given in embodiment 1. Then, each convolutionally interleaved data stream undergoes first interleaving and internal code encoding. Specifically, the 132 consecutive RS symbols, i.e., 33 RS-FEC-symbol-quartets, in each convolutionally interleaved data stream are represented as {A′ i (3t),A′ i (3t+1),A′ i (3t+2),A′ i (3t+3),A′ i (3t+4),A′ i (3t+5),…,A′ i (3t+30),A′ i (3t+31),A′ i (3t+32)} is divided into 12 information bit sequences U. j Each information bit sequence contains 110 bits, represented by (u0, u1, ..., u...). 108 ,u 109 ) represents, and the information bit sequence U j This includes bits 110×j to 110×j+109 of the 33 RS-FEC symbol-quartets shown. For each information bit sequence U... j The first interleaving is performed to obtain the information bit interleaving sequence W. j It contains 110 bits and is represented as (w0, w1, ..., w 108 ,w 109 Then, for each information bit, interleave the sequence W. jPerform BCH(126,110) encoding, and add 16 parity bits to obtain a 126-bit internal codeword C. j The 16 parity bits are represented as (v0, v1, ..., v 14 ,v 15 Then the internal codeword C j The 126 bits are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ), where 0≤j<12. The generator polynomial of BCH(126,110) is as described in Example 1.

[0223] One specific implementation of the first interleaving is as follows: A specific implementation of the first interleaving of the data stream i after convolutional interleaving is to perform the first interleaving on each information bit sequence U = (u0, u1, ..., u...) in the data stream i. 108 ,u 109 Perform a left circular shift (i*δ)% 110 bits to obtain an information bit interleaving sequence W = (w0, w1, ..., w...). 108 ,w 109 ), where w j = u(j+(i*δ)%110)%110. Or, for each information bit sequence U = (u0, u1, ..., u...) in data stream i... 108 ,u 109 Perform a right circular shift. This yields an information bit interleaving sequence W = (w0, w1, ..., w1) consisting of 110 information bits. 108 ,w 109 ),in Where 0≤i<8, 0≤j<110, δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the interleaved concatenated code can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, 80, and 90. Below, taking a rightward loop as an example, the specific loop shift values ​​corresponding to the first interlacing 0 to the first interlacing 31 are...

[0224] The eight second data streams, after undergoing the first interleaving and second FEC encoding processes, are subjected to the second interleaving, DP-16QAM mapping, and DSP framing processing according to the scheme given in Example 1 to obtain two first dual-polarization symbol streams to be transmitted, which will not be elaborated here.

[0225] Example 3: This example 3 provides a specific scheme for 16 first data streams when the transmitting device 01 transmits 1.6T service and the internal code encoding adopts BCH(126,110).

[0226] In this embodiment, 16 first data streams are obtained from the 1.6T 8:16PMA module shown in Figure 8(a), the 1.6T 16:16PMA module shown in Figure 8(b), or the PCS module shown in Figure 8(c). Then, a convolutional interleaver as shown in Figure 14 is used to convolve and interleave each first data stream. When Q≥11, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. Alternatively, a convolutional interleaver as shown in Figure 15 can be used to convolve and interleave each first data stream. When Q≥12, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 12 or 16.

[0227] Then, using the internal code encoding and first interleaving scheme in Example 1, each data stream that has undergone convolutional interleaving is first encoded with internal code and then interleaved with the first interleaving to obtain 16 second data streams. Alternatively, using the first interleaving and internal code encoding scheme in Example 2, each data stream that has undergone convolutional interleaving is first interleaved and then encoded with internal code to obtain 16 second data streams.

[0228] The first interleaving process for data stream i involves performing a first interleaving process on each BCH(126,110) codeword C in data stream i to obtain a codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C in data stream i. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 16, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v15 ). Where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific loop shifts corresponding to the first interlacing 0 to the first interlacing 15. The specific values ​​of are shown in Table 2-a.

[0229] Table 2-a

[0230] In some specific applications, the specific cyclic shifts corresponding to the first interleaving 0 to the first interleaving 15 The values ​​of are shown in Table 2-b.

[0231] Table 2-b

[0232] Then, the 16 second data streams undergo second data processing to obtain two first dual-polarization symbol streams, namely first dual-polarization symbol stream 0 and first dual-polarization symbol stream 1. As an example, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 16 × 126 bits. Each interleaving sequence C′ is called the first bit set. The 16 first bit sets undergo second interleaving processing to obtain two second bit sets, namely second bit set 0 and second bit set 1, with each second bit set containing 8 × 126 bits. Then, through DP-16QAM symbol mapping, second bit set 0 is mapped to 126 consecutive DP-16QAM symbols in first dual-polarization symbol stream 0, and second bit set 1 is mapped to 126 consecutive DP-16QAM symbols in first dual-polarization symbol stream 1. For ease of description, we use... This represents the j-th (0≤j<126) bit in the codeword interleaved sequence C′ obtained from the second data stream i (0≤i<16); (using...) Let represent the (8i+j)th bit of the second bit set q, where 0 ≤ i < 126, 0 ≤ j < 7, and 0 ≤ q < 2. A specific embodiment of the second interleaving is as follows:

[0233] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0234] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0235] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0236] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0237] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0238] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0239] From the second data stream The 2nd ((2×i+q)%63)+i%2th bit in the codeword interleaved sequence.

[0240] From the second data stream The 2nd ((2×i+q)%63)+(i+1)%2th bit in the codeword interleaved sequence.

[0241] Another implementation of the second interleaving and DP-16QAM symbol mapping is as follows: Second interleaving and DP-16QAM symbol mapping are performed on second data streams 0 to 7 to obtain a first dual-polarization symbol stream 0; second interleaving and DP-16QAM symbol mapping are performed on second data streams 8 to 16 to obtain a first dual-polarization symbol stream 1. A specific embodiment of the second interleaving is as follows:

[0242] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0243] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0244] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0245] From the second data stream The 2nd × (i%63) + (i+1)%2th bit in the codeword interleaving sequence.

[0246] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0247] From the second data stream The 2nd × (i%63) + (i+1)%2th bit in the codeword interleaving sequence.

[0248] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0249] From the second data stream The 2nd × (i%63) + (i+1)%2th bit in the codeword interleaving sequence.

[0250] Then, each second bit set is mapped using DP-16QAM symbols to obtain 126 DP-16QAM symbols. Specifically, 8 consecutive bits in the second bit set q are... Mapped to a DP-16QAM symbol S of the first dual-polarization symbol stream q i,q Where 0≤i<126, 0≤q<2, the specific mapping method is as follows: Mapped to DP-16QAM symbol S i,q The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i,q The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i,q The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i,q The Q-path component in the Y-polarization direction.

[0251] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner codeword is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0252] Finally, 6048 DP-16QAM symbols obtained by performing the above second interleaving and DP-16QAM symbol mapping 48 times in succession are inserted with a pilot symbol every 63 DP-16QAM symbols, and encapsulated to obtain a DSP frame as shown in FIG. 18, which contains 96 sub-frames, each sub-frame being 64 DP-16QAM symbols, where the first symbol of each sub-frame is the inserted pilot symbol, and the remaining 63 symbols are DP-16QAM symbols obtained by mapping the second set of bits. The inserted pilot symbol is one of 3 + 3j, 3 - 3j, -3 + 3j, -3 - 3j, where j is the imaginary unit of a complex number.

[0253] Embodiment 4: Embodiment 4 adds a distribution operation based on Embodiment 1 or Embodiment 2, and is a specific solution corresponding to the 1:E distribution scenario.

[0254] In this embodiment, the 8 first data streams are convolutionally interleaved according to the convolutional interleaving scheme given in Embodiment 1, and then each of the convolutionally interleaved first data streams is distributed 1:E to obtain E first sub-data streams, where E = 4 or 8.

[0255] FIG. 19 is a schematic diagram of an implementation manner of distributing a data stream 1:E in an embodiment of the present application. As shown in FIG. 19, B i (t) represents 12 consecutive RS symbols in the i-th convolution data stream, which contains 3 RS-FEC-symbol-quartets, namely A' i (3t), A' i (3t + 1), A' i (3t + 2), that is, B i (t) = (A' i (3t), A' i (3t + 1), A' i (3t + 2)). A specific implementation of the distribution is to distribute B i (E × t + j) in the first data stream i to the first sub-data stream E × i + j, where 0 ≤ i < 8, 0 ≤ j < E, and t is an integer.

[0256] Another specific implementation of the distribution is to divide every consecutive 33 RS-FEC-symbol-quartets in the convolutional interleaver into 12 information bit sequences with a length of 110 bits according to the manner shown in FIG. 16. The j-th data block is called the information bit sequence U jWhere 0 ≤ j < 12, that is, the information bit sequence U0 is bits 0 to 109 in the 33 consecutive RS-FEC symbol-quartets shown; the information bit sequence U1 is bits 110 to 219 in the 33 consecutive RS-FEC symbol-quartets shown; the information bit sequence U2 is bits 220 to 319 in the 33 consecutive RS-FEC symbol-quartets shown; and so on. 11 Let's consider bits 1210 to 1319 in the 33 consecutive RS-FEC-symbol-quartets shown. The distribution involves round-robining the information bit sequences to the E first sub-data streams. For example, when E = 4, for the i-th first data stream, information bit sequences U0, U4, and U8 are distributed to the first sub-data stream 4×i; information bit sequences U1, U5, and U9 are distributed to the first sub-data stream 4×i+1; and information bit sequences U2, U6, and U7 are distributed to the first sub-data stream 4×i+1. 10 Distribute to the first sub-data stream 4×i+2; information bit sequence U3, information bit sequence U7, information bit sequence U 11 Distribute it to the first sub-data stream 4×i+3.

[0257] Then, using the internal code encoding and first interleaving scheme in Example 1, each first sub-data stream is first internally encoded and then first interleaved to obtain m = 8 × E second data streams. Alternatively, using the first interleaving and internal code encoding scheme in Example 2, each first sub-data stream is first interleaved and then internally encoded to obtain m = 8 × E second data streams.

[0258] Then, the m = 8 × E second data streams undergo second interleaving and DP-16QAM symbol mapping to obtain two first dual-polarization symbol streams, namely first dual-polarization symbol stream 0 and first dual-polarization symbol stream 1. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 8 × E × 126 bits. Each interleaving sequence C′ is called a first bit set. The 16 first bit sets undergo second interleaving to obtain two second bit sets, namely second bit set 0 and second bit set 1, with each second bit set containing 4 × E × 126 bits. Then, through DP-16QAM symbol mapping, second bit set 0 is mapped to E × 63 consecutive DP-16QAM symbols in first dual-polarization symbol stream 0, and second bit set 1 is mapped to E × 63 consecutive DP-16QAM symbols in first dual-polarization symbol stream 1. For ease of description, use... This represents the j-th (0≤j<126) bit in the codeword interleaved sequence C′ obtained from the second data stream i (0≤i<16); (using...) Represents the (8i + j)-th bit of the second set of bits q, where 0 ≤ i < E × 63, 0 ≤ j < 7, and 0 ≤ q < 2. A specific embodiment of the second interleaving is as follows:

[0259] From the second data stream The 2×((2×i + q) % 63) + i % 2-th bit in the codeword interleaving sequence.

[0260] From the second data stream The 2×((2×i + q) % 63) + (i + 1) % 2-th bit in the codeword interleaving sequence.

[0261] From the second data stream The 2×((2×i + q) % 63) + i % 2-th bit in the codeword interleaving sequence.

[0262] From the second data stream The 2×((2×i + q) % 63) + (i + 1) % 2-th bit in the codeword interleaving sequence.

[0263] From the second data stream The 2×((2×i + q) % 63) + i % 2-th bit in the codeword interleaving sequence.

[0264] From the second data stream The 2×((2×i + q) % 63) + (i + 1) % 2-th bit in the codeword interleaving sequence.

[0265] From the second data stream The 2×((2×i + q) % 63) + i % 2-th bit in the codeword interleaving sequence.

[0266] From the second data stream The 2×((2×i + q) % 63) + (i + 1) % 2-th bit in the codeword interleaving sequence.

[0267] Another implementation of the second interleaving and DP-16QAM symbol mapping is as follows: Second interleaving and DP-16QAM symbol mapping are performed on the second data stream 0 to the second data stream 4×E-1 to obtain the first dual-polarization symbol stream 0; second interleaving and DP-16QAM symbol mapping are performed on the second data stream 4×E to the second data stream 8×E-1 to obtain the first dual-polarization symbol stream 1. A specific embodiment of the second interleaving is as follows:

[0268] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0269] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0270] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0271] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0272] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0273] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0274] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0275] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0276] Then, each second bit set is mapped using DP-16QAM symbols to obtain 126 DP-16QAM symbols. Specifically, the consecutive 8 bits of the second bit set q are... Mapped to a DP-16QAM symbol S of the first dual-polarization symbol stream q i,qWhere 0≤i<126, 0≤q<2, the specific mapping method is as follows:

[0277] Mapped to DP-16QAM symbol S i,q The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i,q The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i,q The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i,q The Q-path component in the Y-polarization direction.

[0278] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner code is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of the concatenated code.

[0279] Finally, the 6048 DP-16QAM symbols obtained from the second interleaving and DP-16QAM mapping, which are performed 96 / E times consecutively, are encapsulated by inserting a pilot symbol every 63 DP-16QAM symbols, resulting in a DSP frame as shown in Figure 18. This frame contains 96 subframes, each with 64 DP-16QAM symbols. The first symbol in each subframe is the inserted pilot symbol, and the remaining 63 symbols are the DP-16QAM symbols obtained from the second bit set mapping. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j, where j is the imaginary unit of the complex number.

[0280] Example 5: This Example 5 is based on Example 3, with the addition of a distribution operation, and is a specific solution for a 1:E distribution scenario.

[0281] In this embodiment 5, the 16 first data streams are convolutionally interleaved according to the convolutional interleaving scheme given in embodiment 3. Then, the convolutionally interleaved data streams are distributed 1:E to obtain E first sub-data streams, where E = 2 or 4. The specific implementation of the distribution is shown in Figure 19. Using B... i (t) represents 12 consecutive RS symbols in the i-th convolutionally interleaved data stream, which contains 3 RS-FEC-symbol-quartets, denoted as A′. i (3t), A′ i (3t+1), A′i (3t + 2), i.e., B i (t) = (A' i (3t), A' i (3t + 1), A' i (3t + 2)). Specifically, distribute B i (E × t + j) in the first data stream i to the first sub - data stream E × i + j, where 0 ≤ i < 16, 0 ≤ j < E, and t is an integer.

[0282] Then process the m = 8 × E first sub - data according to the inner - code encoding, first interleaving, second interleaving, DP - 16QAM symbol mapping, and DSP framing schemes given in Embodiment 4 to obtain 2 first dual - polarization symbol streams to be transmitted.

[0283] Embodiment 6: This Embodiment 6 is a specific scheme corresponding to the case when the transmitting device 01 transmits 2x800G services based on Embodiment 1, Embodiment 2, or Embodiment 4.

[0284] In this Embodiment 6, obtain 8 first data streams from two 800G 4:4 PMAs as shown in Figure 7(d). Combining 800G PCS processing and 800G 32:4 PAM processing, each first data stream satisfies the format shown in Figure 13. Every consecutive 4 RS symbols come from 4 different RS codewords, that is, from 4 RS encoders RS - A, RS - B, RS - C, and RS - D shown in Figure 7(d). For the sake of convenience of description, these adjacent 4 RS symbols are called RS - FEC - symbol - quartet, and use A i (t) to represent the t - th RS - FEC - symbol - quartet in the i - th first data stream, where 0 ≤ i < 8 and t is an integer. Then perform convolutional interleaving on each first data stream using the convolutional interleaver shown in Figure 14 or Figure 15. The specific convolutional interleaving method is as described in Embodiment 1. When using the convolutional interleaver shown in Figure 14 and Q ≥ 45, in the output data stream of the convolutional interleaver, A' i (3t), A' i (3t + 1), A' i (3t + 2) a total of 12 consecutive RS symbols come from 12 different RS codewords. When using the convolutional interleaver shown in Figure 15 and Q ≥ 46, in the output data stream of the convolutional interleaver, A' i (3t), A' i (3t + 1), A' i (3t + 2) a total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high - speed implementation of the convolutional interleaver, let Q be a multiple of 2 or 4 or 8, such as Q = 46, 48, 52, etc.

[0285] Then, the eight convolutionally interleaved data streams are processed according to the scheme of Embodiment 1 or Embodiment 2, including internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing, to obtain two first dual-polarization symbol streams to be transmitted. Alternatively, the eight convolutionally interleaved data streams are processed according to the scheme of Embodiment 4, including distribution, internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing, to obtain two first dual-polarization symbol streams to be transmitted.

[0286] Example 7: This Example 7 is a solution based on Example 1, Example 2 or Example 4, when considering the transmission of 4x400G services by the transmitting device 01.

[0287] In this embodiment 7, eight first data streams are obtained from the four 400G 2:2 PMA encoders shown in Figure 9(e). Combining 400G PCS processing and 400G 16:2 PAM processing, each first data stream conforms to the format shown in Figure 13. Every four consecutive RS symbols come from four different RS codewords, namely from the aforementioned four RS encoders: RS-A, RS-B, RS-C, and RS-D. These four consecutive RS symbols are represented as RS-FEC symbol-quartet. Using A... i (t) represents the t-th RS-FEC-symbol-quartet in the i-th first data stream, where 0≤i<8 and t is an integer. Then, a convolutional interleaver, as shown in Figure 14 or Figure 15, is used to perform convolutional interleaving on each first data stream. The specific convolutional interleaving method is as described in Example 1. When Q≥91, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 92, 94, 96, 100, etc.

[0288] Then, the eight convolutionally interleaved data streams are subjected to internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing according to the scheme of Embodiment 1 or Embodiment 2 to obtain two first dual-polarization symbol streams to be transmitted. Alternatively, the eight convolutionally interleaved data streams are distributed, internally encoded, first interleaved, second interleaved, DP-16QAM symbol mapping, and DSP framing according to the scheme of Embodiment 4 to obtain two first dual-polarization symbol streams to be transmitted.

[0289] Embodiment 8: Based on Embodiments 1 to 7, Embodiment 8 proposes an inner code encoding scheme with lower redundancy and lower power consumption.

[0290] In this Embodiment 8, p first data are respectively subjected to convolutional interleaving according to the convolutional interleaving scheme given in Embodiment 1 or Embodiment 3, where p = 8 or 16. Then, inner code encoding is performed on each data stream after convolutional interleaving, and the inner code encoding uses extended hamming(128, 120). The specific encoding process is to take three consecutive RS-FEC-symbol-quartet {A′ i (3t), A′ i (3t + 1), A′ i (3t + 2)} in the data stream after convolutional interleaving as an information bit sequence U, which is represented by (u0, u1,..., u 118 , u 119 ). Extended hamming(128, 120) encoding is performed on each information bit sequence U to add 8 parity bits to obtain an inner code codeword C including 128 bits, where the 8 parity bits are represented as (v0, v1,..., v6, v7), and the 128 bits of the inner code codeword C are represented as (u0, u1,..., u 118 , u 119, v0, v1,..., v6, v7). Then, the first interleaving i is performed on the encoded data stream i output by the inner code encoding to obtain a second data stream i, where 0 ≤ i < p. Specifically, the first interleaving i interleaves each extended hamming(128, 120) codeword C in the encoded data stream i to obtain a codeword interleaved sequence C′. More specifically, the 120 information bits (u0, u1,..., u 118 , u 119 ) of each extended hamming(128, 120) codeword C are left circularly shifted by (i * δ) % 120 bits to obtain a sequence W = (w0, w1,..., w 118 , w 119 ) including 120 bits, where w j = u(j + (i * δ) % 120) % 120, 0 ≤ j < 120, and the positions of the 8 parity bits (v0, v1,..., v6, v7) of the codeword C remain unchanged. Alternatively, the 120 information bits (u0, u1,..., u 108 , u 109 ) of each extended hamming(128, 120) codeword C in the encoded data stream i are right circularly shifted by bits to obtain a sequence W = (w0, w1,..., w 108 , w 109 ) including 120 bits, where If 0 ≤ j < 110, then the codeword interleaved sequence C′ represents (w0, w1, …, w 118 , w 119 , v0, v1, …, v6, v7). Where both δ and are integer multiples of 10, and both δ and are greater than 0 and less than 120.

[0291] Then, perform second interleaving and DP-16QAM symbol mapping on m = p second data streams to obtain 2 first dual-polarization symbol streams, namely first dual-polarization symbol stream 0 and first dual-polarization symbol stream 1. Specifically, obtain 1 codeword interleaved sequence C′ from each second data stream, a total of m × 128 bits. Each interleaved sequence C′ is called the first bit set. Perform second interleaving on the first bit set to obtain 2 second bit sets, namely second bit set 0 and second bit set 1, and each second bit set contains m × 64 bits. Then, map second bit set 0 to m × 8 consecutive DP-16QAM symbols in first dual-polarization symbol stream 0 through DP-16QAM symbol mapping, and map second bit set 1 to m × 8 consecutive DP-16QAM symbols in first dual-polarization symbol stream 1. For convenience of description, use to represent the jth (0 ≤ j ≤ 128) bit in the codeword interleaved sequence C′ obtained from the second data stream i (0 ≤ i ≤ m); use to represent the (8i + j)th bit of the second bit set q, where 0 ≤ i < m × 8, 0 ≤ j < m, 0 ≤ q < 2. Then a specific embodiment of the second interleaving is:

[0292] The 2 × ((2 × i + q) % 64) + i % 2 th bit in the codeword interleaved sequence from the second data stream .

[0293] The 2 × ((2 × i + q) % 64) + (i + 1) % 2 th bit in the codeword interleaved sequence from the second data stream .

[0294] The 2 × ((2 × i + q) % 64) + i % 2 th bit in the codeword interleaved sequence from the second data stream .

[0295] The 2 × ((2 × i + q) % 64) + (i + 1) % 2 th bit in the codeword interleaved sequence from the second data stream .

[0296] The codeword interleaved sequence from the second data stream The 2nd ((2×i+q)%64)+i%2th bit in the codeword interleaved sequence.

[0297] From the second data stream The 2nd ((2×i+q)%64)+(i+1)%2th bit in the codeword interleaving sequence.

[0298] From the second data stream The 2nd ((2×i+q)%64)+i%2th bit in the codeword interleaved sequence.

[0299] From the second data stream The 2nd ((2×i+q)%64)+(i+1)%2th bit in the codeword interleaving sequence.

[0300] Another implementation of the second interleaving and DP-16QAM symbol mapping is as follows: Perform second interleaving and DP-16QAM symbol mapping on the second data stream 0 to the second data stream m / 2-1 to obtain the first dual-polarization symbol stream 0; perform second interleaving and DP-16QAM symbol mapping on the second data stream m / 2 to the second data stream m-1 to obtain the first dual-polarization symbol stream 1. A specific embodiment of the second interleaving is then as follows:

[0301] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0302] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0303] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0304] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0305] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0306] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0307] From the second data stream The 2×i+i%2th bit in the codeword interleaving sequence.

[0308] From the second data stream The 2×i+(i+1)%2 bits in the codeword interleaving sequence.

[0309] Then, each second bit set is mapped using DP-16QAM symbols to obtain m×8 DP-16QAM symbols. Specifically, 8 consecutive bits in the second bit set q are... Mapped to a DP-16QAM symbol S of the first dual-polarization symbol stream q i,q Where 0≤i<63, 0≤q<2, the specific mapping method is as follows: Mapped to S i,q The I-path component in the X-polarization direction; Mapped to S i,q The Q-path component in the X-polarization direction; Mapped to S i,q The I-path component in the Y-polarization direction; Mapped to S i,q The Q-path component in the Y-polarization direction.

[0310] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and symbol mapping, each inner codeword can be uniformly mapped to each constellation point of the DP-16QAM symbol, and errors in each DP-16QAM symbol can be uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0311] Finally, the 6144 DP-16QAM symbols obtained from the second interleaving and DP-16QAM symbol mapping, obtained by 768 / m consecutive cycles of the above, are encapsulated by inserting a pilot symbol every 64 DP-16QAM symbols, resulting in a DSP frame as shown in Figure 18. This frame contains 96 subframes, each with 65 DP-16QAM symbols. The first symbol of each subframe is the inserted pilot symbol, and the remaining 64 symbols are the DP-16QAM symbols obtained by mapping the second bit set. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j, where j is the imaginary unit of the complex number.

[0312] It should be noted that, based on embodiment 2, each data stream that has undergone convolutional interleaving can first undergo a first interleaving and then undergo internal code encoding to obtain a second data stream. Alternatively, based on embodiment 4 or embodiment 5, each data stream that has undergone convolutional interleaving can first be distributed and then undergo the first interleaving and internal code encoding.

[0313] Example 9: This Example 9 provides a specific scheme for the four first data streams when the transmitting device 01 transmits 1.6T service and the internal code encoding adopts BCH(126,110).

[0314] In this embodiment, four first data streams are acquired. Then, each first data stream is convolutionally interleaved. When Q ≥ 46, A′ in the data stream output by the convolutional interleaver is... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 46 or 48.

[0315] Then, each convolutionally interleaved data stream is first encoded using internal codes and then subjected to a first interleaving to obtain four second data streams. Alternatively, each convolutionally interleaved data stream is first interleaved and then encoded using internal codes to obtain four second data streams.

[0316] The first interleaving process for data stream i involves performing a first interleaving process on each BCH(126,110) codeword C in data stream i to obtain a codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C in data stream i. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 4, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). Where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific loop shifts corresponding to the first interleaving 0 to the first interleaving 3. The values ​​of are shown in Table 3.

[0317] Table 3

[0318] Example 10: Based on Example 9, consider a specific scheme where the internal code encoding uses BCH(176,160) encoding and corresponds to 4 first data streams. In this example, the convolutional interleaver uses r=4 and d=40. When Q≥35, the 16 consecutive RS symbols in the data stream output by the convolutional interleaver come from 16 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q=36 or 40. Then, each convolutionally interleaved data stream is first encoded using internal code and then first interleaved to obtain 4 second data streams. Alternatively, each convolutionally interleaved data stream is first interleaved and then encoded using internal code to obtain 4 second data streams.

[0319] Example 11: Based on Example 10, consider a specific scheme using BCH(176,160) encoding for the internal code, corresponding to 8 first data streams. In this example, the convolutional interleaver uses r=4 and d=40. When Q≥18, the 16 consecutive RS symbols in the data stream output by the convolutional interleaver come from 16 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q=18, 20, or 24. Then, each convolutionally interleaved data stream is first encoded using the internal code and then subjected to the first interleaving to obtain 8 second data streams. Alternatively, each convolutionally interleaved data stream is first subjected to the first interleaving and then encoded using the internal code to obtain 8 second data streams.

[0320] Example 12: Based on Example 10, consider a specific scheme using BCH(176,160) encoding for the internal code, corresponding to 16 first data streams. In this example, the convolutional interleaver uses r=4 and d=40. When Q≥9, the 16 consecutive RS symbols in the data stream output by the convolutional interleaver come from 16 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q=10, 12, or 16. Then, each convolutionally interleaved data stream is first encoded using the internal code and then subjected to the first interleaving to obtain 16 second data streams. Alternatively, each convolutionally interleaved data stream is first subjected to the first interleaving and then encoded using the internal code to obtain 16 second data streams.

[0321] Figure 20 is a schematic diagram of a data processing device according to an embodiment of this application. As shown in Figure 20, the data processing device includes an acquisition unit 201 and a processing unit 202. The acquisition unit 201 is used to execute the operation of step 101 in the above embodiment, and the processing unit 202 is used to execute the operations of steps 102 and 103 in the above embodiment. It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The integrated unit can be implemented in hardware or in the form of software functional units.

[0322] Figure 21 is a schematic diagram of an optical module structure in an embodiment of this application. As shown in Figure 21, the optical module includes a processor 301 and an interface 302. The processor 301 is used to execute the operations of steps 102 and 103 in the above embodiment. In one possible implementation, the processor 301 includes the processing unit 202 shown in Figure 21. The interface 302 can be a transceiver or an input / output interface. The interface 302 is used to receive signals from other devices and transmit them to the processor 301 or to send signals from the processor 301 to other devices. As an example, after performing the first data processing and the second data processing described above, the processor 301 obtains a first dual-polarization symbol stream and sends the first dual-polarization symbol stream through the interface 302. In this example, the interface 202 can specifically refer to an electrical interface. As another example, after performing the first data processing and the second data processing, the processor 301 obtains a first dual-polarization symbol stream. The modulator in the optical module performs electro-optic conversion and other signal processing based on the first dual-polarization symbol stream to obtain an optical signal, and then sends the optical signal through the interface 302. In this example, the interface 302 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0323] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0324] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0325] Figure 22 is a schematic diagram of a transmitting device according to an embodiment of this application. As shown in Figure 22, the transmitting device includes a host-side device 401 and an optical module 402. The host-side device 401 is used to send data to the optical module 402, and the optical module 402 generates an optical signal based on the data sent by the host-side device 401 and transmits the optical signal through the channel. For example, the host-side device may specifically be a switch, router, or server. The transmitting device can be a communication device including the host-side device 401 and the optical module 402. It should also be understood that the transmitting device in the embodiments of this application is named based on the data flow direction and does not limit the function of the device. For example, the transmitting device may also have a receiving function.

[0326] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0327] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0328] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0329] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0330] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0331] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0332] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0333] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0334] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0335] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0336] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: Obtain p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is a power of 2. Each of the first data streams contains a... RS The adjacent RS symbols are respectively from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2; The p first data streams are subjected to first data processing including forward error correction (FEC) coding and first interleaving to obtain m second data streams, where m is an integer greater than or equal to p; The m second data streams are subjected to a second data processing process, including second interleaving, dual-polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol mapping, and framing, to obtain q first dual-polarization symbol streams, where q is an integer greater than 1.

2. The method according to claim 1, characterized in that, Performing second data processing on the m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain q first dual-polarization symbol streams includes one of the following methods: The m second data streams are subjected to second interleaving and DP-16QAM symbol mapping to obtain q second dual-polarization symbol streams. Target symbol sequences are then inserted into the q second dual-polarization symbol streams to obtain the q first dual-polarization symbol streams. or, The m second data streams are interleaved to obtain q third data streams. Target bit sequences are inserted into the q third data streams to obtain q fourth data streams. DP-16QAM symbol mapping is performed on the q fourth data streams to obtain the q first dual-polarization symbol streams. The target bit sequence is then mapped using DP-16QAM to obtain the target symbol sequence. or, The m second data streams are interleaved a second time to obtain 2×q third data streams. The target bit sequence is inserted into each of the 2×q third data streams to obtain 2×q fourth data streams. DP-16QAM symbol mapping is performed on every two fourth data streams in the 2×q fourth data streams to obtain one first dual-polarization symbol stream, thus obtaining the q first dual-polarization symbol streams. The target bit sequence is obtained by DP-16QAM symbol mapping to obtain the target symbol sequence. or, The m second data streams are interleaved a second time to obtain 4×q third data streams. Two×q of the 4×q third data streams are interleaved with the I component of the target bit sequence, and the other two×q third data streams are interleaved with the Q component of the target bit sequence to obtain 4×q fourth data streams. DP-16QAM symbol mapping is performed on every four fourth data streams to obtain one first dual-polarization symbol stream, resulting in the q first dual-polarization symbol streams. The I component of the target bit sequence is mapped using DP-16QAM to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is mapped using DP-16QAM to obtain the Q component of the target symbol sequence.

3. The method according to claim 1 or 2, characterized in that, The m second data streams are subjected to second data processing including second interleaving, DP-16QAM symbol mapping, and framing to obtain q first dual-polarization symbol streams, including: One first bit set is obtained from each of the second data streams to obtain m first bit sets, each first bit set including N bits, wherein the N bits are obtained by FEC encoding K information bits; The m first bit sets are interleaved a second time to obtain q second bit sets, each second bit set including R bits, each of the second bit sets includes R bits from one of the first bit sets. in, This indicates a round-down operation. This indicates the rounding up operation; Perform DP-16QAM symbol mapping on each second bit set to obtain the corresponding continuous first dual-polarization symbol stream. A dual-polarization DP-16QAM symbol.

4. The method according to claim 1, characterized in that, Performing second data processing on the m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain q first dual-polarization symbol streams includes one of the following methods: Perform second interleaving and DP-16QAM symbol mapping on each m / q second data stream to obtain 1 second dual-polarization symbol stream, resulting in q second dual-polarization symbol streams. Insert the target symbol sequence into each of the q second dual-polarization symbol streams to obtain the q first dual-polarization symbol streams. or, A second interleaving is performed on every m / q second data streams in the m second data streams to obtain 1 third data stream, resulting in q third data streams. Target bit sequences are inserted into each of the q third data streams to obtain q fourth data streams. DP-16QAM symbol mapping is performed on each of the q fourth data streams to obtain the q first dual-polarization symbol streams. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain the target symbol sequence. or, A second interleaving is performed on every m / q second data streams in the m second data streams to obtain 2 third data streams, resulting in 2×q third data streams. Target bit sequences are inserted into each of the 2×q third data streams to obtain 2×q fourth data streams. DP-16QAM symbol mapping is performed on every two fourth data streams in the 2×q fourth data streams to obtain 1 first dual-polarization symbol stream, resulting in the q first dual-polarization symbol streams. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain the target symbol sequence. or, A second interleaving is performed on every m / q second data streams of the m second data streams to obtain 4 third data streams, resulting in 4×q third data streams. Two×q of the 4×q third data streams are inserted with the I component of the target bit sequence, and the other two×q are inserted with the Q component of the target bit sequence to obtain 4×q fourth data streams. DP-16QAM symbol mapping is performed on every four fourth data streams of the 4×q fourth data streams to obtain one first dual-polarization symbol stream, resulting in the q first dual-polarization symbol streams. The I component of the target bit sequence is mapped using DP-16QAM to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is mapped using DP-16QAM to obtain the Q component of the target symbol sequence.

5. The method according to claim 1 or 4, characterized in that, The m second data streams are subjected to second data processing including second interleaving, DP-16QAM symbol mapping, and framing to obtain q first dual-polarization symbol streams, including: One first bit set is obtained from each of the m / q second data streams to obtain m / q first bit sets. Each first bit set includes N bits, and the N bits include K information bits and NK check bits in the codeword encoded by the FEC. The m / q first bit sets are interleaved a second time to obtain a second bit set, the second bit set including 1 bit; Perform DP-16QAM symbol mapping on the second bit set to obtain the continuous first dual-polarization symbol stream. A dual-polarization DP-16QAM symbol.

6. The method according to any one of claims 2 to 5, characterized in that, The first dual-polarization symbol stream includes multiple dual-polarization symbol sequences, and a fixed position in each dual-polarization symbol sequence includes the target symbol sequence. The target symbol sequence includes at least one of the following: frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence.

7. The method according to any one of claims 1 to 6, characterized in that, If m > p, perform first data processing, including FEC encoding and first interleaving, on the p first data streams to obtain m second data streams, including: Each of the p first data streams is distributed to obtain m / p first sub-data streams, resulting in m first sub-data streams. The m first sub-data streams are then subjected to FEC encoding and first interleaving to obtain the m second data streams.

8. The method according to claim 7, characterized in that, Each first sub-data stream obtained by distributing from a first data stream includes K consecutive bits from the first data stream, where K is a positive integer and K is the number of information bits involved in the FEC encoding; Alternatively, each of the first sub-data streams obtained by distributing from a first data stream comprises K0 consecutive bits from the first data stream, where K0 is an integer multiple of 40.

9. The method according to claim 7 or 8, characterized in that, The number of information bits involved in the FEC encoding is K, and each first sub-data stream obtained by distributing it from one first data stream includes K0 consecutive bits in the first data stream, where K = 110 and K0 = 120.

10. The method according to any one of claims 7 to 9, characterized in that, Performing first data processing, including FEC encoding and first interleaving, on the p first data streams to obtain m second data streams includes: The p first data streams are convolutionally interleaved. Each of the p first data streams after convolutional interleaving is distributed to obtain m / p first sub-data streams, resulting in m first sub-data streams. The m first sub-data streams are then subjected to FEC encoding and first interleaving to obtain the m second data streams.

11. The method according to any one of claims 1 to 6, characterized in that, Performing first data processing, including FEC encoding and first interleaving, on the p first data streams to obtain m second data streams includes: The p first data streams are convolutionally interleaved, and the p first data streams after convolutional interleaving are FEC encoded and firstly interleaved to obtain the m second data streams.

12. The method according to claim 10 or 11, characterized in that, Convolutional interleaving of one of the first data streams includes: Bits from the first data stream are delayed using r delay lines, where r is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units (0 units). The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. The input bits are sequentially input to the r delay lines according to their numbers, with d bits being input to each delay line and d bits being output from each delay line at a time. Q and d are both integers greater than or equal to 1.

13. The method according to claim 12, characterized in that, The delay line with the largest sequence number among the r delay lines includes 0 memory units, or the delay line with the smallest sequence number among the r delay lines includes 0 memory units.

14. The method according to claim 12 or 13, characterized in that, p=8, r=3, d=40, Q≥23; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, Q ≥ 11; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, Q ≥ 12; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p=4, r=3, d=40, Q≥45; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p=4, r=3, d=40, Q≥46; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q≥34; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q≥35; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p = 8, r = 4, d = 40, Q ≥ 17; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p = 8, r = 4, d = 40, Q ≥ 18; Alternatively, p = 16, r = 4, d = 40, Q ≥ 9.

15. The method according to any one of claims 1 to 14, characterized in that, The number of information bits involved in the FEC encoding is K. Each codeword after FEC encoding includes N bits. The NK parity bits in the codeword are obtained by FEC encoding the K information bits. The first interleaving is used to cyclically shift each K information bits in the first data stream.

16. The method according to claim 15, characterized in that, p=4, the first interleaving is used to cyclically shift every K information bits in the first data stream i. 4 bits, 0≤i<4 Satisfy one of the following: Alternatively, p=8, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 8 bits, 0≤i<8 Satisfy one of the following: Alternatively, p = 16, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 16 bits, 0≤i<16 Satisfy one of the following:

17. The method according to any one of claims 1 to 16, characterized in that, The first data processing, which includes FEC encoding and first interleaving, of the first data stream includes: The first data stream is subjected to a first interleaving, and the first data stream after the first interleaving is subjected to FEC encoding; or, The first data stream is FEC encoded, and the first data stream after FEC encoding is interleaved for the first time. or, The K information bits in the first data stream are FEC encoded to obtain NK parity bits, and the K information bits are first interleaved to obtain N bits including the NK parity bits and the K information bits after the first interleaving, where K is a positive integer and N > K.

18. The method according to any one of claims 1 to 17, characterized in that, Each codeword encoded by the FEC consists of K information bits and NK check bits, for a total of N bits; N = 128, K = 120, or N = 126, K = 110, or N = 176, K = 160.

19. The method according to any one of claims 1 to 18, characterized in that, m = 4, 8, 16 or 32.

20. The method according to any one of claims 1 to 19, characterized in that, In each of the first data streams, every four adjacent RS symbols come from four RS codewords.

21. The method according to any one of claims 1 to 20, characterized in that, The p first data streams are obtained by processing 16 fifth data streams through a symbol-based physical media adaptation layer (PMA). The 16 fifth data streams are obtained by processing the service data to be sent through a physical coding sublayer (PCS) including RS coding.

22. The method according to claim 21, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA, and the t signals are obtained by processing the 16 fifth data streams through 16:t PMA, where t is a positive integer multiple of 4.

23. The method according to claim 21, characterized in that, The p first data streams are obtained by processing the 16 fifth data streams through 16:p PMA.

24. The method according to any one of claims 1 to 20, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA based on symbol multiplexing.

25. The method according to claim 22 or 24, characterized in that, t = 8, p = 8; or t = 16, p = 8; or t = 4, p = 8; Alternatively, t = 8, p = 16; Alternatively, t = 16, p = 16; Alternatively, t = 4, p = 16; Alternatively, t = 4, p = 4; Alternatively, t = 8, p = 4.

26. The method according to any one of claims 1 to 20, characterized in that, The p first data streams are obtained by processing the service data to be sent through a PCS including RS encoding.

27. The method according to any one of claims 1 to 26, characterized in that, The data processing method is applicable to scenarios including Ethernet, optical transport networks, and space optical communication.

28. A data processing apparatus, characterized in that, The data processing device includes: an acquisition unit and a processing unit; The acquisition unit is used to: acquire p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is an integer power of 2; The processing unit is used to: perform first data processing, including forward error correction (FEC) coding and first interleaving, on the p first data streams to obtain m second data streams, where m is an integer greater than or equal to p; The m second data streams are subjected to a second data processing process, including second interleaving, dual-polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol mapping, and framing, to obtain q first dual-polarization symbol streams, where q is an integer greater than 1.

29. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 27.

30. An optical module, characterized in that, The optical module includes a processor and an interface, the processor being used to perform the method as described in any one of claims 1 to 27 and to transmit and receive signals through the interface.

31. A transmitting device, characterized in that, The transmitting device includes a host-side device and an optical module as described in claim 30, wherein the optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

32. A communication system, characterized in that, include: The transmitting device and the receiving device as described in claim 31, wherein the transmitting device is configured to transmit a signal to the receiving device.

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