Neural network processor and test method therefor, and device and storage medium

Abstract

Disclosed are a neural network processor and a test method therefor, and a device and a storage medium, which relate to the technical field of functional safety. The method comprises: determining first configuration information corresponding to a first computing module in a neural network processor; on the basis of the first configuration information, determining first test data; processing the first test data by means of the first computing module, so as to obtain first test response data; processing the first test response data by means of a second computing module, so as to obtain second test response data; and on the basis of the first test data and the second test response data, determining a test result. In the technical solution of the present disclosure, since an algorithm corresponding to the first computing module and an algorithm corresponding to the second computing module are inverse to each other, test results of the first computing module and / or the second computing module can be accurately determined on the basis of the first test data and the second test response data, thereby realizing the testing of different computing modules. Therefore, the test application range is expanded, and the test efficiency is improved.

Description

Neural network processors, their testing methods, equipment, and storage media

[0001] This disclosure claims priority to Chinese Patent Application No. 202410516837.5, filed on April 26, 2024, entitled "Neural Network Processor and Testing Method, Apparatus and Storage Medium Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of functional safety (FuSa) technology, and in particular to a neural network processor and its testing method, apparatus and storage medium. Background Technology

[0003] Currently, in functional safety (FuSa) protection of neural network processors, the test pattern scheme has become an important testing method for FuSa safety protection due to its advantage of low area overhead.

[0004] When using the TEST PATTERN scheme, the same test data needs to be input into multiple identical computing modules simultaneously. Then, the calculation results after processing this test data by these multiple identical computing modules are compared to test the multiple identical computing modules. In other words, the TEST PATTERN scheme is only applicable to multiple identical computing modules; it cannot be used for FuSa security protection for different computing modules. Summary of the Invention

[0005] Typically, when using the TEST PATTERN scheme for testing, only the same computing modules can be tested. However, the TEST PATTERN scheme cannot be used for FuSa security protection for different computing modules in a neural network processor.

[0006] To address the aforementioned technical problems, this disclosure provides a testing method for neural network processors, comprising:

[0007] Determine the first configuration information corresponding to the first computing module in the neural network processor; the first configuration information is used to configure the test method of the first computing module;

[0008] Based on the first configuration information, determine the first test data;

[0009] The first test data is processed by the first computing module in the neural network processor to obtain the first test response data;

[0010] The second computing module in the neural network processor processes the first test response data from the first computing module to obtain the second test response data; the algorithm corresponding to the second computing module is the inverse of the algorithm corresponding to the first computing module.

[0011] Based on the first test data and the second test response data, determine the test results of the first computing module and / or the second computing module.

[0012] A second aspect of this disclosure provides a neural network processor, comprising:

[0013] The configuration circuit, coupled to the test circuit, is used to receive test configuration commands, generate first configuration information corresponding to the first computing module in response to the test configuration commands, and send the first configuration information to the test circuit.

[0014] A test circuit, coupled to a first calculation module and a comparator, is used to determine first test data based on first configuration information, and to send the first test data to the first calculation module and the comparator.

[0015] The first computing module, coupled to the second computing module, is used to process the first test data and send the obtained first test response data to the second computing module.

[0016] The second calculation module, coupled to the comparator, is used to process the first test response data and send the obtained second test response data to the comparator; the algorithm corresponding to the second calculation module is the inverse of the algorithm corresponding to the first calculation module.

[0017] A comparator is used to determine the test results of the first computing module and / or the second computing module based on the first test data and the second test response data.

[0018] A third aspect of this disclosure provides a computer-readable storage medium storing a computer program for executing a test method for a neural network processor according to the first aspect.

[0019] A fourth aspect of this disclosure provides an electronic device comprising:

[0020] processor;

[0021] Memory used to store processor-executable instructions;

[0022] A test method for a neural network processor that reads executable instructions from memory and executes the instructions to implement the first aspect described above.

[0023] In this embodiment, since the algorithm corresponding to the first calculation module is the inverse of the algorithm corresponding to the second calculation module, after the first calculation module processes the first test data to obtain the first test response data, and then processes the first test response data through the second calculation module to obtain the second test response data, if both the first and second calculation modules are functioning normally, the second test response data output by the second calculation module will be consistent with the first test data; if the logic of the first and / or second calculation modules is malfunctioning, the second test response data output by the second calculation module will be inconsistent with the first test data. Therefore, based on the first test data and the second test response data, the test results of the first and / or second calculation modules can be accurately determined, enabling testing of different calculation modules, thereby expanding the applicability of the TEST PATTERN scheme and improving testing efficiency. Attached Figure Description

[0024] Figure 1 is a schematic diagram of the structure of a neural network processor provided in an exemplary embodiment of the present disclosure.

[0025] Figure 2 is a schematic diagram of the structure of another neural network processor provided by an exemplary embodiment of the present disclosure.

[0026] Figure 3 is a schematic diagram of the structure of another neural network processor provided in an exemplary embodiment of the present disclosure.

[0027] Figure 4 is a flowchart illustrating a testing method for a neural network processor provided in an exemplary embodiment of this disclosure.

[0028] Figure 5 is a flowchart illustrating another testing method for a neural network processor provided by an exemplary embodiment of this disclosure.

[0029] Figure 6 is a flowchart illustrating another test method for a neural network processor provided by an exemplary embodiment of this disclosure.

[0030] Figure 7 is a flowchart illustrating another test method for a neural network processor provided by an exemplary embodiment of this disclosure.

[0031] Figure 8 is a flowchart illustrating another test method for a neural network processor provided by an exemplary embodiment of this disclosure.

[0032] Figure 9 is a schematic diagram of another neural network processor structure provided by an exemplary embodiment of the present disclosure.

[0033] Figure 10 is a schematic diagram of another neural network processor structure provided by an exemplary embodiment of the present disclosure.

[0034] Figure 11 is a schematic diagram of another neural network processor structure provided by an exemplary embodiment of the present disclosure.

[0035] Figure 12 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. Detailed Implementation

[0036] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0037] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0038] Application Overview

[0039] Currently, FuSa (Full Satiety) protection is a key capability in the automotive-grade field and has been widely used in neural network processors. Typically, FuSa protection schemes for neural network processors include the dual-core scheme and the TEST PATTERN scheme. The dual-core scheme is a basic security protection scheme applicable to all computational modules to be protected in the neural network processor. However, because the dual-core scheme requires copying the computational modules to be protected, it incurs a significant area overhead (doubling the original area). The TEST PATTERN scheme is a selective security protection scheme applicable only to multiple identical computational modules in the neural network processor. However, because the TEST PATTERN scheme does not require copying the computational modules to be protected, it has a smaller area overhead, and therefore, the TEST PATTERN scheme has become the preferred FuSa protection scheme for neural network processors.

[0040] Figure 1 is a schematic diagram of the structure of a neural network processor applicable to the TEST PATTERN scheme provided in an embodiment of this disclosure. As shown in Figure 1, the neural network processor 10 may include a first integrated circuit 11 and a second integrated circuit 12; the first integrated circuit 11 may include three identical ALUs, namely ALU 111, ALU 112 and ALU 113, a configuration circuit 114, a pseudo-random data generation circuit 115, and a comparator 116. The second integrated circuit 12 may include two ALUs that are different from ALU 111, namely ALU 121 and ALU 122.

[0041] In this circuit, the algorithm configuration terminal of configuration circuit 114 is coupled to the algorithm configuration terminals of ALUs 111, 112, and 113; the test enable terminal of configuration circuit 114 is coupled to the enable terminal of pseudo-random data generation circuit 115; the test data input terminals of ALUs 111, 112, and 113 are all coupled to the test data output terminal of pseudo-random data generation circuit 115. The calculation result output terminals of ALUs 111, 112, and 113 are all coupled to the comparison input terminal of comparator 116. The output terminal of comparator 116 is used to send the comparison result to the operating system.

[0042] The implementation process of the TEST PATTERN scheme will be explained below with reference to Figure 1.

[0043] As shown in Figure 1, firstly, the configuration circuit 114 receives the test configuration information, sends the enable information in the test configuration information to the test enable terminal of the pseudo-random data generation circuit 115, and sends the algorithm information in the test configuration information to the algorithm configuration terminals of ALU 111, ALU 112 and ALU 113.

[0044] Then, in response to the enable information, the pseudo-random data generation circuit 115 generates corresponding test data and sends the test data to the test data input terminals of ALU 111, ALU 112 and ALU 113.

[0045] Next, the test data input terminals of ALU 111, ALU 112, and ALU 113 respectively receive test data, perform calculations on the test data according to the algorithm corresponding to the algorithm information, and send the calculation results to comparator 116 through the calculation result output terminal.

[0046] Finally, comparator 116 compares the calculation results, obtains the first comparison result, and sends the first comparison result to the operating system.

[0047] In this embodiment of the disclosure, the TEST PATTERN scheme is only applicable to testing the same ALU 111, ALU 112 and ALU 113, and the scope of application is small. For two different computing modules (i.e., computing modules that are instantiated only once), the TEST PATTERN scheme cannot be used for FuSa security protection.

[0048] To address the aforementioned technical issues, this disclosure provides a method for testing a neural network processor. The method involves determining first configuration information corresponding to a first computing module in the neural network processor, determining first test data based on the first configuration information, processing the first test data through the first computing module to obtain first test response data, and then processing the first test response data through a second computing module to obtain second test response data. Since the algorithms corresponding to the first and second computing modules are inverses of each other, when the first test data is processed sequentially by the first and second computing modules, if both modules function correctly, the second test response data output by the second computing module will be consistent with the first test data. Conversely, if either the first or second computing module has a logical error, the second test response data output by the second computing module will be inconsistent with the first test data. Therefore, based on the first and second test response data, the test results of the first and / or second computing modules can be accurately determined, enabling testing of different computing modules. This expands the applicability of the TEST PATTERN scheme and improves testing efficiency.

[0049] Exemplary System

[0050] Figure 2 is a schematic diagram of another neural network processor provided in an exemplary embodiment of the present disclosure. As shown in Figure 2, the neural network processor 20 includes a first integrated circuit 21 and a second integrated circuit 22. The first integrated circuit 21 includes a first configuration circuit 211, a first computing module (ALU) 212, and a test circuit 213; the second integrated circuit 22 includes a second computing module (ALU) 222 and a comparator 223.

[0051] In some embodiments of this disclosure, comparator 223 may be a dual-channel comparator.

[0052] The test enable terminals of the first configuration circuit 211 and the test enable terminal of the test circuit 213 are coupled together. The data output terminal of the test circuit 213 is coupled to the data input terminal of the first calculation module 212 and the first input terminal of the comparator 223. The data output terminal of the first calculation module 212 is coupled to the data input terminal of the second calculation module 222. The data output terminal of the second calculation module 222 is coupled to the second input terminal of the comparator 223. The output terminal of the comparator 223 is coupled to the output terminal of the neural network processor.

[0053] Based on the embodiment shown in Figure 2 above, this disclosure provides another neural network processor. As shown in Figure 3, in this neural network processor 20, the test circuit 213 includes a pseudo-random data generation circuit 2131, a cache 2132, and a selector 2133; the first integrated circuit 21 also includes an address generation circuit 214, a first direct memory access circuit 215, and a second direct memory access circuit 216. The second integrated circuit 22 also includes a second configuration circuit 221.

[0054] In some embodiments of this disclosure, selector 2133 can be a one-to-many data selector. First direct memory access circuit 215 can be used to read data; second direct memory access circuit 216 can be used to write data; the depth of buffer 2132 can be determined based on the number of system cycles required for data processing by first computing module 212 and second computing module 222. In some examples, if the number of system cycles required for data processing by first computing module 212 is n, and the number of system cycles required for data processing by second computing module 222 is m, then the depth of buffer 2132 should be greater than or equal to m+n.

[0055] Specifically, the test enable terminal of the first configuration circuit 211 is coupled to the test enable terminal of the address generation circuit 214; the address configuration terminal of the first configuration circuit 211 is coupled to the address configuration terminal of the address generation circuit 214; the selection control terminal of the first configuration circuit 211 is coupled to the selection control terminal of the selector 2133; and the algorithm configuration terminal of the first configuration circuit 211 is coupled to the algorithm configuration terminal of the first calculation module 212.

[0056] The address output terminal of the address generation circuit 214 is coupled to the read address input terminal of the first direct memory access circuit 215 and the write address input terminal of the second direct memory access circuit 216. The read data output terminal of the first direct memory access circuit 215 is coupled to the input terminal of the register 2132. The output terminal of the register 2132 is coupled to the first input terminal of the selector 2133.

[0057] The test enable terminal of the pseudo-random data generation circuit 2131 is coupled to the test enable terminal of the test circuit 213; the second input terminal of the data output selector 2133 of the pseudo-random data generation circuit 2131 is coupled to the data input terminal of the first calculation module 212.

[0058] The algorithm configuration terminal of the second configuration circuit 221 is coupled to the algorithm configuration terminal of the second calculation module 222.

[0059] Exemplary methods

[0060] Figure 4 is a flowchart illustrating a testing method for a neural network processor according to an exemplary embodiment of this disclosure. This testing method can be applied to the neural network processor 20 shown in Figures 2 and 3. As shown in Figure 4, the testing method for the neural network processor may include steps 401 to 405.

[0061] Step 401: Determine the first configuration information corresponding to the first computing module in the neural network processor.

[0062] The first configuration information is used to configure the testing method of the first computing module.

[0063] For example, the testing methods for the first computing module may include a first testing method that tests the module with actual data to be processed (data input to the first computing module when the neural network processor is working normally) (corresponding to the first test) and a second testing method that tests the module with pseudo-random test data (corresponding to the second test).

[0064] For example, the first configuration information may be control information configuring the neural network generator to test the first computing module according to a first test mode or a second test mode, and may be generated based on a first test configuration instruction sent by the operating system (top level). In some examples, different test modes of the first computing module may correspond to different first configuration information. For example, if the test mode of the first computing module is the first test mode, the first configuration information includes enable information for enabling the first test, address information corresponding to the first computing module, and data selection signals for controlling the selector. If the test mode of the first computing module is the second test mode, the first configuration information may include enable information and data selection signals.

[0065] Referring to Figure 2, the first configuration circuit 211 in the neural network processor 20 can receive the first test configuration instruction corresponding to the first computing module 212 sent by the operating system, generate the first configuration information based on the test configuration instruction, and send the first configuration information to the test circuit 213.

[0066] Step 402: Determine the first test data based on the first configuration information.

[0067] For example, the first test data can be data input to the first computing module to test the first computing module. In some examples, the first test data can be pseudo-random test data, or it can be the actual data to be processed input to the first computing module. The specific implementation of the first test data is not limited in the embodiments of this disclosure.

[0068] In some examples, if the first configuration information is the configuration information corresponding to the first test method, then the data to be processed that is actually input into the first calculation module is determined as the first test data; if the first configuration information is the configuration information corresponding to the second test method, then the pseudo-random test data is determined as the first test data.

[0069] For example, referring to FIG2, the test circuit 213 can receive first configuration information, generate first test data in response to the first configuration information, and send the first test data to the first input terminal of the comparator 223 and the data input terminal of the first calculation module 212 through the output terminal of the test circuit 213.

[0070] Step 403: The first test data is processed by the first computing module in the neural network processor to obtain the first test response data.

[0071] For example, the first test response data includes a first calculation result corresponding to the first test data. In some examples, if the first test data is data to be processed, the first test response data includes the first calculation result corresponding to the data to be processed; if the first test data is pseudo-random test data, the first test response data includes the first calculation result corresponding to the pseudo-random test data.

[0072] For example, referring to FIG2, the first calculation module 212 can calculate the first test data based on the first algorithm corresponding to the first calculation module 212, obtain the first test response data, and send the first test response data to the data input terminal of the second calculation module 222.

[0073] In some examples, referring to Figure 3, the first configuration circuit 211 may also generate first algorithm information corresponding to the first calculation module 212 in response to the first test configuration command, and send the first algorithm information to the first calculation module 212. Then, the first calculation module 212 may first determine the first algorithm based on the first algorithm information, and then perform calculations on the first test data based on the first algorithm.

[0074] Step 404: The second test response data from the first calculation module is processed by the second calculation module in the neural network processor to obtain the second test response data.

[0075] The algorithm corresponding to the second calculation module is the inverse of the algorithm corresponding to the first calculation module.

[0076] For example, when the algorithm corresponding to the first calculation module is a compression algorithm, the algorithm corresponding to the second calculation module is a decompression algorithm, which is the inverse of the compression algorithm; when the algorithm corresponding to the first calculation module is a encoding algorithm, the algorithm corresponding to the second calculation module is a decoding algorithm, which is the inverse of the encoding algorithm. This embodiment does not limit the specific algorithms corresponding to the first and second calculation modules.

[0077] For example, if the first test response data is the first calculation result, then the second test response data is the second calculation result.

[0078] For example, referring to FIG2, the second calculation module 222 can determine the corresponding second algorithm through the second algorithm information corresponding to the second calculation module 222 to calculate the first test response data, obtain the second test response data, and send the second test response data to the second input terminal of the comparator 223.

[0079] In some examples, referring to Figure 3, the second configuration circuit can also receive a second test configuration command, and in response to the second test configuration command, generate second algorithm information corresponding to the second calculation module 222, and send the second algorithm information to the second calculation module 222. Then, the second calculation module 222 can first determine the second algorithm based on the second algorithm information, and then perform calculations on the first test response data based on the second algorithm.

[0080] Step 405: Based on the first test data and the second test response data, determine the test results of the first calculation module and / or the second calculation module.

[0081] For example, test results may include test pass and test fail. Test pass may mean that the internal logic of the calculation module is correct. Test fail may mean that there is an anomaly in the internal logic of the calculation module.

[0082] For example, referring to FIG2, comparator 223 can compare the consistency of the first test data and the second test response data, and determine the test results of the first calculation module and / or the second calculation module based on the comparison results.

[0083] In this embodiment, since the algorithm corresponding to the first calculation module is the inverse of the algorithm corresponding to the second calculation module, after the first calculation module processes the first test data to obtain the first test response data, and then processes the first test response data through the second calculation module to obtain the second test response data, if both the first and second calculation modules are functioning normally, the second test response data output by the second calculation module will be consistent with the first test data. If the logic of the first and / or second calculation modules is malfunctioning, the second test response data output by the second calculation module will be inconsistent with the first test data. Therefore, based on the first test data and the second test response data, the test results of the first and / or second calculation modules can be accurately determined, enabling testing of different calculation modules. This expands the applicability of the TEST PATTERN scheme and improves testing efficiency.

[0084] As shown in Figure 5, based on the embodiment shown in Figure 4 above, step 402 may include the following steps 4021 and 4022.

[0085] Step 4021: In response to the enable information in the first configuration information being enabled for the first test, determine the data to be processed corresponding to the first computing module.

[0086] For example, enable information refers to information used to enable a first test or a second test on the first computing module. Its bit width can be 2 bits, meaning the enable information can include a first enable bit and a second enable bit. In some examples, the first enable bit and the second enable bit can be used to enable different circuits, and different states of the first enable bit and the second enable bit can correspond to enabling different tests on the first computing module. For example, referring to Figure 3, the first enable bit can be used to enable test circuit 213, and the second enable bit can be used to enable pseudo-random data generation circuit 2131 in test circuit 213. Furthermore, when the first enable bit is in an enabled state and the second enable bit is in an disabled state, it can correspond to enabling the first test on the first computing module; when both the first enable bit and the second enable bit are in an enabled state, it can correspond to enabling the second test on the first computing module.

[0087] For example, an enabled state can be represented by a first level (e.g., a high level "1") and an disabled state can be represented by a second level (e.g., a low level "0"). Alternatively, an enabled state can be represented by a second level and an disabled state by a first level. This disclosure does not limit the level of the enabled state. This disclosure uses an example of an enabled state represented by a first level and a disabled state represented by a second level for illustrative purposes.

[0088] For example, the first test enable may include enable information corresponding to the first test mode. Taking the bit width of the enable information as 2 bits as an example, in some examples, the first test enable may include "10" or "01".

[0089] For example, referring to FIG2, the test circuit 213 can acquire the data to be processed corresponding to the first computing module in response to the enable information being a first test enable.

[0090] Step 4022: Determine the first test data based on the data to be processed.

[0091] For example, referring to FIG2, test circuit 213 can determine the data to be processed as the first test data.

[0092] In this embodiment of the disclosure, when the first test enable instruction enables the first test of the first computing module, the first test is enabled in response to the enable information in the first configuration information. This allows the determination of the data to be processed corresponding to the first computing module in actual operation, and based on the data to be processed, the determination of the first test data corresponding to the actual working state of the first computing module. Therefore, based on this first test data, testing can be performed while the first computing module is working, which not only improves testing efficiency but also improves testing accuracy.

[0093] In some examples, the first configuration information may also include address information.

[0094] As shown in Figure 6, based on the embodiment shown in Figure 5 above, step 4021 may include the following steps 501 and 502.

[0095] Step 501: In response to the enable information being enabled for the first test, determine the read data address in the first configuration information.

[0096] For example, referring to FIG3, the first configuration circuit 211 can send enable information to the test circuit 213, and simultaneously send enable information and address information to the address generation circuit 214. In response to the enable information, the address generation circuit 214 enables the first test, generates a read data address and a write data address corresponding to the first calculation module 212 based on the address information, and sends the read data address to the address input of the first direct memory access circuit 215 through the read data address output terminal, and sends the write data address to the address input of the second direct memory access circuit 216 through the write data address output terminal.

[0097] Step 502: Read the data to be processed from the memory corresponding to the read data address.

[0098] For example, referring to FIG3, the first direct memory access circuit 215 can read the data to be processed from the corresponding direct memory access memory based on the read data address and send the data to be processed to the input of the buffer 2132.

[0099] In this embodiment of the disclosure, by responding to the first test enable information, the read data address in the first configuration information is determined, and thus, the data to be processed can be accurately read from the memory corresponding to the read data address.

[0100] In this embodiment of the disclosure, after the first direct memory access circuit 215 reads the data to be processed, it can send the data to be processed to the input of the buffer 2132. The buffer 2132 receives the data to be processed and sends the data to be processed to the second input of the selector 2133. At the same time, in response to the enable information being a first test enable, the test circuit 213 can enable the buffer 2132 and the selector 2133 in the test circuit 213, and disable the pseudo-random data generation circuit 2131 (the pseudo-random data generation circuit 2131 does not work, stops generating, and sends pseudo-random test data to the first input of the selector 2133).

[0101] In some examples, the first configuration information may also include a data selection signal. Referring to Figure 3, the first configuration circuit 211 is also used to send the first configuration information to the selector 2133.

[0102] Referring again to Figure 6, based on the embodiment shown in Figure 5 above, step 4022 may include the following step 503.

[0103] Step 503: In response to the data selection signal in the first configuration information being at the first level, the data to be processed is determined as the first test data.

[0104] For example, referring to FIG3, selector 2133 may select the data to be processed as the first test data in response to the data selection signal being at the first level, and send the first test data to the first input terminal of the first calculation module 212 and the comparator 223.

[0105] In this embodiment of the disclosure, by responding to the data selection signal in the first configuration information as a first level, the data to be processed is input as the first test data into the first computing module, which enables the testing of the first computing module while the first computing module is working, thereby improving testing efficiency.

[0106] For example, referring to FIG3, after the data to be processed is input into the first calculation module 212 as the first test data and the first test data is processed by the first calculation module 212 to obtain the first test response data, the second direct memory access circuit 216 can write the first test response data into the direct memory access memory corresponding to the write data address.

[0107] As shown in Figure 7, based on the embodiment shown in Figure 4 above, step 402 may include steps 4023 to 4025.

[0108] Step 4023: In response to the enable information in the first configuration information being enabled for the second test, determine the pseudo-random parameters in the first configuration information.

[0109] For example, the second test enable may include enable information corresponding to the second test method. Taking a bit width of 2 bits for the enable information as an example, in some examples, the second test enable may include "11".

[0110] For example, a pseudo-random parameter can be used to indicate the type of pseudo-random test data generated (different types of pseudo-random test data can be used to implement different functional tests). In some examples, the pseudo-random parameter may include data type and data length.

[0111] In some examples, as shown in Figure 3, the first configuration circuit 211 can generate pseudo-random parameters in response to a test configuration command and send the pseudo-random parameters to the pseudo-random data generation circuit 2131 in the test circuit 213.

[0112] In other examples, as shown in Figure 3, the first configuration information may include random test data, and the first configuration circuit 211 may send pseudo-random parameters to the pseudo-random data generation circuit 2131 at the same time as sending enable information to the test circuit 213.

[0113] Step 4024: Generate corresponding random test data based on pseudo-random parameters.

[0114] For example, referring to FIG3, the test circuit 213 can enable the pseudo-random data generation circuit 2131, the buffer 2132, and the selector 2133 in response to the enable information being a second test enable. The pseudo-random data generation circuit 2131 can generate corresponding pseudo-random test data in response to pseudo-random parameters and send the pseudo-random test data to the first input terminal of the selector 2133.

[0115] For example, referring to FIG3, the address generation circuit 214 may stop operating in response to the enable information being a second test enable (stop sending read data addresses to the first direct memory access circuit 215 and stop sending write data addresses to the second direct memory access circuit 216). The first direct memory access circuit 215 stops operating (stops sending data to be processed to the register 2132), and the second direct memory access circuit 216 also stops operating. The register 2132, not receiving data to be processed, sends empty data to the second input of the selector 2133.

[0116] Step 4025: Determine the first test data based on the random test data.

[0117] In this embodiment of the disclosure, random test data can be determined as the first test data in response to the data selection signal in the first configuration information being at the second level.

[0118] For example, referring to FIG3, selector 2133 may determine pseudo-random test data as first test data in response to the data selection signal being at the second level, and send the first test data to the first input terminal of the first calculation module 212 and comparator 223.

[0119] In this embodiment of the disclosure, by responding to the data selection signal in the first configuration information as the second level, random test data can be used as the first test data to realize the second test of the first computing module.

[0120] In this embodiment of the disclosure, by enabling the second test in response to the enable information in the first configuration information, pseudo-random parameters in the first configuration information are determined. Thus, when the pseudo-random parameters can accurately represent the target type of the random test data, random test data of the target type can be accurately generated based on the pseudo-random parameters. Furthermore, the first test data determined based on the random test data can achieve the testing of the target function of the first computing module.

[0121] As shown in Figure 8, based on the embodiment shown in Figure 4 above, step 405 may include the following steps 4051 to 4053.

[0122] Step 4051: Compare the first test data and the second test response data to obtain the comparison result.

[0123] For example, the comparison result may include whether the first test data and the second test response data are the same or different. In some examples, a first level may be used to indicate that the first test data and the second test response data are the same, and a second level may be used to indicate that the first test data and the second test response data are different.

[0124] For example, referring to Figure 2 or Figure 3, comparator 223 can compare the first test data and the second test response data to obtain a comparison result.

[0125] Step 4052: In response to the comparison result that the first test data and the second test response data are the same, it is determined that the internal logic of the first calculation module and the second calculation module is normal.

[0126] For example, if the comparison result is the first level, then it is determined that the logic of the first calculation module and the second calculation module is normal.

[0127] Step 4053: In response to the comparison result being different between the first test data and the second test response data, a logical anomaly is determined within the first calculation module and / or the second calculation module.

[0128] For example, if the comparison result is the second level, then it is determined that the logic of the first calculation module and / or the second calculation module is abnormal.

[0129] In this embodiment, since the algorithm corresponding to the first calculation module is inversely related to the algorithm corresponding to the second calculation module, by comparing the first test data and the second test response data input to the first calculation module, it is possible to accurately determine that the internal logic of the first and second calculation modules is normal when the first test data and the second test response data are the same, and to accurately determine that the internal logic of the first and / or second calculation modules is abnormal when the first test data and the second test response data are different. This improves the efficiency and accuracy of the testing.

[0130] Exemplary device

[0131] Based on the above embodiments, this disclosure provides a neural network processor. Figure 9 is a schematic diagram of the structure of another neural network processor provided in an exemplary embodiment of this disclosure. As shown in Figure 9, the neural network processor 90 may include a first configuration circuit 901, a test circuit 902, a first calculation module 903, a second calculation module 904, and a comparator 905.

[0132] The first configuration circuit 901 is coupled to the test circuit 902 and can be used to receive test configuration instructions, generate first configuration information corresponding to the first computing module in response to the first test configuration instructions, and send the first configuration information to the test circuit 902.

[0133] The test circuit 902, coupled to the first calculation module 903 and the comparator 905, can be used to determine the first test data based on the first configuration information, and to send the first test data to the first calculation module 903 and the comparator 905.

[0134] The first computing module 903 is coupled to the second computing module 904 and can be used to process the first test data and send the obtained first test response data to the second computing module 904.

[0135] The second calculation module 904, coupled to the comparator 905, can be used to process the first test response data and send the obtained second test response data to the comparator 905; the algorithm corresponding to the second calculation module 904 is the inverse of the algorithm corresponding to the first calculation module 903.

[0136] Comparator 905 can be used to determine the test results of the first calculation module and / or the second calculation module based on the first test data and the second test response data.

[0137] As shown in Figure 10, based on the embodiment shown in Figure 9 above, the neural network processor 90 may further include: an address generation circuit 906 and a first memory access circuit 907.

[0138] The first configuration circuit 901 is coupled to the address generation circuit 906 and can be used to send the first configuration information to the address generation circuit 906.

[0139] Address generation circuit 906, coupled to first memory access circuit 907, can be used to enable first test in response to enable information in first configuration information, determine read data address in first configuration information, and send read data address by first memory access circuit 907;

[0140] The first memory access circuit 907 is coupled to the test circuit 902 and can be used to read the data to be processed corresponding to the first computing module 903 from the memory corresponding to the read data address, and to send the data to be processed to the test circuit 902.

[0141] As shown in Figure 11, based on the embodiment shown in Figure 10 above, the test circuit 902 may include a pseudo-random data generation circuit 9021, a buffer 9022, and a selector 9023.

[0142] The pseudo-random data generation circuit 9021 is coupled to the first input terminal of the first configuration circuit 901 and the selector 9023, and can be used to enable the first test in response to the enable information in the first configuration information, and stop sending random test data to the selector 9023.

[0143] The buffer 9022 is coupled to the second input terminal of the first memory access circuit 907 and the selector 9023, and is used to receive and buffer the data to be processed.

[0144] Selector 9023, coupled to the first configuration circuit 901, is used to select to send data to be processed to the first calculation module 903 and comparator 905 in response to the data selection signal in the first configuration information being at the first level.

[0145] As shown in Figure 10, the address generation circuit 906 can be used to stop sending the read data address to the first memory access circuit 907 in response to the enable information in the first configuration information being enabled for the second test;

[0146] The first memory access circuit 907 is used to stop determining the data to be processed corresponding to the first calculation module 903 and to stop sending the data to be processed to the test circuit 902 in response to the failure to obtain the data read address.

[0147] As shown in Figure 11, based on the embodiment shown in Figure 10 above, the test circuit 902 may include a pseudo-random data generation circuit 9021, a buffer 9022, and a selector 9023.

[0148] The pseudo-random data generation circuit 9021 is coupled to the first input terminal of the first configuration circuit 901 and the selector 9023. It can be used to enable the second test in response to the enable information in the first configuration information, determine the pseudo-random parameters in the first configuration information, and generate random test data based on the pseudo-random parameters.

[0149] The buffer 9022, coupled to the second input of the first memory access circuit 907 and the selector 9023, can be used to determine that no data to be processed is buffered in response to the failure to acquire the data to be processed.

[0150] Selector 9023, coupled to the first configuration circuit, can be used to select to send random test data to the first calculation module 903 and comparator 9023 in response to the data selection signal in the first configuration information being at the second level.

[0151] Exemplary electronic devices

[0152] Figure 12 is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of the present disclosure. As shown in Figure 12, the electronic device 120 includes one or more processors 1201 and memory 1202.

[0153] The processor 1201 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 120 to perform desired functions.

[0154] The memory 1202 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1201 may execute the program instructions to implement the testing methods of the neural network processors of the various embodiments of this disclosure described above, and / or other desired functions.

[0155] In one example, the electronic device 120 may also include an input device 1203 and an output device 1204, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0156] Of course, for simplicity, only some of the components of the electronic device 120 relevant to this disclosure are shown in Figure 12, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 120 may include any other suitable components depending on the specific application.

[0157] Exemplary computer program products and computer-readable storage media

[0158] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the test methods for neural network processors according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0159] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0160] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the test methods of neural network processors according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0161] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0162] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0163] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A method for testing a neural network processor, the method comprising: Determine the first configuration information corresponding to the first computing module in the neural network processor; The first configuration information is used to configure the testing method of the first computing module; Based on the first configuration information, the first test data is determined; The first test data is processed by the first computing module in the neural network processor to obtain the first test response data; The second computing module in the neural network processor processes the first test response data from the first computing module to obtain the second test response data. The algorithm corresponding to the second calculation module is the inverse of the algorithm corresponding to the first calculation module; Based on the first test data and the second test response data, determine the test results of the first calculation module and / or the second calculation module.

2. The method according to claim 1, wherein, The step of determining the first test data based on the first configuration information includes: In response to the first test enable information in the first configuration information, the data to be processed corresponding to the first computing module is determined. Based on the data to be processed, the first test data is determined.

3. The method according to claim 2, wherein, The response to the enable information in the first configuration information is a first test enable, which determines the data to be processed corresponding to the first computing module, including: In response to the enable information being the first test enabled, the read data address in the first configuration information is determined; The data to be processed is read from the memory corresponding to the read data address.

4. The method according to claim 2, wherein, The step of determining the first test data based on the data to be processed includes: In response to the data selection signal in the first configuration information being at a first level, the data to be processed is determined as the first test data.

5. The method according to claim 1, wherein, The step of determining the first test data based on the first configuration information includes: In response to the enable information in the first configuration information being enabled for the second test, the pseudo-random parameters in the first configuration information are determined. Based on the pseudo-random parameters, generate corresponding random test data; Based on the random test data, the first test data is determined.

6. The method according to claim 5, wherein, The step of determining the first test data based on the random test data includes: In response to the data selection signal in the first configuration information being at the second level, the random test data is determined as the first test data.

7. The method according to any one of claims 1 to 6, wherein, The step of determining the test results of the first calculation module and / or the second calculation module based on the first test data and the second test response data includes: Compare the first test data and the second test response data to obtain the comparison result; In response to the comparison result showing that the first test data and the second test response data are the same, it is determined that the logic of the first calculation module and the second calculation module is normal; In response to the comparison result showing that the first test data and the second test response data are different, it is determined that the logic of the first calculation module and / or the second calculation module is abnormal.

8. A neural network processor, comprising: A first configuration circuit, coupled to a test circuit, is used to receive a test configuration command, generate first configuration information corresponding to the first computing module in response to the test configuration command, and send the first configuration information to the test circuit. The test circuit is coupled to the first calculation module and the comparator, and is used to determine the first test data based on the first configuration information, and to send the first test data to the first calculation module and the comparator. The first computing module, coupled to the second computing module, is used to process the first test data and send the obtained first test response data to the second computing module. The second calculation module, coupled to the comparator, is used to process the first test response data and send the obtained second test response data to the comparator. The algorithm corresponding to the second calculation module is the inverse of the algorithm corresponding to the first calculation module; The comparator is used to determine the test results of the first calculation module and / or the second calculation module based on the first test data and the second test response data.

9. The neural network processor according to claim 8, further comprising: Address generation circuit and first memory access circuit; The first configuration circuit is coupled to the address generation circuit and is used to send the first configuration information to the address generation circuit; The address generation circuit, coupled to the memory access circuit, is used to determine the read data address in the first configuration information in response to the enable information in the first configuration information being enabled for the first test, and to send the read data address to the first memory access circuit. The first memory access circuit, coupled to the test circuit, is used to read the data to be processed corresponding to the first computing module from the memory corresponding to the read data address, and to send the data to be processed to the test circuit.

10. The neural network processor according to claim 9, wherein, The test circuit includes: A pseudo-random data generation circuit, coupled to the first configuration circuit and the first input terminal of the selector, is used to stop sending random test data to the selector in response to the first test enable information in the first configuration information; A buffer, coupled to the memory access circuit and the second input of the selector, is used to receive and buffer the data to be processed. The selector, coupled to the first configuration circuit, is used to select to send the data to be processed to the first calculation module and the comparator in response to the data selection signal in the first configuration information being at a first level.

11. The neural network processor according to claim 9, wherein, The address generation circuit is configured to stop sending the read data address to the memory access circuit in response to the enable information in the first configuration information being enabled for the second test. The memory access circuit is configured to stop determining the data to be processed corresponding to the first computing module and stop sending the data to be processed to the test circuit in response to the failure to obtain the read data address.

12. The neural network processor according to claim 11, wherein, The test circuit includes: A pseudo-random data generation circuit, coupled to the first configuration circuit and the first input terminal of the selector, is used to respond to the enable information in the first configuration information as the second test enable, determine the pseudo-random parameters in the first configuration information, and generate random test data based on the pseudo-random parameters; A buffer, coupled to the memory access circuit and the second input of the selector, is used to determine that the data to be processed is not cached in response to the failure to acquire the data to be processed. The selector, coupled to the first configuration circuit, is used to select to send the random test data to the first calculation module and the comparator in response to the data selection signal in the first configuration information being at the second level.

13. A computer-readable storage medium storing a computer program for performing a test method for a neural network processor according to any one of claims 1-7.

14. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the test method of the neural network processor according to any one of claims 1-7.

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