Time synchronization device, time synchronization system, time synchronization method, and program

Abstract

This time synchronization device comprises: an internal clock and a slave clock; a frequency synchronization unit that synchronizes the frequency of the internal clock with the frequency of the clock of a time master apparatus; a calculation unit that calculates a downlink delay time, which is the time difference between a packet transmission time from the time master apparatus and a packet reception time stamped by the internal clock, and an uplink delay time, which is the time difference between a packet transmission time stamped by the internal clock and a packet reception time at the time master apparatus; a prediction unit that predicts the shortest downlink delay time on the basis of the calculated downlink delay time and predicts the shortest uplink delay time on the basis of the calculated uplink delay time; and a time synchronization unit that synchronizes the time of the slave clock with the time of the clock of the time master apparatus on the basis of the predicted shortest downlink delay time and the predicted shortest uplink delay time.

Description

Time synchronization device, time synchronization system, time synchronization method and program

[0001] The present disclosure relates to a time synchronization device, a time synchronization system, a time synchronization method, and a program.

[0002] As a protocol for time synchronization between devices, IEEE (Institute of Electrical and Electronics Engineers) 1588-2008 (IEEE1588v2) that defines the Precision Time Protocol (PTP) is known. As a related technique, for example, Patent Document 1 describes a technique for performing time synchronization with high precision in a time synchronization device that performs time synchronization using PTP without using a synchronous Ethernet signal (SyncE).

[0003] Patent No. 6198075

[0004] In Patent Document 1, time synchronization is performed using a correction value based on the shortest time of the downlink time difference (MTSD; Master to Slave Delay) and a correction value based on the shortest time of the uplink time difference (STMD; Slave to Master Delay). However, in Patent Document 1, since it takes time to obtain the shortest time, it is difficult to perform highly accurate time synchronization in a shorter time.

[0005] In view of the above problems, one of the objects of the present disclosure is to provide a time synchronization device, a time synchronization system, a time synchronization method, and a program that are capable of performing highly accurate time synchronization in a shorter period of time.

[0006] A time synchronization device according to one aspect of the present disclosure comprises an internal clock and a slave clock, a frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a clock of a time master device, a calculation means for calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, a prediction means for predicting a shortest downstream delay time based on the calculated downstream delay time and predicting a shortest upstream delay time based on the calculated upstream delay time, and a time synchronization means for synchronizing the time of the slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

[0007] A time synchronization system according to one aspect of the present disclosure comprises an internal clock and a slave clock, a frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a clock of a time master device, a calculation means for calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, a prediction means for predicting a shortest downstream delay time based on the calculated downstream delay time and predicting a shortest upstream delay time based on the calculated upstream delay time, and a time synchronization means for synchronizing the time of the slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

[0008] A time synchronization method according to one aspect of the present disclosure synchronizes the frequency of an internal clock with the frequency of a clock of a time master device, calculates a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, predicts the shortest downstream delay time based on the calculated downstream delay time, and predicts the shortest upstream delay time based on the calculated upstream delay time, and synchronizes the time of a slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

[0009] A program according to one aspect of the present disclosure is a program for causing a computer to execute a process of synchronizing the frequency of an internal clock with the frequency of a clock of a time master device, calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device, predicting a shortest downstream delay time based on the calculated downstream delay time, predicting a shortest upstream delay time based on the calculated upstream delay time, and synchronizing the time of a slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

[0010] According to the present disclosure, highly accurate time synchronization can be achieved in a shorter time.

[0011] FIG. 1 is a configuration diagram showing an example of the configuration of a time synchronization device according to a basic example. FIG. 2 is a configuration diagram showing an example of the configuration of a PTP frequency synchronization unit according to a basic example. FIG. 3 is a configuration diagram showing an example of the configuration of a packet filter processing unit according to a basic example. FIG. 4 is a configuration diagram showing an example of the configuration of a PTP time synchronization unit according to a basic example. FIG. 5 is a configuration diagram showing an example of the configuration of a time synchronization device according to some embodiments. FIG. 6 is a flowchart showing an example of a time synchronization method according to some embodiments. FIG. 7 is a configuration diagram showing an example of the configuration of a time synchronization system according to some embodiments. FIG. 8 is a configuration diagram showing an example of the configuration of a PDV filter according to some embodiments. FIG. 9 is a flowchart showing an example of the operation of a time slave device according to some embodiments. FIG. 10 is a graph showing an example of a histogram of delay times according to some embodiments. FIG. 11 is a configuration diagram showing an example of the configuration of computer hardware according to some embodiments.

[0012] Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same elements are given the same reference numerals, and duplicate explanations will be omitted as necessary. Note that the arrows shown in each drawing are examples for explanation purposes and do not limit the type or direction of signals.

[0013] (Basic Example) First, a basic example that forms the basis of the embodiment will be described.

[0014] 1 shows an example of the configuration of a time synchronization device 500 according to the basic example. The time synchronization device 500 is a time slave device that performs time synchronization with a time master device using PTP.

[0015] In PTP, a t1 packet (Sync Message), a t2 packet (Follow-up Message), a t3 packet (Delay Request Message), and a t4 packet (Delay Response Message) are transmitted and received between a time master device and a time slave device, and the times of these transmissions and receptions are used. A downstream delay time (MTSD) is calculated from the difference between the time (t1) when the time master device transmits the t1 packet and the time (t2) when the time slave device receives the t1 packet, and an upstream delay time (STMD) is calculated from the difference between the time (t3) when the time slave device transmits the t3 packet and the time (t4) when the time master device receives the t3 packet, and time synchronization is performed based on these delay times.

[0016] The basic example is an example based on Patent Document 1, and has an internal clock that is frequency-synchronized with the time master device on the sending side, and although there is a time offset with the sending clock, it is used under conditions where frequency synchronization is established. Therefore, even if the internal clock is used to time input and output packets, delays cannot be determined, but it is possible to determine whether the packet arrival time is earlier or later than the previous value.

[0017] In the example of FIG. 1 , the time synchronization device 500 includes a PTP frequency synchronization unit 600 , a packet filter processing unit 700 , and a PTP time synchronization unit 800 .

[0018] The PTP frequency synchronization unit 600 is a PTP frequency servo that performs frequency synchronization with the time master device.

[0019] In the example of FIG. 2, the PTP frequency synchronization unit 600 includes a t2′ packet time stamp unit 610, a phase detector (PD) 620, an infinite impulse response (IIR) filter 630, a phase interpolation (PI) controller 640, and an internal clock 650.

[0020] The PTP frequency synchronization unit 600 controls the operation of the internal clock 650 with a PLL (Phase Locked Loop) using a phase comparator 620, an IIR filter 630, and a PI controller 640 so that the time difference (t2'-t1) between the packet transmission time (t1) from the time master device and the packet reception time (t2') stamped by the t2' packet stamping unit 610 using the internal clock 650 is constant. In other words, the PTP frequency synchronization unit 600 synchronizes the frequency of the output signal (time) of the internal clock 650 with the frequency of the output signal (time) of the time master device.

[0021] The packet filter processing unit 700 constitutes a packet delay variation (PDV) filter that determines packet delay variation using the time of the frequency-synchronized internal clock 650. The PTP frequency synchronization unit 600, packet filter processing unit 700, and PTP time synchronization unit 800 may be collectively referred to as the PDV filter. Fig. 3 shows an example of the configuration of the packet filter processing unit 700.

[0022] In the example of Figure 3, the packet filter processing unit 700 includes a t1 packet receiving unit 710, a Follow-up Message (t2 packet) receiving unit 711, a t3 packet transmitting unit 712, a t4 packet receiving unit 713, a t2' packet embossing unit 730, a t2'-t1 calculation unit 731, a t2'-t1 shortest time search and holding unit 732, a t2'-t1 correction unit 733, a t1 correction value update unit 734, a t3' packet embossing unit 740, a t4-t3' calculation unit 741, a t4-t3' shortest time search and holding unit 742, a t4-t3' correction unit 743, and a t4 correction value update unit 744.

[0023] The packet filter processing unit 700 corrects the packet transmission time (t1) based on the shortest time difference (t2'-t1; MTSD') between the packet transmission time (t1) from the time master device and the packet reception time (t2') stamped by the t2' packet stamping unit 730 using the internal clock 650. Specifically, the t2'-t1 shortest time search and storage unit 732 searches for the shortest time from the time difference (t2'-t1) calculated by the t2'-t1 calculation unit 731 and stores it. The t2'-t1 shortest time search and storage unit 732 separates and outputs the stored shortest time (min PDV) and other times (other min PDV). The t2'-t1 correction unit 733 generates a correction value for the downlink time based on the result of the t2'-t1 shortest time search and storage unit 732. The t2'-t1 correction unit 733 calculates a correction value from the difference between the shortest time (min PDV) and the time other than the shortest time (other min PDV) of the time difference (t2'-t1). The t1 correction value update unit 734 adds the correction value to the Correction Field of the t1 packet.

[0024] The packet filter processing unit 700 also corrects the packet reception time (t4) based on the shortest time difference (t4-t3'; STMD') between the packet transmission time (t3') stamped by the t3' packet stamping unit 740 using the internal clock 650 and the packet reception time (t4) at the time master device. Specifically, the t4-t3' shortest time search and storage unit 742 searches for and stores the shortest time from the time difference (t4-t3') calculated by the t4-t3' calculation unit 741. The t4-t3' shortest time search and storage unit 742 separates and outputs the stored shortest time (min PDV) and other times (other min PDV). The t4-t3' correction unit 743 generates a correction value for the uplink time based on the results of the t4-t3' shortest time search and storage unit 742. The t4-t3' correction unit 743 calculates a correction value from the difference between the shortest time (min PDV) and the time other than the shortest time (other min PDV) of the time difference (t4-t3'). The t4 correction value update unit 744 adds the correction value to the Correction Field of the t4 packet.

[0025] The PTP time synchronization unit 800 is a PTP time servo that performs time synchronization with the time master device. FIG. 4 shows an example of the configuration of the PTP time synchronization unit 800.

[0026] In the example of Figure 4, the PTP time synchronization unit 800 includes an OCXO (Oven Controlled Crystal Oscillator) 810, a slave clock 820, a t2 packet time-stamping unit 830, a t2-t1 calculation unit 831, a t3 packet time-stamping unit 832, a t4-t3 calculation unit 833, a complementation unit 834, an adder 835, and a PI controller 836.

[0027] The PTP time synchronization unit 800 calculates a downstream delay time (t2-t1; MTSD) from the packet transmission time (t1) corrected by the packet filter processing unit 700 and the packet reception time (t2) stamped by the t2 packet stamping unit 830 using the slave clock 820, and calculates an upstream delay time (t4-t3; STMD) from the packet transmission time (t3) stamped by the slave clock 820 and the packet reception time (t4) corrected by the packet filter processing unit 700 using the complementation unit 834, adder 835, and PI controller 836 to PLL-control the operation of the slave clock 820 so that the downstream delay time (t4-t3) and the upstream delay time (t2-t1) are equal. In other words, the PTP time synchronization unit 800 synchronizes the output signal (time) of the slave clock 820 with the output signal (time) of the time master device.

[0028] In this way, in the basic example, frequency synchronization is performed before time synchronization, and an internal clock is generated from the reproduced frequency. The internal clock then stamps the packet arrival time (t2') and packet transmission time (t3'). Based on the shortest MTSD' and shortest STMD' times, the difference between MTSD' and t2' calculated from the packet transmitted each time and the difference between MTSD' and STMD' is stored in the Correction Field area of ​​IEEE 1588-2008, and time synchronization is performed using the shortest delay time.

[0029] However, in the basic example, the shortest MTSD' and STMD' times are searched for and the stored shortest times are repeatedly updated each time a packet is transmitted or received. Therefore, the basic example has a problem in that an enormous amount of time is spent to obtain the shortest times. Therefore, in the embodiment, based on the configuration of the basic example, it is possible to reduce the time required to obtain the shortest times for MTSD' and STMD'.

[0030] Furthermore, while the basic example can be applied to both wired and wireless time synchronization, wireless time synchronization presents its own set of challenges. Wireless time synchronization methods include those using wireless devices such as wireless LANs, using a time synchronization protocol conforming to IEEE 1588-2008, as described above. However, unlike wired connections, this method suffers from delay fluctuations specific to wireless communication. As a result, while time synchronization is possible, the accuracy is limited to milliseconds. There are two specific challenges. The first is the delay fluctuations inherent to wireless communication. The causes of this fluctuation vary depending on usage conditions, including delays due to interference with other wireless networks and reflections from structures. The second is that software processing is used to modulate wireless signals, and while this also has a constant processing sequence, in the case of half-duplex communication, random time periods such as backoff times are inserted, meaning the delay is not always constant. In addition, the software processing clock is asynchronous.

[0031] (First Embodiment) Next, a first embodiment will be described. In this embodiment, an outline of several embodiments will be described.

[0032] 5 shows an example of the configuration of a time synchronization device 10 according to some embodiments. The time synchronization device 10 is a time slave device (time slave device) that performs time synchronization with a time master device (time master device). The time synchronization device 10 is, for example, a wireless time synchronization device that performs wireless communication with the time master device, but it may also be a wired time synchronization device that performs wired communication with the time master device.

[0033] 5 , the time synchronization device 10 includes an internal clock 11, a slave clock 12, a frequency synchronization unit 13, a calculation unit 14, a prediction unit 15, and a time synchronization unit 16. For example, the internal clock 11 is included in the frequency synchronization unit 13. The slave clock 12 is included in the time synchronization unit 16.

[0034] The frequency synchronization unit 13 synchronizes the frequency of the internal clock 11 with the frequency of the clock of the time master device. For example, the frequency synchronization unit 13 corresponds to the PTP frequency synchronization unit 600.

[0035] The calculation unit 14 calculates a downstream delay time (MTSD') which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock 11, and an upstream delay time (STMD') which is the time difference between the packet transmission time stamped by the internal clock 11 and the packet reception time at the time master device. For example, the calculation unit 14 corresponds to the packet filter processing unit 700.

[0036] The prediction unit 15 predicts the shortest downlink delay time based on the downlink delay time calculated by the calculation unit 14, and predicts the shortest uplink delay time based on the uplink delay time calculated by the calculation unit 14. The prediction unit 15 may acquire multiple calculated downlink delay times, perform statistical processing on the multiple downlink delay times, and predict the shortest downlink delay time based on the results of the statistical processing, and may also acquire multiple calculated uplink delay times, perform statistical processing on the multiple uplink delay times, and predict the shortest uplink delay time based on the results of the statistical processing. The time synchronization device 10 may include a statistical processing unit that performs these statistical processes. For example, the prediction unit 15 may generate a statistical distribution of multiple downlink delay times and predict the shortest downlink delay time from the statistical distribution using the least squares method, and may generate a statistical distribution of multiple uplink delay times and predict the shortest uplink delay time from the statistical distribution using the least squares method. The prediction unit 15 may predict the shortest time using methods other than the least squares method.

[0037] The time synchronization unit 16 synchronizes the time of the slave clock 12 with the time of the clock of the time master device based on the shortest downstream delay time and the shortest upstream delay time predicted by the prediction unit 15. For example, the time synchronization unit 16 corresponds to the PTP time synchronization unit 800.

[0038] The time synchronization device 10 may also include a correction unit that corrects the packet transmission time from the time master device based on the shortest downstream delay time predicted by the prediction unit 15, and corrects the packet reception time at the time master device based on the shortest upstream delay time predicted by the prediction unit 15. In this case, the time synchronization unit 16 may synchronize the time of the slave clock with the time of the clock of the time master device based on the corrected packet transmission time from the time master device and the corrected packet reception time at the time master device. For example, the correction unit may calculate a correction value for correcting the packet transmission time from the time master device based on the downstream delay time calculated by the calculation unit 14 and the shortest downstream delay time predicted by the prediction unit 15, and may calculate a correction value for correcting the packet reception time at the time master device based on the upstream delay time calculated by the calculation unit 14 and the shortest upstream delay time predicted by the prediction unit 15. In addition, the correction unit may calculate a correction value to correct the packet transmission time from the time master device based on the downlink delay time calculated by the calculation unit 14 and the provisional shortest downlink delay time, and may calculate a correction value to correct the packet reception time at the time master device based on the uplink delay time calculated by the calculation unit 14 and the provisional shortest uplink delay time, and may reflect the predicted shortest downlink delay time in the provisional shortest downlink delay time according to the prediction by the prediction unit 15, and may reflect the predicted shortest downlink delay time in the provisional shortest uplink delay time.

[0039] Note that each unit in the time synchronization device 10 may be included in one device or multiple devices, or may be included in a time synchronization system including one device or multiple devices. That is, a time synchronization system may include the internal clock 11, the slave clock 12, the frequency synchronization unit 13, the calculation unit 14, the prediction unit 15, and the time synchronization unit 16. The units in the time synchronization device 10 may be distributed. For example, the time synchronization device 10 may include the internal clock 11, the slave clock 12, the frequency synchronization unit 13, the calculation unit 14, and the time synchronization unit 16, and another prediction device may include the prediction unit 15.

[0040] 6 shows an example of a time synchronization method according to some embodiments. For example, the time synchronization method according to some embodiments is performed by the time synchronization device 10 of FIG.

[0041] 6, first, the frequency synchronization unit 13 synchronizes the frequency of the internal clock 11 with the frequency of the clock of the time master device (S11). For example, the frequency synchronization unit 13 performs frequency synchronization with the time master device in the same manner as the PTP frequency synchronization unit 600.

[0042] Next, the calculation unit 14 calculates a downstream delay time (MTSD') which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock 11, and an upstream delay time (STMD') which is the time difference between the packet transmission time stamped by the internal clock 11 and the packet reception time at the time master device (S12). For example, the calculation unit 14 calculates MTSD' and STMD' in the same way as the packet filter processing unit 700.

[0043] Next, the prediction unit 15 predicts the shortest delay time in the downlink direction based on the calculated delay time in the downlink direction, and predicts the shortest delay time in the uplink direction based on the calculated delay time in the uplink direction (S13). For example, the prediction unit 15 predicts the shortest delay time in the downlink direction and the shortest delay time in the uplink direction from a statistical distribution such as a histogram obtained by statistically processing the delay times in the downlink direction and the uplink direction, using the least squares method or the like.

[0044] Next, the time synchronization unit 16 synchronizes the time of the slave clock with the time of the clock of the time master device based on the predicted shortest delay time in the downstream direction and the shortest delay time in the upstream direction (S14). For example, like the PTP time synchronization unit 800, the time synchronization unit 16 performs time synchronization with the time master device using the time corrected based on the predicted shortest delay time in the downstream direction and the shortest delay time in the upstream direction.

[0045] As described above, in this embodiment, a time synchronization device based on the configuration of the basic example is provided with a prediction unit that predicts the shortest downlink delay time (MTSD') and the shortest uplink delay time (STMD'). For example, by predicting the shortest time from a statistical distribution such as a histogram obtained by statistically processing delay times, the time required to obtain the shortest time can be reduced, enabling highly accurate time synchronization to be performed in a shorter time. In particular, in wireless time synchronization, the shortest wireless uplink and downlink delay times can be predicted, allowing wireless fluctuations to be corrected in a shorter time.

[0046] Second Embodiment Next, a second embodiment will be described. In this embodiment, a specific example of the first embodiment will be described.

[0047] Fig. 7 shows an example of the configuration of a time synchronization system 1 according to some embodiments. In the example of Fig. 7, the time synchronization system 1 includes a time slave device 100 and a time master device 200. The time synchronization system 1 is a system that performs time synchronization by PTP between the time slave device 100 and the time master device 200. In this example, the time slave device 100 and the time master device 200 are wireless communication devices capable of wireless communication, but may also be wired communication devices capable of wired communication.

[0048] The time master device 200 is a time synchronization device that operates as a master in PTP time synchronization. The time master device 200 includes a wireless communication unit 201. The wireless communication unit 201 performs wireless communication with the time slave device 100, for example, via Wi-Fi 6 (IEEE802.11ax). The wireless communication unit 201 is not limited to Wi-Fi 6, and may perform wireless communication via other wireless communication standards such as other wireless LANs, carrier wireless such as LTE (Long Term Evolution) or 5G, or Bluetooth. The time master device 200 transmits and receives PTP packets to and from the time slave device 100 via a wireless transmission path via the wireless communication unit 201.

[0049] The time slave device 100 is a time synchronization device that operates as a slave in PTP time synchronization. The time slave device 100 includes a wireless communication unit 101, a PDV filter 110, a statistical processing unit 120, and a prediction unit 130. The statistical processing unit 120 and the prediction unit 130 are not limited to being located inside the time slave device 100, but may also be located outside the time slave device 100. For example, the statistical processing unit 120 and the prediction unit 130 may be located in a cloud-based computer system.

[0050] The wireless communication unit 101 performs wireless communication with the time master device 200, for example, via Wi-Fi 6. Like the time master device 200, the wireless communication unit 101 may perform wireless communication according to other wireless communication standards, not limited to Wi-Fi 6. The time slave device 100 transmits and receives PTP packets to and from the time master device 200 via the wireless transmission path via the wireless communication unit 101.

[0051] The PDV filter 110 is a time synchronization unit that includes a packet filter, similar to the basic example in Fig. 1. As will be described later, the PDV filter 110 includes a PTP frequency synchronization unit 600, a packet filter processing unit 700, and a PTP time synchronization unit 800, similar to the basic example.

[0052] The PDV filter 110 loads the time of the t1 packet into the internal clock 650 and synchronizes the frequency of the internal clock 650 with the frequency of the time master device 200. The PDV filter 110 calculates the time difference (MTSD') between the packet transmission time (t1) from the time master device 200 and the packet reception time (t2') stamped by the internal clock 650, and stores a provisional MTSD' (shortest time). It also calculates the time difference (STMD') between the packet transmission time (t3') stamped by the internal clock 650 and the packet reception time (t4) at the time master device 200, and stores a provisional STMD' (shortest time). The PDV filter 110 outputs the calculated MTSD' and STMD' to the statistical processing unit 120, and obtains the shortest MTSD' and STMD' predicted by the prediction unit 130. The PDV filter 110 reflects the predicted shortest time of MTSD' and the shortest time of STMD' in the provisional MTSD' and STMD', calculates correction values ​​for MTSD and STMD to be stored in the Correction Field, and performs time synchronization with the time master device 200.

[0053] The statistical processing unit 120 performs statistical processing on the MTSD' and STMD' calculated by the PDV filter 110. The statistical processing unit 120 performs data processing required for the prediction by the prediction unit 130. For example, the statistical processing unit 120 statistically distributes the MTSD' and STMD', respectively, and generates histograms of the MTSD' and STMD'. The statistical processing unit 120 is provided with, for example, a database, stores a plurality of MTSD's and STMD's in the database, and generates a histogram using the stored MTSD's and STMD's.

[0054] The prediction unit 130 predicts the shortest times of MTSD' and STMD' based on the results of statistical processing of MTSD' and STMD' by the statistical processing unit 120. For example, the prediction unit 130 predicts the shortest times of MTSD' and STMD' using the least squares method on histograms of MTSD' and STMD'. The prediction of the shortest times is not limited to the least squares method, and maximum likelihood method, machine learning, etc. may also be used. For example, time-series data of MTSD' and STMD' and the shortest times of MTSD' and STMD' may be machine-learned, and the shortest times of MTSD' and STMD' may be input into the trained model to predict the shortest times of MTSD' and STMD'. The prediction unit 130 outputs the predicted shortest times of MTSD' and STMD' to the PDV filter 110, and updates the PDV values ​​(provisional MTSD' and STMD') that serve as the references for the PDV filter 110. The prediction unit 130 may predict the shortest time of MTSD' and the shortest time of STMD' based on the corrected values ​​of MTSD and STMD.

[0055] 8 shows an example of the configuration of the PDV filter 110 according to some embodiments, and in particular shows an example of the configuration of the packet filter processing unit 700. The PDV filter 110 includes a PTP frequency synchronization unit 600, a packet filter processing unit 700, and a PTP time synchronization unit 800, similar to the basic example in FIG.

[0056] The PTP frequency synchronization unit 600 has the same configuration as that shown in FIG. 2 , and the PTP time synchronization unit 800 has the same configuration as that shown in FIG. 4 . As described above, the PTP frequency synchronization unit 600 and the PTP time synchronization unit 800 each have an internal clock 650 and a slave clock 820 as independent clocks (PTP Epoch Counters). The reason for having independent clocks is that each clock has a different purpose. As described above, the internal clock 650 of the PTP frequency synchronization unit 600 is a clock used to determine the quality of received packets, and is generated based on the jitter-wonder-free clean clock output from the OCXO 810. As its name suggests, the slave clock 820 of the PTP time synchronization unit 800 is a clock used to synchronize the time with the master time. The slave clock 820 is a so-called time synchronization clock and serves as a clock within the device.

[0057] 8, the packet filter processing unit 700 is equipped with a t2'-t1 shortest time acquisition and retention unit 732a and a t4-t3' shortest time acquisition and retention unit 742a instead of the t2'-t1 shortest time search and retention unit 732 and the t4-t3' shortest time search and retention unit 742 in comparison with FIG. 3. The other configurations are the same as those in FIG. 3.

[0058] The basic operation of the packet filter processing unit 700 will be described. First, in the downstream direction, the t1 packet receiving unit 710 receives a Sync message (t1 packet) from the time master device 200. The t2' packet stamping unit 730 stamps the time at which the t1 packet receiving unit 710 receives the t1 packet using the internal clock 650 generated by the PTP frequency synchronization unit 600, and sets this time as t2' time. The t2'-t1 calculation unit 731 obtains the t1 time from the Follow-up Message received by the Follow-up Message receiving unit 711, and calculates the difference between the stamped t2' time and the obtained t1 time (t2'-t1; MTSD').

[0059] In this embodiment, the 2-step method, which is common in IEEE1588v2, is used for explanation, and the value obtained from the Follow-up Message by the Follow-up Message receiving unit 711, which is the true time of t1, is used as the t1 time. Note that this embodiment is not limited to either the 1-step method or the 2-step method. The 1-step method is the same as the 2-step method, except that information about the t1 time is included in the t1 packet.

[0060] The t2'-t1 calculation unit 731 outputs the calculated t2'-t1 (MTSD') to the t2'-t1 shortest time acquisition and retention unit 732a and the statistical processing unit 120. The t2'-t1 shortest time acquisition and retention unit 732a retains the provisional MTSD' (shortest time), separates the retained shortest time (min PDV) from times other than the shortest (other min PDV; for example, the calculated MTSD'), and outputs the separated results to the t2'-t1 correction unit 733. The t2'-t1 shortest time acquisition and retention unit 732a may provisionally find the shortest time from the MTSD' calculated by the t2'-t1 calculation unit 731 and retain it, as in the basic example. In addition, the t2'-t1 shortest time acquisition and retention unit 732a acquires the shortest time of the MTSD' predicted by the prediction unit 130 and reflects it in the provisional MTSD'.

[0061] The t2'-t1 correction unit 733 (downstream time correction unit) calculates a correction value for MTSD based on the shortest MTSD' time (provisional MTSD') and a time other than the shortest time output from the t2'-t1 shortest time acquisition and holding unit 732a. The t2'-t1 correction unit 733 uses the difference between the shortest MTSD' time (provisional MTSD') and a time other than the shortest time as a correction value. The t1 correction value update unit 734 adds the correction value calculated by the t2'-t1 correction unit 733 to the Correction Field of the t1 packet.

[0062] In the upstream direction, the t3' packet stamping unit 740, as in the downstream direction, stamps the transmission time of the t3 packet transmitted from the PTP time synchronization unit 800 using the internal clock 650 generated by the PTP frequency synchronization unit 600, and sets this time as the t3' time. The stamped t3' time is used only by the packet filter processing unit 700, and is not overwritten on the t3 time in the original t3 packet. Therefore, the t3 packet transmitting unit 712 transmits the packet from the PTP time synchronization unit 800 as a Delay Request Message (t3 packet) to the time master device 200 as is.

[0063] The t4 packet receiver 713 receives a t4 (Delay Response Message) packet transmitted from the time master device 200. The t4-t3' calculation unit 741 acquires the t4 time from the t4 packet received by the t4 packet receiver 713, and calculates the difference between the acquired t4 time and the stamped t3' time (t4-t3'; STMD').

[0064] The t4-t3' calculation unit 741 outputs the calculated t4-t3' (STMD') to the t4-t3' shortest time acquisition and retention unit 742a and the statistical processing unit 120. The t4-t3' shortest time acquisition and retention unit 742a retains the provisional STMD' (shortest time), separates the retained shortest time (min PDV) from other times (other min PDV; for example, the calculated STMD'), and outputs the separated results to the t4-t3' correction unit 743. The t4-t3' shortest time acquisition and retention unit 742a may provisionally find the shortest time from the STMD' calculated by the t4-t3' calculation unit 741 and retain it, as in the basic example. In addition, the t4-t3' shortest time acquisition and retention unit 742a acquires the shortest time of the STMD' predicted by the prediction unit 130 and reflects it in the provisional STMD'.

[0065] The t4-t3' correction unit 743 (upstream time correction unit) calculates a correction value for the STMD based on the shortest time of STMD' (provisional STMD') and a time other than the shortest time output from the t4-t3' shortest time acquisition and holding unit 742a. ​​The t4-t3' correction unit 743 uses the difference between the shortest time of STMD' (provisional STMD') and a time other than the shortest time as a correction value. The t4 correction value update unit 744 adds the correction value calculated by the t4-t3' correction unit 743 to the Correction Field of the t4 packet.

[0066] As described above, by acquiring the shortest time packet using the packet filter processing unit 700 and correcting the time based on that packet, the difference in delay between upstream and downstream can be minimized, and as a result, highly accurate time accuracy can be achieved. Furthermore, the shortest time packet can be constantly updated. Therefore, the time accuracy does not deteriorate from the previous time, and in this embodiment, the accuracy always improves. Here, the reason why the difference in delay between upstream and downstream is minimized when the shortest time packet is acquired is because the shortest time packet accurately reflects the network propagation delay.

[0067] This embodiment is characterized not by the acquisition of the shortest time packet itself, but by the correction method after acquisition and the method for updating the shortest time packet. That is, this embodiment predicts the shortest delay time in order to shorten the calculation time until fluctuations caused by factors such as delay fluctuations specific to wireless, variations in wireless devices, and processing errors in wireless transmission / reception control software stabilize. For example, by predicting the shortest value using the least squares method based on the downlink correction value obtained by the t2'-t1 correction unit 733 and the uplink correction value obtained by the t4-t3' correction unit 743, it is possible to shorten the time required to calculate the stabilization time, typically on the order of one month or one week, to just a few days, thereby achieving the same shortest delay time as a wired connection, despite being wireless.

[0068] From the above explanation, the t2' packet stamping unit 730 and t3' packet stamping unit 740 of the packet filter processing unit 700 require a clock that is frequency-synchronized with the time master device 200 and is jitter- and wander-free. The reason for this is that if they are not frequency-synchronized, errors will occur in each stamped time, and if there is jitter or wander, the wrong time will be stamped even if frequency-synchronized. As a result, the shortest time packet cannot be obtained accurately, and the packet filter cannot function properly.

[0069] This problem can be solved by using SyncE, but it is not feasible because SyncE cannot be used in a wireless network. Therefore, this embodiment adopts a frequency synchronization method based on wireless packets instead of SyncE.

[0070] Specifically, similar to the basic example, frequency synchronization with the time master device and jitter- and wonder-free clock reproduction are achieved by implementing a PTP frequency synchronization unit 600. The configuration of the PTP frequency synchronization unit 600 is as shown in FIG.

[0071] The basic operation of the PTP frequency synchronization unit 600 will be described. First, the t2' packet stamping unit 610 stamps the time when the t1 packet is received by the t1 packet receiving unit 710 using the internal clock 650, and designates this time as t2'. Next, the phase comparator 620 extracts the t1 time from the follow-up message received by the follow-up message receiving unit 711 and compares the t1 time with the t2' time (i.e., performs a phase comparison). The phase comparator 620 can also be said to compare the t1 time with the time (=phase) from a time counter (internal clock 650) comprised of a DCO (digital oscillator). The differential signal resulting from this comparison is filtered by the IIR filter 630, which removes jitter and noise to produce a smoothed differential signal. The smoothed differential signal is then proportionally and integrally processed by the PI controller 640, which outputs the resulting control signal to the DCO in the internal clock 650, ultimately converging the differential signal to a constant value. This allows frequency synchronization to be achieved.

[0072] The master oscillator (clock CLK) of the DCO in the internal clock 650 is an external OCXO 810. The reason for using an OCXO is that by minimizing the frequency drift of the DCO, it becomes possible to lower the DC loop gain of the PTP frequency synchronization unit 600, thereby enabling the reproduction of a highly accurate clock. Why a DCO is used, why PI control is necessary, and the PI control method for the DCO are all the same as for a normal digital PLL.

[0073] The PTP time synchronization unit 800 has a general configuration for performing time synchronization by PTP. For example, the configuration of the PTP time synchronization unit 800 is as shown in FIG.

[0074] The basic operation of the PTP time synchronization unit 800 will be described. First, a slave clock 820 is constructed based on the clock CLK of the OCXO 810, which is the reference oscillation source. The t2 packet stamping unit 830 stamps the time when the t1 packet receiving unit 710 receives the t1 packet using the slave clock 820, and sets this time as t2 time. After receiving the t1 packet, the t3 packet stamping unit 832 stamps the time when the t3 packet is transmitted using the slave clock 820, and sets this time as t3 time. The t3 packet stamping unit 832 inserts this time into the t3 packet, and transmits it from the t3 packet transmitting unit 712 to the time master device 200.

[0075] The t2-t1 calculation unit 831 obtains the time t1 from the Follow-up Message received by the Follow-up Message receiving unit 711, and calculates the difference (t2-t1; MTSD) between the stamped time t2 and the obtained time t1. At this time, the t2-t1 calculation unit 831 calculates the time difference using the Correction Field of the t1 packet updated by the packet filter processing unit 700.

[0076] The t4-t3 calculation unit 833 acquires the t4 time from the t4 packet received by the t4 packet receiving unit 713, and calculates the difference between the acquired t4 time and the stamped t3 time (t4-t3; STMD). At this time, the t4-t3 calculation unit 833 calculates the time difference using the Correction Field of the t4 packet updated by the packet filter processing unit 700.

[0077] In order to perform PLL control so that the values ​​of t2-t1 (MTSD) and t4-t3 (STMD) are the same, the two's complement of STMD (-STMD) is calculated by a complementing unit 834, and MTSD and -STMD are added by an adder 835. The result of the addition is subjected to proportional and integral processing by a PI controller 836, and the digital oscillator (DCO) in the slave clock 820 is PLL-controlled based on the phase (time) data generated by the PI controller 836. This series of processes is known as time servo processing in PTP.

[0078] 9 shows an example of the operation of the time slave device 100 according to some embodiments. In the example of FIG. 9, the time slave device 100 provisionally loads the internal clock 650 with a t1 packet (S101). First, the t1 packet receiver 710 receives the t1 packet from the time master device 200 and sets the time (timestamp) of the received t1 packet in the internal clock 650.

[0079] Next, the time slave device 100 operates the PDV filter 110 to acquire provisional MTSD' and STMD' (provisional PDV values) (S102). The t2'-t1 shortest time acquisition and retention unit 732a and the t4-t3' shortest time acquisition and retention unit 742a provisionally select the shortest MTSD' and STMD' values ​​from the MTSD' and STMD' values ​​calculated by the t2'-t1 calculation unit 731 and the t4-t3' calculation unit 741. For example, the initial values ​​of provisional MTSD' and STMD' may be the values ​​calculated initially or the shortest time within a predetermined period of time. The t2'-t1 shortest time acquisition and retention unit 732a and the t4-t3' shortest time acquisition and retention unit 742a retain the selected provisional MTSD' and STMD' values. The packet filter processing unit 700 determines the MTSD correction value and the STMD correction value using the retained provisional MTSD' and STMD' as the shortest time, and the PTP time synchronization unit 800 performs time synchronization using the MTSD correction value and the STMD correction value.

[0080] Next, the time slave device 100 waits until the PTP time servo is synchronized (S103). The time slave device 100 waits until the time synchronization is stable in order to start statistical processing. For example, the time slave device 100 may wait until the proportional term of the transfer function in the PLL control of the PTP time servo (PTP time synchronization unit 800) becomes zero. For example, the time slave device 100 may include a storage unit that stores a synchronization flag, and may set the synchronization flag to ON when the PTP time servo is synchronized.

[0081] Next, the time slave device 100 statistically processes the variations in the MTSD' and STMD' (S104). After the PTP time servo is synchronized (e.g., after the synchronization flag is turned on), the statistical processing unit 120 acquires the multiple MTSD's and STMD's calculated by the PDV filter 110 and generates a statistical distribution for the acquired multiple MTSD's and STMD's. For example, the statistical processing unit 120 generates a histogram of MTSD's and a histogram of STMD's as the statistical distribution. The statistical processing unit 120 may generate the histograms from the MTSD's and STMD's acquired over a period of, for example, about 10 minutes, but the time period for acquiring the data is not limited. FIG. 10 shows an example of the generated histogram. In the example of FIG. 10, the horizontal axis represents the delay time (MTSD' or STMD'), and the vertical axis represents the number of delay time data points. Note that the delay time may be a correction value for MTSD or a correction value for STMD.

[0082] Next, the time slave device 100 predicts the shortest times of MTSD' and STMD' based on the results of the statistical processing (S105). The prediction unit 130 predicts the shortest time of MTSD' from the histogram of MTSD', and predicts the shortest time of STMD' from the histogram of STMD'. For example, the prediction unit 130 predicts the shortest time of delay time using the least squares method for the histogram generated as shown in FIG. 10. That is, an approximation curve is obtained using the least squares method from the histogram data, and the shortest time (P1) is estimated based on the approximation curve. Data D1 in the figure is actually the shortest delay time. Eventually, the shortest delay time (shortest correction value) equivalent to the predicted value P1 can be obtained by multiplying the time. However, in this embodiment, the shortest delay time (shortest correction value) is predicted early using the least squares method from the delay time (correction value) obtained by the packet filter processing unit 700.

[0083] Next, the time slave device 100 reflects the predicted shortest time in the provisional MTSD' and STMD' (provisional PDV values) (S106). The prediction unit 130 sets and stores the predicted shortest time of MTSD' and shortest time of STMD' as provisional MTSD' and STMD' in the t2'-t1 shortest time acquisition and storage unit 732a and the t4-t3' shortest time acquisition and storage unit 742a. ​​The packet filter processing unit 700 determines the MTSD correction value and the STMD correction value using the set provisional MTSD' and STMD' as the shortest time, and the PTP time synchronization unit 800 performs time synchronization using the MTSD correction value and the STMD correction value.

[0084] Thereafter, the time slave device 100 repeats steps S103 to S106. That is, the packet filter processing unit 700 operates and the statistical processing unit 120 continues statistical processing using the provisional MTSD' and STMD' (provisional PDV values) predicted in step S105 and reflected in step S106. Furthermore, by constantly repeating these processes, the accuracy of the time difference is improved.

[0085] As described above, in the basic example, measuring the shortest value using a PDV filter can take more than a month, which is not practical when used with radio waves, but by using this embodiment, it is possible to quickly adjust the time and, further, to achieve time accuracy on the order of nanoseconds.

[0086] A specific example of improving the accuracy of time precision by correcting the MTSD and STMD from the predicted shortest time as shown in FIGS. 9 and 10 will be described.

[0087] As described above, first, the packet filter processing unit 700 measures the shortest delay values ​​of the provisional MTSD' and STMD'. Here, the MTSD side is designated as the MTSD_PDV value, and the STMD side is designated as the STMD_PDV value. Note that this PDV value is the time stamped by the frequency-synchronized internal clock 650, so the value itself is the difference from the time when the internal clock 650 was started. This start time is determined by the arrival time of the wireless packet, so the absolute value of the value itself has no meaning unless the start time of the internal clock 650 is known. However, if only the shortest time is to be measured, calculation is possible even if the absolute value is unknown.

[0088] As an example, suppose an MTSD_PDV value of 248 μs and an STMD_PDV value of 251 μs are acquired. Using the PTP architecture, a correction value is added to or subtracted from the wireless delay value in the Correction Field to arrive at this PDV value. Since the PDV value is a delay relative to the internal clock 650, if the internal clock 650 starts 10 μs behind the master clock of the time master device, the actual delay on the MTSD side will be MTSD_PDV value -10 μs = "238 μs," and on the STMD side will be STMD_PDV value +10 μs = 261 μs. In other words, the actual offset from master is (238 - 261) / 2 = -11.5 μs.

[0089] In this example, if the correction value using the least squares method on the MTSD side is -13.5 μs, then the result is 248 - 13.5 - 10 = 224.5 μs. If the correction value using the least squares method on the STMD side is -36 μs, then the result is 251 - 36 + 10 = 225 μs. In this case, the offset from master is 250 ns. If the least squares method is not used, the correction value on the MTSD side of -13.5 μs is actually -12.4 μs, and the correction value on the STMD side of -36 μs is actually -29 μs. When this actual raw information is used, the offset from master is approximately 4 μs, so it can be seen that the time difference is much better when using this embodiment.

[0090] As described above, in this embodiment, frequency synchronization is performed before time synchronization, an internal clock is generated from the recovered frequency, the internal clock is used to stamp the packet arrival time (t2') and packet transmission time (t3'), and provisional MTSD' and STMD' are stored. Using these provisional values ​​as a reference, the differences between the MTSD' and STMD' calculated from t2' and t3' of each transmitted packet are stored in the Correction Field area, thereby providing a mechanism for synchronization at a certain provisional time. Here, the Correction Field value corresponds to wireless fluctuations, so the results are statistically processed to calculate a predicted value of the shortest delay time using the least squares method. This allows the wireless uplink and downlink delays to be roughly calculated, thereby achieving highly accurate wireless time synchronization.

[0091] That is, in this embodiment, in a high-precision wireless time synchronization system, by predicting the "shortest delay" by the least squares method from the statistical distribution results based on the "packet delay variation" generated by the PDV filter, it is possible to achieve time accuracy (offset) on the order of nanoseconds, on par with wired networks, even in a wireless network. Specifically, it is possible to reduce delay fluctuations due to radio wave interference, etc., which are unique to wireless, to "zero." This embodiment does not require any changes to the IEEE 1588v2 protocol itself, and it is possible to quickly improve the accuracy of time.

[0092] According to this embodiment, by quantitatively grasping the fluctuation components, statistical processing becomes possible, and from the statistical results, it becomes possible to predict the shortest delay time by the least squares method. For example, by performing statistical processing and prediction processing in the cloud, the physical processing load on the time synchronization device can be reduced, and highly accurate time synchronization becomes possible.

[0093] Correcting the uplink / downlink asymmetry, which is a weakness of PTP, requires accurate measurement of the uplink / downlink delay times. However, by calculating the shortest delay time, the shortest delay time can be considered to be an almost accurate delay time based on the wireless propagation characteristics, even without measuring the exact uplink / downlink delay times. Furthermore, since the shortest delay time due to variations in wireless devices and wireless software, rather than the wireless itself, can be simultaneously measured, the shortest delay time includes not only the wireless but also the variations in the device itself. Therefore, according to this embodiment, there is no need to specify the wireless system (device), and it can be applied to all wireless systems, such as carrier wireless, Wi-Fi, and Bluetooth, and wireless time synchronization can be performed independently of the wireless system (device).

[0094] The present disclosure is not limited to the above-described embodiment, and can be modified as appropriate within the scope of the present disclosure.

[0095] Each component in the above-described embodiments may be configured with hardware or software, or both, and may be configured with a single piece of hardware or software, or may be configured with multiple pieces of hardware or software. Each device, such as a time synchronization device (time master device, time slave device), and each function (processing) may be realized by a computer 20 having a processor 21 such as a CPU and a memory 22 serving as a storage device, as shown in FIG. 11. For example, a program for performing the method in the embodiment (time synchronization method) may be stored in the memory 22, and each function may be realized by the processor 21 executing the program stored in the memory 22.

[0096] These programs include instructions (or software code) that, when loaded into a computer, cause the computer to perform one or more functions described in the embodiments. The programs may be stored on a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, computer-readable media or tangible storage media include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technology, CD-ROM, digital versatile disc (DVD), Blu-ray disc or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device. The programs may also be transmitted on a transitory computer-readable medium or communication medium. By way of example and not limitation, transitory computer-readable media or communication media include electrical, optical, acoustic, or other forms of propagated signals.

[0097] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0098] Each drawing is merely an example for describing one or more embodiments. Each drawing may not relate to only one particular embodiment, but may also relate to one or more other embodiments. As will be understood by those skilled in the art, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings to create, for example, an embodiment not explicitly shown or described. Not all features or steps shown in any one drawing are necessary to describe an exemplary embodiment, and some features or steps may be omitted. The order of steps described in any drawing may be changed as appropriate.

[0099] Some or all of the above embodiments may be described as, but are not limited to, the following supplementary notes: (Supplementary Note 1) A time synchronization device comprising an internal clock and a slave clock, frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a clock of a time master device, calculation means for calculating a downstream delay time that is the time difference between a packet transmission time from the time master device and a packet reception time stamped by the internal clock, and an upstream delay time that is the time difference between the packet transmission time stamped by the internal clock and a packet reception time at the time master device, prediction means for predicting a shortest downstream delay time based on the calculated downstream delay time, and predicting a shortest upstream delay time based on the calculated upstream delay time, and time synchronization means for synchronizing the time of the slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time. (Supplementary Note 2) The time synchronization device according to Supplementary Note 1, wherein the prediction means acquires a plurality of the calculated downlink delay times, performs statistical processing on the plurality of downlink delay times, and predicts the shortest downlink delay time based on a result of the statistical processing, and acquires a plurality of the calculated uplink delay times, performs statistical processing on the plurality of uplink delay times, and predicts the shortest uplink delay time based on a result of the statistical processing. (Supplementary Note 3) The time synchronization device according to Supplementary Note 2, wherein the prediction means generates a statistical distribution of the plurality of downlink delay times and predicts the shortest downlink delay time from the statistical distribution by a least squares method, and generates a statistical distribution of the plurality of uplink delay times and predicts the shortest uplink delay time from the statistical distribution by a least squares method.(Supplementary Note 4) The time synchronization device according to any one of Supplementary Notes 1 to 3, further comprising: a correction means for correcting a packet transmission time from the time master device based on the predicted shortest downlink delay time, and correcting a packet reception time at the time master device based on the predicted shortest uplink delay time, wherein the time synchronization means synchronizes the time of the slave clock with the time of the clock of the time master device based on the corrected packet transmission time from the time master device and the corrected packet reception time at the time master device. (Supplementary Note 5) The time synchronization device according to Supplementary Note 4, wherein the correction means calculates a correction value for correcting the packet transmission time from the time master device based on the calculated downlink delay time and the predicted shortest downlink delay time, and calculates a correction value for correcting the packet reception time at the time master device based on the calculated uplink delay time and the predicted shortest uplink delay time. (Supplementary Note 6) The time synchronization device according to Supplementary Note 5, wherein the correction means calculates a correction value for correcting a packet transmission time from the time master device based on the calculated downlink delay time and tentative shortest downlink delay time, and calculates a correction value for correcting a packet reception time at the time master device based on the calculated uplink delay time and tentative shortest uplink delay time, and reflects the predicted shortest downlink delay time in the tentative shortest downlink delay time in accordance with the prediction by the prediction means. (Supplementary Note 7) The time synchronization device according to Supplementary Note 6, wherein the prediction means repeatedly predicts the shortest downlink delay time and the shortest uplink delay time, and the correction means reflects the predicted shortest downlink delay time in the tentative shortest downlink delay time and reflects the predicted shortest downlink delay time in the tentative shortest uplink delay time each time the prediction is made. (Supplementary Note 8) The time synchronization device according to any one of Supplementary Notes 1 to 7, further comprising a wireless communication unit that performs wireless communication with the time master device.(Supplementary Note 9) A time synchronization system comprising: an internal clock and a slave clock; frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a clock of a time master device; calculation means for calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; prediction means for predicting a shortest downstream delay time based on the calculated downstream delay time, and predicting a shortest upstream delay time based on the calculated upstream delay time; and time synchronization means for synchronizing the time of the slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time. (Supplementary Note 10) The time synchronization system according to Supplementary Note 9, comprising a time synchronization device and a prediction device, wherein the time synchronization device comprises the internal clock, the slave clock, the calculation means, and the time synchronization means, and the prediction device comprises the prediction means. (Supplementary Note 11) The time synchronization system according to Supplementary Note 9 or 10, wherein the prediction means acquires a plurality of the calculated downlink delay times, performs statistical processing on the plurality of downlink delay times, and predicts the shortest downlink delay time based on the result of the statistical processing, and acquires a plurality of the calculated uplink delay times, performs statistical processing on the plurality of uplink delay times, and predicts the shortest uplink delay time based on the result of the statistical processing. (Supplementary Note 12) The time synchronization system according to Supplementary Note 11, wherein the prediction means generates a statistical distribution of the plurality of downlink delay times and predicts the shortest downlink delay time from the statistical distribution by a least squares method, and generates a statistical distribution of the plurality of uplink delay times and predicts the shortest uplink delay time from the statistical distribution by a least squares method.(Supplementary Note 13) The time synchronization system according to any one of Supplementary Notes 9 to 12, comprising correction means for correcting a packet transmission time from the time master device based on the predicted shortest downlink delay time, and correcting a packet reception time at the time master device based on the predicted shortest uplink delay time, wherein the time synchronization means synchronizes the time of the slave clock with the time of the clock of the time master device based on the corrected packet transmission time from the time master device and the corrected packet reception time at the time master device. (Supplementary Note 14) The time synchronization system according to Supplementary Note 13, wherein the correction means calculates a correction value for correcting the packet transmission time from the time master device based on the calculated downlink delay time and the predicted shortest downlink delay time, and calculates a correction value for correcting the packet reception time at the time master device based on the calculated uplink delay time and the predicted shortest uplink delay time. (Supplementary Note 15) A time synchronization method comprising: synchronizing the frequency of an internal clock with the frequency of a clock of a time master device; calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; predicting a shortest downstream delay time based on the calculated downstream delay time, and predicting a shortest upstream delay time based on the calculated upstream delay time; and synchronizing the time of a slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time. (Supplementary Note 16) The time synchronization method according to Supplementary Note 15, further comprising: acquiring a plurality of the calculated downlink delay times, performing statistical processing on the plurality of downlink delay times, and predicting the shortest downlink delay time based on the results of the statistical processing; and acquiring a plurality of the calculated uplink delay times, performing statistical processing on the plurality of uplink delay times, and predicting the shortest uplink delay time based on the results of the statistical processing.(Supplementary Note 17) The time synchronization method according to Supplementary Note 16, further comprising generating a statistical distribution of the plurality of downlink delay times, predicting the shortest downlink delay time from the statistical distribution using a least squares method, and generating a statistical distribution of the plurality of uplink delay times, and predicting the shortest uplink delay time from the statistical distribution using a least squares method. (Supplementary Note 18) A program for causing a computer to execute the following processes: synchronizing the frequency of an internal clock with the frequency of a clock of a time master device; calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; predicting a shortest downstream delay time based on the calculated downstream delay time, and predicting a shortest upstream delay time based on the calculated upstream delay time; and synchronizing the time of a slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time. (Supplementary Note 19) The program according to Supplementary Note 18, which acquires a plurality of the calculated downlink delay times, performs statistical processing on the plurality of downlink delay times, and predicts the shortest downlink delay time based on the results of the statistical processing, and also acquires a plurality of the calculated uplink delay times, performs statistical processing on the plurality of uplink delay times, and predicts the shortest uplink delay time based on the results of the statistical processing. (Supplementary Note 20) The program according to Supplementary Note 19, which generates a statistical distribution of the plurality of downlink delay times, and predicts the shortest downlink delay time from the statistical distribution by the least squares method, and also generates a statistical distribution of the plurality of uplink delay times, and predicts the shortest uplink delay time from the statistical distribution by the least squares method.

[0100] Some or all of the elements (e.g., configurations and functions) described in Supplementary Notes 2 to 8 that are dependent on Supplementary Note 1 (time synchronization device) may also be dependent on Supplementary Note 9 (time synchronization system), Supplementary Note 15 (time synchronization method), and Supplementary Note 18 (program) in the same dependency relationship as Supplementary Notes 2 to 8. Some or all of the elements described in any Supplementary Note may be applied to various hardware, software, recording means for recording software, systems, and methods.

[0101] 1 Time synchronization system 10 Time synchronization device 11 Internal clock 12 Slave clock 13 Frequency synchronization unit 14 Calculation unit 15 Prediction unit 16 Time synchronization unit 20 Computer 21 Processor 22 Memory 100 Time slave device 101 Wireless communication unit 110 PDV filter 120 Statistical processing unit 130 Prediction unit 200 Time master device 201 Wireless communication unit 500 Time synchronization device 600 PTP frequency synchronization unit 610 t2' packet stamping unit 620 Phase comparator 630 IIR filter 640 PI controller 650 Internal clock 700 Packet filter processing unit 710 t1 packet receiving unit 711 Follow-up message receiving unit 712 t3 packet transmitting unit 713 t4 packet receiving unit 730 t2' packet stamping unit 731 t2'-t1 calculation unit 732 t2'-t1 shortest time search and hold unit 732a t2'-t1 shortest time acquisition and hold unit 733 t2'-t1 correction unit 734 t1 correction value update unit 740 t3' packet timestamp unit 741 t4-t3' calculation unit 742 t4-t3' shortest time search and hold unit 742a t4-t3' shortest time acquisition and hold unit 743 t4-t3' correction unit 744 t4 correction value update unit 800 PTP time synchronization unit 810 OCXO 820 Slave clock 830 t2 packet timestamp unit 831 t2-t1 calculation unit 832 t3 packet timestamp unit 833 t4-t3 calculation unit 834 Complement unit 835 Adder 836 PI controller

Claims

1. A time synchronization device comprising: an internal clock and a slave clock; frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a clock of a time master device; calculation means for calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; prediction means for predicting a shortest downstream delay time based on the calculated downstream delay time, and predicting a shortest upstream delay time based on the calculated upstream delay time; and time synchronization means for synchronizing the time of the slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

2. The time synchronization device described in claim 1, wherein the prediction means acquires a plurality of the calculated downlink delay times, performs statistical processing on the plurality of downlink delay times, and predicts the shortest downlink delay time based on the results of the statistical processing, and also acquires a plurality of the calculated uplink delay times, performs statistical processing on the plurality of uplink delay times, and predicts the shortest uplink delay time based on the results of the statistical processing.

3. The time synchronization device according to claim 2, wherein the prediction means generates a statistical distribution of the multiple downstream delay times and predicts the shortest downstream delay time from the statistical distribution using the least squares method, and generates a statistical distribution of the multiple upstream delay times and predicts the shortest upstream delay time from the statistical distribution using the least squares method.

4. A time synchronization device as described in any one of claims 1 to 3, comprising a correction means for correcting the packet transmission time from the time master device based on the predicted shortest delay time in the downlink direction, and for correcting the packet reception time at the time master device based on the predicted shortest delay time in the uplink direction, and wherein the time synchronization means synchronizes the time of the slave clock with the time of the clock of the time master device based on the corrected packet transmission time from the time master device and the corrected packet reception time at the time master device.

5. The time synchronization device described in claim 4, wherein the correction means calculates a correction value for correcting the packet transmission time from the time master device based on the calculated downlink delay time and the predicted shortest downlink delay time, and calculates a correction value for correcting the packet reception time at the time master device based on the calculated uplink delay time and the predicted shortest uplink delay time.

6. The time synchronization device described in claim 5, wherein the correction means calculates a correction value for correcting the packet transmission time from the time master device based on the calculated downlink delay time and the provisional shortest downlink delay time, and calculates a correction value for correcting the packet reception time at the time master device based on the calculated uplink delay time and the provisional shortest uplink delay time, and reflects the predicted shortest downlink delay time in the provisional shortest downlink delay time according to the prediction by the prediction means, and reflects the predicted shortest downlink delay time in the provisional shortest uplink delay time.

7. The time synchronization device according to claim 6, wherein the prediction means repeatedly predicts the shortest downlink delay time and the shortest uplink delay time, and the correction means reflects the predicted shortest downlink delay time in the tentative shortest downlink delay time and reflects the predicted shortest downlink delay time in the tentative shortest uplink delay time each time the prediction is made.

8. A time synchronization device according to any one of claims 1 to 7, comprising a wireless communication unit that performs wireless communication with the time master device.

9. A time synchronization system comprising: an internal clock and a slave clock; frequency synchronization means for synchronizing the frequency of the internal clock with the frequency of a clock in a time master device; calculation means for calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; prediction means for predicting a shortest downstream delay time based on the calculated downstream delay time, and predicting a shortest upstream delay time based on the calculated upstream delay time; and time synchronization means for synchronizing the time of the slave clock with the time of the clock in the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

10. A time synchronization system according to claim 9, comprising a time synchronization device and a prediction device, wherein the time synchronization device comprises the internal clock, the slave clock, the calculation means, and the time synchronization means, and the prediction device comprises the prediction means.

11. The time synchronization system described in claim 9 or 10, wherein the prediction means acquires a plurality of the calculated downlink delay times, performs statistical processing on the plurality of downlink delay times, and predicts the shortest downlink delay time based on the results of the statistical processing, and also acquires a plurality of the calculated uplink delay times, performs statistical processing on the plurality of uplink delay times, and predicts the shortest uplink delay time based on the results of the statistical processing.

12. The time synchronization system described in claim 11, wherein the prediction means generates a statistical distribution of the multiple downstream delay times and predicts the shortest downstream delay time from the statistical distribution using the least squares method, and generates a statistical distribution of the multiple upstream delay times and predicts the shortest upstream delay time from the statistical distribution using the least squares method.

13. A time synchronization system as described in any one of claims 9 to 12, further comprising a correction means for correcting the packet transmission time from the time master device based on the predicted shortest delay time in the downlink direction, and for correcting the packet reception time at the time master device based on the predicted shortest delay time in the uplink direction, wherein the time synchronization means synchronizes the time of the slave clock with the time of the clock of the time master device based on the corrected packet transmission time from the time master device and the corrected packet reception time at the time master device.

14. The time synchronization system described in claim 13, wherein the correction means calculates a correction value for correcting the packet transmission time from the time master device based on the calculated downlink delay time and the predicted shortest downlink delay time, and calculates a correction value for correcting the packet reception time at the time master device based on the calculated uplink delay time and the predicted shortest uplink delay time.

15. A time synchronization method comprising: synchronizing the frequency of an internal clock with the frequency of a clock of a time master device; calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; predicting a shortest downstream delay time based on the calculated downstream delay time, and predicting a shortest upstream delay time based on the calculated upstream delay time; and synchronizing the time of a slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

16. A time synchronization method as described in claim 15, further comprising: acquiring a plurality of the calculated downlink delay times, performing statistical processing on the plurality of downlink delay times, and predicting the shortest downlink delay time based on the results of the statistical processing; and acquiring a plurality of the calculated uplink delay times, performing statistical processing on the plurality of uplink delay times, and predicting the shortest uplink delay time based on the results of the statistical processing.

17. A time synchronization method according to claim 16, further comprising generating a statistical distribution of the plurality of downlink delay times and predicting the shortest downlink delay time from the statistical distribution using the least squares method, and generating a statistical distribution of the plurality of uplink delay times and predicting the shortest uplink delay time from the statistical distribution using the least squares method.

18. A program for causing a computer to execute the following process: synchronizing the frequency of an internal clock with the frequency of the clock of a time master device; calculating a downstream delay time, which is the time difference between the packet transmission time from the time master device and the packet reception time stamped by the internal clock, and an upstream delay time, which is the time difference between the packet transmission time stamped by the internal clock and the packet reception time at the time master device; predicting the shortest downstream delay time based on the calculated downstream delay time, and predicting the shortest upstream delay time based on the calculated upstream delay time; and synchronizing the time of a slave clock with the time of the clock of the time master device based on the predicted shortest downstream delay time and the predicted shortest upstream delay time.

19. The program described in claim 18, which obtains multiple calculated downlink delay times, performs statistical processing on the multiple downlink delay times, and predicts the shortest downlink delay time based on the results of the statistical processing, and also obtains multiple calculated uplink delay times, performs statistical processing on the multiple uplink delay times, and predicts the shortest uplink delay time based on the results of the statistical processing.

20. The program according to claim 19, which generates a statistical distribution of the multiple downlink delay times and predicts the shortest downlink delay time from the statistical distribution using the least squares method, and generates a statistical distribution of the multiple uplink delay times and predicts the shortest uplink delay time from the statistical distribution using the least squares method.

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