Semiconductor light-receiving element and method for manufacturing semiconductor light-receiving element

Abstract

This semiconductor light-receiving element 1 is characterized in that: the element 1 includes a support substrate 200, a junction layer 50 on the support substrate 200, a semiconductor stack 10 having a light receiving part 33 above the junction layer 50, and an optical filter 80 positioned above the semiconductor stack 10 and transmitting a wavelength range including a light reception peak wavelength; a first conductivity type electrode 40 and a first conductivity type contact layer 31 located on the first conductivity type electrode 40 are provided in at least a part of the space between the junction layer 50 and the semiconductor stack 10; and the semiconductor stack 10 does not receive incident light from the junction layer 50 side.

Description

Semiconductor light receiving element and method for manufacturing the same

[0001] The present invention relates to a semiconductor light-receiving element and a method for manufacturing the semiconductor light-receiving element.

[0002] In recent years, it has become increasingly important for light-receiving elements to selectively receive only light of a desired wavelength in order to prevent malfunction of the sensor. As a method for blocking light other than light of the desired wavelength, a method using an optical filter is known.

[0003] For example, Patent Document 1 discloses a semiconductor light-receiving element that has an optical filter made of a dielectric multilayer film on the back surface of a substrate and that can selectively allow light on the long wavelength side to enter from multiplexed light that includes light on the long wavelength side and light on the short wavelength side.

[0004] In Patent Document 2, a first absorption layer having an absorption edge wavelength shorter than that of the absorption layer is provided on a side farther from the semiconductor substrate, and a second absorption layer having an absorption edge wavelength shorter than that of the absorption layer is provided on a side closer to the semiconductor substrate, thereby allowing light of a desired wavelength, including light incident from the side surface of the semiconductor substrate, to be selectively incident.

[0005] JP 2002-33503 A Japanese Patent No. 3046970 A

[0006] However, conventional methods are insufficient to selectively receive only light having a desired wavelength from a wide wavelength band. For example, in the semiconductor light-receiving element disclosed in Patent Document 1, light incident from the side of the substrate does not pass through an optical filter, so all light incident on the semiconductor light-receiving element is incident on the light-absorbing layer. That is, light of wavelengths other than the desired wavelength is received from the side of the substrate that does not have an optical filter, resulting in noise. Furthermore, covering the side of a thick substrate with an optical filter is difficult to achieve and results in poor productivity. To achieve high light-receiving sensitivity, it is common to design the desired wavelength to match the peak light-receiving wavelength of the semiconductor light-receiving element. Therefore, hereinafter, the desired wavelength range transmitted by the optical filter will be described as a wavelength range including the peak light-receiving wavelength of the semiconductor light-receiving element.

[0007] The semiconductor light-receiving element of Patent Document 2 employs a method of selectively absorbing incident light by providing a semiconductor layer such as an absorption layer. However, this method has the problem that it can transmit light with wavelengths longer than the absorption edge wavelength, but cannot transmit light with wavelengths shorter than the absorption edge wavelength. Furthermore, the semiconductor absorption layer is epitaxially grown and must have a semiconductor composition with a lattice constant close to that of the substrate, which imposes limitations on the absorption edge wavelength. Therefore, in a structure in which an absorption layer is formed from a semiconductor layer and only light of a desired wavelength is selectively transmitted, the wavelengths that can be selected are limited.

[0008] The present invention aims to provide a semiconductor light-receiving element with a low noise ratio by blocking incident light from the support substrate side with a bonding layer for a support substrate-bonded semiconductor light-receiving element, and a method for manufacturing the semiconductor light-receiving element.

[0009] The present inventors have intensively studied ways to solve the above problems and have come up with the idea of ​​providing, for example, a light-reflecting bonding layer between the support substrate and the light-absorbing layer. The present inventors have found that providing a light-blocking bonding layer on top of the support substrate makes it possible to reliably block incident light from the support substrate side and reduce noise, which has led to the completion of the present invention. That is, the gist of the present invention is as follows.

[0010] (1) A semiconductor light-receiving element comprising: a support substrate; a bonding layer on the support substrate; a semiconductor laminate having a light-receiving portion located on the bonding layer; and an optical filter located on the semiconductor laminate and transmitting a wavelength range including a peak light-receiving wavelength; wherein the semiconductor laminate has a first conductivity type electrode and a first conductivity type contact layer located on the first conductivity type electrode at least in a portion between the bonding layer and the semiconductor laminate; and wherein light is not incident on the semiconductor laminate from the bonding layer side.

[0011] (2) The semiconductor light-receiving element according to (1), further comprising a second conductivity type contact layer and a second conductivity type electrode between the semiconductor laminate and the optical filter, and a pad electrode on the second conductivity type electrode.

[0012] (3) The semiconductor light receiving element according to (1) or (2) above, wherein the first conductivity type electrode covers the bottom and side surfaces of the first conductivity type contact layer between the bonding layer and the semiconductor laminate, and a dielectric layer is provided in a second region different from a first region including the first conductivity type electrode or the first conductivity type contact layer.

[0013] (4) The semiconductor light-receiving element according to (2), wherein the semiconductor laminate has a light-absorbing layer, the light-receiving portion is located in a partial region in the in-plane direction of the light-absorbing layer, and the second conductivity type electrode has a shape that surrounds the light-receiving portion from above, except for the region of the pad electrode.

[0014] (5) The semiconductor light-receiving element according to (4), wherein the peak light-receiving wavelength is 800 nm or more and 2500 nm or less, and the light-absorbing layer is an InGaAs layer.

[0015] (6) The semiconductor light-receiving element according to any one of (1) to (5) above, further comprising the optical filter on a side surface of the semiconductor laminate.

[0016] (7) The semiconductor light-receiving element according to any one of (1) to (6) above, wherein the thickness of the semiconductor laminate is 20 μm or less, and the total thickness including the support substrate is 100 μm or more.

[0017] (8) A method for manufacturing a semiconductor light-receiving element, comprising: a growth step of forming a semiconductor laminate having a light-receiving portion on a growth substrate; a contact region formation step of forming a first conductivity type contact layer and a first conductivity type electrode on at least a portion of the semiconductor laminate; a bonding layer formation step of forming a bonding layer on the semiconductor laminate; a bonding step of bonding a support substrate via the bonding layer; a substrate removal step of removing the growth substrate; and a step of forming an optical filter that transmits a wavelength range including a light-receiving peak wavelength on the semiconductor laminate exposed by the substrate removal step.

[0018] According to the present invention, a semiconductor light-receiving element with a low noise ratio can be provided by blocking incident light from the support substrate side with a bonding layer in a support substrate-bonded semiconductor light-receiving element.

[0019] 7 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention; FIG. 8 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention, continuing from FIG. 1; FIG. 9 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention, continuing from FIG. 2; FIG. 10 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention, continuing from FIG. 3; FIG. 11 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention, continuing from FIG. 12; FIG. 12 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention, continuing from FIG. 13; FIG. 13 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention, continuing from FIG. 14; FIG. 15 is a schematic cross-sectional view illustrating a part of a manufacturing process of a semiconductor light-receiving element according to one embodiment of the present invention, continuing from FIG. 15; FIG. 1 is a logarithmic scale graph showing the light receiving sensitivity of Example 1 of the present invention and a comparative example.

[0020] Prior to describing the embodiments of the present invention, the following points will be explained in advance.

[0021] First, in the present invention, "light is not incident from the bonding layer side of the semiconductor laminate" means that light incident on the support substrate is reflected at the bonding layer or is absorbed or scattered by the support substrate and does not pass through the bonding layer, so that light is not incident from the bonding layer side to the semiconductor laminate. It is permissible for light incident on the semiconductor laminate from a location other than the bonding layer side of the semiconductor laminate to be reflected at the bonding layer side of the semiconductor laminate, and this is not included in the above interpretation.

[0022] In the present specification, when the term "InGaAs" is used without specifying the element composition ratio, it means that the composition ratio of the sum of the group III elements In (indium) and Ga (gallium) to the group V element As (arsenic) is 1:1, and the ratio of the group III elements In to Ga is any compound. ｘ Ga （１－ｘ） When expressed in terms of In and As, preferably, x is 0<x<1. However, "InGaAs" may contain up to 5% (molar concentration, the same applies hereinafter) of Al relative to the total of In and Ga, or up to 5% of P (phosphorus) and Sb (antimony) relative to As. Furthermore, even when simply written as "InP", it may contain up to 5% of group III and group V elements other than In and P. The composition ratios of group III and group V elements can be measured by photoluminescence measurement, X-ray diffraction measurement, etc.

[0023] Furthermore, in this specification, a layer that functions electrically as p-type is referred to as a p-type semiconductor layer (sometimes abbreviated as "p-type layer"), and a layer that functions electrically as n-type is referred to as an n-type semiconductor layer (sometimes abbreviated as "n-type layer"). On the other hand, when specific impurities such as Si, Zn, S, etc. are not intentionally added, the layer is called "i-type" or "undoped." This III-V compound semiconductor layer may contain unavoidable impurities during the manufacturing process. Specifically, in this specification, when the dopant concentrations of both p-type and n-type impurities are low and the dopant concentrations of these impurities are close to the lower limit of detection by SIMS, the layer is treated as "i-type" or "undoped." In the case of Si concentration, the lower limit of detection of SIMS analysis described below is 2 × 10 １４ / cm ３ Therefore, the average Si concentration in the layer is 2.5 × 10 １４ / cm ３ If it is less than 1 / 2, it is considered to be "i-type" or "undoped."

[0024] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. In each drawing, the aspect ratio of the substrate and each layer is exaggerated from the actual ratio for the sake of convenience. In addition, the description will be given taking as an example a case where the first conductivity type is p-type and the second conductivity type is n-type.

[0025] (Method for Manufacturing a Semiconductor Photodetector) A method for manufacturing a semiconductor photodetector according to the present invention includes at least a growth step, a contact region forming step, a bonding layer forming step, a bonding step, a substrate removal step, and an optical filter forming step. The method for manufacturing a semiconductor photodetector 1 according to an embodiment of the present invention, which is described in detail below with reference to FIGS. 1 to 9 , includes a first step (growth step), a second step, a third step (contact region forming step (p-type contact layer formation)), a fourth step (contact region forming step (first conductivity type electrode formation)), a fifth step (bonding layer forming step, bonding step), a sixth step (substrate removal step), a seventh step, an eighth step, a ninth step (optical filter forming step), and a tenth step. In the first step, a plurality of compound semiconductor layers, including at least a window layer 13 and a light absorption layer 14, are stacked on a growth substrate 100 ( FIG. 1 ). In the second step, a predetermined pattern is formed in a second contact layer 16 (described later). A dielectric layer 20 is also formed ( FIG. 2 ). In the third step, p-type impurities are diffused from the surface side of the second contact layer 16 using the dielectric layer 20 as a mask. The second contact layer 16 becomes the p-type contact layer 31, and the interface between the p-type impurity-diffused region of the semiconductor layer (p-type region 32) and the p-type impurity-undiffused region in the light absorption layer 14 becomes the light receiving portion 33 ( FIG. 3 ). In the fourth step, a dielectric layer 20 is prepared to the same height as a first conductivity-type electrode 40 (described later), and the first conductivity-type electrode 40 is formed on the surface of the p-type contact layer 31 ( FIG. 4 ). In the fifth step, a bonding layer (growth substrate side) 51 is formed on the first conductivity-type electrode 40 and the dielectric layer 20. A support substrate 200 having a bonding layer (support substrate side) 52 on its surface is bonded to the bonding layer (growth substrate side) 51 via the bonding layer (support substrate side) 52 ( FIG. 5 ). In the sixth step, the growth substrate 100 is removed, and the semiconductor stacked film 11 is simultaneously etched to expose the surface of the first contact layer 12 ( FIG. 6 ). In a seventh step, a predetermined pattern is formed in the first contact layer 12, and the periphery of the semiconductor laminate 10 is dry-etched (FIG. 7). In an eighth step, a protective film 60 is formed around the dry-etched semiconductor laminate 10, and an n-type electrode 70 is further formed on the first contact layer 12 (FIG. 8). In a ninth step, an optical filter 80 is formed around the protective film 60, and a pad electrode 71 for electrical conduction is formed (FIG. 9).In a tenth step, the support substrate 200 is ground, and a back surface electrode 72 is formed on the back surface of the support substrate 200 .

[0026] <First Step> As described above, the first step is a step of stacking a plurality of compound semiconductor layers, including at least a window layer 13 and a light absorption layer 14, on a growth substrate 100 ( FIG. 1 ). A compound substrate such as GaAs, InP, or InAs can be used as the growth substrate 100. The growth substrate 100 is preferably an n-type substrate. For ease of explanation, the following describes an embodiment in which an n-type InP growth substrate 100 is used as the growth substrate 100. A commonly available n-type InP growth substrate 100 can be used, and its thickness need only be sufficient to physically support the semiconductor layers described below.

[0027] In the first step, the first contact layer 12, the window layer 13, the light absorption layer 14, the second buffer layer 15, and the second contact layer 16 may be formed in this order on the n-type InP growth substrate 100. The light absorption layer 14 is preferably an InGaAs layer. The light absorption layer 14 is preferably undoped. The first contact layer 12 may be an n-type InGaAs layer, the window layer 13 may be an n-type InP layer, the second buffer layer 15 may be an n-type InP layer, and the second contact layer 16 may be an undoped InGaAs layer. When the first contact layer 12 is an InGaAs layer, the lattice mismatch between the n-type InP growth substrate 100 and the InGaAs first contact layer 12 can be alleviated by providing the first buffer layer 11, which is an n-type InP layer, between the n-type InP growth substrate 100 and the first contact layer 12. The window layer 13, the light absorption layer 14, and the second buffer layer 15 are referred to as the semiconductor laminate 10, and the total thickness of the semiconductor laminate 10 is preferably 20 μm or less, and more preferably 15 μm or less. For convenience of explanation, the present embodiment will be described assuming that the n-type InP first buffer layer 11 is present, but the n-type InP first buffer layer 11 has an optional configuration.

[0028] Here, each of the semiconductor layers described above can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering. For example, trimethylindium (TMIn) is used as an In source, trimethylgallium (TMGa) is used as a Ga source, and arsine (AsH) is used as an As source. ３ ) in a predetermined mixing ratio, and these source gases are vapor-phase grown using a carrier gas, thereby forming each layer with a desired thickness depending on the growth time. When each layer is doped to a p-type or n-type, a dopant source gas may be further used as desired.

[0029] <Second Step> As described above, the second step is a step of forming a predetermined pattern on the second contact layer 16 and forming the dielectric layer 20 (FIG. 2). The predetermined pattern can be formed on the second contact layer 16 by forming a resist pattern on the surface of the second contact layer 16, etching openings, and peeling off the resist. When the second contact layer 16 is an InGaAs layer, for example, H ２ SO ４ : H ２ O ２ : H ２ Furthermore, the region where Zn diffusion is not performed is covered with a dielectric layer 20. That is, the dielectric layer 20 is formed on the surface of the second buffer layer 15 including the surface of the second contact layer 16. The dielectric layer 20 is made of SiO ２ , SiON, etc., but Si ３ N ４ The thickness of the dielectric layer 20 is preferably the same as that of the second contact layer 16. The dielectric layer 20 can be formed by, for example, plasma CVD (Chemical Vapor Deposition). Thereafter, a resist pattern is formed on the dielectric layer 20, openings are etched, and the resist is peeled off, thereby forming the dielectric layer 20 in a predetermined pattern. Si ３ N４ The etching solution in step 3 is an aqueous HF solution. The formed dielectric layer 20 can be used as a mask when diffusing p-type impurities in the third step.

[0030] <Step 3> As described above, the third step is a step of diffusing p-type impurities from the second contact layer 16 to the light absorption layer 14, using the mask openings not covered by the dielectric layer 20 as the diffusion inlet. For example, Zn can be used as the p-type impurity. Because Zn is difficult to diffuse into the dielectric layer 20 formed in the second step, the p-type impurity is diffused from the mask openings not covered by the dielectric layer 20. Zn can be diffused in the thickness direction from the mask openings including the surface of the second contact layer 16 using the MOCVD method. It is preferable to adjust the conditions so that Zn diffuses 0.1 μm to 0.5 μm from the interface between the second buffer layer 15 and the light absorption layer 14 toward the light absorption layer 14. By diffusing Zn, the second contact layer 16 becomes a p-type contact layer 31, converting the second buffer layer 15 and portions of the light absorption layer 14 to p-type. The interface between the p-type impurity-diffused region (p-type region 32) of the semiconductor layer and the p-type impurity non-diffused region in the light absorption layer 14 is designated as the light receiving portion 33 ( FIG. 3 ). This allows the semiconductor stack 10 having the light receiving portion 33 to be formed on the n-type InP growth substrate 100. The p-type contact layer 31, p-type region 32, and light receiving portion 33 are collectively designated as the Zn-diffused region 30. Note that the area of ​​the light receiving portion 33 when viewed from above may be considered to be the same area as the mask opening in the dielectric layer 20 used as a mask during the p-type impurity diffusion. The extent of the light receiving portion 33 can also be confirmed by line analysis using SIMS.

[0031] <Step 4> As described above, step 4 is a step of preparing a dielectric layer 20 that matches the height of the first conductivity-type electrode 40 (hereinafter referred to as the p-type electrode 40) and forming the p-type electrode 40 on the surface of the p-type contact layer 31 ( FIG. 4 ). FIG. 4 shows an example in which an additional dielectric layer 20 is formed to cover the dielectric layer 20 formed in step 2. As an alternative method, the dielectric layer 20 may be etched away in step 2 and then formed again, or the dielectric layer 20 may be formed so that the heights match at the time of step 2. The reason for matching the heights is to prevent poor bonding during bonding, as described below. Here, a groove or recess may be formed at the boundary between the dielectric layer 20 and the p-type electrode 40 (the black portion in FIG. 4 ).

[0032] The dielectric layer 20 formed here is preferably made of the same material as the dielectric layer 20 used in the second step. A resist pattern is formed on the newly formed dielectric layer 20, and the area where the p-type electrode 40 will be formed is opened, with the dielectric layer 20 in the opening removed. A metal layer is then formed on top of this by vapor deposition. The resist is then swelled, and the metal outside the predetermined pattern is removed to form the p-type electrode 40. The main metal material constituting the p-type electrode 40 can be Au, Al, Pt, Ti, Ag, or the like. For example, the p-type electrode 40 can be Ti / Pt / Au. The thickness (or total thickness) of the p-type electrode 40 is not limited, but is preferably 100 nm to 300 nm, and more preferably 150 nm to 250 nm. The formed p-type electrode 40 may be subjected to an alloying process.

[0033] <Fifth Step> As described above, the fifth step is a step of forming a bonding layer (growth substrate side) 51 on the p-type electrode 40 and the dielectric layer 20, and bonding a support substrate 200 having a bonding layer (support substrate side) 52 provided on its surface to the bonding layer (growth substrate side) 51 via the bonding layer (support substrate side) 52 ( FIG. 5 ). The bonding layer (growth substrate side) 51 and the bonding layer (support substrate side) after bonding are collectively referred to as the bonding layer 50. The bonding layer (growth substrate side) 51 and the bonding layer (support substrate side) 52 are preferably metal layers, but if an opaque substrate is used, materials transparent to a wavelength range including the peak light-receiving wavelength, such as polyimide, epoxy, or silicone, can be used. The bonding layer (growth substrate side) 51 is formed to a certain thickness on the groove or recess at the boundary between the dielectric layer 20 and the p-type electrode 40 formed in the fourth step so as to fill the groove or recess. Therefore, a similar groove or recess may be formed on the surface of the bonding layer (growth substrate side) 51 (the blackened area in FIG. 5 ). Eutectic materials such as AuSn and AuSi may also be used. It is sufficient that light incident from the side of the support substrate 200 is prevented from entering the light receiving portion 33 by any of the support substrate 200, the bonding layer 50, and the p-type electrode 40. Here, a reflective embodiment will be described in which the bonding layer (growth substrate side) 51 and the bonding layer (support substrate side) 52 are both made of metal layers.

[0034] The bonding layer (growth substrate side) 51 may include multiple metal layers. When including a metal layer made of Au (hereinafter referred to as "Au metal layer"), the thickness of the Au is preferably 100 nm or more. The metal constituting the bonding layer (growth substrate side) 51 may be Al, Pt, Ti, Ag, or the like, in addition to Au. For example, the bonding layer (growth substrate side) 51 may be a single layer made of Au alone, or the bonding layer (growth substrate side) 51 may include two or more Au metal layers. In order to ensure bonding with the subsequent bonding layer (support substrate side) 52, it is preferable that the outermost surface of the bonding layer (growth substrate side) 51 (the surface opposite the p-type electrode 40) be an Au metal layer. For example, the bonding layer (growth substrate side) 51 may be formed by depositing metal layers in the order of Ti, Pt, and Au on the p-type electrode 40 and the dielectric layer 20. The thickness of one Au metal layer in the bonding layer (growth substrate side) 51 can be, for example, 100 nm to 2000 nm. The bonding layer (growth substrate side) 51 made of a metal layer can be formed by deposition using a general method such as vapor deposition.

[0035] Next, the support substrate 200 is prepared. The support substrate 200 is preferably conductive. Examples include a Si substrate, a compound semiconductor substrate, a metal substrate (Cu-Mo, Mo, etc.), or a ceramic substrate (AlN sintered body, etc.). The thickness of the support substrate 200 is preferably 180 μm to 300 μm, but it may be thicker or thinner. A bonding layer (support substrate side) 52 can be formed on the support substrate 200. To ensure reliable bonding with the bonding layer (growth substrate side) 51 containing the metal layer described above, the outermost surface of the bonding layer (growth substrate side) 52 of the support substrate 200 is preferably Au, and the thickness of the Au is preferably 100 nm or more. To facilitate bonding, it is preferable that the outermost surface on the bonding layer (support substrate side) 52 side is an Au metal layer, and the metal layer on the bonding layer (growth substrate side) 51 on the bonding layer (support substrate side) 52 side is also Au, and bonding between the Au layers is performed by Au-Au diffusion. The bonding layer (growth substrate side) 51 and the bonding layer (support substrate side) 52 are arranged facing each other and bonded together, and then heated and pressurized to bond them at a temperature of about 250°C to 400°C with a force of about 5 kN to 20 kN, thereby forming the bonding layer 50.

[0036] <Sixth Step> As described above, the sixth step is a step of removing the n-type InP growth substrate 100 and simultaneously etching the n-type InP first buffer layer 11 to expose the surface of the first contact layer 12 ( FIG. 6 ; hereafter, for simplicity, grooves or recesses are omitted from the drawings). The n-type InP growth substrate 100 can be removed by wet etching using, for example, a diluted hydrochloric acid solution. The n-type InP first buffer layer 11 can be removed in a similar manner.

[0037] <Seventh Step> Hereinafter, when the wafer before singulation is viewed from above, the area that is separated by planned lines (planned separation lines) along which the wafer will be individually separated when singulated into each chip, and that is to remain as the upper surface of the semiconductor laminate 10 in the chip after singulation, will be referred to as the chip area. As described above, the seventh step is a step of forming a predetermined pattern in the first contact layer 12 and forming a mesa pattern on the periphery of the chip area of ​​the semiconductor laminate 10 ( FIG. 7 ). A resist pattern is formed on the surface of the first contact layer 12, openings are etched, and the resist is stripped off, thereby forming the predetermined pattern in the first contact layer 12. When the first contact layer 12 is an InGaAs layer, an example of an etching solution is H ２ SO ４ : H ２ O ２ : H ２ Next, the outer periphery of the semiconductor laminate 10 is removed by dry etching. For example, SiO ２ (Thickness: 200 nm to 700 nm) is formed. ２ A resist pattern is formed on the semiconductor layer 10, and an opening is etched using an HF solution, and the resist is then peeled off. The opening (the outer periphery of the chip region of the semiconductor layer 10) is then etched by dry etching. The gas conditions used for dry etching are, for example, SiCl ４ Ar = several to several tens of sccm; several tens to 100 sccm. Finally, the SiO ２However, as will be described in Example 2 below, dry etching of the outer periphery of the chip region of the semiconductor laminate 10 may not be performed.

[0038] <Eighth Step> As described above, the eighth step is a step of forming a protective film 60 around the semiconductor laminate 10, and further forming a second conductivity type electrode 70 (hereinafter referred to as n-type electrode 70) on the first contact layer 12 ( FIG. 8 ). The protective film 60 is formed around the semiconductor laminate 10 and the first contact layer 12 by plasma CVD. The protective film 60 is made of SiO ２ , SiON, etc., but Si ３ N ４ The thickness of the protective film 60 is preferably 100 nm to 250 nm, and more preferably 150 nm to 200 nm. Next, to form the n-type electrode 70 on the first contact layer 12, the protective film 60 on the first contact layer 12 is removed. A predetermined resist pattern (electrode pattern) is formed on the protective film 60, and the protective film 60 in the opening is etched. A metal layer for conduction is formed by vapor deposition, and the resist is swelled to remove metal other than the electrode pattern, thereby forming the n-type electrode 70. The n-type electrode 70 can be formed from Ti, Pt, Au, Al, or the like. For example, the n-type electrode 70 can be formed of Ti / Pt / Au / Ti. The thickness (or total thickness) of the n-type electrode 70 is not limited, but is preferably 100 nm to 300 nm, and more preferably 150 nm to 250 nm. The formed n-type electrode 70 may be subjected to an alloying process. Here, in order to prevent the n-type electrode 70 from casting a shadow and reducing the amount of light reaching the light receiving section 33 , it is preferable to form the n-type electrode 70 at a position surrounding the outside of the light receiving section 33 .

[0039] <Step 9> As described above, step 9 is a step of forming an optical filter 80 around the protective film 60 and forming a pad electrode 71 for electrical conduction ( FIG. 9 ). In FIG. 9 , the optical filter 80 is formed so as to cover not only the top surface but also the side surfaces of the semiconductor laminate 10. However, the optical filter may be formed only on the protective film 60 on the top surface of the semiconductor laminate 10. In this embodiment, a dielectric multilayer film (interference filter) is assumed as the optical filter 80. However, this is not limited thereto. For example, an absorption filter that absorbs wavelengths outside the wavelength range including the peak light receiving wavelength may also be used. The pad electrode 71 is formed on the n-type electrode 70 and electrically connected to the n-type electrode 70. The surface of the pad electrode 71 is required to be uncovered by the optical filter 80 and exposed so as to allow electrical wiring to the outside. The formation of the optical filter 80 or the pad electrode 71 may be performed in any order. If the optical filter 80 is formed first, a predetermined pattern is first formed using a resist, and then a dielectric multilayer film is formed by vapor deposition or sputtering. For example, the dielectric multilayer film is a combination of low refractive index and high refractive index, and is made of SiO ２ / α-Si (amorphous silicon), AlO ３ / α-Si, SiO ２ / Si ３ N ４ , Si ３ N ４ / α-Si, SiO ２ / Ta ２ O ５ , Ta ２ O ５ Materials such as SiO / α-Si can be used. ２and α-Si multilayer films are used. The resist is swelled to remove the dielectric multilayer film outside the predetermined pattern, forming the optical filter 80. The optical filter 80 is preferably formed not only on the top but also on the side of the semiconductor laminate 10. The thickness of the optical filter 80 on the protective film 60 is preferably 300 nm to 20,000 nm, and more preferably 1,000 nm to 6,000 nm. Next, a pad electrode 71 is formed on the n-type electrode 70 for electrical continuity. A resist pattern is formed on the optical filter 80, and the optical filter 80 in the opening is removed to expose a portion of the surface of the n-type electrode 70. A metal layer constituting the pad electrode 71 is formed by vapor deposition, and the resist is swelled to remove the metal layer outside the predetermined pattern, forming the pad electrode 71 on the exposed portion of the n-type electrode 70. The pad electrode 71 can be formed of Ti, Pt, Au, Al, or the like. For example, the pad electrode 71 can be made of Ti / Pt / Au. The thickness (or total thickness) of the pad electrode 71 is not limited as long as it can be electrically connected to the n-type electrode 70. An alloying treatment may be performed on the formed pad electrode 71. When the pad electrode 71 is formed first, a predetermined pattern is formed on the pad electrode 71 using a resist, and the optical filter on the pad electrode 71 is peeled off to expose the surface of the pad electrode 71.

[0040] <Step 10> As described above, step 10 is a step of grinding the support substrate 200 and forming a back electrode 72 on the back surface of the support substrate 200 ( FIG. 10 ). The thickness of the support substrate 200 after grinding is preferably 80 μm to 280 μm, more preferably 200 μm or less. The total thickness including the support substrate 200 is preferably 100 μm to 300 μm, more preferably 100 μm to 220 μm. After grinding the support substrate 200, the back surface of the support substrate 200 is cleaned, and the back electrode 72 is formed by vapor deposition. For example, Ti / Pt / Au can be used as the back electrode 72. The thickness (or total thickness) of the back electrode 72 is not limited, but is preferably 100 nm to 500 nm. The formed back electrode 72 may be subjected to an alloying process.

[0041] Thereafter, the wafer is cut along the separation lines using a laser dicer to separate the wafer into individual chips.

[0042] (Variation 1) As Variation 1 of the above embodiment, a different type of light receiving section will be presented. In the above embodiment, a PIN junction is formed in the light receiving section 33 in the undoped light absorbing layer 14 by Zn diffusion, but the light absorbing layer 14 may be doped to form a PN junction light receiving section 33. Furthermore, the PIN junction or PN junction light receiving section 33 may be formed by doping during epitaxial growth rather than by Zn diffusion. Furthermore, the doping amount may be adjusted so as to form an APD (avalanche photodiode) type.

[0043] (Variation 2) As a variation 2 of the above embodiment, although the p-type electrode 40 is formed so as to cover the plate-shaped p-type contact layer 31 in the above embodiment, the shape of the p-type contact layer 31 may be any shape, such as an island shape, a striped shape, or a doughnut shape, and the shape of the p-type electrode 40 may also be changed to match the shape of the p-type contact layer 31 as long as it is in contact with the p-type contact layer 31. Furthermore, in the fourth step, the p-type electrode 40 may also be provided on the dielectric layer 20 in FIG. 3 so that the entire surface is covered with the p-type electrode 40, which also serves as the junction layer 51.

[0044] (Semiconductor Photodetector) Next, a semiconductor photodetector 1 obtained through at least the above-described growing step, contact region forming step, bonding layer forming step, bonding step, substrate removal step, and optical filter forming step will be described. As shown in Fig. 10, this semiconductor photodetector 1 includes a support substrate 200, a bonding layer 50 on the support substrate 200, a semiconductor laminate 10 having a light-receiving portion 33 on the bonding layer 50, and an optical filter 80 that transmits a wavelength range including the peak light-receiving wavelength on the semiconductor laminate 10. Furthermore, the semiconductor photodetector 1 has a p-type electrode 40 and a p-type contact layer 31 on the p-type electrode 40 at least in a portion between the bonding layer 50 and the semiconductor laminate 10, and is characterized in that light is not incident on the semiconductor laminate 10 from the bonding layer 50 side.

[0045] The optical filter 80, which transmits a wavelength range including the peak light-receiving wavelength, has a high transmittance in the wavelength range including the peak light-receiving wavelength, with the transmittance being 50% or more, and preferably 75% or more. That is, the optical filter 80 has the peak light-receiving wavelength of the semiconductor light-receiving element within a wavelength range with a transmittance of 50% or more. This wavelength range may be set to match the light-receiving sensitivity spectrum having the peak light-receiving wavelength of the semiconductor light-receiving element. For example, it is preferable to approximate the half-width range of the peak light-receiving sensitivity spectrum to the wavelength range including the peak light-receiving wavelength that the optical filter 80 transmits. The transmittance of the optical filter 80 at the peak light-receiving wavelength is preferably 75% or more, and more preferably 85% or more. Furthermore, it is preferable that the transmittance at wavelengths that are at least a certain distance from the peak light-receiving wavelength is low, and the transmittance of unwanted noise wavelengths outside this wavelength range is preferably 10% or less.

[0046] The relationship between the transmittance and wavelength of the optical filter 80 can be confirmed by measuring the transmittance spectrum of the optical filter 80 using a spectrophotometer. In the case of an optical filter 80 made of a dielectric multilayer film, the transmittance spectrum changes depending on the angle of incidence of light, so the transmittance spectrum for perpendicular incidence can be used, or the transmittance spectrum for omnidirectional incidence can be obtained by integrating the intensity values ​​of the transmittance spectrum for each angle of incidence while taking into account the area ratio (cosine function) of the incident surface for each angle of incidence.

[0047] The technical significance of providing a bonding layer 50 on the support substrate 200 in the semiconductor photodetector 1 will be described. In a semiconductor photodetector fabricated using an n-type InP substrate, a semiconductor layer is stacked on the n-type InP substrate, and an optical filter is stacked on the semiconductor layer. Light incident from the side of the n-type InP substrate enters the semiconductor layer from the n-type InP substrate side. That is, light incident on the semiconductor layer from the n-type InP substrate side does not pass through the optical filter and enters the photodetector without being blocked. In such a case, light having unnecessary wavelengths enters the photodetector and becomes noise components, reducing the sensitivity of the photodetector.

[0048] In contrast to this, according to this embodiment, by bonding the semiconductor stack 10 having the light receiving portion 33 to the support substrate 200 via a bonding layer 50 made of metal or the like, light from the support substrate 200 side is reflected by the bonding layer 50, and light having unnecessary wavelengths does not enter the semiconductor stack 10 including the light receiving portion 33. This makes it possible to reduce noise.

[0049] The semiconductor light-receiving element 1 may have an n-type contact layer 12 and an n-type electrode 70 between the semiconductor laminate 10 and the optical filter 80, and may further have a pad electrode 71 on the n-type electrode 70 that penetrates the optical filter 80. Furthermore, in the semiconductor light-receiving element 1, it is preferable that the p-type electrode 40 covers the bottom surface and side surfaces of the p-type contact layer 31 between the junction layer 50 and the semiconductor laminate 10.

[0050] In the semiconductor light-receiving element 1, the semiconductor laminate 10 may include a light-absorbing layer 14, and may include a light-receiving portion 33 in a partial region of the light-absorbing layer 14 in the in-plane direction. Furthermore, from a bird's-eye view, the p-type contact layer 31 only needs to have an area sufficient to reduce the contact resistance with the p-type electrode 40, and it is sufficient for it to overlap with the light-receiving portion 33 by 5% or more. This is to ensure that the current received and converted by the light-receiving portion 33 flows without loss due to resistance. Furthermore, by minimizing the overlapping area, unintended light absorption by the p-type contact layer 31 can be suppressed, thereby improving light-receiving sensitivity. From a bird's-eye view, the p-type contact layer 31 and the p-type electrode 40 have an overlapping portion and are in direct contact. The p-type electrode 40 may have an area equal to or greater than the p-type contact layer 31, and it is also preferable for it to overlap with the light-receiving portion 33 by 70% or more. This is because the area of ​​the p-type electrode 40 that does not overlap with the p-type contact layer 31 is expected to reflect light and increase light-receiving efficiency.

[0051] Furthermore, when viewed from above, the n-type electrode 70 can be placed anywhere on the semiconductor laminate 10. To prevent the n-type electrode 70 from casting a shadow and reducing the amount of light received, the n-type electrode 70 preferably has a shape that surrounds the light receiving portion 33 from the outside, excluding the pad electrode 71 area. In the conventional case where the p-type electrode 31 side is the main light incident surface (comparative example), the p-type electrode 31 needs to be formed along the outer periphery of the light receiving portion 33 and within the area of ​​the light receiving portion 33 from the outside, and the p-type electrode 31 blocks part of the light directed toward the light receiving portion 33. In this embodiment, the n-type electrode 70 can be shaped to surround the light receiving portion 33 from the outside, thereby increasing the area of ​​the light incident surface surrounded by the n-type electrode 70 and maximizing the area that can be received by the light receiving portion 33, thereby improving light receiving sensitivity.

[0052] In the semiconductor light-receiving element 1, the light-receiving peak wavelength (the wavelength at which the intensity in the light-receiving sensitivity spectrum is maximum) of the light-receiving portion 33 is preferably 800 nm or more and 2500 nm or less, more preferably 850 nm or more and 2000 nm or less, and even more preferably 900 nm or more and 1700 nm or less. The light-absorbing layer 14 is preferably an InGaAs layer. The half-width of the peak of the light-receiving sensitivity spectrum is, for example, 50 nm or more and 200 nm or less.

[0053] The semiconductor light receiving element 1 may further include an optical filter 80 on the side surface of the semiconductor laminate 10. Because the thickness of the semiconductor laminate 10 is sufficiently thinner than the thickness of the substrate, the amount of light reaching the light receiving portion through the side surface of the semiconductor laminate 10 is small, but having the optical filter 80 on the side surface of the semiconductor laminate 10 increases the noise reduction effect even slightly. Furthermore, the total thickness of the semiconductor laminate 10 is preferably 20 μm or less, and more preferably 15 μm or less. The thickness of the entire semiconductor light receiving element 1 including the support substrate 200 is preferably 100 μm or more and 300 μm or less, and more preferably 100 μm or more and 220 μm or less.

[0054] As already described in the embodiment of the manufacturing method, the semiconductor laminate 10 may include, in order from the bonding layer 50 side, a second buffer layer 15, a light absorption layer 14, and an n-type window layer 13. The semiconductor light-receiving element 1 may further have any other configuration. For example, as shown in FIG. 10 , the semiconductor light-receiving element 1 may be provided with a back electrode 72.

[0055] Other Embodiments The semiconductor light receiving element 1 and the manufacturing method of the semiconductor light receiving element 1 according to this embodiment have been described above using an example in which the first conductivity type is p-type and the second conductivity type is n-type. However, as another embodiment, a modification in which the first conductivity type is n-type and the second conductivity type is p-type is also possible. For example, in the first step, the first contact layer 12 can be a p-type InGaAs layer, the window layer 13 can be a p-type InP layer, the second buffer layer 15 can be an n-type InP layer, and the second contact layer 16 can be an n-type InGaAs layer. Alternatively, steps 2 to 4 can be omitted, and the first conductivity type electrode can be formed over the entire surface of the second contact layer 16. After bonding the support substrate 200 in step 5, steps 6 to 10 can be performed with the p-type and n-type electrodes interchanged.

[0056] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples. For reference numerals, please refer to Figures 1 to 10.

[0057] Example 1 A 3-inch n-type InP growth substrate 100 (thickness: 625 μm, Si doping, carrier density: 2 to 6×10 １８ / cm ３ An n-type InP first buffer layer 11 (thickness: 500 nm, Si doped, carrier density: 3×10) was deposited on the substrate (both surfaces mirror-finished) by MOCVD. １８ / cm ３ ), n-type In ０．５３ Ga ０．４７ As first contact layer 12 (thickness: 140 nm, Si doped, carrier density: 1×10 １８ / cm ３ ), an n-type InP window layer 13 (thickness: 1000 nm, Si doped, carrier density: 1×10 １８ / cm ３ ), i-type In ０．５３ Ga ０．４７As light absorption layer 14 (thickness: 2960 nm), n-type InP second buffer layer 15 (thickness: 1000 nm, slightly doped with Si, carrier density: 8×10 １５ / cm ３ ), i-type In ０．５３ Ga ０．４７ An As second contact layer 16 (thickness: 100 nm) was then formed. This state is shown in FIG.

[0058] A pattern as shown in FIG. 2 was formed on the i-type InGaAs second contact layer 16. This pattern was formed by forming a resist pattern, etching openings (etching portions), and then removing the resist. Here, H ２ SO ４ : H ２ O ２ : H ２ Next, a Si layer was deposited by plasma CVD on the n-type InP second buffer layer 15 including the i-type InGaAs second contact layer 16 that had been patterned. ３ N ４ The dielectric layer 20 (thickness: 100 nm) made of Si was deposited. ３ N ４ A resist pattern is formed on the insulating film, openings are etched, and then the resist is peeled off to form the Si as shown in FIG. ３ N ４ The dielectric layer 20 was formed. ３ N ４ An aqueous HF solution was used as the etching solution.

[0059] Zn was diffused in the depth direction of the i-type InGaAs second contact layer 16 by supplying a Zn source gas while heating using the MOCVD method. Zn was diffused into the i-type InGaAs second contact layer 16, the n-type InP second buffer layer 15, and a region extending 350 nm from the interface between the n-type InP second buffer layer 15 and the i-type InGaAs light absorption layer 14 toward the i-type InGaAs light absorption layer 14. DEZn (diethyl zinc) was used as the Zn source. Because Zn diffusion can form a p-type region, the p-type InGaAs contact layer 31, the n-type InP second buffer layer 15, and the InGaAs absorption layer 14 have p-type regions 32 after Zn diffusion. The interface between the p-type region 32 and the i-type InGaAs light absorption layer 14 is the light receiving portion 33. The carrier density in the p-type region is 2 × 10 １８ / cm ３ Let's say.

[0060] By plasma CVD method, Si ３ N ４ The dielectric layer 20 (thickness: 200 nm) made of Si was formed and etched to form the Si layer shown in FIG. ３ N ４ The dielectric layer 20 was formed on the p-type InGaAs contact layer 31. Furthermore, a p-type electrode 40 (Ti (thickness: 30 nm) / Pt (thickness: 50 nm) / Au (thickness: 120 nm)) was formed by vapor deposition on the p-type InGaAs contact layer 31. The vapor-deposited p-type electrode 40 was alloyed by heating at 300°C for 10 minutes. When the semiconductor light-receiving element 1 was viewed from above, the shape of the p-type electrode 40 was similar to that of the light-receiving portion 33, with the center aligned, and the area of ​​the p-type electrode 40 overlapped with the area of ​​the light-receiving portion 33 by 77.4% (p-type electrode 40 / light-receiving portion 33 = area ratio 77.4%).

[0061] A bonding layer (growth substrate side) 51 (Ti (thickness: 30 nm) / Pt (thickness: 50 nm) / Au (thickness: 1000 nm)) was formed by vapor deposition on the dielectric layer 20 and the p-type electrode 40. Meanwhile, a bonding layer (support substrate side) 52 (Ti (thickness: 600 nm) / Pt (thickness: 20 nm) / Au (thickness: 900 nm)) was formed by vapor deposition on a conductive Si substrate (thickness: 200 μm, B-doped, 0.005 Ω·cm) that served as the support substrate 200.

[0062] The bonding layer (growth substrate side) 51 and the bonding layer (support substrate side) 52 were arranged facing each other and subjected to thermal compression bonding at 300° C. and 7 kN. Then, the n-type InP growth substrate 100 and the n-type InP first buffer layer 11 were removed by wet etching. The etching solution used was H ２ SO ４ : H ２ O ２ : H ２ The solution was a mixture of InP and InGaAs with a ratio of HCl:CH 3 : 1:1:7. The stacked structure thus far was immersed in the InP and InGaAs etching solutions, respectively, for a total of two hours. This process etched the n-type InP first buffer layer 11 (FIG. 6). The InP and InGaAs etching solutions used here were HCl:CH 3 : 1:1:7, respectively. ３ COOH=1:1 and H ２ SO ４ : H ２ O ２ : H ２ O=3:1:1.

[0063] As shown in FIG. 7, the n-type InGaAs first contact layer 12 was etched so that only the portion where the n-type electrode 70 was to be formed remained. ２ SO ４ : H ２ O ２ : H ２ A solution of SiO2 was used, in which the ratio of SiO2 to SiO2 was 1:1:7. ２ A resist pattern was formed with an opening around the periphery of the chip area, and the SiO ２ The layer was etched with an aqueous HF solution. After the resist was removed, the opening (SiO２ The semiconductor laminate 10 below the portion where the film is not formed was dry-etched until it reached the dielectric layer 20, thereby forming a mesa pattern. At this time, the dry etching conditions were SiCl ４ 9 sccm, Ar 20 sccm, ICP plasma 190 W, pressure 0.25 Pa, and stage temperature 200° C. The remaining SiO 2 layer was then removed by etching using an aqueous HF solution.

[0064] By plasma CVD, Si is formed around the semiconductor laminate 10 including the n-type InGaAs first contact layer 12. ３ N ４ A protective film 60 (thickness: 177 nm) was formed. An electrode pattern was formed on the n-type InGaAs first contact layer 12, and the protective film 60 on the electrode pattern was removed by etching. The etching solution used was an aqueous HF solution. Next, an n-type electrode 70 (Ti (thickness: 30 nm) / Pt (thickness: 50 nm) / Au (thickness: 120 nm) / Ti (thickness: 10 nm)) was formed on the n-type InGaAs first contact layer 12 by forming a resist pattern, vapor-depositing the n-type electrode 70, and lifting off the resist pattern, as shown in FIG. 8 . Here, when viewed from above the semiconductor light-receiving element 1, the n-type electrode 70 had a frame shape surrounding the light-receiving portion 33 at a fixed interval, and the width of the inner periphery of the n-type electrode 70 relative to the width of the light-receiving portion 33 was 112%.

[0065] By forming a resist pattern, depositing the optical filter 80, and lifting off the resist pattern, the optical filter 80 was formed so as to cover the upper and side surfaces of the semiconductor laminate 10 except for a portion of the surface of the n-type electrode 70. The optical filter 80 was deposited by sputtering, and the optical filter 80 was made of silicon dioxide (SiO ２ The optical filter 80 is a multilayer film of amorphous silicon (α-Si) and amorphous silicon (α-Si), with a total thickness of 3171 nm. The configuration of the optical filter 80 is shown in Table 1. The optical transmission characteristics of this optical filter (the value obtained by integrating the transmittance of each wavelength at each incident angle of 0° to 90°, taking into account the area ratio with respect to the incident angle) were 89% transmittance at 1010 nm and 2% transmittance at 1300 nm, which is an unwanted noise wavelength.

[0066] Furthermore, a circular pad electrode 71 (Ti (30 nm) / Pt (50 nm) / Au (1000 nm)) was formed on the n-type electrode 70 exposed from the optical filter 80 by forming a resist pattern, depositing the pad electrode 71, and lifting off the resist pattern, as shown in FIG. 9 .

[0067] The rear surface of the support substrate 200 was polished to a thickness of about 150 μm. After cleaning the support substrate 200, a rear electrode 72 (Ti (10 nm) / Pt (50 nm) / Au (200 nm)) was formed on the rear surface of the support substrate 200 by vapor deposition.

[0068] The optical filter 80, dielectric layer 20, bonding layer 50, support substrate 200, and back electrode 72 on the planned separation line between chip regions created by the mesa pattern were cut using a laser dicer and separated into individual semiconductor light-receiving element chips.

[0069]

[0070] 11 is a schematic cross-sectional view of a semiconductor light-receiving element according to Example 2. In Example 2, the seventh step, dry etching for forming a mesa pattern, was not performed, and the semiconductor light-receiving element chip of Example 2 was obtained in the same manner as Example 1, except that, with the protective film 60 and the optical filter 80 remaining only on the top surface of the semiconductor laminate 10, the semiconductor laminate 10 and the optical filter 80, including the semiconductor laminate 10, from the back electrode 72 were cut along the planned separation lines using a laser dicer to separate the chip. No optical filter was formed on the side surface of the semiconductor laminate 10 in the semiconductor light-receiving element chip of Example 2.

[0071] Comparative Example: A schematic diagram of a semiconductor light-receiving element according to a comparative example is shown in FIG. 12. This semiconductor light-receiving element according to the comparative example is a conventional semiconductor light-receiving element that does not use a bonding layer. The semiconductor light-receiving element according to the comparative example was fabricated as follows. First, an InP buffer layer 15 (thickness: 1 μm), an InGaAs light absorption layer 14 (thickness: 2.7 μm), an n-type InP window layer 13 (thickness: 1 μm), and an i-type InGaAs contact layer 16 (thickness: 0.1 nm) were sequentially formed on the surface of an n-type InP substrate 100 (thickness: approximately 625 μm) using the MOCVD method. Next, the i-type InGaAs contact layer 16 was patterned to have a rectangular frame shape with rounded corners. Next, a Si film was used as a mask during Zn diffusion by plasma CVD. ３ N ４ A dielectric layer 20 (thickness: 100 nm) made of InGaAs was then formed, followed by patterning to have a square opening with rounded corners that contained the i-type InGaAs contact layer 16, and etching was performed. Zn was diffused into the region not covered by the dielectric layer 20 by supplying a Zn source gas while heating using the MOCVD method, converting the i-type InGaAs contact layer to p-type, forming a p-type InGaAs contact layer 31. The Zn-diffused regions of the n-type InP window layer 13 and the InGaAs light absorption layer 14 were converted to p-type, forming a p-type region 32 and a light receiving portion 33. Next, a Si ３ N ４A protective film 60 (thickness: 177 nm) was formed on the entire surface of the p-type InGaAs contact layer 31, including the inner periphery of the frame shape, to form a dielectric layer 20 that also served as the protective film 60. The dielectric layer 20 on the p-type InGaAs contact layer 31 was then removed by patterning and etching. A frame-shaped p-type electrode 40 (Ti (thickness: 30 nm) / Pt (thickness: 50 nm) / Au (thickness: 1000 nm) / Ti (thickness: 10 nm)) was then formed on the p-type InGaAs contact layer 31. Next, a circular pad electrode (Ti (thickness: 30 nm) / Pt (thickness: 50 nm) / Au (thickness: 1000 nm), not shown) was formed on a portion of the p-type electrode 40. Furthermore, an optical filter 80 similar to that of Example 1 was formed, except for the surface of the pad electrode. The back surface of the n-type InP substrate 100 was polished to a thickness of approximately 150 μm. Finally, an n-type back electrode 72 (Au (10 nm) / Ge (34 nm) / Au (57 nm) / Ni (34 nm) / Au (550 nm) / Ti (50 nm) / Pt (50 nm) / Au (200 nm)) was formed on the back surface of the n-type InP substrate 100. Both the p-type electrode 40 and the n-type back electrode 72 were alloyed by annealing. Thereafter, the optical filter 80 to the n-type back electrode 72 were cut using a laser dicer and separated into individual pieces to obtain semiconductor photodetector chips of the comparative example.

[0072] The method for measuring the light-receiving sensitivity of Examples 1 and 2 and the comparative example will be described. An optical fiber connected to a spectral light source was inserted into a 1-inch integrating sphere, which served as the light source. The light taken into the integrating sphere was scattered internally, resulting in uniform light within the sphere. By placing a light-receiving element (semiconductor light-receiving element sample) inside the integrating sphere, uniform light was irradiated onto the light-receiving element, generating a photocurrent. The light-receiving spectrum was measured by measuring the photocurrent at each wavelength. Here, the light-receiving element was irradiated with light at an incident angle of -90° to 90°.

[0073] The individualized semiconductor light-receiving element chips of Examples 1 and 2 and the Comparative Example were mounted (mounted) on a TO gold stem using silver paste and wire-bonded to prepare semiconductor light-receiving element samples, and the photocurrent value (A) was measured. Specifically, silver paste was first applied to the surface of the TO gold stem using a dispenser. The individualized chips were placed on top of the silver paste and bonded, and then heat-treated to harden the silver paste and secure (mount) the chips. Wire bonding was then performed to connect the chip pad electrodes to the TO gold stem with Au wires, establishing electrical continuity. The integrating sphere was provided with a terminal socket for the TO gold stem, and the TO gold stem was inserted into the socket to establish electrical continuity, thereby measuring the light-receiving sensitivity within the integrating sphere. Although the optical output (W) emitted from the spectral light source and incident on the actual sample was unknown, a relative comparison was possible. Therefore, the signal ratio when the light-receiving sensitivity at 1010 nm of the Comparative Example was set to 1 was used as the test result. The results at 1010 nm and 1300 nm for the Comparative Example, Examples 1, and 2 are shown in Table 2. Furthermore, for Example 1 and the Comparative Example, spectra at each wavelength (photosensitivity spectra) calculated by setting the photosensitivity at 1010 nm for the Comparative Example to 1 are shown in Figures 13A and 13B. Figures 13A and 13B are graphs of the same data, with the vertical axis in Figure 13A being on a linear scale and the vertical axis in Figure 13B being on a logarithmic scale.

[0074]

[0075] As shown in Table 2, when the photosensitivity at the peak light-receiving wavelength (1010 nm) of the comparative example is taken as 1.00, the photosensitivity at the noise wavelength (1300 nm) of the comparative example is 0.033, the photosensitivity at the peak light-receiving wavelength of Example 1 is 1.25, and the photosensitivity at the noise wavelength of Example 1 is 0.017. Furthermore, the photosensitivity at the peak light-receiving wavelength of Example 2 is 1.25, and the photosensitivity at the noise wavelength of Example 2 is 0.020. The photosensitivity at the peak light-receiving wavelength is higher in Examples 1 and 2, which is thought to be due to the wider opening of the n-type electrode on the light incident surface side (see FIG. 13A ). Furthermore, the noise ratio, which is the value obtained by dividing the photosensitivity at the noise wavelength by the photosensitivity at the peak light-receiving wavelength, is 3.3% for the comparative example, while the noise ratio is 1.4% for Example 1 and 1.6% for Example 2. In Examples 1 and 2, the ratio of noise components was reduced compared to the comparative example (see FIG. 13B). This is thought to be because the metal bonding layer on the support substrate prevented light from entering the semiconductor stack from the bonding layer side. Furthermore, the noise ratio in Example 1 was 1.4%, while the noise ratio in Example 2 was 1.6%, demonstrating that forming the optical filter 80 on not only the top surface but also the side surface of the semiconductor stack 10 as in Example 1 can reduce the light receiving sensitivity at noise wavelengths more than forming the optical filter 80 only on the top surface of the semiconductor stack 10 as in Example 2.

[0076] REFERENCE SIGNS LIST 1 semiconductor light receiving element 100 growth substrate 200 support substrate 10 semiconductor laminate 11 first buffer layer 12 first contact layer 13 window layer 14 light absorption layer 15 second buffer layer 16 second contact layer 20 dielectric layer 30 Zn diffusion region 31 p-type (first conductivity type) contact layer 32 p-type region 33 light receiving portion 40 p-type (first conductivity type) electrode 50 bonding layer 51 bonding layer (growth substrate side) 52 bonding layer (support substrate side) 60 protective film 70 n-type (second conductivity type) electrode 71 pad electrode 72 back electrode 80 optical filter

Claims

1. A semiconductor light-receiving element comprising: a support substrate; a bonding layer on the support substrate; a semiconductor laminate having a light-receiving portion located on the bonding layer; and an optical filter located on the semiconductor laminate and transmitting a wavelength range including a peak light-receiving wavelength; wherein the semiconductor laminate has a first conductivity type electrode and a first conductivity type contact layer located on the first conductivity type electrode at least in a portion between the bonding layer and the semiconductor laminate; and wherein light is not incident on the semiconductor laminate from the bonding layer side.

2. The semiconductor light-receiving element according to claim 1, further comprising a second conductivity type contact layer and a second conductivity type electrode between the semiconductor laminate and the optical filter, and a pad electrode on the second conductivity type electrode.

3. The semiconductor light-receiving element according to claim 1, wherein the first conductivity type electrode covers the bottom and side surfaces of the first conductivity type contact layer between the bonding layer and the semiconductor laminate, and a dielectric layer is provided in a second region different from a first region including the first conductivity type electrode or the first conductivity type contact layer.

4. The semiconductor light-receiving element according to claim 2, wherein the semiconductor laminate has a light-absorbing layer, the light-receiving portion is located in a partial area in the in-plane direction of the light-absorbing layer, and the second conductivity type electrode has a shape that surrounds the light-receiving portion from above, excluding the area of ​​the pad electrode.

5. The semiconductor photodetector according to claim 4, wherein the peak light-receiving wavelength is 800 nm or more and 2500 nm or less, and the light absorption layer is an InGaAs layer.

6. The semiconductor light receiving element according to claim 1, further comprising the optical filter on a side surface of the semiconductor laminate.

7. The semiconductor light-receiving element according to claim 1, wherein the thickness of the semiconductor laminate is 20 μm or less, and the total thickness including the support substrate is 100 μm or more.

8. A method for manufacturing a semiconductor light-receiving element, comprising: a growth step of forming a semiconductor laminate having a light-receiving portion on a growth substrate; a contact region formation step of forming a first conductivity type contact layer and a first conductivity type electrode on at least a portion of the semiconductor laminate; a bonding layer formation step of forming a bonding layer on the semiconductor laminate; a bonding step of bonding a support substrate via the bonding layer; a substrate removal step of removing the growth substrate; and a step of forming an optical filter that transmits a wavelength range including the light-receiving peak wavelength on the semiconductor laminate exposed by the substrate removal step.

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