Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units, a plurality of data signal lines, a plurality of data connecting lines, and a plurality of power supply traces, wherein the data signal lines are configured to provide data signals to a pixel driving circuit, the data connecting lines are configured to provide data signals to the data signal lines, and the power supply traces are configured to provide power supply signals to a light-emitting device. The display substrate at least comprises a first region (110) and a second region (120), wherein the first region (110) is a region in which the data connecting lines are arranged, the second region (120) is a region in which the power supply traces are arranged, at least one power supply trace comprises a first power supply trace (91) and a second power supply trace (92), and in at least one circuit unit of the second region (120), the first power supply trace (91) and the second power supply trace (92) are connected to each other by means of a power transfer strip (93) to form a mesh-connected structure.

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a driving structure layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate; the driving structure layer comprises at least a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines and a plurality of power supply lines, at least one circuit unit comprising a pixel driving circuit, the data signal line being configured to provide a data signal to the pixel driving circuit, the data connection line being configured to provide a data signal to the data signal line; the light emitting structure layer comprises at least a plurality of light emitting units, at least one light emitting unit comprising a light emitting device, the power supply line being configured to provide a power supply signal to the light emitting device; in a plane parallel to the substrate, the display substrate comprises at least a first area and a second area, the first area being an area where the data connection line is disposed, and the second area being an area where the power supply line is disposed; at least one power supply line comprises a first power supply line extending along a first direction and a second power supply line extending along a second direction, the first direction and the second direction intersecting; in at least one circuit unit of the second area, the first power supply line and the second power supply line are connected to each other through a power supply adapter strip, forming a grid communication structure.

[0006] In an example embodiment, in a direction perpendicular to the substrate, the driving structure layer comprises a plurality of conductive layers, the first power supply trace and the second power supply trace are disposed in different conductive layers, and the first power supply trace and the power supply transfer bar are disposed in the same conductive layer.

[0007] In an example embodiment, the plurality of conductive layers at least comprises a first source-drain metal layer, a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer disposed on a side of the second source-drain metal layer away from the substrate, the first power supply trace and the power supply transfer bar are disposed in the second source-drain metal layer, and the second power supply trace is disposed in the third source-drain metal layer.

[0008] In an example embodiment, at least one circuit unit of the second region further comprises a power supply connection electrode, the power supply connection electrode is disposed in the second source-drain metal layer, one end of the power supply transfer bar is connected with the first power supply trace, the other end of the power supply transfer bar is connected with the power supply connection electrode, and the second power supply trace is connected with the power supply connection electrode through a via.

[0009] In an example embodiment, in at least one circuit unit, the first power supply trace, the power supply transfer bar, and the power supply connection electrode are an integrated structure connected with each other.

[0010] In an example embodiment, a projection of the second power supply trace on the substrate at least partially overlaps with a projection of the power supply transfer bar on the substrate.

[0011] In an example embodiment, in the first direction, the power supply transfer bar has a first power supply transfer bar edge and a second power supply transfer bar edge, the second power supply transfer bar edge is located on a side of the first power supply transfer bar edge in the first direction, the second power supply trace has a first power supply trace edge and a second power supply trace edge, the first power supply trace edge is located on a side of the first power supply transfer bar edge away from the second power supply trace edge, and the second power supply trace edge is located on a side of the second power supply transfer bar edge away from the first power supply trace edge; a distance between the first power supply trace edge and the first power supply transfer bar edge is greater than or equal to 0.6 μm, a distance between the second power supply trace edge and the second power supply transfer bar edge is greater than or equal to 0.6 μm, and the distances are dimensions in the first direction.

[0012] In an example embodiment, at least one circuit unit further comprises a spacer, the spacer is disposed in the first source-drain metal layer, and a projection of the spacer on the substrate at least partially overlaps with a projection of the power supply transfer bar on the substrate.

[0013] In an example embodiment, the power adapter strip has a first power adapter strip edge and a second power adapter strip edge, the second power adapter strip edge being located on one side of the first power adapter strip edge in the first direction, the spacer has a first spacer edge and a second spacer edge, the first spacer edge being located on one side of the first power adapter strip edge away from the second spacer edge, the second spacer edge being located on one side of the second power adapter strip edge away from the first spacer edge; a distance between the first spacer edge and the first power adapter strip edge is greater than or equal to 0.6 μm, a distance between the second spacer edge and the second power adapter strip edge is greater than or equal to 0.6 μm, the distance being a dimension in the first direction.

[0014] In an example embodiment, the at least one circuit unit further comprises an initial signal line configured to provide an initial signal to the pixel driving circuit, the spacer is connected to the initial signal line.

[0015] In an example embodiment, the plurality of light emitting units comprises at least a red light emitting unit emitting red light, a blue light emitting unit emitting blue light, a first green light emitting unit emitting green light, and a second green light emitting unit emitting green light, the red light emitting unit comprises at least a first anode, the blue light emitting unit comprises at least a second anode, the first green light emitting unit comprises at least a third anode, and the second green light emitting unit comprises at least a fourth anode; a projection of the first anode on the substrate at least partially overlaps with a projection of the power adapter strip on the substrate, projections of the second anode, the third anode, and the fourth anode on the substrate do not overlap with the projection of the power adapter strip on the substrate; or, a projection of the second anode on the substrate at least partially overlaps with the projection of the power adapter strip on the substrate, projections of the first anode, the third anode, and the fourth anode on the substrate do not overlap with the projection of the power adapter strip on the substrate; or, projections of the first anode and the second anode on the substrate at least partially overlap with the projection of the power adapter strip on the substrate, projections of the third anode and the fourth anode on the substrate do not overlap with the projection of the power adapter strip on the substrate; or, a projection of the third anode and / or the fourth anode on the substrate at least partially overlaps with the projection of the power adapter strip on the substrate, projections of the first anode and the second anode on the substrate do not overlap with the projection of the power adapter strip on the substrate.

[0016] In an exemplary embodiment, the first anode, the second anode, the third anode, or the fourth anode comprises at least an anode main portion and an anode shielding portion, the anode shielding portion is connected with the anode main portion, and a projection of the anode shielding portion on the substrate at least partially overlaps with a projection of the power adapter strip on the substrate.

[0017] In an exemplary embodiment, a projection of the anode shielding portion on the substrate contains a projection of the power adapter strip on the substrate, and an area of the projection of the anode shielding portion on the substrate is greater than an area of the projection of the power adapter strip on the substrate.

[0018] In an exemplary embodiment, the second region comprises at least a second transition region and a second normal region, the second transition region is located between the first region and the second normal region; the second transition region comprises a plurality of first repeating units and a plurality of second repeating units, the second normal region comprises a plurality of first repeating units, the first repeating unit is a repeating unit provided with the power adapter strip, and the second repeating unit is a repeating unit without the power adapter strip; the number of the first repeating units in one repeating row of the second transition region is less than or equal to the number of the first repeating units in one repeating row of the second normal region, and / or the number of the first repeating units in one repeating column of the second transition region is less than or equal to the number of the first repeating units in one repeating column of the second normal region.

[0019] In an exemplary embodiment, the second transition region comprises at least a first sub-region, the first sub-region is arranged on a side of the first region in the opposite direction of the first direction; the first sub-region comprises a plurality of repeating rows, at least one repeating row comprises at least one first repeating unit and a plurality of second repeating units, the number of the first repeating units in the jth repeating row is greater than or equal to the number of the first repeating units in the ith repeating row, the jth repeating row is located on a side of the ith repeating row away from the first region, and i and j are natural numbers.

[0020] In an exemplary embodiment, the second transition region comprises at least a second sub-region, the second sub-region is arranged on a side of the first region in the first direction or a side of the first region in the opposite direction of the first direction; the second sub-region comprises a plurality of repeating columns, at least one repeating column comprises at least one first repeating unit and a plurality of second repeating units, the number of the first repeating units in the jth repeating column is greater than or equal to the number of the first repeating units in the ith repeating column, the jth repeating column is located on a side of the ith repeating column away from the first region, and i and j are natural numbers.

[0021] In an exemplary embodiment, the repeating unit includes 8 circuit units, the 8 circuit units form a first unit row and a second unit row, and form a first unit column, a second unit column, a third unit column and a fourth unit column, a power supply connection electrode is arranged between the third unit column and the fourth unit column in the first unit row, and a power supply connection electrode is arranged between the first unit column and the second unit column in the second unit row.

[0022] In another aspect, the present disclosure also provides a display device including the aforementioned display substrate.

[0023] In yet another aspect, the present disclosure also provides a method for manufacturing a display substrate, including:

[0024] forming a driving structure layer on a substrate, the driving structure layer including at least a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines and a plurality of power supply traces, at least one circuit unit including a pixel driving circuit, the data signal lines being configured to provide data signals to the pixel driving circuit, the data connection lines being configured to provide data signals to the data signal lines;

[0025] forming a light emitting structure layer on the driving structure layer, the light emitting structure layer including at least a plurality of light emitting units, at least one light emitting unit including a light emitting device, the power supply traces being configured to provide power supply signals to the light emitting device;

[0026] In a plane parallel to the substrate, the display substrate includes at least a first region and a second region, the first region being a region where the data connection lines are arranged, and the second region being a region where the power supply traces are arranged; at least one power supply trace includes a first power supply trace extending along a first direction and a second power supply trace extending along a second direction, the first direction and the second direction intersecting; in at least one circuit unit of the second region, the first power supply trace and the second power supply trace are connected to each other through a power supply transfer strip, forming a grid communication structure.

[0027] Other aspects can become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating the principles of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and do not limit the present disclosure.

[0029] FIG. 1 is a structural schematic diagram of a display device;

[0030] FIG. 2 is a structural schematic diagram of a display substrate;

[0031] FIG. 3 is a schematic diagram of a planar structure of a display region in a display substrate;

[0032] FIG. 4 is a schematic diagram of a cross-sectional structure of a display region in a display substrate;

[0033] FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0034] FIG. 6 is a schematic diagram of a structure of a data connection line according to an example embodiment of the present disclosure;

[0035] FIG. 7 is a schematic diagram of a region division according to an example embodiment of the present disclosure;

[0036] FIG. 8 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure;

[0037] FIG. 9 is a schematic diagram of a structure of a data connection line and a power supply trace according to an example embodiment of the present disclosure;

[0038] FIG. 10 is a schematic diagram after forming a first semiconductor layer pattern according to an example embodiment of the present disclosure;

[0039] FIGS. 11A and 11B are schematic diagrams after forming a first conductive layer pattern according to an example embodiment of the present disclosure;

[0040] FIGS. 12A and 12B are schematic diagrams after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0041] FIGS. 13A and 13B are schematic diagrams after forming a second semiconductor layer pattern according to an example embodiment of the present disclosure;

[0042] FIGS. 14A and 14B are schematic diagrams after forming a third conductive layer pattern according to an example embodiment of the present disclosure;

[0043] FIG. 15 is a schematic diagram after forming a sixth insulating layer pattern according to an example embodiment of the present disclosure;

[0044] FIGS. 16A and 16B are schematic diagrams after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0045] FIG. 17 is a schematic diagram after forming a first planar layer pattern according to an example embodiment of the present disclosure;

[0046] FIGS. 18A and 18B are schematic diagrams after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0047] FIG. 18C is a schematic diagram of a positional relationship between a data transfer bar and a pad in FIG. 18A;

[0048] FIG. 18D is a schematic diagram of a positional relationship between a power supply transfer bar and a pad in FIG. 18A;

[0049] FIG. 19 is a schematic diagram after forming a second planar layer pattern according to an example embodiment of the present disclosure;

[0050] FIGS. 20A and 20B are schematic diagrams of the sixth conductive layer pattern formed according to an embodiment of the present disclosure;

[0051] FIG. 20C is a schematic diagram of the position relationship between the data transfer strip and the second data connection line in FIG. 20A;

[0052] FIG. 20D is a schematic diagram of the position relationship between the power transfer strip and the second power connection line in FIG. 20A;

[0053] FIG. 21 is a schematic diagram of the third planarization layer pattern formed according to an embodiment of the present disclosure;

[0054] FIGS. 22A and 22B are schematic diagrams of the anode conductive layer pattern formed according to an embodiment of the present disclosure;

[0055] FIG. 23 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0056] FIG. 24 is a schematic diagram of a repeating unit in a second normal region according to an exemplary embodiment of the present disclosure;

[0057] FIG. 25 is a schematic diagram of a repeating unit in a first sub-region according to an exemplary embodiment of the present disclosure;

[0058] FIG. 26 is a schematic diagram of a repeating unit in a second sub-region according to an exemplary embodiment of the present disclosure.

[0059] The following signs are explained: 11-first active layer; 12-second active layer; 13-third active layer; 14-fourth active layer; 15-fifth active layer; 16-sixth active layer; 17-seventh active layer; 18-eighth active layer; 21-first scanning signal line; 22-second scanning signal line; 23-third scanning signal line; 24-fourth scanning signal line; 25-emitting signal line; 31-first plate; 32-second plate; 33-opening; 34-plate connecting strip; 35-shielding line; 41-first initial signal line; 42-second initial signal line; 43-third initial signal line; 44-first initial connecting line; 45-second initial connecting line; 46-third initial connecting line; 51-first connecting electrode; 52-second connecting electrode; 53-third connecting electrode; 54-fourth connecting electrode; 55-fifth connecting electrode; 56-sixth connecting electrode; 57-seventh connecting electrode; 58-eighth connecting electrode; 59-ninth connecting electrode; 60-pad; 61-eleventh connecting electrode; 62-twelfth connecting electrode; 63-thirteenth connecting electrode; 71-first power supply line; 72-data signal line; 73-anode connecting electrode; 80-data lead-out line; 81-first data connecting line; 82-second data connecting line; 83-data transfer strip; 84-data connecting electrode; 91-first power supply trace; 92-second power supply trace; 93-power supply transfer strip; 94-power supply connecting electrode; 100-display area; 101-substrate; 102-driving structure layer; 103-emitting structure layer; 104-encapsulation structure layer; 110-first area; 120-second area; 130-second transition area;130-1 - first sub-region; 130-2 - second sub-region; 140 - second normal region; 200 - binding region; 300 - frame region. DETAILED DESCRIPTION

[0060] For the purposes of the present disclosure, the technical solutions and advantages will be more apparent, below, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. Those skilled in the art can easily understand the fact that the means and content can be converted into various forms without departing from the spirit of the present disclosure and the scope thereof. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0061] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example: the width-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line, can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure. The drawings described in the present disclosure are only schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0062] The ordinal numbers "first", "second", "third" and the like in the present specification are set in order to avoid confusion of the components, and are not intended to be limited in terms of numbers.

[0063] In the present specification, for the convenience of description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to explain the positional relationship of the components with reference to the drawings, only for the purpose of facilitating the description of the present specification and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately replaced according to the situation.

[0064] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, can be fixedly connected, or detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected via an intervening member, or communication between two elements inside. The specific meaning of the above terms in the present disclosure can be understood in light of the specific circumstances for those skilled in the art.

[0065] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0066] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0067] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit or receive an electrical signal between elements to be connected. Examples of the element having a certain electrical action include an electrode and a wiring, a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having another function.

[0068] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus, a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus, a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0069] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0070] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There can be some small deformation due to a tolerance, there can be a lead angle, an arc edge, and deformation, etc.

[0071] In the present disclosure, "about" means not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0072] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0073] FIG. 2 is a structural schematic diagram of a display substrate. As shown in FIG. 2, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 can be a flat area including a plurality of sub-pixels constituting a pixel array, the plurality of sub-pixels being configured to display dynamic pictures or static images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display substrate can adopt a flexible substrate, and thus the display substrate can be deformable, for example, curled, bent, folded, or rolled up.

[0074] In an exemplary embodiment, the binding area 200 can include, in sequence along a direction away from the display area, a lead-out line area, a bending area, a driving chip area, and a binding pin area, the lead-out line area being connected to the display area 100 and including at least data lead-out lines. The bending area can be connected to the lead-out line area and can include at least a composite insulating layer provided with a recess configured to bend the binding area to the back of the display area. The driving chip area can include an integrated circuit (IC) configured to be connected to the plurality of data lead-out lines. The binding pin area can include a bonding pad configured to be connected to an external flexible printed circuit (FPC).

[0075] In an exemplary embodiment, the frame area 300 can include, in sequence along a direction away from the display area 100, a circuit area, a power line area, a crack dam area, and a cutting area. The circuit area can be connected to the display area 100 and can include at least a gate drive circuit connected to a scanning signal line and a light-emitting signal line in the display area 100. The power line area can be connected to the circuit area and can include at least a frame power lead extending along a direction parallel to an edge of the display area and connected to a cathode in the display area 100. The crack dam area can be connected to the power line area and can include at least a plurality of cracks provided on a composite insulating layer. The cutting area can be connected to the crack dam area and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0076] In an exemplary embodiment, the lead-out line area in the binding area 200 and the power line area in the frame area 300 can be provided with an isolation dam, the isolation dam extending along a direction parallel to an edge of the display area and forming a ring structure surrounding the display area 100, the edge of the display area being an edge of the display area on one side of the binding area or the frame area.

[0077] FIG. 3 is a schematic diagram of a planar structure of a display region in a display substrate. As shown in FIG. 3, the display region can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected to the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0078] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG manner.

[0079] In other example embodiments, a pixel unit can include three sub-pixels arranged in a horizontal parallel manner or a vertical parallel manner, and the present disclosure does not limit the same.

[0080] FIG. 4 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, and the present disclosure does not limit the same.

[0081] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device that can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, the second encapsulation layer being arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0082] FIG. 5 is an equivalent circuit schematic diagram of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0083] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0084] In an example embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power supply line VDD.

[0085] In an exemplary embodiment, the first transistor T1 can be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is connected to the third node N3.

[0086] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3.

[0087] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0088] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0089] In an exemplary embodiment, the fifth transistor T5 can be referred to as a first emission control transistor, a gate electrode of the fifth transistor T5 is connected to the emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0090] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second emission control transistor, a gate electrode of the sixth transistor T6 is connected to the emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0091] In an exemplary embodiment, the seventh transistor T7 can be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0092] In an exemplary embodiment, the eighth transistor T8 can be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0093] In an example embodiment, the first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0094] In an example embodiment, the first power supply line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, the second power supply line VSS is configured to provide a constant second voltage signal to the light emitting device, and the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial voltage signal, the second initial voltage signal, and the third initial voltage signal can be constant voltage signals, which are not limited in the present disclosure.

[0095] In an example embodiment, the first transistor T1 to the eighth transistor T8 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 can include P-type transistors and N-type transistors.

[0096] In an example embodiment, the first transistor T1 to the eighth transistor T8 can be low temperature poly-silicon transistors, or can be oxide transistors, or can be low temperature poly-silicon transistors and metal oxide transistors. The active layer of the low temperature poly-silicon transistor adopts low temperature poly-silicon (LTPS), and the active layer of the metal oxide transistor adopts metal oxide semiconductor (Oxide). The low temperature poly-silicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon transistor and the metal oxide transistor on one display substrate forms an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0097] In an example embodiment, the second transistor T2 can be a metal oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be low temperature poly-silicon transistors.

[0098] With the development of display technology, consumers have higher and higher requirements on display effect and display quality of display products. Full screen and narrow frame products have gradually become the development trend of display products due to their large screen ratio and ultra-narrow frame. Therefore, the narrow frame design or even the frameless design of OLED display products is paid more and more attention. In a display substrate, the data signals of integrated circuits in a binding area need to be introduced into a wider display area in a fanout manner through data lead-out lines, so that the lead-out line area occupies a larger space, resulting in a larger width of the lower frame. In addition, the gate drive circuit and the power lead line need to be arranged in the frame area, and the gate drive circuit and the power lead line occupy a larger space, resulting in a larger width of the left and right frames.

[0099] To reduce the width of the lower frame, the exemplary embodiments of the present disclosure provide a display substrate adopting a Fanout in Panel (FIP) structure. A plurality of data connection lines are arranged in a display area. One end of the plurality of data connection lines is connected to a plurality of data signal lines in the display area. The other end of the plurality of data connection lines extends to a binding area and is connected to an integrated circuit through a plurality of data lead-out lines in a lead-out line area. Since the lead-out line area does not need to be arranged with fan-shaped diagonal lines, the width of the lead-out line area is reduced, thereby reducing the width of the lower frame.

[0100] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, the display substrate includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; the driving structure layer includes at least a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines, and a plurality of power supply lines, at least one circuit unit includes a pixel driving circuit, the data signal line is configured to provide a data signal to the pixel driving circuit, and the data connection line is configured to provide a data signal to the data signal line; the light-emitting structure layer includes at least a plurality of light-emitting units, at least one light-emitting unit includes a light-emitting device, and the power supply line is configured to provide a power supply signal to the light-emitting device; in a plane parallel to the substrate, the display substrate includes at least a first area and a second area, the first area is an area where the data connection line is arranged, and the second area is an area where the power supply line is arranged; at least one power supply line includes a first power supply line extending along a first direction and a second power supply line extending along a second direction, the first direction and the second direction intersect; in at least one circuit unit of the second area, the first power supply line and the second power supply line are connected to each other through a power supply adapter strip, forming a grid communication structure.

[0101] In an example embodiment, the driving structure layer comprises a plurality of conductive layers in a direction perpendicular to the substrate, the first power supply trace and the second power supply trace are arranged in different conductive layers, and the first power supply trace and the power supply transfer bar are arranged in the same conductive layer.

[0102] In an example embodiment, the plurality of conductive layers comprises at least a first source-drain metal layer, a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer arranged on a side of the second source-drain metal layer away from the substrate, the first power supply trace and the power supply transfer bar are arranged in the second source-drain metal layer, and the second power supply trace is arranged in the third source-drain metal layer.

[0103] FIG. 6 is a schematic diagram of a structure of a data connection line in an example embodiment of the present disclosure, the data connection line adopts a FIP structure. As shown in FIG. 6, in a plane parallel to the display substrate, the display substrate can comprise a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In a plane perpendicular to the display substrate, the display substrate can comprise a driving structure layer arranged on a substrate, a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, and an encapsulation structure layer arranged on a side of the light-emitting structure layer away from the substrate.

[0104] In an example embodiment, the driving structure layer of the display area 100 can comprise a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit can comprise a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area 100 can comprise a plurality of light-emitting units, and at least one light-emitting unit can comprise a light-emitting device connected to a pixel driving circuit of a corresponding circuit unit, the light-emitting device being configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0105] In an example embodiment, the circuit unit referred to in the present disclosure refers to an area divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to an area divided according to the light-emitting device. In an example embodiment, the position of the light-emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light-emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0106] In an example embodiment, a plurality of circuit units arranged in sequence along a first direction X can be referred to as a unit row, a plurality of circuit units arranged in sequence along a second direction Y can be referred to as a unit column, the plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X and the second direction Y intersect.

[0107] In the example embodiment, the driving structure layer of the display area 100 can further include a plurality of data signal lines 72, a plurality of first data connection lines 81 and a plurality of second data connection lines 82. The plurality of first data connection lines 81 can be in the shape of a straight line or a broken line extending along the first direction X, and the plurality of data signal lines 72 and the plurality of second data connection lines 82 can be in the shape of a straight line or a broken line extending along the second direction Y.

[0108] In the example embodiment, the plurality of data signal lines 72 are arranged in a set interval along the first direction X, at least one data signal line 72 is connected to the plurality of pixel driving circuits in one unit column, and the data signal line 72 is configured to provide a data signal to the connected pixel driving circuit. The plurality of first data connection lines 81 are arranged in a set interval along the second direction Y, and the plurality of second data connection lines 82 are arranged in a set interval along the first direction X. The first end of at least one first data connection line 81 is connected to one data signal line 72, and the second end is connected to the first end of one second data connection line 82. The second end of the second data connection line 82 extends to the binding area and is connected to one data lead-out line 80, so that the data signal line 72 in the display area is connected to the data lead-out line 80 in the binding area 200 through the first data connection line 81 and the second data connection line 82, forming an FIP structure (also referred to as an FIAA structure). In the example embodiment, the first data connection line 81 and the second data connection line 82 are collectively referred to as a data connection line.

[0109] In the example embodiment, the binding area 200 can include a lead-out line area, a bending area, a driving chip area and a binding pin area arranged in sequence along the direction away from the display area, the lead-out line area is connected to the display area 100, and the bending area is connected to the lead-out line area. The lead-out line area can be provided with a plurality of data lead-out lines 80, the plurality of data lead-out lines 80 extend along the direction away from the display area, the first end of a part of the data lead-out lines 80 is connected to the second data connection line 82 in the display area 100, and the first end of another part of the data lead-out lines 80 is connected to the data signal line 72 in the display area 100. The second end of all the data lead-out lines 80 extends along the second direction Y and crosses the bending area to be connected to the integrated circuit of the driving chip area, so that the integrated circuit applies the data signal to the data signal line through the data lead-out line and the data connection line. Since the first data connection line 81 and the second data connection line 82 are arranged in the display area, the length of the binding area in the second direction Y can be effectively reduced, the lower frame width is greatly reduced, the screen-to-body ratio is improved, and the full-screen display is facilitated.

[0110] In an exemplary embodiment, the number of data connection lines in the display region can be the same as the number of data signal lines, and each data signal line is connected to a corresponding lead wire through a data connection line. Alternatively, the number of data connection lines in the display region can be less than the number of data signal lines, and a part of the data signal lines in the display region are connected to the corresponding lead wires through the data connection lines, and the other part of the data signal lines are directly connected to the lead wires, which is not limited in the present disclosure.

[0111] In an exemplary embodiment, the data lead wire 80 can be directly connected to the data signal line 72 and the second data connection line 82, or can be connected through a via, which is not limited in the present disclosure.

[0112] In an exemplary embodiment, the display region can have a center line O, and the plurality of data signal lines 72, the plurality of first data connection lines 81, and the plurality of second data connection lines 82 on the display substrate can be symmetrically arranged relative to the center line O, and the center line O can be a straight line that bisects the plurality of unit columns of the display region and extends along the second direction Y.

[0113] FIG. 7 is a schematic diagram of a region division according to an exemplary embodiment of the present disclosure. As shown in FIG. 7, the driving structure layer of the display region 100 can further include a plurality of first power supply wires 91 and a plurality of second power supply wires 92. The shape of the first power supply wire 91 can be a straight line or a polyline extending along the first direction X, and the plurality of first power supply wires 91 can be arranged in sequence along the second direction Y. The shape of the second power supply wire 92 can be a straight line or a polyline extending along the second direction Y, and the plurality of second power supply wires 92 can be arranged in sequence along the first direction X. In an exemplary embodiment, the first power supply wire 91 and the second power supply wire 92 together can be referred to as a power supply wire.

[0114] In an exemplary embodiment, in a direction perpendicular to the display substrate, the driving structure layer can include a plurality of conductive layers. The first data connection line 81 and the first power supply wire 91 can be arranged in the same layer (such as the second source-drain metal layer) and formed synchronously through the same patterning process. A first break K1 is arranged between the first data connection line 81 and the first power supply wire 91 arranged in the same unit row, and the first break K1 is configured to realize mutual insulation between the first data connection line 81 and the first power supply wire 91. The second data connection line 82 and the second power supply wire 92 can be arranged in the same layer (such as the third source-drain metal layer) and formed synchronously through the same patterning process. A second break K2 is arranged between the second data connection line 82 and the second power supply wire 92 arranged in the same unit column, and the second break K2 is configured to realize mutual insulation between the second data connection line 82 and the second power supply wire 92.

[0115] In an example embodiment, the first data connection lines 81 and the first power supply lines 91 can be collectively referred to as first lines. In some unit rows, the first lines can include the first data connection lines 81 and the first power supply lines 91 arranged in sequence along the first direction X. In other unit rows, the first lines can include only the first power supply lines 91.

[0116] In an example embodiment, the second data connection lines 82 and the second power supply lines 92 can be collectively referred to as second lines. In some unit columns, the second lines can include the second data connection lines 82 and the second power supply lines 92 arranged in sequence along the second direction Y. In other unit columns, the second lines can include only the second power supply lines 92.

[0117] In an example embodiment, since the data connection lines are arranged in a portion of the display area and the power supply lines are arranged in another portion of the display area, the display area can be divided into a first area 110 and a second area 120 according to the positions of the data connection lines and the power supply lines. The first area 110 can be an area in which the first data connection lines 81 or the second data connection lines 82 are arranged, or the first area 110 can be an area in which no power supply line is arranged, such as the dark area in FIG. 7. The second area 120 can be an area in which the first power supply lines 91 and the second power supply lines 92 are arranged, or the second area 120 can be an area in which no data connection line is arranged, such as the area outside the dark area in FIG. 7.

[0118] In an example embodiment, the first area 110 can be referred to as an FIP area, and the second area 120 can be referred to as a non-FIP area or a SIP area.

[0119] In an example embodiment, the first area 110 and the second area 120 can be symmetrically arranged with respect to a center line.

[0120] In an example embodiment, in the second area 120, at least one first power supply line 91 and at least one second power supply line 92 can be connected to each other to form a meshed communication structure for transmitting power supply signals.

[0121] In an example embodiment, the data signal lines 72 and the first data connection lines 81 can be arranged in different conductive layers, the first data connection lines 81 and the second data connection lines 82 can be arranged in different conductive layers, the first end of the first data connection line 81 is connected to the data signal line 72 through a first connection hole, the second end of the first data connection line 81 is connected to the first end of the second data connection line 82 through a second connection hole after extending along the first direction X or the opposite direction of the first direction X, and the second end of the second data connection line 82 is connected to the data lead-out line in the bonding area after extending along the second direction Y toward the bonding area.

[0122] FIG. 8 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure. In an example embodiment, in a plane parallel to the display substrate, the display substrate can include at least a display area, a binding area on one side of the display area, and a frame area on the other side of the display area. In a direction perpendicular to the display substrate, the display substrate can include at least a driving structure layer disposed on a base and a light-emitting structure layer disposed on a side of the driving structure layer away from the base. The driving structure layer of the display area can include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit can include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area can include a plurality of light-emitting units, and at least one light-emitting unit can include a light-emitting device connected to the pixel driving circuit of the corresponding circuit unit, the light-emitting device being configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0123] In an example embodiment, the circuit unit referred to in the present disclosure refers to an area divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to an area divided according to the light-emitting device. In an example embodiment, the position and shape of the orthographic projection of the light-emitting unit on the base can correspond to the position and shape of the orthographic projection of the circuit unit on the base, or the position and shape of the orthographic projection of the light-emitting unit on the base can not correspond to the position and shape of the orthographic projection of the circuit unit on the base.

[0124] As shown in FIG. 8, in at least one circuit unit, the pixel driving circuit can be connected to a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a fourth scan signal line 24, a light-emitting signal line 25, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first power supply line 71, and a data signal line 72, respectively.

[0125] In an example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, and the light-emitting signal line 25 are configured to provide a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a light-emitting control signal to the pixel driving circuit, respectively, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively, the first power supply line 71 is configured to provide a first power supply signal to the pixel driving circuit, and the data signal line 72 is configured to provide a data signal to the pixel driving circuit. The plurality of signal lines connected to the pixel driving circuit can be located within the corresponding circuit unit.

[0126] In the example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light emission signal line 25, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can have a shape of a straight line or a broken line in which a main portion extends along the first direction X. The first power supply line 71 and the data signal line 72 can have a shape of a straight line or a broken line in which a main portion extends along the second direction Y.

[0127] In the present disclosure, A extending along B means that A can include a main portion and a sub-portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the B direction, and the length of the main portion extending along the B direction is greater than the length of the sub-portion extending along other directions. In the following description, A extending along B means that the main portion of A extends along B.

[0128] In the example embodiment, the pixel driving circuit can include at least a storage capacitor and a plurality of transistors. The storage capacitor can include a first plate and a second plate stacked, and the plurality of transistors can include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, a seventh transistor T7 as a second reset transistor, and an eighth transistor T8 as a third reset transistor. Among them, the second transistor T2 can be a metal oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be low-temperature polysilicon transistors.

[0129] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, and the first electrode of the second transistor T2 and the first electrode plate of the storage capacitor (also the gate electrode of the third transistor T3) are connected. The first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line 72. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 25, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the second scan signal line 22, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0130] In the exemplary embodiment, in at least one circuit unit, the fourth scan signal line 24 can be disposed on the side opposite to the second direction Y of the storage capacitor (third transistor T3), and the first scan signal line 21 can be disposed on the side away from the storage capacitor of the fourth scan signal line 24. The light emission signal line 25 can be disposed on the side of the second direction Y of the storage capacitor, the second scan signal line 22 can be disposed on the side away from the storage capacitor of the light emission signal line 25, and the third scan signal line 23 can be disposed on the side away from the storage capacitor of the second scan signal line 22.

[0131] In the exemplary embodiment, the orthogonal projection of the first initial signal line 41 on the substrate at least partially overlaps the orthogonal projection of the second scan signal line 22 on the substrate, the orthogonal projection of the second initial signal line 42 on the substrate at least partially overlaps the orthogonal projection of the third scan signal line 23 on the substrate, and the orthogonal projection of the third initial signal line 43 on the substrate at least partially overlaps the orthogonal projection of the light emission signal line 25 on the substrate.

[0132] In the exemplary embodiment, the at least one circuit unit can further include a first initial connection line 44. The first initial connection line 44 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and can be connected to the first initial signal line 41. The first initial signal line 41 and the first initial connection line 44 form a mesh-like communication structure for transmitting the first initial signal in a mesh shape.

[0133] In an example embodiment, the at least one circuit unit can further include a second initial connection line 45. The second initial connection line 45 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and be connected to the second initial signal line 42. The second initial signal line 42 and the second initial connection line 45 form a meshed communication structure for transmitting a second initial signal in a meshed manner.

[0134] In an example embodiment, the at least one circuit unit can further include a third initial connection line 46. The third initial connection line 46 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and be connected to the third initial signal line 43. The third initial signal line 43 and the third initial connection line 46 form a meshed communication structure for transmitting a third initial signal in a meshed manner.

[0135] FIG. 9 is a schematic view of a structure of data connection lines and power supply lines according to an example embodiment of the present disclosure. As shown in FIG. 9, the display area can further include a plurality of data connection lines configured to provide data signals to the data signal lines, and a plurality of power supply lines configured to provide second power supply signals to the light emitting devices.

[0136] In an example embodiment, the at least one data connection line can include a first data connection line 81 and a second data connection line 82, and the at least one power supply line can include a first power supply line 91 and a second power supply line 92. The first data connection line 81 and the first power supply line 91 can have a shape of a straight line or a broken line extending along the first direction X, and the second data connection line 82 and the second power supply line 92 can have a shape of a straight line or a broken line extending along the second direction Y.

[0137] In an example embodiment, a first break K1 is provided between the first data connection line 81 and the first power supply line 91 provided in the same unit row, and the first break K1 is configured to achieve mutual insulation between the first data connection line 81 and the first power supply line 91. A second break K2 is provided between the second data connection line 82 and the second power supply line 92 provided in the same unit column, and the second break K2 is configured to achieve mutual insulation between the second data connection line 82 and the second power supply line 92.

[0138] In an example embodiment, in the at least one circuit unit of the first area 110, the first data connection line 81 and the second data connection line 82 can be connected to each other by a data transfer bar 83 to form a data connection line.

[0139] In the exemplary embodiment, the at least one circuit unit of the first region 110 can include a data transfer bar 83 and a data connection electrode 84. The data transfer bar 83 can have a shape of a bar extending along the second direction Y. The data connection electrode 84 can have a shape of a block (e.g., a rectangle). One end of the data transfer bar 83 can be connected to the first data connection line 81. The other end of the data transfer bar 83 can be connected to the data connection electrode 84. The second data connection line 82 can be connected to the data connection electrode 84 through a via. Thus, the first data connection line 81 and the second data connection line 82 can be connected to each other.

[0140] In the exemplary embodiment, the first data connection line 81, the data transfer bar 83, and the data connection electrode 84 can be an integrated structure connected to each other in the at least one circuit unit.

[0141] In the exemplary embodiment, a projection of the second data connection line 82 on the substrate can at least partially overlap a projection of the data transfer bar 83 on the substrate.

[0142] In the exemplary embodiment, the at least one circuit unit of the first region 110 can include the data connection electrode 84 without the data transfer bar 83. The second data connection line 82 can be connected to the separately provided data connection electrode 84 through a via.

[0143] In the exemplary embodiment, the first power supply line 91 and the second power supply line 92 can be connected to each other through a power transfer bar 93 in the at least one circuit unit of the second region 120. Thus, the first power supply line 91 and the second power supply line 92 can form a meshed connection structure.

[0144] In the exemplary embodiment, the at least one circuit unit of the second region 120 can include the power transfer bar 93 and a power connection electrode 94. The power transfer bar 93 can have a shape of a bar extending along the second direction Y. The power connection electrode 94 can have a shape of a block (e.g., a rectangle). One end of the power transfer bar 93 can be connected to the first power supply line 91. The other end of the power transfer bar 93 can be connected to the power connection electrode 94. The second power supply line 92 can be connected to the power connection electrode 94 through a via. Thus, the first power supply line 91 and the second power supply line 92 can be connected to each other.

[0145] In the exemplary embodiment, the first power supply line 91, the power transfer bar 93, and the power connection electrode 94 can be an integrated structure connected to each other in the at least one circuit unit.

[0146] In the exemplary embodiment, a projection of the second power supply line 92 on the substrate can at least partially overlap a projection of the power transfer bar 93 on the substrate.

[0147] In an exemplary embodiment, at least one circuit unit of the second region 120 can include the power connection electrode 94 without the power transfer bar 93, and the second power supply line 92 is connected to the separately provided power connection electrode 94 through a via.

[0148] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer can include a plurality of conductive layers, the first data connection line 81 and the second data connection line 82 can be provided in different conductive layers, and the first power supply line 91 and the second power supply line 92 can be provided in different conductive layers.

[0149] In an exemplary embodiment, the first data connection line 81, the data transfer bar 83, the data connection electrode 84, the first power supply line 91, the power transfer bar 93, and the power connection electrode 94 can be provided in the same conductive layer, and the second data connection line 82 and the second power supply line 92 can be provided in the same conductive layer.

[0150] In an exemplary embodiment, the plurality of conductive layers can include at least a first source-drain metal layer, a second source-drain metal layer provided on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer provided on a side of the second source-drain metal layer away from the substrate, the first data connection line 81, the data transfer bar 83, the data connection electrode 84, the first power supply line 91, the power transfer bar 93, and the power connection electrode 94 can be provided in the second source-drain metal layer, and the second data connection line 82 and the second power supply line 92 can be provided in the third source-drain metal layer.

[0151] In an exemplary embodiment, the position, shape, and connection structure of the power transfer bar 93 in one circuit unit in the second region 120 can be substantially the same as the position, shape, and connection structure of the data transfer bar 83 in another circuit unit in the first region 110.

[0152] In an exemplary embodiment, the position, shape, and connection structure of the power connection electrode 94 in one circuit unit in the second region 120 can be substantially the same as the position, shape, and connection structure of the data connection electrode 84 in another circuit unit in the first region 110.

[0153] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0154] In the exemplary embodiments, taking 32 circuit units (4 unit rows and 8 unit columns) as an example, the preparation process of the driving circuit layer can include the following operations.

[0155] (1) Forming a first semiconductor layer pattern. In the exemplary embodiments, forming the first semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a first semiconductor thin film on a substrate, patterning the first semiconductor thin film by a patterning process, forming a first insulating layer arranged on the substrate, and a first semiconductor layer pattern arranged on the first insulating layer, as shown in FIG. 10.

[0156] In the exemplary embodiments, the first semiconductor layer pattern of each circuit unit can include at least a first active layer 11 of a first transistor T1, a third active layer 13 of a third transistor T3 to an eighth active layer 18 of an eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected with each other, and the first active layer 11 and the eighth active layer 18 are separately arranged.

[0157] In the exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 can be located on one side of the third active layer 13 in the circuit unit, and the fourth active layer 14 and the fifth active layer 15 can be located on the other side of the third active layer 13 in the circuit unit. In the second direction Y, the fourth active layer 14 can be located on one side of the third active layer 13 in the circuit unit in the opposite direction of the second direction Y, and the first active layer 11, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 can be located on one side of the third active layer 13 in the circuit unit in the second direction Y.

[0158] In the exemplary embodiment, the third active layer 13 can have an inverted "Ω" shape, the first active layer 11, the fourth active layer 14, the fifth active layer 15, and the sixth active layer 16 can have an "I" shape, and the seventh active layer 17 and the eighth active layer 18 can have an "L" shape.

[0159] In the exemplary embodiment, the first active layer 11, the third active layer 13 to the eighth active layer 18 can each include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer can be connected to each other, and the first region 13-1 of the third active layer can serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 13-2 of the third active layer can serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer can be separately provided.

[0160] In an example embodiment, in one unit row, the first region 15-1 of the fifth active layer in part of two adjacent circuit units can be connected to each other, and the fifth active layer in the two circuit units can be an integrated structure connected to each other. For example, the fifth active layer in the Nth unit column and the fifth active layer in the N+1th unit column can be an integrated structure connected to each other, the fifth active layer in the N+2th unit column and the fifth active layer in the N+3th unit column can be an integrated structure connected to each other, the fifth active layer in the N+4th unit column and the fifth active layer in the N+5th unit column can be an integrated structure connected to each other, and the fifth active layer in the N+6th unit column and the fifth active layer in the N+7th unit column can be an integrated structure connected to each other. Since the first region of the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming the fifth active layer of the adjacent circuit units into an integrated structure connected to each other, it can be ensured that the first electrode of the fifth transistor T5 in the adjacent circuit units has the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0161] In an example embodiment, in one unit row, the first region 18-1 of the eighth active layer in part of two adjacent circuit units can be connected to each other, and the eighth active layer in the two circuit units can be an integrated structure connected to each other. For example, the eighth active layer in the Nth unit column and the eighth active layer in the N+1th unit column can be an integrated structure connected to each other, the eighth active layer in the N+2th unit column and the eighth active layer in the N+3th unit column can be an integrated structure connected to each other, the eighth active layer in the N+4th unit column and the eighth active layer in the N+5th unit column can be an integrated structure connected to each other, and the eighth active layer in the N+6th unit column and the eighth active layer in the N+7th unit column can be an integrated structure connected to each other. Since the first region 18-1 of the eighth active layer in each circuit unit is configured to be connected to the third initial signal line formed subsequently, by forming the first region 18-1 of the eighth active layer of the adjacent circuit units into an integrated structure connected to each other, it can be ensured that the first electrode of the eighth transistor in the adjacent circuit units has the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0162] In an example embodiment, the first semiconductor layer of adjacent unit columns can be mirror symmetrical with respect to the column boundary line. For example, the first semiconductor layer in the Nth unit column and the first semiconductor layer in the N+1th unit column can be mirror symmetrical with respect to the column boundary line, the first semiconductor layer in the N+1th unit column and the first semiconductor layer in the N+2th unit column can be mirror symmetrical with respect to the column boundary line, and the first semiconductor layer in the N+2th unit column and the first semiconductor layer in the N+3th unit column can be mirror symmetrical with respect to the column boundary line. In an example embodiment, the shape of the first semiconductor layer in a plurality of unit rows can be substantially the same.

[0163] In the example embodiment, the first semiconductor layer can adopt polycrystalline silicon (p-Si), i.e., the first transistor, the third transistor to the seventh transistor are LTPS transistors. In the example embodiment, the patterning of the first semiconductor thin film by the patterning process can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, performing crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the first semiconductor layer pattern.

[0164] (2) Forming the first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the first conductive thin film by a patterning process to form a second insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG. 11A and FIG. 11B, which is a plan view of the first conductive layer in FIG. 11A. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0165] In the example embodiment, the first conductive layer pattern of each circuit unit at least includes: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light-emitting signal line 25, and a first plate 31 of a storage capacitor.

[0166] In the example embodiment, the shape of the first plate 31 can be a rectangular shape, and the corner of the rectangular shape can be provided with a chamfer. The orthographic projection of the first plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In the example embodiment, the first plate 31 can simultaneously serve as the lower plate of the storage capacitor and the gate electrode of the third transistor T3.

[0167] In the example embodiment, the shape of the first scan signal line 21 can be a straight line shape or a broken line shape with the main body part extending along the first direction X. The first scan signal line 21 can be located on the side opposite to the second direction Y of the first plate 31. The region where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0168] In the example embodiment, the shape of the second scan signal line 22 can be a straight line shape or a broken line shape with the main body part extending along the first direction X. The second scan signal line 22 can be located on the side of the second direction Y of the first plate 31. The region where the second scan signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the region where the second scan signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0169] In an example embodiment, the third scan signal line 23 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and the third scan signal line 23 can be located on a side of the second scan signal line 22 away from the first plate 31. An area of the third scan signal line 23 overlapping the first active layer can serve as a gate electrode of the first transistor T1.

[0170] In an example embodiment, the light emission signal line 25 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and the light emission signal line 25 can be located between the second scan signal line 22 and the first plate 31. An area of the light emission signal line 25 overlapping the fifth active layer can serve as a gate electrode of the fifth transistor T5, and an area of the light emission signal line 25 overlapping the sixth active layer can serve as a gate electrode of the sixth transistor T6.

[0171] In an example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can have a non-equal-width design, with a width being a dimension of the second direction Y. This can not only facilitate layout of the pixel structure, but also reduce parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0172] In an example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can include an area overlapping the first semiconductor layer and an area not overlapping the first semiconductor layer. The width of the signal line in the area overlapping the first semiconductor layer can be greater than the width of the signal line in the area not overlapping the first semiconductor layer.

[0173] In an example embodiment, the first conductive layer of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the first conductive layer of the Nth unit column and the first conductive layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line, the first conductive layer of the N+1th unit column and the first conductive layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line, and the first conductive layer of the N+2th unit column and the first conductive layer of the N+3th unit column can be mirror-symmetrical with respect to the column boundary line. In an example embodiment, the shape of the first conductive layer in the plurality of unit rows can be substantially the same.

[0174] In an example embodiment, after forming the first conductive layer pattern, the first semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield. The first semiconductor layer in the area shielded by the first conductive layer forms a channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, i.e., the first region and the second region of the first transistor T1, the third transistor T3 to the eighth transistor T8 are conductorized.

[0175] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by using a patterning process, forming a third insulating layer covering the first conductive layer, and forming the second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 12A and 12B, which is a plan view of the second conductive layer in FIG. 12A. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0176] In an exemplary embodiment, the second conductive layer pattern of each circuit unit at least includes: a second plate 32 of a storage capacitor and a shield line 35.

[0177] In an exemplary embodiment, the second plate 32 can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The orthographic projection of the second plate 32 on the substrate at least partially overlaps the orthographic projection of the first plate 31 on the substrate. The second plate 32 can serve as an upper plate of a storage capacitor, and the first plate 31 and the second plate 32 constitute a storage capacitor of a pixel driving circuit.

[0178] In an exemplary embodiment, the second plate 32 is provided with an opening 33, which can have a rectangular shape and can be located in the middle of the second plate 32, so as to form a ring-shaped structure of the second plate 32. The opening 33 exposes the third insulating layer covering the first plate 31, and the orthographic projection of the first plate 31 on the substrate contains the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a thirteenth via hole formed subsequently, the thirteenth via hole is located in the opening 33 and exposes the first plate 31, so as to connect a first connection electrode formed subsequently with the first plate 31.

[0179] In an exemplary embodiment, in one unit row, the second plates 32 in part of the two adjacent circuit units are integrally connected to each other. For example, the second plate 32 in the Nth unit column and the second plate 32 in the N+1th unit column can be integrally connected to each other through the plate connecting strip 34. For another example, the second plate 32 in the N+2th unit column and the second plate 32 in the N+3th unit column can be integrally connected to each other through the plate connecting strip 34. For another example, the second plate 32 in the N+4th unit column and the second plate 32 in the N+5th unit column can be integrally connected to each other through the plate connecting strip 34. For another example, the second plate 32 in the N+6th unit column and the second plate 32 in the N+7th unit column can be integrally connected to each other through the plate connecting strip 34. Since the second plate 32 in each circuit unit is connected with the first power supply line formed subsequently, by forming the second plates 32 in part of the adjacent circuit units into an integrally connected structure, the second plates in the integrally connected structure can be reused as the power signal lines, and the second plates in the adjacent circuit units can have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0180] In an exemplary embodiment, the shielding line 35 can be in a straight line shape or a broken line shape with the main body part extending along the first direction X, and can be located between the first scan signal line 21 and the second plate 32. The shielding line 35 is configured as a shielding layer of the second transistor T2, shields the channel region of the second transistor T2, ensures the electrical performance of the oxide second transistor T2, and is also configured as a bottom gate electrode of the second transistor T2.

[0181] In an exemplary embodiment, the shielding line 35 can be designed in a non-equal width, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines.

[0182] In an exemplary embodiment, the second conductive layers in the adjacent unit columns can be mirror symmetrical with respect to the column boundary line. For example, the second conductive layer in the Nth unit column and the second conductive layer in the N+1th unit column can be mirror symmetrical with respect to the column boundary line, the second conductive layer in the N+1th unit column and the second conductive layer in the N+2th unit column can be mirror symmetrical with respect to the column boundary line, and the second conductive layer in the N+2th unit column and the second conductive layer in the N+3th unit column can be mirror symmetrical with respect to the column boundary line. In an exemplary embodiment, the shapes of the second conductive layers in the plurality of unit rows can be substantially the same.

[0183] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a fourth insulating thin film and a second semiconductor thin film, patterning the second semiconductor thin film by a patterning process, forming a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIGS. 13A and 13B, FIG. 13B being a plan view of the second semiconductor layer in FIG. 13A.

[0184] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit at least includes a second active layer 12 of a second transistor T2.

[0185] In an exemplary embodiment, the second active layer 12 can have an "L" shape, and a normal projection of the second active layer 12 on the substrate at least partially overlaps a normal projection of the shielding line 35 on the substrate.

[0186] In an exemplary embodiment, a first region 12-1 of the second active layer can be located on a side of the shielding line 35 away from the second plate 32, and a second region 12-2 of the second active layer can be located on a side of the shielding line 35 close to the second plate 32.

[0187] In an exemplary embodiment, the second semiconductor layer of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the second semiconductor layer of the Nth unit column and the second semiconductor layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line, the second semiconductor layer of the N+1th unit column and the second semiconductor layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line, and the second semiconductor layer of the N+2th unit column and the second semiconductor layer of the N+3th unit column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shape of the second semiconductor layer in the plurality of unit rows can be substantially the same.

[0188] In an exemplary embodiment, the second semiconductor layer can be an oxide, i.e., the second transistor T2 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film can be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0189] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a fifth insulating thin film and a third conductive thin film, patterning the third conductive thin film by a patterning process, forming a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIGS. 14A and 14B, FIG. 14B being a plan view of the third conductive layer in FIG. 14A. In an exemplary embodiment, the second conductive layer can be referred to as a third gate metal (GATE3) layer.

[0190] In the example embodiment, the third conductive layer pattern of each circuit unit at least includes a fourth scan signal line 24, a first initial signal line 41, a second initial signal line 42, and a third initial signal line 43.

[0191] In the example embodiment, the fourth scan signal line 24 can be in a straight line shape or a broken line shape with a main body part extending along the first direction X, can be located between the first scan signal line 21 and the second plate 32, and the area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0192] In the example embodiment, the fourth scan signal line 24 and the shielding line 35 can be connected to the same signal source, so that the shielding line 35 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a top gate bottom gate structure of the second transistor T2.

[0193] In the example embodiment, the first initial signal line 41 can be in a straight line shape or a broken line shape with a main body part extending along the first direction X, can be located between the third scan signal line 23 and the light-emitting signal line 25, and the first initial signal line 41 of each circuit unit can be provided with a first initial connection block 41-1 in a block shape (such as a rectangular shape) connected to the first initial signal line 41, and configured to be connected to the first region of the first active layer through a seventh connection electrode formed later.

[0194] In the example embodiment, the first initial signal line 41 and the second scan signal line 22 can at least partially overlap in the orthographic projection on the substrate, and the first initial signal line 41 transmitting a constant voltage can shield the influence of the second scan signal line 22 on the pixel driving circuit, improving the driving quality of the pixel driving circuit.

[0195] In the example embodiment, the second initial signal line 42 can be in a straight line shape or a broken line shape with a main body part extending along the first direction X, can be located on the side of the first initial signal line 41 away from the second plate 32, and the second initial signal line 42 of each circuit unit can be provided with a second initial connection block 42-1 in a block shape (such as a rectangular shape) connected to the second initial signal line 42, and configured to be connected to the first region of the seventh active layer through an eighth connection electrode formed later.

[0196] In the example embodiment, the orthogonal projection of the second initial signal line 42 on the substrate at least partially overlaps the orthogonal projection of the third scan signal line 23 on the substrate, and the second initial signal line 42 transmitting a constant voltage can shield the third scan signal line 23 from affecting the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0197] In the example embodiment, the third initial signal line 43 can be in a straight line shape or a broken line shape with a main body extending along the first direction X, and the third initial signal line 43 can be located between the second plate 32 and the first initial signal line 41. The third initial signal line 43 of each circuit unit can be provided with a third initial connecting block 43-1, the third initial connecting block 43-1 can be in a block shape (e.g., a rectangular shape) and connected to the third initial signal line 43, and the third initial connecting block 43-1 is configured to be connected to the first region of the eighth active layer through the ninth connecting electrode formed subsequently.

[0198] In the example embodiment, the orthogonal projection of the third initial signal line 43 on the substrate at least partially overlaps the orthogonal projection of the light-emitting signal line 25 on the substrate, and the third initial signal line 43 transmitting a constant voltage can shield the light-emitting signal line 25 from affecting the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0199] In the example embodiment, the third conductive layer of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the third conductive layer of the Nth unit column and the third conductive layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line, the third conductive layer of the N+1th unit column and the third conductive layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line, and the third conductive layer of the N+2th unit column and the third conductive layer of the N+3th unit column can be mirror-symmetrical with respect to the column boundary line. In the example embodiment, the shapes of the third conductive layers in the plurality of unit rows can be substantially the same.

[0200] (6) Forming a sixth insulating layer pattern. In the example embodiment, forming the sixth insulating layer pattern can include: depositing a sixth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth insulating thin film using a patterning process to form a sixth insulating layer covering the third conductive layer, the sixth insulating layer being provided with a plurality of vias, as shown in FIG. 15.

[0201] In an example embodiment, the plurality of vias of each circuit unit at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0202] In an example embodiment, a normal projection of the first via V1 on the substrate is within a range of a normal projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 are etched away to expose a surface of the first region of the first active layer, and the first via V1 is configured to allow the seventh connection electrode formed subsequently to connect with the first region of the first active layer through the via.

[0203] In an example embodiment, a normal projection of the second via V2 on the substrate is within a range of a normal projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away to expose a surface of the second region of the first active layer, and the second via V2 is configured to allow the second connection electrode formed subsequently to connect with the second region of the first active layer through the via.

[0204] In an example embodiment, a normal projection of the third via V3 on the substrate is within a range of a normal projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the third via V3 are etched away to expose a surface of the first region of the second active layer, and the third via V3 is configured to allow the first connection electrode formed subsequently to connect with the first region of the second active layer through the via.

[0205] In an example embodiment, a normal projection of the fourth via V4 on the substrate is within a range of a normal projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the fourth via V4 are etched away to expose a surface of the second region of the second active layer, and the fourth via V4 is configured to allow the second connection electrode formed subsequently to connect with the second region of the second active layer through the via.

[0206] In an example embodiment, the fifth via V5 is configured such that a fifth connection electrode formed subsequently is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the via. The fifth via V5 has a normal projection on the substrate within the range of the normal projection on the substrate of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer), and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 are etched away to expose the surface of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer).

[0207] In an example embodiment, the sixth via V6 is configured such that a second connection electrode formed subsequently is connected to the second region of the third active layer (also the first region of the sixth active layer) through the via. The sixth via V6 has a normal projection on the substrate within the range of the normal projection on the substrate of the second region of the third active layer (also the first region of the sixth active layer), and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second region of the third active layer (also the first region of the sixth active layer).

[0208] In an example embodiment, the seventh via V7 is configured such that a third connection electrode formed subsequently is connected to the first region of the fourth active layer through the via. The seventh via V7 has a normal projection on the substrate within the range of the normal projection on the substrate of the first region of the fourth active layer, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the seventh via V7 are etched away to expose the surface of the first region of the fourth active layer.

[0209] In an example embodiment, the eighth via V8 is configured such that a fourth connection electrode formed subsequently is connected to the first region of the fifth active layer through the via. The eighth via V8 has a normal projection on the substrate within the range of the normal projection on the substrate of the first region of the fifth active layer, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the first region of the fifth active layer. In an example embodiment, since the first regions of the fifth active layers of some adjacent circuit units in a unit row are connected to each other, the some adjacent circuit units can share one eighth via V8.

[0210] In an example embodiment, the ninth via V9 is located within the range of the normal projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the ninth via V9 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the ninth via V9 is configured to allow the sixth connection electrode formed subsequently to connect with the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0211] In an example embodiment, the tenth via V10 is located within the range of the normal projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via V10 is configured to allow the eighth connection electrode formed subsequently to connect with the first region of the seventh active layer through the via.

[0212] In an example embodiment, the eleventh via V11 is located within the range of the normal projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via V11 is configured to allow the ninth connection electrode formed subsequently to connect with the first region of the eighth active layer through the via. In an example embodiment, since the first regions of the eighth active layers of some adjacent circuit units in a unit row are connected with each other, the some adjacent circuit units can share one eleventh via V11.

[0213] In an example embodiment, the twelfth via V12 is located within the range of the normal projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the twelfth via V12 are etched away to expose the surface of the second region of the eighth active layer, and the twelfth via V12 is configured to allow the fifth connection electrode formed subsequently to connect with the second region of the eighth active layer through the via.

[0214] In an example embodiment, the thirteenth via V13 is located within the range of the normal projection of the opening 33 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched away to expose the surface of the first plate 31, and the thirteenth via V13 is configured to allow the first connection electrode formed subsequently to connect with the first plate 31 through the via.

[0215] In the example embodiment, the fourth via V4 is configured such that a fourth connection electrode formed subsequently connects with the first initial connection block 41-1 via the via. In the example embodiment, the fourth via V4 is formed in the sixth insulating layer 6, and the sixth insulating layer 6 in the fourth via V4 is etched away to expose the surface of the first initial connection block 41-1. In the example embodiment, the fourth via V4 is formed such that the fourth via V4 is located within the range of the orthogonal projection of the first initial connection block 41-1 on the substrate.

[0216] In the example embodiment, the fifth via V5 is configured such that a fifth connection electrode formed subsequently connects with the second initial connection block 42-1 via the via. In the example embodiment, the fifth via V5 is formed in the sixth insulating layer 6, and the sixth insulating layer 6 in the fifth via V5 is etched away to expose the surface of the second initial connection block 42-1. In the example embodiment, the fifth via V5 is formed such that the fifth via V5 is located within the range of the orthogonal projection of the second initial connection block 42-1 on the substrate.

[0217] In the example embodiment, the sixth via V6 is configured such that a sixth connection electrode formed subsequently connects with the third initial connection block 43-1 via the via. In the example embodiment, the sixth via V6 is formed in the sixth insulating layer 6, and the sixth insulating layer 6 in the sixth via V6 is etched away to expose the surface of the third initial connection block 43-1. In the example embodiment, the sixth via V6 is formed such that the sixth via V6 is located within the range of the orthogonal projection of the third initial connection block 43-1 on the substrate.

[0218] In the example embodiment, the seventh via V7 is configured such that a seventh connection electrode formed subsequently connects with the third initial connection block 43-1 via the via. In the example embodiment, the seventh via V7 is formed in the sixth insulating layer 6, and the sixth insulating layer 6 in the seventh via V7 is etched away to expose the surface of the third initial connection block 43-1. In the example embodiment, the seventh via V7 is formed such that the seventh via V7 is located within the range of the orthogonal projection of the third initial connection block 43-1 on the substrate.

[0219] (7) Forming a fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth conductive thin film by using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 16A and FIG. 16B, which is a plan view of the fourth conductive layer in FIG. 16A. In the example embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0220] In the example embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, and a ninth connection electrode 59.

[0221] In the example embodiment, the first connection electrode 51 can have a strip shape with a main body extending along the second direction Y, a first end of the first connection electrode 51 is connected to the first region of the second active layer through the third via V3, and a second end of the first connection electrode 51 is connected to the first plate 31 through the thirteenth via V13 after extending along the second direction Y. In the example embodiment, since the first plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 makes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 31 have the same potential, forming the first node N1 of the pixel driving circuit.

[0222] In the example embodiment, the second connection electrode 52 can have a strip shape with a main body extending along the second direction Y, a first end of the second connection electrode 52 is connected to the second region of the first active layer of the current circuit unit through the second via V2, and a second end of the second connection electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) of the next circuit unit through the sixth via V6 after extending along the second direction Y, and the portion between the first end and the second end of the second connection electrode 52 is connected to the second region of the second active layer of the next circuit unit through the fourth via V4. In the example embodiment, the second connection electrode 52 makes the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential, forming the third node N3 of the pixel driving circuit.

[0223] In the example embodiment, the third connection electrode 53 can have a block shape (e.g., a rectangular shape), the third connection electrode 53 is connected to the first region of the fourth active layer through the seventh via V7, and the third connection electrode 53 is configured to be connected to the eleventh connection electrode formed subsequently.

[0224] In the example embodiment, the fourth connection electrode 54 can have a strip shape extending along the second direction Y, a first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the eighth via V8, and a second end of the fourth connection electrode 54 is connected to the plate connection strip 34 through the fourteenth via V14 after extending in the opposite direction of the second direction Y. Since the plate connection strip 34 is connected to the second plate 32, the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor in the circuit unit have the same potential.

[0225] In the example embodiment, since one eighth via V8 and one fourteenth via V14 are shared by two adjacent circuit units in one unit row, the two adjacent circuit units can share one fourth connection electrode 54.

[0226] In the example embodiment, the at least one circuit unit can further include a power connection electrode 54-1. The power connection electrode 54-1 can have a strip shape extending along the first direction X, a first end of the power connection electrode 54-1 can be connected to a second end of the fourth connection electrode 54, a second end of the power connection electrode 54-1 can extend away from the fourth connection electrode 54, and the power connection electrode 54-1 can be configured to be connected to a subsequently formed twelfth connection electrode.

[0227] In the example embodiment, the fourth connection electrode 54 and the power connection electrode 54-1 in the at least one circuit unit can be an integrated structure connected to each other. Since the two adjacent circuit units can share one fourth connection electrode 54, the fourth connection electrode 54 and the power connection electrode 54-1 in the two adjacent circuit units can be an integrated structure connected to each other, which can ensure that the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor in the adjacent circuit units have the same potential, and is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0228] In the example embodiment, the fifth connection electrode 55 can have a strip shape with a main body extending along the second direction Y, a first end of the fifth connection electrode 55 can be connected to the first region of the third active layer through a fifth via V5, and a second end of the fifth connection electrode 55 can be connected to the second region of the eighth active layer through a twelfth via V12. In the example embodiment, since the first region of the third active layer also serves as the second region of the fourth active layer and the second region of the fifth active layer, the fifth connection electrode 55 can make the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 have the same potential, and form a second node N2 of the pixel driving circuit.

[0229] In the example embodiment, the sixth connection electrode 56 can have a block shape (e.g., a rectangular shape), and the sixth connection electrode 56 can be connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a ninth via V9. In the example embodiment, the sixth connection electrode 56 can simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 can be configured to be connected to a subsequently formed thirteenth connection electrode.

[0230] In an exemplary embodiment, the seventh connection electrode 57 can have a strip shape extending along the second direction Y, a first end of the seventh connection electrode 57 is connected to the first region of the first active layer through the first via V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 through the fifteenth via V15. In an exemplary embodiment, since the first initial connection block 41-1 is connected to the first initial signal line 41, the seventh connection electrode 57 writes the first initial signal transmitted by the first initial signal line 41 to the first electrode of the first transistor T1.

[0231] In an exemplary embodiment, the eighth connection electrode 58 can have a strip shape extending along the second direction Y, a first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer through the tenth via V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 through the sixteenth via V16. In an exemplary embodiment, since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 writes the second initial signal transmitted by the second initial signal line 42 to the first electrode of the seventh transistor T7.

[0232] In an exemplary embodiment, the ninth connection electrode 59 can have a fold line shape extending along the second direction Y, a first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer through the eleventh via V11, and a second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 through the seventeenth via V17. In an exemplary embodiment, the ninth connection electrode 59 can be the first electrode of the eighth transistor T8, and since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 writes the third initial signal transmitted by the third initial signal line 43 to the first electrode of the eighth transistor T8.

[0233] In an exemplary embodiment, since one eleventh via V11 is shared by part of two adjacent circuit units in one unit row, the first end of one ninth connection electrode 59 can be shared by part of the adjacent circuit units.

[0234] In an exemplary embodiment, the ninth connection electrodes 59 of part of the adjacent circuit units can be an integrated structure connected to each other, which can ensure that the first electrodes of the eighth transistors T8 of part of the adjacent circuit units have the same potential, thereby improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0235] In the example embodiment, the fourth conductive layer of the at least one circuit unit can further include a pad 60. The pad 60 can be in a block shape (e.g., a rectangular shape), can be disposed on a side of the ninth connection electrode 59 of the unit structure close to the second plate 32, and can be connected to the ninth connection electrode 59. The pad 60 is configured to pad a subsequent formed adapter block and has a shielding effect.

[0236] In the example embodiment, the pad 60 can be disposed between two circuit units adjacent in the first direction X and at a position where a data adapter strip or a power adapter strip is subsequently formed. For example, in the Mth unit row, the pad 60 can be disposed between the N+2th unit column and the N+3th unit column and between the N+6th unit column and the N+7th unit column. For another example, in the M+1th unit row, the pad 60 can be disposed between the Nth unit column and the N+1th unit column and between the N+4th unit column and the N+5th unit column.

[0237] In the example embodiment, the fourth conductive layer of the at least one circuit unit can further include a first initial connection line 44 and a first initial connection strip 44-1. The first initial connection line 44 can be in a straight line shape or a broken line shape with a main body portion extending along the second direction Y, and can be disposed between two adjacent circuit units. The first initial connection strip 44-1 can be in a strip shape extending along the first direction X, and can be disposed between the first initial connection line 44 and the seventh connection electrode 57. The first end of the first initial connection strip 44-1 is connected to the first initial connection line 44, and the second end of the first initial connection strip 44-1 is connected to the seventh connection electrode 57.

[0238] In the example embodiment, the first initial connection line 44 can be disposed between the N+1th unit column and the N+2th unit column, and the first initial connection strips 44-1 can be respectively disposed on both sides of the first initial connection line 44 in the first direction X, so as to achieve the connection of the first initial connection line 44 to the seventh connection electrode 57 in the N+1th unit column and the seventh connection electrode 57 in the N+2th unit column. Since the seventh connection electrode 57 is connected to the first initial signal line 41, the mutual connection between the first initial signal line 41 extending along the first direction X and the first initial connection line 44 extending along the second direction Y is achieved. The first initial signal line 41 and the first initial connection line 44 form a meshed communication structure for transmitting the first initial signal in a meshed manner, which can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0239] In the example embodiment, the first initial connection line 44 and the plurality of first initial connection strips 44-1 can be a unit structure connected to each other.

[0240] In an exemplary embodiment, the fourth conductive layer of the at least one circuit unit can further include a second initial connection line 45 and a second initial connection bar 45-1. The second initial connection line 45 can be in a linear shape or a broken line shape with a main body extending along the second direction Y, and can be arranged between two adjacent circuit units. The second initial connection bar 45-1 can be in a bar shape extending along the first direction X, and can be arranged between the second initial connection line 45 and the eighth connection electrode 58, with a first end of the second initial connection bar 45-1 connected to the second initial connection line 45 and a second end of the second initial connection bar 45-1 connected to the eighth connection electrode 58.

[0241] In an exemplary embodiment, the second initial connection line 45 can be arranged between the N+3th unit column and the N+4th unit column, and the second initial connection bar 45-1 can be arranged on both sides of the second initial connection line 45 along the first direction X, so as to realize the connection of the second initial connection line 45 to the eighth connection electrode 58 in the N+3th unit column and the eighth connection electrode 58 in the N+4th unit column, respectively. Since the eighth connection electrode 58 is connected to the second initial signal line 42, the second initial signal line 42 extending along the first direction X and the second initial connection line 45 extending along the second direction Y are connected to each other, and the second initial signal line 42 and the second initial connection line 45 form a meshed communication structure for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0242] In an exemplary embodiment, the second initial connection line 45 and the plurality of second initial connection bars 45-1 can be an integral structure connected to each other.

[0243] In an exemplary embodiment, the fourth conductive layer of the at least one circuit unit can further include a third initial connection line 46 and a third initial connection bar 46-1. The third initial connection line 46 can be in a linear shape or a broken line shape with a main body extending along the second direction Y, and can be arranged between two adjacent circuit units. The third initial connection bar 46-1 can be in a broken line segment extending along the first direction X, and can be arranged between the third initial connection line 46 and the ninth connection electrode 59, with a first end of the third initial connection bar 46-1 connected to the third initial connection line 46 and a second end of the third initial connection bar 46-1 connected to the ninth connection electrode 59.

[0244] In the example embodiment, the third initial connection line 46 can be arranged between the N+5th unit column and the N+6th unit column, and the third initial connection bars 46-1 can be arranged on both sides of the third initial connection line 46 in the first direction X, respectively, so as to realize the connection of the third initial connection line 46 to the ninth connection electrode 59 in the N+5th unit column and the ninth connection electrode 59 in the N+6th unit column, respectively. Since the ninth connection electrode 59 is connected to the third initial signal line 43, the interconnection between the third initial signal line 43 extending in the first direction X and the third initial connection line 46 extending in the second direction Y is realized, and the third initial signal line 43 and the third initial connection line 46 form a meshed communication structure for transmitting the third initial signal, which can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0245] (8) Forming a first planar layer pattern. In the example embodiment, forming the first planar layer pattern can include: coating a first planar film on the substrate on which the aforementioned pattern is formed, and patterning the first planar film by using a patterning process to form a first planar layer covering the fourth conductive layer pattern, and the first planar layer is provided with a plurality of vias, as shown in FIG. 17.

[0246] In the example embodiment, the plurality of vias in each circuit unit at least includes: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0247] In the example embodiment, the orthogonal projection of the twenty-first via V21 on the substrate is within the range of the orthogonal projection of the third connection electrode 53 on the substrate, the first planar layer in the twenty-first via V21 is etched away to expose the surface of the third connection electrode 53, and the twenty-first via V21 is configured to allow the eleventh connection electrode formed subsequently to be connected to the third connection electrode 53 through the via.

[0248] In the example embodiment, the orthogonal projection of the twenty-second via V22 on the substrate is within the range of the orthogonal projection of the power supply connection electrode 54-1 of the fourth connection electrode 54 on the substrate, the first planar layer in the twenty-second via V22 is etched away to expose the surface of the power supply connection electrode 54-1, and the twenty-second via V22 is configured to allow the twelfth connection electrode formed subsequently to be connected to the power supply connection electrode 54-1 through the via.

[0249] In an example embodiment, the orthogonal projection of the twenty-third via V23 on the substrate is located within the range of the orthogonal projection of the sixth connection electrode 56 on the substrate, the first planar layer in the twenty-third via V23 is etched away to expose the surface of the sixth connection electrode 56, and the twenty-third via V23 is configured to enable the thirteenth connection electrode formed subsequently to connect with the sixth connection electrode 56 through the via.

[0250] In an example embodiment, the plurality of vias on the first planar layer of the adjacent unit columns can be mirror symmetrical with respect to the column boundary line, and the shapes of the plurality of vias on the first planar layer in the plurality of unit rows can be substantially the same.

[0251] (9) Forming a fifth conductive layer pattern. In an example embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film by using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 18A and 18B, where FIG. 18B is a plan view of the fifth conductive layer in FIG. 18A. In an example embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0252] In an example embodiment, the fifth conductive layer of each circuit unit at least includes: an eleventh connection electrode 61, a twelfth connection electrode 62, and a thirteenth connection electrode 63.

[0253] In an example embodiment, the shape of the eleventh connection electrode 61 can be a strip shape with a main body portion extending along the second direction Y, the eleventh connection electrode 61 is connected with the third connection electrode 53 through a twenty-first via V21, and the eleventh connection electrode 61 is configured to be connected with a data signal line formed subsequently.

[0254] In an example embodiment, the shape of the twelfth connection electrode 62 can be a polyline shape with a main body portion extending along the second direction Y, the twelfth connection electrode 62 is connected with the power supply connection electrode 54-1 through a twenty-second via V22, and the twelfth connection electrode 62 is configured to be connected with a first power supply line formed subsequently.

[0255] In an example embodiment, the orthogonal projection of the twelfth connection electrode 62 on the substrate at least partially overlaps with the orthogonal projection of the first connection electrode 51 on the substrate. Since the twelfth connection electrode 62 is connected with the first power supply line formed subsequently, the twelfth connection electrode 62 with a constant potential can effectively shield the data voltage jump and other signals from affecting the first node N1 in the pixel driving circuit, thereby avoiding the data voltage jump and other signals from affecting the potential of the first node N1, and improving the driving performance of the pixel driving circuit.

[0256] In the example embodiment, the orthogonal projection of the twelfth connection electrode 62 on the substrate at least partially overlaps with the orthogonal projection of the second active layer of the second transistor T2 on the substrate. In the example embodiment, the twelfth connection electrode 62 can shield the second active layer, block the light emission of the light emitting device and the reflection of the film layer light to the oxide of the second transistor T2, and can prevent the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor.

[0257] In the example embodiment, in one unit row, the twelfth connection electrodes 62 in two adjacent circuit units can be an integrated structure connected to each other, and the shielding effect of the second transistor T2 can be improved. For example, the twelfth connection electrodes 62 in the N+1th unit column and the N+2th unit column are connected to each other, and the twelfth connection electrodes 62 in the two adjacent circuit units are an integrated structure connected to each other. For another example, the twelfth connection electrodes 62 in the N+3th unit column and the N+4th unit column are connected to each other, and the twelfth connection electrodes 62 in the two adjacent circuit units are an integrated structure connected to each other.

[0258] In the example embodiment, the thirteenth connection electrode 63 can have a shape of a strip extending along the second direction Y, the thirteenth connection electrode 63 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the thirteenth connection electrode 63 is configured to be connected to the anode connection electrode formed subsequently.

[0259] In the example embodiment, the fifth conductive layer can further include a first trace, the first trace can have a shape of a straight line or a polyline extending along the first direction X, and the first trace can be located between the second initial signal line 42 and the third initial signal line 43.

[0260] In the example embodiment, in at least one unit row, the first trace can include a first data connection line 81 and a first power supply trace 91, the first data connection line 81 can be disposed in the first region (FIP region), and the first power supply trace 91 can be disposed in the second region (non-FIP region or SIP region).

[0261] In the example embodiment, in at least one unit row, the first trace can only include the first power supply trace 91.

[0262] In the example embodiment, a first break K1 can be disposed between the first data connection line 81 and the first power supply trace 91 disposed in the same unit row, the first break K1 can cut off the first data connection line 81 located in the FIP region from the first power supply trace 91 located in the non-FIP region, so that the first data connection line 81 and the first power supply trace 91 on both sides of the first break K1 are insulated from each other.

[0263] In the example embodiment, the orthographic projection of the first fracture K1 on the substrate can be located within the range of the orthographic projection of the first initial connection line 44, the second initial connection line 45 or the third initial connection line 46 on the substrate, so that the first initial connection line 44, the second initial connection line 45 or the third initial connection line 46 can pad the first fracture K1 from below, effectively eliminate the film layer difference of different areas, facilitate shadow elimination and avoid display substrate appearance defects.

[0264] In the example embodiment, the end of the first data connection line 81 away from the first fracture K1 is configured to be connected with the subsequently formed data signal line, and the end of the first data connection line 81 close to the first fracture K1 is configured to be connected with the subsequently formed second data connection line.

[0265] In the example embodiment, the orthographic projection of at least one first data connection line 81 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, so that the first initial signal line 41 with constant potential can effectively shield the influence of voltage jump in the first data connection line 81 on the pixel driving circuit.

[0266] In the example embodiment, the fifth conductive layer of the first region (FIP region) can further include a plurality of data connection electrodes 84. The shape of the data connection electrode 84 can be block-shaped (such as rectangular), and the data connection electrode 84 is configured to be connected with the subsequently formed second data connection line.

[0267] In the example embodiment, in the first direction X, the data connection electrode 84 can be arranged between part of two adjacent circuit units, and in the second direction Y, the data connection electrode 84 can be arranged on the side of the first data connection line 81 close to the second initial signal line 42.

[0268] In some possible embodiments, the data connection electrode 84 can be arranged on the side of the first data connection line 81 away from the second initial signal line 42, which is not limited in the present disclosure.

[0269] In an example embodiment, the first region can include a plurality of repeating units, and the repeating unit can be a basic unit constituting the first region. The first region can be constituted by repeating and continuously arranging the repeating units along the first direction X and the second direction Y. In an example embodiment, at least one repeating unit can include 2 rows of units and 4 columns of units, i.e., 8 circuit units. The 2 rows of units can be a first row of units and a second row of units, and the 4 columns of units can be a first column of units, a second column of units, a third column of units, and a fourth column of units. Each row of units can include 4 circuit units arranged in sequence along the first direction X, and each column of units can include 2 circuit units arranged in sequence along the second direction Y. In an example embodiment, a plurality of repeating units arranged in sequence along the first direction X can be referred to as a repeating row, and a plurality of repeating units arranged in sequence along the second direction Y can be referred to as a repeating column.

[0270] In an example embodiment, at least one repeating unit can include 2 data connection electrodes 84, and 1 data connection electrode 84 can be included in each of the first row of units and the second row of units, and the data connection electrodes 84 in the 2 rows of units can be arranged in a staggered manner. For example, the Nth column of units to the N+3th column of units in the Mth row of units and the M+1th row of units can be a first repeating unit, and the data connection electrode 84 can be arranged between the N+2th column of units and the N+3th column of units in the Mth row of units and between the Nth column of units and the N+1th column of units in the M+1th row of units, i.e., in the first repeating unit, the data connection electrode 84 is arranged between the third column of units and the fourth column of units in the first row of units and between the first column of units and the second column of units in the second row of units. For another example, the Nth column of units to the N+3th column of units in the M+2th row of units and the M+3th row of units can be a second repeating unit, and the data connection electrode 84 can be arranged between the N+2th column of units and the N+3th column of units in the M+2th row of units and between the Nth column of units and the N+1th column of units in the M+3th row of units, i.e., in the second repeating unit, the data connection electrode 84 is arranged between the third column of units and the fourth column of units in the first row of units and between the first column of units and the second column of units in the second row of units.

[0271] In the example embodiment, the at least one repeating unit of the first area (FIP area) can further include a data transfer strip 83. The data transfer strip 83 can have a strip shape extending along the second direction Y, and can be disposed on the side of the first data connection line 81 close to the second initial signal line 42. The first end of the data transfer strip 83 is connected to the side of the first data connection line 81 close to the second initial signal line 42, and the second end of the data transfer strip 83 extends towards the second initial signal line 42 and is connected to the data connection electrode 84. Since the data connection electrode 84 is configured to be connected to the subsequently formed second data connection line, the data transfer strip 83 is configured to realize the mutual connection between the first data connection line and the second data connection line, i.e., the first data connection line and the second data connection line are connected to each other through the data transfer strip.

[0272] In some possible embodiments, the data transfer strip 83 can be disposed on the side of the first data connection line 81 away from the second initial signal line 42, which is not limited in the present disclosure.

[0273] In the example embodiment, the data transfer strip 83 can be disposed in part of the repeating units. For example, two data transfer strips 83 can be disposed in the first repeating unit, one data transfer strip 83 can be disposed between the N+2th unit column and the N+3th unit column, and the other data transfer strip 83 can be disposed between the Nth unit column and the N+1th unit column. For another example, no data transfer strip 83 is disposed in the second repeating unit.

[0274] In the example embodiment, only one data transfer strip 83 is disposed in one of the repeating units in a repeating row of the first area, and only one data transfer strip 83 is disposed in one of the repeating units in a repeating column of the first area, so that one second data connection line formed subsequently is connected to one first data connection line through only one data transfer strip 83, to realize the corresponding connection between the plurality of first data connection lines and the plurality of second data connection lines.

[0275] In the example embodiment, the position and connection structure of the data connection electrode 84 in one repeating unit can be substantially the same as the position and connection structure of the data connection electrode 84 in another repeating unit, except that the data connection electrode 84 in part of the repeating units is connected to the first data connection line 81 through the data transfer strip 83, and the data connection electrode 84 in another part of the repeating units is isolated and not connected to the first data connection line 81 or other electrodes. The same design of the transfer area in the present disclosure can not only improve the uniformity of the subsequent etching process, but also enable the same display effect under transmission and reflection light at different positions, realize shadow elimination, effectively avoid the occurrence of appearance defects and mura of the display substrate, and improve the display quality and display performance.

[0276] In the example embodiment, in the at least one circuit unit, the first data connection line 81, the data transfer bar 83, and the data connection electrode 84 can be an integrated structure connected to each other.

[0277] In the example embodiment, in the at least one circuit unit, a projection of the data transfer bar 83 on the substrate at least partially overlaps with a projection of the pad 60 on the substrate, so that the pad 60 can elevate the data transfer bar 83. Since the pad 60 is connected to the ninth connection electrode 59, and the ninth connection electrode 59 is connected to the third initial signal line 43, the pad 60 with a constant potential can shield the influence of voltage jump in the data transfer bar 83 on the pixel driving circuit.

[0278] FIG. 18C is a schematic view of the positional relationship between the data transfer bar and the pad in FIG. 18A. As shown in FIG. 18C, in the at least one circuit unit, a projection of the data transfer bar 83 on the substrate can be within the range of a projection of the pad 60 on the substrate. In the first direction X, the data transfer bar 83 can have a first data transfer bar edge 83-1 and a second data transfer bar edge 83-2, and the second data transfer bar edge 83-2 can be located on one side of the first data transfer bar edge 83-1 in the first direction X. The pad 60 can have a first pad edge 60-1 and a second pad edge 60-2, and the first pad edge 60-1 can be located on a side of the first data transfer bar edge 83-1 away from the second pad edge 60-2, and the second pad edge 60-2 can be located on a side of the second data transfer bar edge 83-2 away from the first pad edge 60-1.

[0279] In the example embodiment, a distance between the first pad edge 60-1 and the first data transfer bar edge 83-1 can be greater than or equal to 0.6 μm, and a distance between the second pad edge 60-2 and the second data transfer bar edge 83-2 can be greater than or equal to 0.6 μm, and the distance can be a dimension in the first direction X.

[0280] In the example embodiment, the fifth conductive layer of the second region (the non-FIP region or the SIP region) can further include a plurality of power supply connection electrodes 94. The power supply connection electrode 94 can have a block shape (e.g., a rectangular shape), and the power supply connection electrode 94 is configured to be connected to a second power supply line formed later.

[0281] In the example embodiment, in the first direction X, the power supply connection electrode 94 can be disposed between part of two adjacent circuit units, and in the second direction Y, the power supply connection electrode 94 can be disposed on a side of the first power supply line 91 close to the second initial signal line 42.

[0282] In some possible implementation manners, the power supply connection electrode 94 can be arranged on the side of the first power supply trace 91 away from the second initial signal line 42, which is not limited in the disclosure.

[0283] In the example implementation manners, the second region can include a plurality of repeating units, and the repeating unit can be a basic unit constituting the second region. The second region can be constituted by repeating and continuously arranging the repeating units along the first direction X and the second direction Y. In the example implementation manners, the arrangement manner of the repeating units in the second region is substantially the same as that in the first region. At least one repeating unit can include 2 unit rows and 4 unit columns, i.e., 8 circuit units. A plurality of repeating units arranged in sequence along the first direction X can be referred to as a repeating row, and a plurality of repeating units arranged in sequence along the second direction Y can be referred to as a repeating column.

[0284] In the example implementation manners, the at least one repeating unit can include 2 power supply connection electrodes 94. The first unit row and the second unit row each include 1 power supply connection electrode 94, and the power supply connection electrodes 94 in the 2 unit rows are arranged in a staggered manner. For example, the N+4th unit column to the N+7th unit column in the Mth unit row and the M+1th unit row are a first repeating unit. The power supply connection electrode 94 can be arranged between the N+6th unit column and the N+7th unit column in the Mth unit row, and between the N+4th unit column and the N+5th unit column in the M+1th unit row, i.e., in the first repeating unit, the power supply connection electrode 94 is arranged between the third unit column and the fourth unit column in the first unit row, and between the first unit column and the second unit column in the second unit row. For another example, the N+4th unit column to the N+7th unit column in the M+2th unit row and the M+3th unit row are a second repeating unit. The power supply connection electrode 94 can be arranged between the N+6th unit column and the N+7th unit column in the M+2th unit row, and between the N+4th unit column and the N+5th unit column in the M+3th unit row, i.e., in the second repeating unit, the power supply connection electrode 94 is arranged between the third unit column and the fourth unit column in the first unit row, and between the first unit column and the second unit column in the second unit row.

[0285] In the example embodiment, at least one of the repeating units of the second area (non-FIP area or SIP area) can further include a power transfer strip 93. The power transfer strip 93 can have a strip shape extending along the second direction Y, and can be disposed on the side of the first power supply line 91 close to the second initial signal line 42. The first end of the power transfer strip 93 is connected to the side of the first power supply line 91 close to the second initial signal line 42, and the second end of the power transfer strip 93 extends toward the second initial signal line 42 and is connected to the power supply connection electrode 94. Since the power supply connection electrode 94 is configured to be connected to the second power supply line formed later, the power transfer strip 93 is configured to realize the mutual connection between the first power supply line and the second power supply line, i.e., the first power supply line and the second power supply line are connected to each other through the power transfer strip 93.

[0286] In some possible embodiments, the power transfer strip 93 can be disposed on the side of the first power supply line 91 away from the second initial signal line 42, which is not limited in the disclosure.

[0287] In the example embodiment, the power transfer strip 93 can be disposed in part of the repeating units. For example, two power transfer strips 93 can be disposed in the second repeating unit, one power transfer strip 93 can be disposed between the N+6th unit column and the N+7th unit column, and the other power transfer strip 93 can be disposed between the N+4th unit column and the N+5th unit column. For another example, no data transfer strip 83 is disposed in the first repeating unit.

[0288] In the example embodiment, in the repeating units of one repeating row of the second area, the data transfer strip 83 can be disposed in part of the repeating units, and the number of the power transfer strips 93 in one repeating row can be less than or equal to the number of the power supply connection electrodes 94. In the repeating units of one repeating column of the second area, the data transfer strip 83 can be disposed in part of the repeating units, and the number of the power transfer strips 93 in one repeating column can be less than or equal to the number of the power supply connection electrodes 94.

[0289] In the example embodiment, the positions and connection structures of the power supply connection electrodes 94 in one repeating unit can be substantially the same as those in another repeating unit, except that the power supply connection electrodes 94 in part of the repeating units are connected to the first power supply line 91 through the power transfer strip 93, and the power supply connection electrodes 94 in another part of the repeating units are isolated and not connected to the first power supply line 91 or other electrodes. The same design of the transfer area in the disclosure can not only improve the uniformity of the subsequent etching process, but also enable the same display effect under transmission and reflection light at different positions, realize shadow elimination, effectively avoid the occurrence of appearance defects and mura of the display substrate, and improve the display quality and display performance.

[0290] In an example embodiment, in the at least one circuit unit, the first power supply wire 91, the power supply adapter strip 93, and the power supply connection electrode 94 can be an integrated structure connected to each other.

[0291] In an example embodiment, in the at least one circuit unit, the power supply adapter strip 93 can be at least partially overlapped with the cushion block 60 on the substrate, so that the cushion block 60 can elevate the power supply adapter strip 93.

[0292] FIG. 18D is a schematic diagram of the positional relationship between the power supply adapter strip and the cushion block in FIG. 18A. As shown in FIG. 18D, in the at least one circuit unit, the power supply adapter strip 93 can be located within the range of the cushion block 60 on the substrate. In the first direction X, the power supply adapter strip 93 can have a first power supply adapter strip edge 93-1 and a second power supply adapter strip edge 93-2, and the second power supply adapter strip edge 93-2 can be located on one side of the first power supply adapter strip edge 93-1 in the first direction X. The cushion block 60 can have a first cushion block edge 60-1 and a second cushion block edge 60-2, and the first cushion block edge 60-1 can be located on the side away from the second cushion block edge 60-2 of the first power supply adapter strip edge 93-1, and the second cushion block edge 60-2 can be located on the side away from the first cushion block edge 60-1 of the second power supply adapter strip edge 93-2.

[0293] In an example embodiment, the distance between the first cushion block edge 60-1 and the first power supply adapter strip edge 93-1 can be greater than or equal to 0.6 μm, and the distance between the second cushion block edge 60-2 and the second power supply adapter strip edge 93-2 can be greater than or equal to 0.6 μm, and the distance can be the size in the first direction X.

[0294] In an example embodiment, the position, shape, and connection structure of the power supply adapter strip 93 in one circuit unit in the second area can be substantially the same as the position, shape, and connection structure of the data adapter strip 83 in another circuit unit in the first area, and the position, shape, and connection structure of the power supply connection electrode 94 in one circuit unit in the second area can be substantially the same as the position, shape, and connection structure of the data connection electrode 84 in another circuit unit in the first area. The present disclosure provides that the data adapter strip and the power supply adapter strip have the same topography and via connection structure, and the data connection electrode and the power supply connection electrode have the same topography and via connection structure. Through the same design of the adapter area, not only the uniformity of the subsequent etching process can be improved, but also the same display effect under transmitted and reflected light can be achieved in different areas, the shadow is eliminated, the appearance defect and mura of the display substrate are effectively avoided, and the display quality and display performance are improved.

[0295] (10) forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, patterning the second planar film using a patterning process, forming a second planar layer covering the fifth conductive layer pattern, the second planar layer being provided with a plurality of vias, as shown in FIG. 19.

[0296] In an exemplary embodiment, the plurality of vias in each circuit unit at least includes: a thirty-first via V31, a thirty-second via V32, and a thirty-third via V33.

[0297] In an exemplary embodiment, the thirty-first via V31 has a projection on the substrate within the projection of the eleventh connecting electrode 61 on the substrate, the second planar layer in the thirty-first via V31 is etched away, exposing the surface of the eleventh connecting electrode 61, and the thirty-first via V31 is configured to allow a data signal line formed subsequently to connect to the eleventh connecting electrode 61 through the via.

[0298] In an exemplary embodiment, the thirty-second via V32 has a projection on the substrate within the projection of the twelfth connecting electrode 62 on the substrate, the second planar layer in the thirty-second via V32 is etched away, exposing the surface of the twelfth connecting electrode 62, and the thirty-second via V32 is configured to allow a first power supply line formed subsequently to connect to the twelfth connecting electrode 62 through the via.

[0299] In an exemplary embodiment, the thirty-third via V33 has a projection on the substrate within the projection of the thirteenth connecting electrode 63 on the substrate, the second planar layer in the thirty-third via V33 is etched away, exposing the surface of the thirteenth connecting electrode 63, and the thirty-third via V33 is configured to allow an anode connecting electrode formed subsequently to connect to the thirteenth connecting electrode 63 through the via.

[0300] In an exemplary embodiment, the at least one circuit unit can further include a thirty-fourth via V34. The thirty-fourth via V34 has a projection on the substrate within the projection of the data connecting electrode 84 on the substrate, the second planar layer in the thirty-fourth via V34 is removed, exposing the surface of the data connecting electrode 84, and the thirty-fourth via V34 is configured to allow a second data connecting line formed subsequently to connect to the data connecting electrode 84 through the via.

[0301] In an exemplary embodiment, the at least one circuit unit can further include a thirty-fifth via V35. A projection of the thirty-fifth via V35 on the substrate is within a projection of the power connection electrode 94 on the substrate, a second planar layer in the thirty-fifth via V35 is removed to expose a surface of the power connection electrode 94, and the thirty-fifth via V35 is configured to allow a second power supply line formed subsequently to pass through the via and connect with the power connection electrode 94.

[0302] (11) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer can include: depositing a sixth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth conductive thin film by using a patterning process to form a sixth conductive layer disposed on the second planar layer, as shown in FIGS. 20A and 20B, which is a plan view of the sixth conductive layer in FIG. 20A. In an exemplary embodiment, the sixth conductive layer can be referred to as a third source-drain metal (SD3) layer.

[0303] In an exemplary embodiment, the sixth conductive layer of each circuit unit at least includes: a first power supply line 71, a data signal line 72, and an anode connection electrode 73.

[0304] In an exemplary embodiment, the first power supply line 71 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the first power supply line 71 is connected with the twelfth connection electrode 62 through a thirty-second via V32. Since the twelfth connection electrode 62 is connected with the fourth connection electrode 54, and the fourth connection electrode 54 is connected with the first region of the fifth active layer and the second plate 32 of the storage capacitor respectively, the first power supply line 71 writes the first power supply signal to the fifth transistor T5 and the second plate 32 of the storage capacitor.

[0305] In an exemplary embodiment, the first power supply line 71 can be a broken line with non-uniform width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power supply line and the data signal line.

[0306] In an exemplary embodiment, in one unit row, the first power supply lines 71 in part of two adjacent circuit units can be an integrated structure connected with each other. For example, the first power supply lines 71 in the N+1th unit column and the N+2th unit column are connected with each other, and the first power supply lines 71 in the two adjacent circuit units are an integrated structure connected with each other. For another example, the first power supply lines 71 in the N+3th unit column and the N+4th unit column are connected with each other, and the first power supply lines 71 in the two adjacent circuit units are an integrated structure connected with each other.

[0307] In the example embodiment, the shape of the data signal line 72 can be a straight line or a broken line with a main body extending along the second direction Y, and the data signal line 72 is connected to the eleventh connection electrode 61 through the thirty-first via V31. Since the eleventh connection electrode 61 is connected to the third connection electrode 53 through a via, and the third connection electrode 53 is connected to the first region of the fourth active layer through a via, the connection between the data signal line 72 and the first electrode of the fourth transistor T4 is achieved, and the data signal line 72 can write a data signal to the first electrode of the fourth transistor T4.

[0308] In the example embodiment, since the data signal line is arranged in the third source-drain metal (SD3) layer, and a thick first planar layer and a second planar layer are arranged between the data signal line and the corresponding signal line, the distance between the data signal line and the corresponding signal line is increased, and the parasitic capacitance between the data signal line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the data signal line.

[0309] In the example embodiment, the shape of the anode connection electrode 73 can be a block shape (e.g., a rectangular shape), the anode connection electrode 73 is connected to the thirteenth connection electrode 63 through the thirty-third via V33, and the anode connection electrode 73 is configured to be connected to a subsequently formed anode. Since the thirteenth connection electrode 63 is connected to the sixth connection electrode 56 through a via, and the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through a via, the connection between the subsequently formed anode and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 can be achieved, and the pixel driving circuit can drive the light emitting device to emit light.

[0310] In the example embodiment, the sixth conductive layer can further include a second trace, the shape of the second trace can be a straight line or a broken line with a main body extending along the second direction Y, and the second trace can be arranged between two data signal lines 72 of adjacent unit columns. For example, the second trace can be arranged between the data signal line 72 of the Nth unit column and the data signal line 72 of the (N+1)th unit column. For another example, the second trace can be arranged between the data signal line 72 of the (N+2)th unit column and the data signal line 72 of the (N+3)th unit column. For another example, the second trace can be arranged between the data signal line 72 of the (N+4)th unit column and the data signal line 72 of the (N+5)th unit column.

[0311] In the example embodiment, in at least one unit column, the second trace can include a second data connection line 82 and a second power trace 92 arranged in sequence along the second direction Y, the second data connection line 82 can be arranged in the first region (FIP region), and the second power trace 92 can be arranged in the second region (non-FIP region or SIP region).

[0312] In an example embodiment, in the at least one unit column, the second routing line can only include the second power routing line 92.

[0313] In an example embodiment, a second break K2 can be arranged between the second data connection line 82 and the second power routing line 92 arranged in the same unit column, the second break K2 can cut off the second data connection line 82 located in the FIP region from the second power routing line 92 located in the non-FIP region, so that the second data connection line 82 and the second power routing line 92 on both sides of the second break K2 are insulated from each other.

[0314] In an example embodiment, the orthographic projection of the second break K2 on the substrate can be located within the range of the orthographic projection of the fourth connection electrode 54 on the substrate, so that the fourth connection electrode 54 can pad the second break K2 from below, which can effectively eliminate the film layer difference of different regions, facilitate shadow elimination, and avoid appearance defects of the display substrate.

[0315] In an example embodiment, in the first region (FIP region), the second data connection line 82 can be connected to a plurality of data connection electrodes 84 through a plurality of thirty-fourth vias V34. Since one end of the second data connection line 82 is configured to extend to the binding region and be connected to the data lead-out line, one data connection electrode 84 connected by the second data connection line 82 is connected to the first data connection line 81 through the data transfer bar 83, and the first data connection line 81 is configured to be connected to the data signal line in the display region, thereby realizing the mutual connection between the first data connection line 81 extending along the first direction X and the second data connection line 82 extending along the second direction Y, and the data lead-out line in the binding region is connected to the data signal line 72 in the display region through the second data connection line 82 and the first data connection line 81.

[0316] In an example embodiment, the orthographic projection of the second data connection line 82 on the substrate at least partially overlaps the orthographic projection of the data transfer bar 83 on the substrate.

[0317] FIG. 20C is a schematic view of the positional relationship between the data transfer bar and the second data connection line in FIG. 20A. As shown in FIG. 20C, in the at least one circuit unit, the orthographic projection of the data transfer bar 83 on the substrate can be located within the range of the orthographic projection of the second data connection line 82 on the substrate, so that the data transfer bar 83 in the second source-drain metal layer is covered and protected by the second data connection line 82 in the third source-drain metal layer.

[0318] In an example embodiment, in the first direction X, the data transfer bar 83 can have a first data transfer bar edge 83-1 and a second data transfer bar edge 83-2, the second data transfer bar edge 83-2 can be located on one side of the first data transfer bar edge 83-1 in the first direction X. The second data connection line 82 can have a first data connection line edge 82-1 and a second data connection line edge 82-2, the first data connection line edge 82-1 can be located on one side of the first data transfer bar edge 83-1 away from the second data connection line edge 82-2, and the second data connection line edge 82-2 can be located on one side of the second data transfer bar edge 83-2 away from the first data connection line edge 82-1.

[0319] In an example embodiment, the distance between the first data connection line edge 82-1 and the first data transfer bar edge 83-1 can be greater than or equal to 0.6 μm, and the distance between the second data connection line edge 82-2 and the second data transfer bar edge 83-2 can be greater than or equal to 0.6 μm, and the distance can be a dimension in the first direction X.

[0320] In an example embodiment, in the second area (non-FIP area or SIP area), the second power supply line 92 is connected to the plurality of power supply connection electrodes 94 through the plurality of thirty-fifth vias V35. Since part of the power supply connection electrodes 94 are connected to the first power supply line 91 through the power supply transfer bar 93, the interconnection between the first power supply line 91 and the second power supply line 92 is achieved, and the first power supply line 91 extending along the first direction X and the second power supply line 92 extending along the second direction Y form a mesh-like network communication structure for transmitting power supply signals.

[0321] In an example embodiment, the first power supply line 91 or the second power supply line 92 can be connected to a power supply lead for transmitting a second power supply signal after extending to the frame area or the bonding area, achieving a second power supply line in a panel (VSS in Panel, SIP for short) structure. Not only can effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, but also can greatly reduce the width of the frame power supply lead, greatly reduce the frame width, improve the screen ratio, and be beneficial to realize the full-screen display.

[0322] In an example embodiment, the second power supply line 92 has an orthographic projection on the substrate, and the orthographic projection of the power supply transfer bar 93 on the substrate at least partially overlaps.

[0323] FIG. 20D is a schematic view of the positional relationship between the power transfer bar and the second power supply trace in FIG. 20A. As shown in FIG. 20D, in at least one circuit unit, the orthogonal projection of the power transfer bar 93 on the substrate can be located within the orthogonal projection of the second power supply trace 92 on the substrate, so that the power transfer bar 93 in the second source-drain metal layer is covered and protected by the second power supply trace 92 in the third source-drain metal layer.

[0324] In an example embodiment, in the first direction X, the power transfer bar 93 can have a first power transfer bar edge 93-1 and a second power transfer bar edge 93-2, the second power transfer bar edge 93-2 can be located on one side of the first power transfer bar edge 93-1 in the first direction X. The second power supply trace 92 can have a first power supply trace edge 92-1 and a second power supply trace edge 92-2, the first power supply trace edge 92-1 can be located on a side away from the second power supply trace edge 92-2 of the first power transfer bar edge 93-1, and the second power supply trace edge 92-2 can be located on a side away from the first power supply trace edge 93-1 of the second power transfer bar edge 93-2.

[0325] In an example embodiment, the distance between the first power supply trace edge 92-1 and the first power transfer bar edge 93-1 can be greater than or equal to 0.6 μm, and the distance between the second power supply trace edge 92-2 and the second power transfer bar edge 93-2 can be greater than or equal to 0.6 μm, the distance being a dimension in the first direction X.

[0326] In an example embodiment, the orthogonal projection of at least one second trace (the second data connection line 82 and the second power supply trace 92) on the substrate can at least partially overlap with the orthogonal projection of the column boundary line on the substrate.

[0327] In an example embodiment, in the first direction X, two data signal lines 72 located on both sides of a second trace can be mirror symmetrical with respect to the second trace.

[0328] In an example embodiment, in the first direction X, between a second trace and two data signal lines 72, two first power supply lines 71 of adjacent unit columns can be arranged, and the two first power supply lines 71 can be mirror symmetrical with respect to the second trace.

[0329] In an example embodiment, in the first direction X, between two first power supply lines 71 and two data signal lines 72, two second traces of adjacent unit columns can be arranged, and the two second traces can be mirror symmetrical with respect to the column boundary line.

[0330] In the example embodiment, since the second data connection line is arranged in the third source-drain metal (SD3) layer, and a relatively thick first planar layer and a second planar layer are arranged between the second data connection line and the corresponding signal line, the distance between the second data connection line and the corresponding signal line is increased, the parasitic capacitance between the second data connection line and the corresponding signal line is reduced, and thus the capacitive load of the second data connection line is effectively reduced.

[0331] In the example embodiment, since the first data connection line is arranged in the second source-drain metal (SD2) layer and the second data connection line is arranged in the third source-drain metal (SD3) layer, the first data connection line and the second data connection line only need one planar layer via to realize connection, the occupied space is minimized, and high-resolution display is facilitated.

[0332] (12) Forming a third planar layer pattern. In the example embodiment, forming the third planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a third planar film, patterning the third planar film by using a patterning process, and forming a third planar layer covering the sixth conductive layer pattern, the third planar layer being provided with a plurality of anode vias V40, as shown in FIG. 21.

[0333] In the example embodiment, the orthographic projection of each circuit unit anode via V40 on the substrate is within the range of the orthographic projection of the anode connection electrode 73 on the substrate, the third planar layer in the anode via V40 is removed, the surface of the anode connection electrode 73 is exposed, and the anode via V40 is configured to enable the anode to be connected to the anode connection electrode 73 through the via formed subsequently.

[0334] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer can include a plurality of circuit units, each of which can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0335] In the plane perpendicular to the display substrate, the driving circuit layer can include, in sequence on the substrate, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, a second planar layer, a sixth conductive layer, and a third planar layer. The first semiconductor layer can include at least active layers of the first transistor, the third transistor to the eighth transistor, the first conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer can include at least a second plate of the storage capacitor, the second semiconductor layer can include at least an active layer of the second transistor, the third conductive layer can include at least a first initial signal line, a second initial signal line, a third initial signal line, and a fourth scan signal line, the fourth conductive layer can include at least a first data connection line and a first power supply line, and the fifth conductive layer can include at least a first power supply line, a data signal line, a second data connection line, and a second power supply line.

[0336] In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), or the like, for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0337] In exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first planar layer, the second planar layer and the third planar layer can be made of an organic material, such as resin, etc.

[0338] In exemplary embodiments, the pixel driving circuit in the adjacent two circuit units in one unit row can be substantially mirror-symmetrical with respect to the column boundary line, which is a straight line located between the adjacent two circuit units and extending along the second direction Y. For example, the pixel driving circuit of the Nth unit column and the pixel driving circuit of the (N+1)th unit column can be mirror-symmetrical with respect to the column boundary line. For another example, the pixel driving circuit of the (N+1)th unit column and the pixel driving circuit of the (N+2)th unit column can be mirror-symmetrical with respect to the column boundary line.

[0339] In exemplary embodiments, the pixel driving circuit in the adjacent two circuit units can be substantially mirror-symmetrical with respect to the column boundary line can include any one or more of the following: the first semiconductor layer in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the first conductive layer in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the second conductive layer in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the second semiconductor layer in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the third conductive layer in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the fourth conductive layer in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the fifth conductive layer (except for the data connection strip, the data connection electrode, the power connection strip and the power connection electrode, etc.) in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, and the sixth conductive layer (except for the anode connection electrode, etc.) in the adjacent two circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line.

[0340] In exemplary embodiments, after the preparation of the driving circuit layer is completed, the light-emitting structure layer can be prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer can include the following operations.

[0341] (13) forming an anode conductive layer pattern. In an example embodiment, forming the anode conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing an anode conductive thin film, patterning the anode conductive thin film using a patterning process, forming an anode conductive layer disposed on the third planar layer, the anode conductive layer including at least a plurality of anode patterns, as shown in FIGS. 22A and 22B, which is a plan view of the anode conductive layer in FIG. 22A.

[0342] In an example embodiment, the plurality of anode patterns can include a first anode 90A located at a red light-emitting unit that emits red light, a second anode 90B located at a blue light-emitting unit that emits blue light, a third anode 90C located at a first green light-emitting unit that emits green light, and a fourth anode 90D located at a second green light-emitting unit that emits green light, and the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can be respectively connected to the anode connection electrode 73 of the circuit unit through an anode via V40.

[0343] In an example embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can include an anode main body portion and an anode connection portion connected to each other, the anode main body portion can have a shape of a rhombus, the corner portion of the rhombus can be provided with a rounded chamfer, and the anode connection portion can have a shape of a strip, a first end of the anode connection portion is connected to the anode main body portion, and a second end of the anode connection portion extends away from the anode main body portion and is connected to the anode connection electrode 73 through the anode via V40.

[0344] In an example embodiment, the at least one anode can further include an anode shielding portion 90-1. The anode shielding portion 90-1 can have a shape of a block (e.g., a rectangle) and can be disposed on one side of the anode main body portion in the second direction Y. A first end of the anode shielding portion 90-1 is connected to the anode main body portion, a second end of the anode shielding portion 90-1 extends away from the anode main body portion, and a normal projection of the anode shielding portion 90-1 on the substrate at least partially overlaps with a normal projection of the data transfer bar 83 or the power transfer bar 93 on the substrate.

[0345] In an example embodiment, the normal projection of the data transfer bar 83 or the power transfer bar 93 on the substrate can be located within the range of the normal projection of the anode shielding portion 90-1 on the substrate, and the area of the normal projection of the anode shielding portion 90-1 on the substrate is greater than the area of the normal projection of the data transfer bar 83 or the power transfer bar 93 on the substrate, so that the data transfer bar 83 or the power transfer bar 93 in the second source / drain metal layer is covered and protected by the anode shielding portion 90-1 in the anode conductive layer.

[0346] In some embodiments, the anode shielding portion 90-1 can be connected to the anode main portion of the first anode 90A, the first anode 90A including the anode shielding portion 90-1 has a projection on the substrate that at least partially overlaps the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, and the second anode 90B, the third anode 90C, and the fourth anode 90D have projections on the substrate that do not overlap the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, i.e., the data adapter strip 83 or the power adapter strip 93 is provided only in the circuit unit corresponding to the red light emitting unit.

[0347] In other embodiments, the anode shielding portion 90-1 can be connected to the anode main portion of the second anode 90B, the second anode 90B including the anode shielding portion 90-1 has a projection on the substrate that at least partially overlaps the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, and the first anode 90A, the third anode 90C, and the fourth anode 90D have projections on the substrate that do not overlap the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, i.e., the data adapter strip 83 or the power adapter strip 93 is provided only in the circuit unit corresponding to the blue light emitting unit.

[0348] In yet other embodiments, the anode shielding portion 90-1 can be connected to the anode main portion of the first anode 90A and the second anode 90B, the first anode 90A and the second anode 90B including the anode shielding portion 90-1 have projections on the substrate that at least partially overlap the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, and the third anode 90C and the fourth anode 90D have projections on the substrate that do not overlap the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, i.e., the data adapter strip 83 or the power adapter strip 93 can be provided in the circuit units corresponding to the red light emitting unit and the blue light emitting unit.

[0349] In yet other embodiments, the anode shielding portion 90-1 can be connected to the anode main portion of the third anode 90C and / or the fourth anode 90D, the third anode 90C and / or the fourth anode 90D including the anode shielding portion 90-1 have projections on the substrate that at least partially overlap the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, and the first anode 90A and the second anode 90B have projections on the substrate that do not overlap the projection on the substrate of the data adapter strip 83 or the power adapter strip 93, i.e., the data adapter strip 83 or the power adapter strip 93 can be provided only in the circuit unit corresponding to the green light emitting unit.

[0350] In some possible embodiments, the first anode or the second anode can not be provided with an anode shielding portion, and a normal projection of the anode main body portion of the first anode or the anode main body portion of the second anode on the substrate at least partially overlaps with a normal projection of the data adapter strip or the power adapter strip on the substrate, so that the data adapter strip or the power adapter strip is covered and protected by the anode main body portion in the anode conductive layer. Since the data adapter strip or the power adapter strip is elevated by the pad of the fourth conductive layer below and is covered and protected by the second trace of the sixth conductive layer above, the anode can have good flatness even if the anode main body portion overlaps with the data adapter strip or the power adapter strip.

[0351] In example embodiments, the anode conductive layer can have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO.

[0352] In example embodiments, the subsequent manufacturing process can include: first forming a pixel definition layer, the pixel definition layer being provided with a plurality of pixel openings, and the plurality of pixel openings respectively exposing the first anode, the second anode, the third anode, and the fourth anode. Then, an organic light-emitting layer is formed by evaporation or inkjet printing process, and then a cathode is formed on the organic light-emitting layer, and then an encapsulation structure layer is formed, which can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, and the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to prevent external water vapor from entering the light-emitting structure layer.

[0353] FIG. 23 is a structural schematic diagram of another display substrate according to an example embodiment of the present disclosure. As shown in FIG. 23, the display area can include a first area 110 and a second area 120, the first area 110 can be referred to as an FIP area, which is an area provided with the first data connection line 81 or the second data connection line 82, and the second area 120 can be referred to as a non-FIP area or an SIP area, which is an area provided with the first power supply trace 91 and the second power supply trace 92, or an area without the first data connection line 81 and the second data connection line 82.

[0354] In example embodiments, the second area 120 can include at least a second transition area 130 and a second normal area 140, the second transition area 130 can be arranged at a position close to the first area 110 in the second area 120, and the second normal area 140 can be arranged at a position away from the first area 110 on a side of the second transition area 130, that is, the second transition area 130 can be located between the first area 110 and the second normal area 140.

[0355] In an exemplary embodiment, the second transition area 130 and the second normal area 140 can each include a plurality of repeating units. The structure of the repeating units in the second transition area 130 and the second normal area 140 can be substantially the same, except that the number of repeating units in which the power transfer bar is disposed in one repeating row of the second transition area 130 can be less than or equal to the number of repeating units in which the power transfer bar is disposed in one repeating row of the second normal area 140, and the number of repeating units in which the power transfer bar is disposed in one repeating column of the second transition area 130 can be less than or equal to the number of repeating units in which the power transfer bar is disposed in one repeating column of the second normal area 140.

[0356] In an exemplary embodiment, the repeating units can include first repeating units and second repeating units, the first repeating units can be repeating units in which the power transfer bar is disposed, and the second repeating units can be repeating units in which the power transfer bar is not disposed, i.e., in the first repeating units, the first power supply wiring and the second power supply wiring are connected to each other by the power transfer bar and the power connection electrode, and in the second repeating units, the first power supply wiring and the second power supply wiring are not connected.

[0357] In an exemplary embodiment, the number of first repeating units in one repeating row of the second transition area 130 can be less than or equal to the number of first repeating units in one repeating row of the second normal area 140, and the number of first repeating units in one repeating column of the second transition area 130 can be less than or equal to the number of first repeating units in one repeating column of the second normal area 140.

[0358] FIG. 24 is a schematic view of a repeating unit in a second normal area according to an exemplary embodiment of the disclosure, which is a magnified view of region A in FIG. 23. As shown in FIGS. 23 and 24, the second normal area 140 can include a plurality of first repeating units Q1 forming a plurality of repeating rows and a plurality of repeating columns, i.e., the power transfer bar is disposed in each of the plurality of repeating units of the second normal area 140.

[0359] In an exemplary embodiment, the second transition area 130 can include at least a first sub-area 130-1 and a second sub-area 130-2. The first sub-area 130-1 can have a bar shape extending along the first direction X, and can be disposed on a side of the first area 110 away from the binding area (in the opposite direction of the second direction Y). The second sub-area 130-2 can have a bar shape extending along the second direction Y, and can be disposed on a side of the first area 110 close to the center line O (the first direction X or the opposite direction of the first direction X).

[0360] FIG. 25 is a schematic diagram of a repeating unit in a first sub-region of an exemplary embodiment of the present disclosure, which is a zoomed-in view of region B in FIG. 23. As shown in FIG. 23 and FIG. 25, the first sub-region 130-1 can include a plurality of repeating rows, which can include the m1th repeating row to the m10th repeating row arranged in sequence along a direction away from the binding region, and at least one repeating row can include at least one first repeating unit Q1 and a plurality of second repeating units Q2.

[0361] In an exemplary implementation, the number of first repeating units Q1 in the jth repeating row can be greater than or equal to the number of first repeating units Q1 in the ith repeating row, the jth repeating row is located on a side of the ith repeating row away from the first region, i.e., along a direction away from the binding region, the number of repeating units in which the power transfer bar is arranged gradually increases in the plurality of repeating rows, and i and j are natural numbers. For example, the m1th repeating row can include 1 first repeating unit Q1, and the m2th repeating row can include 1 first repeating unit Q1. For another example, the m4th repeating row can include 2 first repeating units Q1, and the m5th repeating row can include 3 first repeating units Q1. For another example, the m7th repeating row can include 3 first repeating units Q1, and the m8th repeating row can include 4 first repeating units Q1.

[0362] In an exemplary implementation, the position of the first repeating unit Q1 in one repeating row can be arranged according to the layout requirement, which is not limited in the present disclosure.

[0363] In an exemplary implementation, in the first region, one repeating row generally includes 1 repeating unit in which the data transfer bar is arranged. In the second normal region, one repeating row generally includes a plurality of repeating units in which the power transfer bar is arranged. The present disclosure gradually changes the number of power transfer bars between the first region and the second normal region by arranging the varying relationship of the number of power transfer bars in the plurality of repeating rows of the first sub-region, and the number of power transfer bars in the plurality of repeating rows of the first sub-region gradually increases along a direction away from the first region, which can effectively eliminate the film layer difference between different regions, is conducive to shadow elimination, and avoids appearance defects of the display substrate.

[0364] FIG. 26 is a schematic diagram of a repeating unit in a second sub-region of an exemplary embodiment of the present disclosure, which is a zoomed-in view of region C in FIG. 23. As shown in FIG. 23 and FIG. 26, the second sub-region 130-2 can include a plurality of repeating columns, which can include the n1th repeating column to the n8th repeating column arranged in sequence along a direction close to the center line O, and at least one repeating column can include at least one first repeating unit Q1 and a plurality of second repeating units Q2.

[0365] In an example embodiment, the number of first repeating units Q1 in the jth repeating column can be greater than or equal to the number of first repeating units Q1 in the ith repeating column, the jth repeating column is located on the side of the ith repeating column away from the first region, i.e. in the direction close to the center line O, the number of circuit units provided with the power transfer bar in the plurality of repeating columns gradually increases, i and j are natural numbers. For example, the nth1 repeating column can include 1 first repeating unit Q1, and the nth2 repeating column can include 2 first repeating units Q1. For another example, the nth3 repeating column can include 2 first repeating units Q1, and the nth4 repeating column can include 3 first repeating units Q1. For another example, the nth5 repeating column can include 3 first repeating units Q1, and the nth6 repeating column can include 4 first repeating units Q1.

[0366] In an example embodiment, the position of the first repeating unit Q1 in one repeating column can be set according to the layout requirement, which is not limited in the present disclosure.

[0367] In an example embodiment, in the first region, one repeating column generally includes one repeating unit provided with a data transfer bar. In the second normal region, one repeating column generally includes a plurality of repeating units provided with a power transfer bar. The present disclosure gradually changes the number of power transfer bars in the plurality of repeating columns in the second sub-region, and performs a gradual change process on the number of power transfer bars between the first region and the second normal region. Along the direction away from the first region, the number of power transfer bars in the plurality of repeating columns in the second sub-region gradually increases, which can effectively eliminate the film layer difference between different regions, is beneficial to the elimination of shadows, and avoids the appearance defect of the display substrate.

[0368] The display substrate provided by the example embodiment of the present disclosure sets the first power supply line and the second power supply line in the display region, and the first power supply line and the second power supply line are connected to each other through the power transfer bar to form a grid communication structure, which realizes the SIP structure. Not only can effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, realize low power consumption, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, but also can greatly reduce the width of the frame power supply lead, greatly reduce the frame width, improve the screen ratio, and be beneficial to realize the full-screen display.

[0369] The example embodiment of the present disclosure sets the data connection line in the display region, and the data lead-out line of the binding region is connected to the data signal line through the data connection line to realize the FIP structure, so that the fan-shaped diagonal line does not need to be set in the lead-out line area, effectively reducing the length of the lead-out line area, greatly reducing the lower frame width, improving the screen ratio, and being beneficial to realize the full-screen display.

[0370] The number of power adapter strips in the second transition region is set to change, and the number of power adapter strips between the first region and the second normal region is gradually changed, which can effectively eliminate the film layer difference between different regions, is conducive to shadow elimination, and avoids appearance defects of the display substrate.

[0371] The pad block is set to pad the data adapter strip or the power connection strip, and the pad block with a constant potential can shield the influence of the data voltage jump on the pixel driving circuit.

[0372] The second wire is set to at least partially overlap the normal projection of the data adapter strip or the power connection strip on the substrate, so that the data adapter strip or the power connection strip in the second source-drain metal layer is covered and protected by the second wire of the third source-drain metal layer.

[0373] The anode shielding part is set to at least partially overlap the normal projection of the data adapter strip or the power adapter strip on the substrate, so that the data adapter strip or the power adapter strip in the second source-drain metal layer is covered and protected by the anode shielding part in the anode conductive layer.

[0374] The first initial connection line, the second initial connection line and the third initial connection line are set, the first initial connection line and the first initial signal line form a mesh communication structure, the second initial connection line and the second initial signal line form a mesh communication structure, and the third initial connection line and the third initial signal line form a mesh communication structure, which can not only effectively reduce the resistance of the initial signal line, reduce the voltage drop of the initial signal, effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0375] The preparation process of the present disclosure can be well compatible with the existing preparation process, and the process is simple to implement, high in production efficiency, low in production cost and high in yield.

[0376] The structure and its preparation process shown in the foregoing of the present disclosure are only exemplary, and in the exemplary embodiments, the corresponding structure can be changed according to actual needs, and the patterning process can be increased or reduced, which is not limited in the present disclosure.

[0377] In the exemplary embodiments, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0378] The present disclosure also provides a preparation method of a display substrate for manufacturing the display substrate provided in the above embodiments. In an exemplary embodiment, the preparation method can include:

[0379] forming a driving structure layer on the substrate, the driving structure layer comprising at least a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines, a plurality of data connection lines, and a plurality of power supply lines, at least one circuit unit comprising a pixel driving circuit, the data signal lines being configured to provide data signals to the pixel driving circuit, the data connection lines being configured to provide data signals to the data signal lines;

[0380] forming a light emitting structure layer on the driving structure layer, the light emitting structure layer comprising at least a plurality of light emitting units, at least one light emitting unit comprising a light emitting device, the power supply lines being configured to provide power supply signals to the light emitting device;

[0381] in a plane parallel to the substrate, the display substrate comprising at least a first region and a second region, the first region being a region where the data connection lines are arranged, and the second region being a region where the power supply lines are arranged; at least one power supply line comprising a first power supply line extending along a first direction and a second power supply line extending along a second direction, the first direction and the second direction intersecting; in at least one circuit unit of the second region, the first power supply line and the second power supply line are connected to each other by a power supply transfer strip, forming a grid communication structure.

[0382] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized by, The display substrate comprises a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; the driving structure layer comprises at least a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines and a plurality of power supply lines, at least one circuit unit comprises a pixel driving circuit, the data signal lines are configured to provide data signals to the pixel driving circuit, and the data connection lines are configured to provide data signals to the data signal lines; The light-emitting structure layer comprises at least a plurality of light-emitting units, at least one light-emitting unit comprises a light-emitting device, and the power supply lines are configured to provide power supply signals to the light-emitting device; In a plane parallel to the substrate, the display substrate comprises at least a first region and a second region, the first region is a region in which the data connection lines are arranged, and the second region is a region in which the power supply lines are arranged; at least one power supply line comprises a first power supply line extending along a first direction and a second power supply line extending along a second direction, the first direction and the second direction intersect; in at least one circuit unit of the second region, the first power supply line and the second power supply line are connected to each other through a power supply adapter strip, forming a grid communication structure. 2.The display substrate of claim 1, wherein, In a direction perpendicular to the substrate, the driving structure layer comprises a plurality of conductive layers, the first power supply line and the second power supply line are arranged in different conductive layers, and the first power supply line and the power supply adapter strip are arranged in the same conductive layer. 3.The display substrate of claim 2, wherein, The plurality of conductive layers comprise at least a first source-drain metal layer, a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer arranged on a side of the second source-drain metal layer away from the substrate, the first power supply line and the power supply adapter strip are arranged in the second source-drain metal layer, and the second power supply line is arranged in the third source-drain metal layer. 4.The display substrate of claim 3, wherein, At least one circuit unit of the second region further comprises a power supply connection electrode, the power supply connection electrode is arranged in the second source-drain metal layer, one end of the power supply adapter strip is connected to the first power supply line, the other end of the power supply adapter strip is connected to the power supply connection electrode, and the second power supply line is connected to the power supply connection electrode through a via hole. 5.The display substrate of claim 4, wherein, In at least one circuit unit, the first power supply line, the power supply adapter strip and the power supply connection electrode form an integrated structure. 6.The display substrate of claim 3, wherein, A projection of the second power supply line on the substrate at least partially overlaps a projection of the power supply adapter strip on the substrate. 7.The display substrate of claim 6, wherein, In the first direction, the power transfer bar has a first power transfer bar edge and a second power transfer bar edge, the second power transfer bar edge being located on a side of the first power transfer bar edge in the first direction, the second power trace has a first power trace edge and a second power trace edge, the first power trace edge being located on a side of the first power transfer bar edge away from the second power trace edge, the second power trace edge being located on a side of the second power transfer bar edge away from the first power trace edge; a distance between the first power trace edge and the first power transfer bar edge is greater than or equal to 0.6 μm, a distance between the second power trace edge and the second power transfer bar edge is greater than or equal to 0.6 μm, the distance being a dimension in the first direction. 8.The display substrate of claim 3, wherein, The at least one circuit unit further comprises a spacer disposed in the first source-drain metal layer, a footprint of the spacer on the substrate at least partially overlaps with a footprint of the power transfer bar on the substrate. 9.The display substrate of claim 8, wherein, In the first direction, the power transfer bar has a first power transfer bar edge and a second power transfer bar edge, the second power transfer bar edge being located on a side of the first power transfer bar edge in the first direction, the spacer has a first spacer edge and a second spacer edge, the first spacer edge being located on a side of the first power transfer bar edge away from the second spacer edge, the second spacer edge being located on a side of the second power transfer bar edge away from the first spacer edge; a distance between the first spacer edge and the first power transfer bar edge is greater than or equal to 0.6 μm, a distance between the second spacer edge and the second power transfer bar edge is greater than or equal to 0.6 μm, the distance being a dimension in the first direction. 10.The display substrate of claim 8, wherein, The at least one circuit unit further comprises an initial signal line configured to provide an initial signal to the pixel driving circuit, the spacer is connected to the initial signal line. 11.The display substrate of claim 1, wherein, The plurality of light emitting units at least comprises a red light emitting unit emitting red light, a blue light emitting unit emitting blue light, a first green light emitting unit emitting green light and a second green light emitting unit emitting green light, the red light emitting unit at least comprises a first anode, the blue light emitting unit at least comprises a second anode, the first green light emitting unit at least comprises a third anode, and the second green light emitting unit at least comprises a fourth anode; A footprint of the first anode on the substrate at least partially overlaps with a footprint of the power transfer bar on the substrate, and footprints of the second anode, the third anode and the fourth anode on the substrate do not overlap with the footprint of the power transfer bar on the substrate; Alternatively, a footprint of the second anode on the substrate at least partially overlaps with a footprint of the power transfer bar on the substrate, and footprints of the first anode, the third anode and the fourth anode on the substrate do not overlap with the footprint of the power transfer bar on the substrate; Or, the orthographic projection of the first anode and the second anode on the substrate at least partially overlaps with the orthographic projection of the power adapter bar on the substrate, and the orthographic projection of the third anode and the fourth anode on the substrate does not overlap with the orthographic projection of the power adapter bar on the substrate. Or, the orthographic projection of the third anode and / or the fourth anode on the substrate at least partially overlaps with the orthographic projection of the power adapter bar on the substrate, and the orthographic projection of the first anode and the second anode on the substrate does not overlap with the orthographic projection of the power adapter bar on the substrate. 12.The display substrate of claim 11, wherein, The first anode, the second anode, the third anode or the fourth anode comprises at least an anode main part and an anode shielding part, the anode shielding part is connected with the anode main part, and the orthographic projection of the anode shielding part on the substrate at least partially overlaps with the orthographic projection of the power adapter bar on the substrate. 13.The display substrate of claim 12, wherein, The orthographic projection of the anode shielding part on the substrate contains the orthographic projection of the power adapter bar on the substrate, and the area of the orthographic projection of the anode shielding part on the substrate is greater than the area of the orthographic projection of the power adapter bar on the substrate. 14.The display substrate according to any one of claims 1 to 13, wherein The second region comprises at least a second transition region and a second normal region, the second transition region is located between the first region and the second normal region; the second transition region comprises a plurality of first repeating units and a plurality of second repeating units, the second normal region comprises a plurality of first repeating units, the first repeating unit is a repeating unit provided with the power adapter bar, and the second repeating unit is a repeating unit without the power adapter bar; the number of the first repeating units in one repeating row of the second transition region is less than or equal to the number of the first repeating units in one repeating row of the second normal region, and / or the number of the first repeating units in one repeating column of the second transition region is less than or equal to the number of the first repeating units in one repeating column of the second normal region. 15.The display substrate of claim 14, wherein, The second transition region comprises at least a first sub-region, the first sub-region is arranged on the side of the first region in the opposite direction of the first direction; the first sub-region comprises a plurality of repeating rows, at least one repeating row comprises at least one first repeating unit and a plurality of second repeating units, the number of the first repeating units in the jth repeating row is greater than or equal to the number of the first repeating units in the ith repeating row, the jth repeating row is located on the side away from the first region of the ith repeating row, and i and j are natural numbers. 16.The display substrate of claim 14, wherein, The second transition region comprises at least a second sub-region, the second sub-region is arranged on the side of the first region in the first direction or the side of the first region in the opposite direction of the first direction; the second sub-region comprises a plurality of repeating columns, at least one repeating column comprises at least one first repeating unit and a plurality of second repeating units, the number of the first repeating units in the jth repeating column is greater than or equal to the number of the first repeating units in the ith repeating column, the jth repeating column is located on the side away from the first region of the ith repeating column, and i and j are natural numbers. 17.The display substrate of claim 14, wherein, The repeating unit includes 8 circuit units, the 8 circuit units form a first unit row and a second unit row, and form a first unit column, a second unit column, a third unit column and a fourth unit column, a power supply connection electrode is arranged between the third unit column and the fourth unit column in the first unit row, and a power supply connection electrode is arranged between the first unit column and the second unit column in the second unit row.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for manufacturing a display substrate, comprising: forming a driving structure layer on a substrate, the driving structure layer comprising at least a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines and a plurality of power supply lines, at least one circuit unit comprising a pixel driving circuit, the data signal lines being configured to provide data signals to the pixel driving circuit, the data connection lines being configured to provide data signals to the data signal lines; forming a light emitting structure layer on the driving structure layer, the light emitting structure layer comprising at least a plurality of light emitting units, at least one light emitting unit comprising a light emitting device, the power supply lines being configured to provide power supply signals to the light emitting device; in a plane parallel to the substrate, the display substrate comprises at least a first region and a second region, the first region being a region where the data connection lines are arranged, and the second region being a region where the power supply lines are arranged; at least one power supply line comprises a first power supply line extending along a first direction and a second power supply line extending along a second direction, the first direction and the second direction intersecting; in at least one circuit unit of the second region, the first power supply line and the second power supply line are connected to each other through a power supply transfer strip, forming a grid communication structure.

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