Semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic apparatus. The semiconductor device comprises: one or more memory cells, and a first word line (1), a second word line (4), a first bit line (2), and a second bit line (3); each memory cell comprises: a first transistor and a second transistor; a first gate (1-1) and a reference electrode (42) are oppositely arranged and insulated from each other to form a pillar structure; the first bit line (2) is located on the side of the first gate (1-1) distant from the reference electrode (42); the first semiconductor layer (81) is arranged around the side wall of the pillar structure, at least part of the inner surface of the first semiconductor layer (81) is in direct contact with the reference electrode (42), and at least part of the outer surface of the first semiconductor layer (81) is in direct contact with the first bit line (2); a second gate (41) surrounds the first semiconductor layer (81), and the second gate (41) is insulated from both the first semiconductor layer (81) and the first bit line (2).

Description

Semiconductor device, manufacturing method thereof, and electronic device

[0001] The present disclosure claims priority to the Chinese patent application No. 202410527633.1, filed on April 28, 2024, and entitled "Semiconductor device, manufacturing method thereof, and electronic device", the content of which is hereby incorporated by reference into the present disclosure. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, the technical field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] In one aspect, the embodiments of the present disclosure provide a semiconductor device, comprising: one or more memory cells and a first word line, a second word line, a first bit line and a second bit line disposed on a substrate; the memory cell comprises: a first transistor and a second transistor;

[0008] The first transistor is a double-gate structure, and the first transistor comprises a first gate, a first semiconductor layer, a second gate and a reference electrode;

[0009] The first gate is connected with the first word line, and the first gate is oppositely disposed with the reference electrode and insulated from each other, forming a columnar structure;

[0010] The first bit line is located on the side of the first gate away from the reference electrode;

[0011] The first semiconductor layer is disposed around the sidewall of the columnar structure, and the inner surface of at least part of the first semiconductor layer is in direct contact with the reference electrode, and the outer surface of at least part of the first semiconductor layer is in direct contact with the first bit line;

[0012] The second gate surrounds a partial region of an outer surface of the first semiconductor layer, and the second gate is insulated from the first semiconductor layer and the first bit line;

[0013] The second transistor comprises a third gate and a second semiconductor layer, the second semiconductor layer surrounds the sidewall of the third gate and is insulated from each other, at least part of the second semiconductor layer is connected with the second gate, and at least part of the second semiconductor layer is connected with the second bit line.

[0014] In another aspect, the embodiments of the present disclosure also provide a manufacturing method of a semiconductor device, comprising:

[0015] Forming first insulating medium layers and second insulating medium layers alternately arranged on a substrate to form a stack structure;

[0016] Forming an isolation groove in the stack structure, and filling an isolation material in the isolation groove to form a first isolation layer;

[0017] Forming a first hole in the stack structure;

[0018] Forming an initial second gate on the sidewall of the first hole;

[0019] Forming a first gate insulating layer on the initial second gate;

[0020] Forming a first semiconductor layer on the first gate insulating layer;

[0021] Forming a second conductive thin film covering the first semiconductor layer, and filling the first hole by a second shielding thin film;

[0022] Etching to remove part of the second shielding thin film in the first hole to form a second hole, the second hole exposes at least part of the second conductive thin film, and the remaining second shielding thin film forms a second shielding layer;

[0023] Etching to remove the second conductive thin film exposed by the second hole, and retaining the second conductive thin film covered by the second shielding layer to form a reference signal line comprising a reference electrode;

[0024] Forming a first gate in the second hole, the first gate is insulated from the reference signal line;

[0025] Forming a first lateral groove and a second lateral groove in the stack structure, the first lateral groove exposes at least part of the initial second gate;

[0026] Etching to remove the exposed initial second gate to form a second gate, and exposing at least part of the first semiconductor layer, and forming a second insulating layer on the end surface of the second gate;

[0027] a first bit line is formed on the inner wall of the first lateral trench, the first bit line is connected with the exposed first semiconductor layer, and the first bit line is isolated from the second gate by the second insulating layer; and a second bit line is formed on the inner wall of the second lateral trench;

[0028] a third hole is formed in the stack structure, the third hole exposes at least part of the second gate and at least part of the second bit line;

[0029] a second semiconductor layer and a third gate are sequentially formed on the inner wall of the third hole, the second semiconductor layer is connected with the exposed second gate and second bit line respectively, and the third gate fills the third hole.

[0030] In another aspect, the embodiments of the present disclosure also provide an electronic device including the semiconductor device described in any of the above embodiments.

[0031] Other aspects can become apparent from a review of the drawings and detailed description.

[0032] SUMMARY

[0033] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions.

[0034] FIG. 1 is an equivalent circuit diagram of a semiconductor device provided by an example embodiment;

[0035] FIG. 2 is a structural schematic diagram of a memory cell of a semiconductor device provided by an example embodiment;

[0036] FIG. 3A is a schematic diagram of a semiconductor device in a cross section parallel to a substrate direction provided by an example embodiment;

[0037] FIG. 3B is a cross-sectional view of a semiconductor device perpendicular to a substrate direction provided by an example embodiment;

[0038] FIG. 3C is a cross-sectional view of a semiconductor device perpendicular to a substrate direction provided by an example embodiment;

[0039] FIG. 3D is a schematic diagram of a longitudinal cross section of a semiconductor device provided by an example embodiment;

[0040] FIG. 4 is a schematic diagram of a semiconductor device after a stack structure is formed in a manufacturing process provided by an example embodiment;

[0041] FIG. 5 is a schematic diagram of a semiconductor device after a first isolation layer is formed in a manufacturing process provided by an example embodiment;

[0042] Figure 6 is a schematic view of a cross section parallel to the substrate direction after forming a first hole in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0043] Figure 7A is a schematic view of a cross section parallel to the substrate direction after forming a third via in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0044] Figure 7B is a schematic view of a longitudinal cross section after forming a third via in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0045] Figure 8 is a schematic view of a cross section parallel to the substrate direction after forming a first conductive film in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0046] Figure 9A is a schematic view of a cross section parallel to the substrate direction after forming an initial second gate in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0047] Figure 9B is a schematic view of a longitudinal cross section after forming an initial second gate in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0048] Figure 10A is a schematic view of a cross section parallel to the substrate direction after forming a first gate insulating layer in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0049] Figure 10B is a schematic view of a longitudinal cross section after forming a first gate insulating layer in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0050] Figure 11 is a schematic view of a cross section parallel to the substrate direction after forming a first semiconductor film in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0051] Figure 12 is a schematic view of a cross section parallel to the substrate direction after forming a first shielding film in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0052] Figure 13A is a schematic view of a cross section parallel to the substrate direction after forming a first shielding layer in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0053] Figure 13B is a schematic view of a longitudinal cross section after forming a first shielding layer in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0054] Figure 14 is a schematic view of a cross section parallel to the substrate direction after forming a first semiconductor layer in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0055] Figure 15A is a schematic view of a cross section parallel to the substrate direction after removing a first shielding layer in the manufacturing process of a semiconductor device according to an exemplary embodiment;

[0056] FIG. 15B is a longitudinal sectional view of the semiconductor device after the first barrier layer is removed in the manufacturing process according to an exemplary embodiment;

[0057] FIG. 16 is a schematic view of a cross section parallel to the substrate direction after the second conductive film and the second barrier film are formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0058] FIG. 17A is a schematic view of a cross section parallel to the substrate direction after the second hole and the second barrier layer are formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0059] FIG. 17B is a longitudinal sectional view of the semiconductor device after the second hole and the second barrier layer are formed in the manufacturing process according to an exemplary embodiment;

[0060] FIG. 18 is a schematic view of a cross section parallel to the substrate direction after the reference electrode is formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0061] FIG. 19 is a schematic view of a cross section parallel to the substrate direction after the first insulating film is formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0062] FIG. 20 is a schematic view of a cross section parallel to the substrate direction after the first insulating layer is formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0063] FIG. 21A is a schematic view of a cross section parallel to the substrate direction after the second gate insulating layer and the first gate are formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0064] FIG. 21B is a longitudinal sectional view of the semiconductor device after the second gate insulating layer and the first gate are formed in the manufacturing process according to an exemplary embodiment;

[0065] FIG. 22A is a schematic view of a cross section parallel to the substrate direction after the first trench and the second trench are formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0066] FIG. 22B is a longitudinal sectional view of the semiconductor device after the first trench and the second trench are formed in the manufacturing process according to an exemplary embodiment;

[0067] FIG. 23A is a schematic view of a cross section parallel to the substrate direction after the first lateral trench and the second lateral trench are formed in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0068] FIG. 23B is a longitudinal sectional view of the semiconductor device after the first lateral trench and the second lateral trench are formed in the manufacturing process according to an exemplary embodiment;

[0069] FIG. 24A is a schematic view of a cross section parallel to the substrate direction after exposing the first gate insulating layer in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0070] FIG. 24B is a longitudinal cross section view after exposing the first gate insulating layer in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0071] FIG. 25 is a schematic view of a cross section parallel to the substrate direction after forming the second insulating film in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0072] FIG. 26 is a schematic view of a cross section parallel to the substrate direction after forming the second insulating layer and exposing the first semiconductor layer in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0073] FIG. 27 is a schematic view of a cross section parallel to the substrate direction after forming the third conductive film in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0074] FIG. 28A is a schematic view of a cross section parallel to the substrate direction after forming the first bit line and the second bit line in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0075] FIG. 28B is a longitudinal cross section view after forming the first bit line and the second bit line in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0076] FIG. 29 is a schematic view of a cross section parallel to the substrate direction after forming the second isolation layer in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0077] FIG. 30 is a schematic view of a cross section parallel to the substrate direction after forming the third hole in the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0078] FIG. 31 is a longitudinal cross section view after forming the third lateral groove in the manufacturing process of the semiconductor device according to an exemplary embodiment.

[0079] DETAILED DESCRIPTION

[0080] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0081] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings of the terms to those having ordinary skill in the art to which the present disclosure belongs.

[0082] Embodiments of the present disclosure are not necessarily limited by the size of the components shown in the drawings, which are given by way of illustration. Furthermore, the drawings are schematically shown ideal examples, and embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0083] In the present disclosure, ordinal numbers such as "first", "second", "third" and the like are provided in order to avoid confusion of components, and do not indicate any order, number or importance.

[0084] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, which are only for the convenience of the description of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0085] In the present disclosure, a transistor refers to an element including at least a gate, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (also referred to as a drain terminal, a drain region, or a drain electrode) and the source electrode (also referred to as a source terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0086] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0087] In the present disclosure, "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced with "conductive film". Similarly, "insulating film" can be replaced with "insulating layer".

[0088] In the present disclosure, "A and B are provided in the same layer" means that A and B are formed by the same patterning process. "The orthogonal projection of B is within the range of the orthogonal projection of A" means that the boundary of the orthogonal projection of B falls within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0089] The "A and B are integrated structure" in the embodiments of the present disclosure can refer to no obvious fault or gap, or no obvious boundary interface in microstructure. Generally, the connected film layers are integrated on a film layer. For example, A and B use the same material to form a film layer and have a connected structure by the same patterning process.

[0090] The semiconductor device provided by the embodiments of the present disclosure includes one or more memory cells, and a first word line, a second word line, a first bit line and a second bit line, wherein the memory cell includes a first transistor and a second transistor.

[0091] The first transistor is a double-gate structure, and the first transistor includes a first gate, a first semiconductor layer, a second gate and a reference electrode.

[0092] The first gate is connected with the first word line, and the first gate is arranged opposite to the reference electrode and insulated from each other to form a columnar structure.

[0093] The first bit line is located on a side of the first gate away from the reference electrode.

[0094] The first semiconductor layer is arranged around the sidewall of the columnar structure, and an inner surface of at least part of the first semiconductor layer is in direct contact with the reference electrode, and an outer surface of at least part of the first semiconductor layer is in direct contact with the first bit line.

[0095] The second gate surrounds part of the outer surface of the first semiconductor layer, and the second gate is insulated from the first semiconductor layer and the first bit line.

[0096] The second transistor includes a third gate and a second semiconductor layer, and the second semiconductor layer is arranged around the sidewall of the third gate and insulated from each other, at least part of the second semiconductor layer is connected with the second gate, and at least part of the second semiconductor layer is connected with the second bit line.

[0097] The semiconductor device of the present disclosure is illustrated by some exemplary embodiments.

[0098] FIG. 1 is an equivalent circuit diagram of a semiconductor device provided by an exemplary embodiment. In an exemplary embodiment, as shown in FIG. 1, the semiconductor device of the embodiments of the present disclosure can be a 2T0C structure, and can include a first transistor T1 and a second transistor T2. The first transistor T1 can be a double-gate structure, and the first transistor T1 is connected with a first word line 1 and a first bit line 2 respectively. The second transistor T2 can be a single-gate structure, and the second transistor T2 is connected with a second word line 4 and a second bit line 3 respectively.

[0099] In an example embodiment, the first transistor T1 can include a first gate, a first semiconductor layer, a second gate 41, and a reference electrode 42, the first gate of the first transistor T1 is connected with the first word line 1, the second gate 41 of the first transistor T1 can be connected with the second transistor T2, and the first gate and the second gate 41 are both insulated from the first semiconductor layer; a first contact end of the first semiconductor layer is connected with the first bit line 2, and a second contact end of the first semiconductor layer is connected with the reference electrode 42; the reference electrode 42 is insulated from the first gate and connected with the first semiconductor layer.

[0100] In an example embodiment, the semiconductor device of the present disclosure further includes a reference signal line, and the reference electrode 42 is connected with the reference signal line.

[0101] In an example embodiment, the second transistor T2 can include a third gate and a second semiconductor layer, the third gate of the second transistor T2 is connected with the second word line 4; a first contact end of the second semiconductor layer is connected with the second bit line 3, and a second contact end of the second semiconductor layer is connected with the second gate 41 of the first transistor T1.

[0102] FIG. 2 is a structural schematic diagram of a storage unit of a semiconductor device provided by an example embodiment. In an example embodiment, as shown in FIG. 2, in a plane parallel to the plane where the substrate is located, the semiconductor device of the present disclosure can include at least one storage unit 100 disposed on the substrate, and a first word line 1, a first bit line 2, a second word line 4, and a second bit line 3. The first word line 1 and the second word line 4 both extend along a direction perpendicular to the substrate, and the shapes of the first word line 1 and the second word line 4 both include a linear shape. The first bit line 2 and the second bit line 3 both extend along a direction parallel to the substrate, and the first bit line 2 and the second bit line 3 are substantially parallel, and the shapes of the first bit line 2 and the second bit line 3 both include a linear shape. The storage unit 100 can include a first transistor and a second transistor disposed on the substrate.

[0103] In an example embodiment, the first transistor can include a first gate 1-1, a first semiconductor layer 81, a second gate 41, and a reference electrode 42. The first gate 1-1 is integrated with the first word line 1 as a part of the first word line 1, and the shape of the first gate 1-1 can include a column shape along a direction perpendicular to the substrate. The reference electrode 42 is perpendicular to the substrate, and the shape of the reference electrode 42 includes a layer shape. The reference electrode 42 is disposed opposite to the first gate 1-1. For example, the opposite disposition can be a complete opposite disposition, or can be an interleaved opposite disposition, etc. The reference electrode 42 and the first gate 1-1 are disposed with an insulating layer 110 therebetween. The insulating layer 110 is disposed around the sidewall of the first gate 1-1. The shape of the first semiconductor layer 81 includes a ring shape extending along a direction perpendicular to the substrate. The first semiconductor layer 81 is disposed around the sidewall of the columnar portion of the first gate 1-1, and the first semiconductor layer 81 and the first gate 1-1 are disposed with the insulating layer 110 therebetween. The second gate 41 has a U shape in a cross section parallel to the plane in which the substrate lies. The second gate 41 is disposed around the outer sidewall of the first semiconductor layer 81. The second gate 41 and the first semiconductor layer 81 are disposed with a first gate insulating layer 51 therebetween. The first gate insulating layer 51 is disposed around the sidewall of the first semiconductor layer 81. The first gate insulating layer 51 separates the second gate 41 from the first semiconductor layer 81.

[0104] In an example embodiment, the shape of the insulating layer 110 includes a ring shape perpendicular to the substrate. The insulating layer 110 is disposed around the sidewall of the first gate 1-1. At least part of the insulating layer 110 is disposed between the first gate 1-1 and the reference electrode 42. At least part of the insulating layer 110 is disposed between the first gate 1-1 and the first semiconductor layer 81. The inner surface of the sidewall of the insulating layer 110 is connected to the sidewall of the first gate 1-1. The sidewall of the insulating layer 110 away from the first bit line 2 is connected to the sidewall of the reference electrode 42.

[0105] In an example embodiment, the reference electrode 42 is located on the side of the first gate 1-1 away from the first bit line 2. The reference electrode 42 and the first gate 1-1 are disposed with the insulating layer 110 therebetween. In a cross section parallel to the plane in which the substrate lies, the shape of the opposite portion of the reference electrode 42 and the first gate 1-1 includes a U shape. The opening of the U shape faces the first gate 1-1. The insulating layer 110 away from the first bit line 2 fills the U shape.

[0106] In an example embodiment, the reference electrode 42, the insulating layer 110, and the first gate 1-1 combine to form a columnar structure. The columnar structure is perpendicular to the substrate. In a cross section parallel to the plane in which the substrate lies, the columnar structure includes a circular shape, an elliptical shape, a rectangular shape, etc.

[0107] In an example embodiment, the columnar structures of a plurality of memory cells stacked in a direction perpendicular to the plane in which the substrate lies are integrated into a unitary structure. The plurality of columnar structures form a line shape.

[0108] In an example embodiment, the first bit line 2 and the reference electrode 42 are located on opposite sides of the first gate 1-1. The shape of the first semiconductor layer 81 includes a rectangular ring shape perpendicular to the substrate, the first semiconductor layer 81 surrounds the sidewall of the columnar structure, the first semiconductor layer 81 includes a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, the first sidewall is located on the side close to the first bit line 2, the second sidewall is located on the side away from the first bit line 2, the third sidewall and the fourth sidewall are oppositely arranged, and the two ends of the third sidewall and the fourth sidewall are connected with the first sidewall and the second sidewall respectively. The outer surface of the first sidewall directly contacts the first bit line 2, the inner surface of the second sidewall directly contacts the reference electrode 42, and the outer surfaces of the second sidewall, the third sidewall, and the fourth sidewall all directly contact the first gate insulating layer 51.

[0109] In an example embodiment, the first gate insulating layer 51 is located on the side of the first semiconductor layer 81 away from the columnar structure, the first gate insulating layer 51 includes a U shape in the cross section parallel to the substrate plane, and the first gate insulating layer 51 surrounds the sidewall of the first semiconductor layer 81. The U-shaped opening of the first gate insulating layer 51 faces the first bit line 2, and the end surface of the first gate insulating layer 51 facing the first bit line 2 is provided with a second insulating layer 112, the second insulating layer 112 is connected with the first bit line 2, and the second insulating layer 112 separates the second gate 41 from the first bit line 2. For example, the first gate insulating layer 51 includes a fifth sidewall, a sixth sidewall, and a seventh sidewall, the fifth sidewall is located on the side away from the first bit line 2, the sixth sidewall and the seventh sidewall are oppositely arranged, the ends of the sixth sidewall and the seventh sidewall away from the first bit line 2 are connected with the fifth sidewall respectively, and the ends of the sixth sidewall and the seventh sidewall close to the first bit line 2 are all provided with the second insulating layer 112, the second insulating layer 112 is connected with the first bit line 2, and the second insulating layer 112 separates the second gate 41 from the first bit line 2. The inner surfaces of the fifth sidewall, the sixth sidewall, and the seventh sidewall are all connected with the sidewall of the first semiconductor layer 81, and the outer surfaces of the fifth sidewall, the sixth sidewall, and the seventh sidewall are all connected with the sidewall of the second gate 41.

[0110] In an example embodiment, the second gate 41 is located on a side of the first gate insulating layer 51 away from the columnar structure, the second gate 41 includes a U shape in a cross section parallel to the plane of the substrate, the U shape of the second gate 41 is open toward the first bit line 2, the second gate 41 includes an eighth sidewall, a ninth sidewall, and a tenth sidewall, the eighth sidewall is located on a side away from the first bit line 2, the ninth sidewall and the tenth sidewall are oppositely arranged, the ninth sidewall and the tenth sidewall are connected with the eighth sidewall at ends away from the first bit line 2, and the ninth sidewall and the tenth sidewall are insulated from the first bit line 2 at ends close to the first bit line 2 by the second insulating layer 112 of the first gate insulating layer 51. The inner surfaces of the eighth sidewall, the ninth sidewall, and the tenth sidewall are connected with the sidewall of the first gate insulating layer 51, and the outer surface of the eighth sidewall is connected with the second semiconductor layer 82 of the second transistor.

[0111] In an example embodiment, the second transistor can include a third gate 4-1 and a second semiconductor layer 82. The third gate 4-1 has a shape including a columnar structure arranged along a direction perpendicular to the substrate, and the third gate 4-1 is connected with the second word line 4 in an integrated manner as a part of the second word line 4. The second semiconductor layer 82 has a shape including a ring structure arranged along a direction perpendicular to the substrate, and the second semiconductor layer 82 surrounds the sidewall of the third gate 4-1. A third gate insulating layer 53 is arranged between the second semiconductor layer 82 and the third gate 4-1, and the third gate insulating layer 53 has a shape including a ring structure arranged along a direction perpendicular to the substrate. The third gate insulating layer 53 separates the second semiconductor layer 82 from the third gate 4-1. A first side of the second semiconductor layer 82 is connected with the second bit line 3, and a second side of the second semiconductor layer 82 is connected with the second gate 41.

[0112] FIG. 3A is a schematic diagram of a cross section parallel to the substrate of a semiconductor device according to an example embodiment, and FIG. 3D is a schematic diagram of a longitudinal cross section of a semiconductor device according to an example embodiment. As shown in FIGS. 3A and 3D, the semiconductor device according to an example embodiment of the present disclosure can include a plurality of memory cells stacked along a direction perpendicular to the substrate 101. The first word line 1 and the second word line 4 both extend along a direction perpendicular to the substrate 101 and pass through memory cells of different layers. The region opposite to the first semiconductor layer 81 of the first word line 1 forms a first gate 1-1, and the region opposite to the second semiconductor layer 82 of the second word line 4 forms a third gate 4-1. Adjacent first semiconductor layers 81 in a direction perpendicular to the substrate are disconnected from each other. Adjacent second gates 41 in a direction perpendicular to the substrate are disconnected from each other. In an example, adjacent second semiconductor layers 82 in a direction perpendicular to the substrate are connected in an integrated manner.

[0113] In an exemplary embodiment, the semiconductor device further comprises a reference signal line 6, which can be a signal line supplying a high level or a low level, or a signal line grounded. The shape of the reference signal line 6 comprises a line shape, and the reference signal line 6 is perpendicular to the substrate and extends through different memory cells. The reference electrode 42 is connected to the reference signal line 6 as a part of the reference signal line 6.

[0114] In an exemplary embodiment, the semiconductor device further comprises a second isolation layer 105, which extends along the second direction D2 and is located between two adjacent second bit lines 3 in the first direction D1 to isolate the adjacent second bit lines 3. In the embodiment of the present disclosure, the plane formed by the first direction D1 and the second direction D2 is parallel to the plane of the substrate 101, and the third direction D3 is perpendicular to the plane of the substrate 101.

[0115] In an exemplary embodiment, the semiconductor device further comprises a first isolation layer 104, which has a rectangular shape and extends along the first direction D1. A plurality of first isolation layers 104 are arranged along the first direction D1 at intervals, and at least one of the first bit line 2, the second bit line 3 and the second isolation layer 105 is arranged between two adjacent first isolation layers 104 in the first direction D1. A plurality of second isolation layers 104 are arranged along the first direction D1 at intervals, and a memory cell is arranged between two adjacent first isolation layers 104 in the second direction D2.

[0116] In an exemplary embodiment, the first gate 1-1 extends along a direction perpendicular to the substrate, and the sidewall of the first gate 1-1 is surrounded by at least part of the first semiconductor layer 81. The cross section of the first gate 1-1 in a direction parallel to the substrate can be circular, elliptical or rectangular, etc. without limitation, and the cross section of the first gate 1-1 in a direction parallel to the substrate is adapted to the shape of the hole in which the first gate 1-1 is located.

[0117] In an exemplary embodiment, the second gate insulating layer 52 has a ring shape and surrounds the sidewall of the first gate 1-1. At least part of the second gate insulating layer 52 isolates the first gate 1-1 from the first semiconductor layer 81, at least part of the second gate insulating layer 52 isolates the first gate 1-1 from the second shielding layer 72, and at least part of the second gate insulating layer 52 isolates the first gate 1-1 from the first insulating layer 111.

[0118] In an exemplary embodiment, the reference electrode 42 is located on one side of the first gate 1-1 in the first direction D1, and the shape of the part of the reference electrode 42 opposite to the first gate 1-1 comprises a U shape. The opening of the reference electrode 42 faces the first gate 1-1. The reference electrode 42 comprises two end faces both facing the first gate 1-1.

[0119] In an example embodiment, the storage unit further comprises an insulating layer, the insulating layer surrounds the sidewall of the first gate 1-1, the insulating layer comprises a second gate insulating layer 52, a second shielding layer 72 and a first insulating layer 111. The shape of the second shielding layer 72 comprises a rectangle, the second shielding layer 72 is located between the first gate 1-1 and the reference electrode 42, the second shielding layer 72 fills the U-shaped reference electrode 42 and directly contacts the sidewall of the reference electrode 42. The shape of the first insulating layer 111 comprises a layer, the first insulating layer 111 covers two end faces of the U-shaped reference electrode 42, and the first insulating layer 111 is arranged between the two end faces of the reference electrode 42 and the first gate 1-1. In an example, the insulating layer comprises a second shielding layer and a first insulating layer, the second shielding layer fills the U-shaped opening of the reference electrode, and the first insulating layer covers two end faces of the reference electrode facing the first gate.

[0120] The first end of the first insulating layer 111 is connected with the second shielding layer 72, and the second end of the first insulating layer 111 is connected with the first semiconductor layer 81. The shape of the second gate insulating layer 52 comprises a ring, the second gate insulating layer 52 surrounds the sidewall of the first gate 1-1, the second gate insulating layer 52 directly contacts the sidewall of the first gate 1-1, at least part of the second gate insulating layer 52 is arranged between the first gate 1-1 and the second shielding layer 72, at least part of the second gate insulating layer 52 is arranged between the first gate 1-1 and the first insulating layer 111, and at least part of the second gate insulating layer 52 is arranged between the first gate 1-1 and the first semiconductor layer 81.

[0121] In an example embodiment, the reference electrode 42, the insulating layer and the first gate 1-1 combine to form a columnar structure, the columnar structure comprises a circle, an ellipse, a rectangle and the like in a cross section parallel to the plane where the substrate is located.

[0122] In an example embodiment, the shape of the first semiconductor layer 81 comprises a ring, the first semiconductor layer 81 surrounds the sidewall of the above-mentioned columnar structure, and the first semiconductor layer 81 is isolated from the first gate 1-1 by the second gate insulating layer 52.

[0123] In an example embodiment, the storage unit further comprises a first gate insulating layer 51, the shape of the first gate insulating layer 51 comprises a U shape, the opening of the first gate insulating layer 51 faces the first bit line 2, the first gate insulating layer 51 surrounds the sidewall of the first semiconductor layer 81, and the first gate insulating layer 51 isolates the first semiconductor layer 81 from the second gate 41.

[0124] In an example embodiment, the second gate 41 has a U shape, the opening of the second gate 41 faces the first bit line 2, and the second gate 41 surrounds the sidewall of the first semiconductor layer 81 through the first gate insulating layer 51. The second gate 41 includes two end faces, and both of the two end faces of the second gate 41 face the first bit line 2.

[0125] In an example embodiment, the memory cell further includes a second insulating layer 112, the second insulating layer 112 has a layer shape, the second insulating layer 112 includes a first side face and a second side face oppositely arranged in the first direction D1, the first side face of the second insulating layer 112 covers the end face of the second gate 41, the second side face of the second insulating layer 112 directly contacts the first bit line 2, and the second insulating layer 112 isolates the first bit line 2 from the second gate 41. The second insulating layer 112 includes a first end face and a second end face oppositely arranged in the second direction D2, the first end face of the second insulating layer 112 is connected with the first semiconductor layer 81, and the second end face of the second insulating layer 112 is connected with the first isolation layer 104.

[0126] In an example embodiment, the third gate 4-1 is located on the side of the first gate 1-1 close to the second bit line 3, and the third gate 4-1 has a block shape. The second semiconductor layer 82 has a ring shape, surrounds the sidewall of the third gate 4-1, and is isolated from the third gate 4-1 through the third gate insulating layer 53. The side of the second semiconductor layer 82 away from the second bit line 3 directly contacts the second gate 41, and the side of the second semiconductor layer 82 close to the second bit line 3 directly contacts the second bit line 3.

[0127] FIG. 3B is a cross-sectional view I of a semiconductor device provided by an example embodiment, in a direction perpendicular to the substrate. As shown in FIG. 3B, the second word line 4 extends in a direction perpendicular to the substrate, that is, the second word line 4 extends in the third direction D3. For example, the second semiconductor layer 82 can have a sidewall and a top wall, and both the sidewall and the top wall of the second semiconductor layer 82 surround the sidewall of the second word line 4 through the third gate insulating layer 53. Alternatively, the second semiconductor layer 82 can have a sidewall, and the sidewall of the second semiconductor layer 82 surrounds the sidewall of the second word line 4 through the third gate insulating layer 53.

[0128] FIG. 3C is a cross-sectional view II of a semiconductor device provided by an example embodiment, in a direction perpendicular to the substrate. As shown in FIG. 3C, the first semiconductor layers 81 of different layers are disconnected with each other in the direction perpendicular to the substrate 101.

[0129] The semiconductor device provided by the embodiments of the present disclosure has a simple structure, can reduce the steps of the photolithography process in the manufacturing process, and the photolithography areas of different photolithography processes do not overlap, thereby reducing the process difficulty and production cost.

[0130] The semiconductor device provided by the embodiment of the present disclosure can form the first bit line and the second bit line on the same conductive film through one patterning process, thereby reducing the process steps, and reducing the process difficulty and production cost.

[0131] The technical scheme of the embodiment is described below through the manufacturing process of the semiconductor device of the embodiment. The "patterning process" in the embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, and the like, which are mature manufacturing processes in the related art. The "photolithography process" in the embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, and no specific limitation is made herein. In the description of the embodiment, it should be understood that "film" refers to a film layer of a certain material made on a substrate by deposition or coating process. If the "film" does not need patterning process or photolithography process during the entire manufacturing process, the "film" can also be referred to as "layer". If the "film" still needs patterning process or photolithography process during the entire manufacturing process, it is referred to as "film" before the patterning process, and referred to as "layer" after the patterning process. The "layer" after the patterning process or photolithography process includes at least one "pattern".

[0132] In the embodiment, the semiconductor device can include a plurality of memory cell layers arranged along a direction perpendicular to the substrate, and the number of memory cell layers included in the semiconductor device is not limited by the embodiment of the present disclosure. Each memory cell layer can include at least one memory cell, and the number of memory cells included in the memory cell layer is not limited by the embodiment of the present disclosure.

[0133] In an exemplary embodiment, the semiconductor device can be the semiconductor device described in any of the above exemplary embodiments, and the manufacturing process of the semiconductor device can include:

[0134] Step 101, forming a stack structure.

[0135] Forming the stack structure includes forming the first insulating dielectric layer 102 and the second insulating dielectric layer 103 arranged alternately on the substrate 101, and the first insulating dielectric layer 102 and the second insulating dielectric layer 103 arranged alternately form the stack structure, as shown in FIG. 4.

[0136] In an example embodiment, the first insulating medium layer 102 and the second insulating medium layer 103 can be deposited by a deposition method. The deposition process can include at least one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) or evaporation. In an example, a chemical vapor deposition process can be used to form the stack structure.

[0137] In an example embodiment, the material of the first insulating medium layer 102 and the material of the second insulating medium layer 103 can include insulating materials with different etching selectivity. In an example, the material of the first insulating medium layer 102 can include nitride, such as silicon nitride. The material of the second insulating medium layer 103 can include oxide, such as silicon dioxide.

[0138] In an example embodiment, the substrate can be a semiconductor substrate, such as a silicon substrate. The substrate can further include peripheral circuits and the like disposed on the substrate.

[0139] Step 102, forming a first isolation layer.

[0140] Forming the first isolation layer includes: on the basis of the substrate with the aforementioned pattern, forming an isolation groove 21 in the stack structure by an etching (first photolithography) process, the isolation groove 21 extending along a direction perpendicular to the substrate 101, penetrating through the stack structure, and extending to the surface of the substrate; and then, filling the isolation groove 21 with an isolation material by a chemical vapor deposition process to form the first isolation layer 104, as shown in FIG. 5. In an embodiment of the present disclosure, the etching can include at least one of physical etching and chemical etching. The chemical etching includes at least one of dry etching and wet etching.

[0141] In an example embodiment, the material of the first isolation layer 104 can include oxide, such as silicon dioxide.

[0142] Step 103, forming a first hole.

[0143] Forming the first hole includes: on the basis of the substrate with the aforementioned pattern, forming a first hole 22 in the stack structure by an etching (second photolithography) process, the first hole 22 not overlapping with the orthographic projection of the isolation groove 21 on the substrate, the first hole 22 extending along a direction perpendicular to the substrate 101, penetrating through the stack structure, and extending to the surface of the substrate, as shown in FIG. 6.

[0144] In an example embodiment, in a plane parallel to the substrate, the shape of the first hole 22 includes a rectangle, a circle, an ellipse, and the like. The first hole 22 is located on one side of the isolation groove 21 in the second direction D2 and in the region between two adjacent isolation grooves 21 in the second direction D2.

[0145] In an example embodiment, in a plane perpendicular to the substrate, the first hole 22 comprises first vias 221 and second vias 222 arranged alternately. The first vias 221 and the second vias 222 are different regions of the first hole 22.

[0146] The first via 221 is located in the first insulating medium layer 102, penetrating the first insulating medium layer 102, and exposes the sidewall of the first insulating medium layer 102; the second via 222 is located in the second insulating medium layer 103, penetrating the second insulating medium layer 103, and exposes the sidewall of the second insulating medium layer 103; the first via 221 and the second via 222 completely overlap in the orthographic projection on the substrate, and the sidewall of the adjacent first via 221 and the sidewall of the second via 222 are substantially flush.

[0147] Step 104, forming a third via.

[0148] Forming the third via comprises: on the basis of the substrate with the foregoing pattern, by a lateral etching process, etching and removing the part of the first insulating medium layer 102 exposed by the first via 221 along the direction parallel to the substrate, so that the sidewall of the first via extends along the direction parallel to the substrate relative to the sidewall of the second via 222, and a third via 223 is formed, as shown in FIGS. 7A and 7B. For example, the etching process can adopt a wet etching process.

[0149] In an example embodiment, in a plane parallel to the substrate, the shape of the third via 223 comprises a rectangle, a circle or an ellipse, etc. The third via 223 exposes the sidewall of the first isolation layer 104 on both sides of the second direction D2. The orthographic projection of the third via 223 on the substrate covers the orthographic projection of the second via 222 on the substrate, the edge of the orthographic projection of the third via 223 on the substrate exceeds the edge of the orthographic projection of the second via 222 on the substrate, and the edge 222-1 of the second via 222 protrudes relative to the sidewall of the third via 223.

[0150] Step 105, forming a first conductive film.

[0151] Forming the first conductive film comprises: on the basis of the substrate with the foregoing pattern, by an atomic layer deposition process, depositing a layer of the first conductive film 31 on the stack structure, at least part of the first conductive film 31 covers the sidewall of the second via 222 and the upper and lower surfaces of the edge of the second via 222, and the first conductive film 31 is in direct contact with the second insulating medium layer 103 exposed by the second via 222; at least part of the first conductive film 31 covers the sidewall of the third via 223, and is in direct contact with the first insulating medium layer 102 and the first isolation layer 104 exposed by the third via 223, as shown in FIG. 8.

[0152] In an example embodiment, the first conductive film 31 can include polysilicon (Poly).

[0153] Step 106, forming an initial second gate.

[0154] Forming the initial second gate includes: on the basis of the formed substrate of the aforementioned pattern, etching to remove the first conductive film on the sidewall of the second via 222 and the first conductive film on the upper surface and the lower surface of the edge of the second via 222, exposing the sidewall of the second via 222, the upper surface and the lower surface of the edge 222-1 of the second via 222, and the upper surface and the lower surface of the edge 222-1 of the second via 222 exposed are in communication with the third via 223; retaining the first conductive film on the sidewall of the third via 223, forming the initial second gate 411, as shown in FIGS. 9A and 9B.

[0155] In an example embodiment, in the direction perpendicular to the substrate, the initial second gate 411 on the sidewall of the adjacent third via 223 is disconnected from each other. For example, the initial second gate 411 on the sidewall of the adjacent third via 223 is disconnected from each other through the edge 222-1 of the second via 222.

[0156] In an example embodiment, the initial second gate 411 can include a conductive layer such as polysilicon (Poly) or metal, and the initial second gate 411 can form a second gate in a subsequent process, and the second gate is used for storing electric charge.

[0157] Step 107, forming a first gate insulating layer.

[0158] Forming the first gate insulating layer includes: on the basis of the formed substrate of the aforementioned pattern, forming the first gate insulating layer 51 on the initial second gate 411 on the sidewall of the third via 223 by an atomic layer deposition process, as shown in FIGS. 10A and 10B.

[0159] In an example embodiment, in the direction perpendicular to the substrate, the first gate insulating layer 51 on the sidewall of the adjacent third via 223 is disconnected from each other. For example, the first gate insulating layer 51 on the sidewall of the adjacent third via 223 is disconnected from each other through the edge 222-1 of the second via 222.

[0160] In an example embodiment, the material of the first gate insulating layer 51 can include an oxide, such as silicon oxynitride, silicon oxide, etc.

[0161] Step 108, forming a first semiconductor film.

[0162] The forming of the first semiconductor thin film includes: on the basis of the substrate with the pattern formed, a first semiconductor thin film 32 is deposited on the stack structure by an atomic layer deposition process, at least part of the first semiconductor thin film 32 covers the sidewall of the second via hole 222, and the upper surface and the lower surface of the edge 222-1 of the second via hole 222; at least part of the first semiconductor thin film 32 covers the first gate insulating layer 51 corresponding to the sidewall of the third via hole 223, and directly contacts the first gate insulating layer 51, as shown in FIG. 11.

[0163] Step 109, forming a first shielding thin film.

[0164] The forming of the first shielding thin film includes: on the basis of the substrate with the pattern formed, a first shielding thin film 61 is deposited on the stack structure by an atomic layer deposition process, at least part of the first shielding thin film 61 covers the first semiconductor thin film 32 on the sidewall of the second via hole 222, and the upper surface and the lower surface of the edge of the second via hole 222; at least part of the first shielding thin film 61 covers the first semiconductor thin film 32 corresponding to the sidewall of the third via hole 223, as shown in FIG. 12.

[0165] In an exemplary embodiment, the material of the first shielding thin film 61 can include nitride, for example, silicon nitride.

[0166] Step 110, forming a first shielding layer.

[0167] The forming of the first shielding layer includes: on the basis of the substrate with the pattern formed, the first shielding thin film on the sidewall of the second via hole 222 and the upper surface and the lower surface of the edge of the second via hole 222 are etched and removed by an etching process; the first shielding thin film corresponding to the sidewall of the third via hole 223 is reserved to form a first shielding layer 71, as shown in FIGS. 13A and 13B.

[0168] In an exemplary embodiment, in the direction perpendicular to the substrate, the first shielding layer 71 on the sidewall of the adjacent third via hole 223 is disconnected from each other. For example, the first shielding layer 71 on the sidewall of the adjacent third via hole 223 is disconnected from each other through the edge of the second via hole 222.

[0169] In an exemplary embodiment, the material of the first shielding layer 71 can include nitride, for example, silicon nitride.

[0170] Step 111, forming a first semiconductor layer.

[0171] The forming of the first semiconductor layer includes: on the basis of the substrate with the pattern formed, the first semiconductor thin film on the side wall of the second via hole 222 and the upper surface and the lower surface of the edge of the second via hole 222 are etched and removed by an etching process; the first semiconductor thin film corresponding to the side wall of the third via hole 223 is shielded by the first shielding layer 71, so that the first semiconductor thin film 32 corresponding to the side wall of the third via hole 223 is reserved, and the first semiconductor layer 81 is formed to be disconnected with each other, as shown in FIG. 14.

[0172] In an exemplary embodiment, the first semiconductor layer 81 on the side wall of the adjacent third via hole 223 is disconnected with each other in the direction perpendicular to the substrate. For example, the first semiconductor layer 81 on the side wall of the adjacent third via hole 223 is disconnected with each other through the edge of the second via hole 222.

[0173] In an exemplary embodiment, the material of the first semiconductor layer 81 can include polycrystalline silicon (Poly silicon) or metal oxide, and the material of the metal oxide can be indium gallium zinc oxide (IGZO). When the material of the metal oxide is IGZO, the leakage current of the first transistor is small, thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0174] Step 112, removing the first shielding layer.

[0175] The removing of the first shielding layer includes: on the basis of the substrate with the pattern formed, the first shielding layer 71 corresponding to the side wall of the third via hole 223 is etched and removed by an etching process, so that the first semiconductor layer 81 on the side wall of the third via hole 223 is exposed, as shown in FIG. 15A and FIG. 15B.

[0176] Step 113, forming a second conductive thin film and a second shielding thin film.

[0177] The forming of the second conductive film and the second shielding film includes: on the basis of the substrate with the aforementioned pattern, a layer of the second conductive film 33 is first deposited on the stack structure by an atomic layer deposition process, at least part of the second conductive film 33 covers the sidewall of the second via hole 222, and the upper surface and the lower surface of the edge of the second via hole 222; at least part of the second conductive film 33 covers the first semiconductor layer 81 corresponding to the sidewall of the third via hole 223, and directly contacts the first semiconductor layer 81; then, the second shielding film 62 is filled into the first hole 22 by a chemical vapor deposition process, that is, the second shielding film 62 fills the second via hole 222 and the third via hole 223, as shown in FIG. 16.

[0178] In an exemplary embodiment, the material of the second shielding film 62 can include an oxide, for example, silicon oxynitride. The shape of the second shielding film 62 includes a columnar structure extending along a direction perpendicular to the substrate, and the second shielding film 62 fills the second via hole 222 and the third via hole 223.

[0179] Step 114, forming a second hole and a second shielding layer.

[0180] The forming of the second hole and the second shielding layer includes: on the basis of the substrate with the aforementioned pattern, the first hole 22 includes a first region 22-1 and a second region 22-2, and the first region 22-1 and the second region 22-2 are located on opposite sides of the first hole 22 in the first direction D1; the second shielding film of the first region 22-1 is etched and removed by an etching (third photolithography) process, to form a second hole 23, and the second shielding film of the second region 22-2 is retained to form a second shielding layer 72, and the second shielding layer 72 covers the second conductive film 33 of the second region 22-2; the second conductive film 33 of the sidewall of the second via hole 222 in the first region 22-1 is exposed by the second hole 23, and the second shielding film remains in the third via hole 223 in the first region 22-1, as shown in FIGS. 17A and 17B.

[0181] In an exemplary embodiment, the second hole 23 extends along a direction perpendicular to the substrate, penetrates through the stack structure, and extends to the surface of the substrate. The orthographic projection of the second hole 23 on the substrate is located inside the orthographic projection of the first hole 22 on the substrate.

[0182] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the second hole 23 includes a rectangle.

[0183] Step 115, forming a reference electrode.

[0184] The forming of the reference electrode includes: on the basis of the substrate with the aforementioned pattern, first, through a lateral etching process, etching and removing the residual second shielding film in the third via hole 223 of the first region 22-1 and part of the second shielding layer 72 of the second region 22-2 along the direction parallel to the substrate, exposing the second conductive film corresponding to the sidewall of the third via hole 223 and the second conductive film on the upper and lower surfaces of the edge of the second via hole 222; then, through an etching process, etching and removing the second conductive film on the sidewall of the second via hole 222 in the first region 22-1, the second conductive film on the upper and lower surfaces of the edge of the second via hole 222 and the second conductive film corresponding to the sidewall of the third via hole 223; the second conductive film in the second region 22-2 is shielded by the second shielding layer 72, and the second conductive film in the second region 22-2 is retained, so that the retained second conductive film forms the reference electrode 42, as shown in FIG. 18, the reference electrode 42 has two end faces 42-1, and the two end faces 42-1 are spaced apart along the second direction D2.

[0185] In an exemplary embodiment, in the plane perpendicular to the substrate, the reference electrodes 42 of the sidewalls of adjacent third via holes 223 are connected into one body through the reference electrodes 42 of the sidewalls of the second via holes 222 and the upper and lower surfaces of the edges of the second via holes 222, and the connected reference electrodes 42 form a reference signal line.

[0186] In an exemplary embodiment, the material of the reference electrode 42 can include metal.

[0187] Step 116, forming a first insulating film.

[0188] The forming of the first insulating layer includes: on the basis of the substrate with the aforementioned pattern, through an atomic layer deposition process, depositing a layer of first insulating film 91 on the stack structure, at least part of the first insulating film 91 covering the sidewall of the second via hole in the first region 22-1, at least part of the first insulating film 91 covering the upper and lower surfaces of the edge of the second via hole in the first region 22-1; at least part of the first insulating film 91 covers the first semiconductor layer 81 on the sidewall of the third via hole in the first region 22-1; at least part of the first insulating film 91 covers the second shielding layer 72 in the second region 22-2 and the two end faces 42-1 of the reference electrode 42, as shown in FIG. 19.

[0189] Step 117, forming a first insulating layer.

[0190] The forming of the first insulating layer includes: on the basis of the substrate formed with the aforementioned patterns, the first insulating thin film on the side wall of the second via hole in the first region 22-1, the upper and lower surfaces of the edge of the second via hole, the side wall of the third via hole, and the second shielding layer 72 in the second region 22-2 are removed by an etching process; the first insulating thin film on the two end surfaces 42-1 of the reference electrode 42 in the second region 22-2 is reserved, and a first insulating layer 111 is formed, which covers the two end surfaces 42-1 of the reference electrode 42, as shown in FIG. 20.

[0191] In an example embodiment, the material of the first insulating layer 111 can include an oxide, for example, silicon dioxide.

[0192] Step 118, forming a second gate insulating layer and a first gate.

[0193] The forming of the second gate insulating layer and the first gate includes: on the basis of the substrate formed with the aforementioned patterns, a layer of the second gate insulating layer 52 is first deposited on the stack structure by an atomic layer deposition process, at least part of the second gate insulating layer 52 covers the side wall of the second via hole in the first region 22-1, the upper and lower surfaces of the edge of the second via hole, and the first semiconductor layer 81 corresponding to the side wall of the third via hole; at least part of the second gate insulating layer 52 covers the second shielding layer 72 in the second region 22-2 and the first insulating layer 111; then, by a chemical vapor deposition process, the second hole is filled with a conductive material to form a first word line 1, and the region of the first word line 1 opposite to the first semiconductor layer 81 forms a first gate 1-1, as shown in FIGS. 21A and 21B.

[0194] In an example embodiment, the material of the second gate insulating layer 52 can include an oxide, for example, silicon dioxide.

[0195] In an example embodiment, the material of the first gate 1-1 can include a metal.

[0196] Step 119, forming a first trench and a second trench.

[0197] The forming of the first trench and the second trench includes: on the basis of the substrate formed with the aforementioned patterns, a mask layer 10 is first formed on the surface of the stack structure away from the substrate; then, by an etching (fourth photolithography) process, the first trench 121 and the second trench 122 are formed in the stack structure through the shielding of the mask layer 10, the first trench 121 and the second trench 122 are located on the opposite sides of the first hole in the first direction D1, the first trench 121 exposes the side wall of the first insulating dielectric layer 102 corresponding to one side of the first hole, and the second trench 122 exposes the side wall of the first insulating dielectric layer 102 corresponding to the other side of the first hole, as shown in FIGS. 22A and 22B.

[0198] In an example embodiment, in a plane parallel to the substrate, the first trench 121 and the second trench 122 each include a line shape extending along the second direction D2; in a plane perpendicular to the substrate, the first trench 121 and the second trench 122 extend along a direction perpendicular to the substrate, through the stack structure, and to the surface of the substrate.

[0199] Step 120, forming a first lateral trench and a second lateral trench.

[0200] Forming the first lateral trench and the second lateral trench includes: on the basis of the substrate with the foregoing pattern, by a lateral etching process, etching and removing the first insulating medium layer 102 exposed by the first trench 121 to form a first lateral trench 131, the first lateral trench 131 exposing the initial second gate 411; by a lateral wet etching process, etching and removing part of the first insulating medium layer 102 exposed by the second trench 122 to form a second lateral trench 132, as shown in FIGS. 23A and 23B.

[0201] Step 121, exposing a first gate insulating layer.

[0202] Exposing the first gate insulating layer includes: on the basis of the substrate with the foregoing pattern, by an etching process, etching and removing the initial second gate exposed by the first lateral trench 131 to form a second gate 41, and exposing the sidewall of the first gate insulating layer 51 and forming two end faces 41-1 of the second gate 41, as shown in FIGS. 24A and 24B.

[0203] In an example embodiment, the material of the first gate insulating layer can include an oxide, such as silicon dioxide.

[0204] Step 122, forming a second insulating film.

[0205] Forming the second insulating film includes: on the basis of the substrate with the foregoing pattern, by an atomic layer deposition process, depositing a layer of second insulating film 92 on the stack structure, at least part of the second insulating film 92 covering the sidewall, top wall and bottom wall of the first lateral trench 131, covering the two end faces 41-1 of the second gate 41 exposed by the first lateral trench 131 and the first gate insulating layer 51; at least part of the second insulating film 92 covering the sidewall, top wall and bottom wall of the second lateral trench 132, as shown in FIG. 25.

[0206] Step 123, forming a second insulating layer and exposing a first semiconductor layer.

[0207] The forming of the second insulating layer and the exposing of the first semiconductor layer includes: on the basis of the substrate formed with the foregoing pattern, etching and removing part of the second insulating film and part of the first gate insulating layer 51 by an etching process, exposing the side wall of the first semiconductor layer 81, and only retaining the second insulating film on the two end surfaces 41-1 of the second gate 41, the retained second insulating film forming the second insulating layer 112, at this time, the side wall of the first lateral groove 131 includes the side wall of the first semiconductor layer 81 and the second insulating layer 112, as shown in FIG. 26.

[0208] In an exemplary embodiment, the material of the second insulating layer 112 can include an oxide, such as silicon dioxide.

[0209] Step 124, forming a third conductive film.

[0210] The forming of the third conductive film includes: on the basis of the substrate formed with the foregoing pattern, depositing a layer of the third conductive film 34 on the stack structure by an atomic layer deposition process, at least part of the third conductive film 34 covering the side wall, top wall and bottom wall of the first lateral groove 131, covering the second insulating layer 112 and the first semiconductor layer 81 exposed by the first lateral groove 131; and at least part of the third conductive film 34 covering the side wall, top wall and bottom wall of the second lateral groove 132, as shown in FIG. 27.

[0211] In an exemplary embodiment, the material of the third conductive film 34 can include a metal.

[0212] Step 125, forming a first bit line and a second bit line.

[0213] The forming of the first bit line and the second bit line includes: on the basis of the substrate formed with the foregoing pattern, etching and removing the third conductive film by an etching process, retaining the third conductive film on the side wall of the first lateral groove 131 to form the first bit line 2, the first bit line 2 being isolated from the second gate 41 by the second insulating layer 112, and the first bit line 2 being connected to the exposed first semiconductor layer 81; and retaining the third conductive film on the side wall of the second lateral groove 132 to form the second bit line 3, as shown in FIGS. 28A and 28B.

[0214] In an exemplary embodiment, the first bit line 2 and the second bit line 3 can be manufactured by one etching process using the same conductive film.

[0215] In an exemplary embodiment, in a direction perpendicular to the substrate, the first bit line 2 on the side wall of the adjacent first lateral groove 131 is disconnected from each other, and the second bit line 3 on the side wall of the adjacent second lateral groove 132 is disconnected from each other. In a direction parallel to the substrate, the shape of the first bit line 2 includes a linear shape extending along the second direction D2, and the shape of the second bit line 3 includes a linear shape extending along the second direction D2.

[0216] In an exemplary embodiment, the material of the first bit line 2 and the material of the second bit line 3 can include metal.

[0217] Step 126, forming a second isolation layer.

[0218] Forming the second isolation layer includes: on the basis of forming the aforementioned patterned substrate, filling the isolation material in the first groove 121 and the second groove 122 by a chemical vapor deposition process, forming the second isolation layer 105, as shown in FIG. 29.

[0219] Step 127, forming a third hole.

[0220] Forming the third hole includes: on the basis of forming the aforementioned patterned substrate, forming the third hole 24 in the stacked structure by an etching (fifth photolithography) process, the third hole 24 extends along the direction perpendicular to the substrate 101, penetrates through the stacked structure, and extends to the surface of the substrate, the third hole 24 exposes the sidewall of the first insulating medium layer 102, as shown in FIG. 30.

[0221] In an exemplary embodiment, the shape of the third hole 24 in the plane parallel to the substrate includes a rectangle. In the first direction D1, the third hole 24 is located between the first hole 22 and the second bit line 3, and in the second direction D2, the third hole 24 is located between two adjacent first isolation layers 104.

[0222] Step 128, forming a third lateral groove.

[0223] Forming the third lateral groove includes: on the basis of forming the aforementioned patterned substrate, etching and removing the first insulating medium layer 102 exposed by the third hole 24 by a lateral etching process, forming the third lateral groove 133, the third lateral groove 133 extends to the sidewall of the second gate 41 on the first side of the first direction D1, exposing the sidewall of the second gate 41, and the third lateral groove 133 extends to the sidewall of the second bit line 3 on the second side of the first direction D1, exposing the sidewall of the second bit line 3, as shown in FIG. 31.

[0224] Step 129, forming a second semiconductor layer, a third gate insulating layer, and a second word line.

[0225] The forming of the second semiconductor layer, the third gate insulating layer and the second word line comprises: on the basis of forming the aforementioned patterned substrate, first forming the second semiconductor layer 82 on the sidewall and bottom wall of the third hole 24 by atomic layer deposition process, at least part of the second semiconductor layer 82 covering and directly contacting the second gate 41 and the second bit line 3 exposed by the third lateral groove 133; then, forming the third gate insulating layer 53 on the sidewall and bottom wall of the second semiconductor layer 82 by atomic layer deposition process; and then, filling the conductive material in the third hole 24 by chemical vapor deposition process to form the second word line 4, the second word line 4 forming the third gate 4-1 in the region opposite to the second semiconductor layer 82, as shown in FIGS. 3A, 3B, 3C and 3D.

[0226] In an exemplary embodiment, the second semiconductor layer 82 can comprise a metal oxide, and the material of the metal oxide can be Indium Gallium Zinc Oxide (IGZO). When the material of the metal oxide is IGZO, the leakage current of the second transistor is small, thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0227] In an exemplary embodiment, the second semiconductor layer 82 can be a one-piece structure in the direction perpendicular to the substrate. The process steps can be reduced, and the process flow and materials can be saved.

[0228] In an exemplary embodiment, after forming the second semiconductor layer 82, it further comprises removing the second semiconductor layer 82 corresponding to the second insulating medium layer 103, forming the second semiconductor layer 82 spaced apart in the direction perpendicular to the substrate, and then sequentially forming the third gate insulating layer 53 and the second word line 4.

[0229] In an exemplary embodiment, the material of the third gate insulating layer 53 can comprise an oxide, for example, silicon dioxide.

[0230] In an example embodiment, the material of the third gate 4-1 can include metal.

[0231] The manufacturing method of the semiconductor device provided by the embodiments of the present disclosure can reduce the steps of the photolithography process, and the photolithography regions of different photolithography processes do not overlap, thereby reducing the process difficulty and production cost.

[0232] The manufacturing method of the semiconductor device provided by the embodiments of the present disclosure can form the first bit line and the second bit line by using the same conductive thin film through one preparation process, thereby reducing the process steps, and reducing the process difficulty and production cost.

[0233] The embodiments of the present disclosure further provide a manufacturing method of a semiconductor device, comprising:

[0234] Forming first insulating medium layers and second insulating medium layers alternately arranged on a substrate to form a stack structure;

[0235] Forming an isolation groove in the stack structure, and filling an isolation material in the isolation groove to form a first isolation layer;

[0236] Forming a first hole in the stack structure;

[0237] Forming an initial second gate on the sidewall of the first hole;

[0238] Forming a first gate insulating layer on the initial second gate;

[0239] Forming a first semiconductor layer on the first gate insulating layer;

[0240] Forming a second conductive thin film covering the first semiconductor layer, and filling the first hole through a second shielding thin film;

[0241] Etching to remove part of the second shielding thin film in the first hole to form a second hole, the second hole exposes at least part of the second conductive thin film, and the remaining second shielding thin film forms a second shielding layer;

[0242] Etching to remove the second conductive thin film exposed by the second hole, and retaining the second conductive thin film covered by the second shielding layer to form a reference signal line comprising a reference electrode;

[0243] Forming a first gate in the second hole, the first gate is insulated from the reference signal line;

[0244] Forming a first lateral groove and a second lateral groove in the stack structure, the first lateral groove exposes at least part of the initial second gate;

[0245] Etching to remove the exposed initial second gate to form a second gate, and exposing at least part of the first semiconductor layer, and forming a second insulating layer on the end surface of the second gate;

[0246] a first bit line is formed on the inner wall of the first lateral groove, the first bit line is connected with the exposed first semiconductor layer, and the first bit line is isolated from the second gate by the second insulating layer; and a second bit line is formed on the inner wall of the second lateral groove;

[0247] a third hole is formed in the stack structure, the third hole exposes at least part of the second gate and at least part of the second bit line;

[0248] a second semiconductor layer and a third gate are sequentially formed on the inner wall of the third hole, the second semiconductor layer is connected with the exposed second gate and second bit line respectively, and the third gate fills the third hole.

[0249] In an exemplary embodiment, an isolation groove is formed in the stack structure by a first photolithography process;

[0250] a first hole is formed in the stack structure by a second photolithography process;

[0251] a part of the second shielding film in the first hole is etched and removed by a third photolithography process;

[0252] a first trench and a second trench are formed in the stack structure by a fourth photolithography process;

[0253] a third hole is formed in the stack structure by a fifth photolithography process.

[0254] In an exemplary embodiment, the forming of the initial second gate on the sidewall of the first hole includes:

[0255] The first hole includes first vias and second vias arranged alternately, the first vias are located in the first insulating dielectric layer and expose the sidewall of the first insulating dielectric layer, and the second vias are located in the second insulating dielectric layer and expose the sidewall of the second insulating dielectric layer;

[0256] a third via is formed by a lateral etching process, the first insulating dielectric layer exposed by the first via is etched and removed along a direction parallel to the substrate, and the edge of the second via protrudes relative to the sidewall of the third via;

[0257] a first conductive film is deposited on the stack structure by a deposition process, at least part of the first conductive film covers the sidewall of the second via, the upper surface and the lower surface of the edge of the second via, and at least part of the first conductive film covers the sidewall of the third via;

[0258] etching and removing the first conductive film on the sidewall of the second via and the first conductive film on the upper surface and the lower surface of the edge of the second via; and retaining the first conductive film on the sidewall of the third via to form an initial second gate.

[0259] In an exemplary embodiment, the forming of the first semiconductor layer on the first gate insulating layer comprises:

[0260] depositing a first semiconductor film on the stack structure by a deposition process, at least part of the first semiconductor film covering the sidewall of the second via and the upper surface and the lower surface of the edge of the second via; and at least part of the first semiconductor film covering the first gate insulating layer corresponding to the sidewall of the third via.

[0261] depositing a first shielding film on the stack structure by a deposition process, at least part of the first shielding film covering the first semiconductor film on the sidewall of the second via and the upper surface and the lower surface of the edge of the second via; and at least part of the first shielding film covering the first semiconductor film corresponding to the sidewall of the third via.

[0262] etching and removing the first shielding film on the sidewall of the second via and the upper surface and the lower surface of the edge of the second via by an etching process; and retaining the first shielding film corresponding to the sidewall of the third via to form a first shielding layer.

[0263] etching and removing the first semiconductor film on the sidewall of the second via and the upper surface and the lower surface of the edge of the second via by an etching process; and retaining the first semiconductor film corresponding to the sidewall of the third via by the first shielding layer, so as to form a first semiconductor layer.

[0264] In an exemplary embodiment, the etching and removing part of the second shielding film in the first hole to form a second hole comprises:

[0265] The first hole comprises a first region and a second region. The second shielding film in the first region is etched and removed by an etching process to form a second hole. The second shielding film in the second region is retained to form a second shielding layer. The second hole exposes the second conductive film on the sidewall of the second via in the first region. The second shielding film remains in the third via in the first region.

[0266] In an exemplary embodiment, the etching and removing the second conductive film exposed by the second hole, and retaining the second conductive film covered by the second shielding layer to form a reference signal line comprising a reference electrode comprises:

[0267] The second shielding film remaining in the third via of the first region and part of the second shielding layer of the second region are removed by a lateral etching process along a direction parallel to the substrate, exposing the second conductive film corresponding to the sidewall of the third via and the second conductive film on the upper and lower surfaces of the edge of the second via;

[0268] The second conductive film on the sidewall of the second via in the first region, the second conductive film on the upper and lower surfaces of the edge of the second via and the second conductive film corresponding to the sidewall of the third via are removed by an etching process; the second conductive film in the second region is shielded by the second shielding layer, and the second conductive film in the second region is retained, forming a reference signal line containing a reference electrode.

[0269] In an exemplary embodiment, the forming of the first gate in the second hole includes:

[0270] The first insulating film is deposited on the stack structure by a deposition process, at least part of the first insulating film covering the sidewall of the second via in the first region, at least part of the first insulating film covering the upper and lower surfaces of the edge of the second via in the first region; at least part of the first insulating film covering the first semiconductor layer on the sidewall of the third via in the first region; at least part of the first insulating film covering the second shielding layer and the two end faces of the reference electrode in the second region;

[0271] The first insulating film on the sidewall of the second via in the first region, the upper and lower surfaces of the edge of the second via, the sidewall of the third via and the second shielding layer in the second region are removed by an etching process; the first insulating film on the two end faces of the reference electrode in the second region is retained, forming a first insulating layer;

[0272] The second gate insulating layer is first deposited on the stack structure by a deposition process, at least part of the second gate insulating layer covering the sidewall of the second via in the first region, the upper and lower surfaces of the edge of the second via, the first semiconductor layer corresponding to the sidewall of the third via in the first region; at least part of the second gate insulating layer covering the second shielding layer and the first insulating layer in the second region;

[0273] The second hole is filled with conductive material by a deposition process to form a first word line, and the region opposite to the first semiconductor layer forms a first gate.

[0274] In an exemplary embodiment, the forming of the first lateral slot and the second lateral slot in the stack structure, and the first lateral slot exposing at least part of the initial second gate includes:

[0275] A mask layer is formed on the surface of the stack structure away from the substrate side;

[0276] The first trench and the second trench are formed in the stack structure by shielding through a mask layer, the first trench exposes a sidewall of the first insulating medium layer corresponding to one side of the first hole, and the second trench exposes a sidewall of the first insulating medium layer corresponding to the other side of the first hole;

[0277] The first insulating medium layer exposed by the first trench is etched and removed through a lateral etching process to form a first lateral groove, and the first lateral groove exposes the initial second gate; and the first insulating medium layer exposed by the second trench is etched and removed through a lateral etching process to form a second lateral groove.

[0278] In an exemplary embodiment, the exposed initial second gate is etched and removed to form a second gate; at least part of the first semiconductor layer is exposed, and a second insulating layer is formed on the end surface of the second gate, comprising:

[0279] The initial second gate exposed by the first lateral groove is etched and removed through an etching process to expose the sidewall of the first gate insulating layer and form the end surface of the second gate;

[0280] A second insulating film is deposited on the stack structure through a deposition process, at least part of the second insulating film covers the end surface of the second gate exposed by the first lateral groove and the first gate insulating layer; at least part of the second insulating film covers the sidewall, top wall and bottom wall of the second lateral groove;

[0281] Part of the second insulating film and part of the first gate insulating layer are etched and removed through an etching process to expose the sidewall of the first semiconductor layer, only the second insulating film on the end surface of the second gate is reserved, and the reserved second insulating film forms a second insulating layer.

[0282] In an exemplary embodiment, the first bit line is formed on the inner wall of the first lateral groove, and the second bit line is formed on the inner wall of the second lateral groove, comprising:

[0283] A third conductive film is deposited on the stack structure through a deposition process, at least part of the third conductive film covers the second insulating layer and the first semiconductor layer exposed by the first lateral groove; at least part of the third conductive film covers the sidewall, top wall and bottom wall of the second lateral groove;

[0284] The third conductive film is etched and removed, the third conductive film on the sidewall of the first lateral groove is reserved to form a first bit line, and the third conductive film on the sidewall of the second lateral groove is reserved to form a second bit line;

[0285] An isolation material is filled in the first trench and the second trench through a deposition process to form a second isolation layer.

[0286] In an exemplary embodiment, the first bit line and the second bit line are formed on the same conductive film through one patterning process.

[0287] The embodiments of the present disclosure also provide an electronic device comprising the semiconductor device of any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0288] Although the embodiments of the present disclosure are disclosed as described above, the content described is merely an embodiment adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. It should be noted that the above embodiments or examples are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the specific embodiments and descriptions shown and described herein. Various modifications, replacements, or omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A semiconductor device comprising: A plurality of memory cells provided on a substrate, and a first word line, a second word line, a first bit line, and a second bit line; The memory cell includes a first transistor and a second transistor; The first transistor is a double-gate structure, and includes a first gate, a first semiconductor layer, a second gate, and a reference electrode; The first gate is connected to the first word line, and is disposed opposite the reference electrode with insulation therebetween, forming a columnar structure; The first bit line is disposed on a side of the first gate away from the reference electrode; The first semiconductor layer is disposed around a sidewall of the columnar structure, with an inner surface of at least a portion of the first semiconductor layer in direct contact with the reference electrode, and an outer surface of at least a portion of the first semiconductor layer in contact with the first bit line; The second gate surrounds a portion of an outer surface of the first semiconductor layer, and is insulated from both the first semiconductor layer and the first bit line; The second transistor includes a third gate and a second semiconductor layer, and the second semiconductor layer surrounds a sidewall of the third gate with insulation therebetween, with at least a portion of the second semiconductor layer connected to the second gate, and at least a portion of the second semiconductor layer connected to the second bit line.

2. The semiconductor device according to claim 1, further comprising a reference signal line extending in a direction perpendicular to the substrate, the reference electrode being a portion of the reference signal line.

3. The semiconductor device of claim 1, wherein, The reference electrode has a U-shape in a cross section parallel to the substrate, and a U-shaped opening of the reference electrode faces the first bit line.

4. The semiconductor device according to claim 3, further comprising an insulating layer having a shape including a ring shape, the insulating layer surrounding a sidewall of the first gate, with at least a portion of the insulating layer disposed between the first gate and the reference electrode, and at least a portion of the insulating layer disposed between the first gate and the first semiconductor layer.

5. The semiconductor device of claim 4, wherein, The insulating layer includes a shielding layer filling the U-shaped opening of the reference electrode, and a first insulating layer covering both end surfaces of the reference electrode facing the first gate.

6. The semiconductor device of claim 5, wherein, The insulating layer further includes a second gate insulating layer surrounding a sidewall of the first gate, the second gate insulating layer being in contact with the sidewall of the first gate, with at least a portion of the second gate insulating layer disposed between the first gate and the shielding layer, at least a portion of the second gate insulating layer disposed between the first gate and the first insulating layer, and at least a portion of the second gate insulating layer disposed between the first gate and the first semiconductor layer.

7. The semiconductor device of claim 1, wherein, The first semiconductor layer has a shape including a ring shape.

8. The semiconductor device according to claim 1, further comprising a first gate insulating layer, at least a portion of the first gate insulating layer being disposed between the first semiconductor layer and the second gate.

9. The semiconductor device of claim 8, wherein, The first gate insulating layer is U-shaped in a cross section parallel to the substrate direction, and the U-shaped opening of the first gate insulating layer faces the first bit line and is in contact with the first bit line; the second gate is U-shaped in a cross section parallel to the substrate direction, and the U-shaped opening of the second gate faces the first bit line.

10. The semiconductor device of claim 9, wherein, A second insulating layer is arranged on the end surface of the first gate insulating layer facing the first bit line, and the second insulating layer separates the second gate from the first bit line.

11. The semiconductor device of claim 1, wherein, The shape of the second semiconductor layer comprises a ring shape.

12. The semiconductor device of claim 1, wherein, The plurality of memory cells are stacked in a direction perpendicular to the substrate, and the first semiconductor layers of adjacent memory cells in the direction perpendicular to the substrate are disconnected from each other.

13. The semiconductor device of claim 1, wherein, The plurality of memory cells are stacked in a direction perpendicular to the substrate, and the second gates of adjacent memory cells in the direction perpendicular to the substrate are disconnected from each other.

14. A semiconductor device manufacturing method, comprising: forming first insulating medium layers and second insulating medium layers arranged alternately on a substrate to form a stack structure; forming an isolation groove in the stack structure, and filling an isolation material in the isolation groove to form a first isolation layer; forming a first hole in the stack structure; forming an initial second gate on the sidewall of the first hole; forming a first gate insulating layer on the initial second gate; forming a first semiconductor layer on the first gate insulating layer; forming a second conductive thin film covering the first semiconductor layer, and filling the first hole with a second shielding thin film; etching to remove part of the second shielding thin film in the first hole to form a second hole, the second hole exposes at least part of the second conductive thin film, and the remaining second shielding thin film forms a second shielding layer; etching to remove the second conductive thin film exposed by the second hole, and the second conductive thin film covered by the second shielding layer forms a reference signal line containing a reference electrode; forming a first gate in the second hole, the first gate is insulated from the reference signal line; forming a first lateral groove and a second lateral groove in the stack structure, the first lateral groove exposes at least part of the initial second gate; etching to remove the exposed initial second gate to form a second gate; at least part of the first semiconductor layer is exposed, and a second insulating layer is formed on the end surface of the second gate; forming a first bit line on the inner wall of the first lateral groove, the first bit line is connected to the exposed first semiconductor layer, and the first bit line is separated from the second gate by the second insulating layer; a second bit line is formed on the inner wall of the second lateral groove; forming a third hole in the stack structure, the third hole exposes at least part of the second gate and at least part of the second bit line; forming a second semiconductor layer and a third gate in sequence on the inner wall of the third hole, the second semiconductor layer is connected to the exposed second gate and second bit line respectively, and the third gate fills the third hole.

15. The semiconductor device manufacturing method according to claim 14, wherein: the isolation groove is formed in the stack structure by a first-time photolithography process; the first hole is formed in the stack structure by a second-time photolithography process; forming a second hole in the first hole by etching away part of the second blocking film through a third photoetching process; forming a first trench and a second trench in the stack structure through a fourth photoetching process; forming a third hole in the stack structure through a fifth photoetching process.

16. The method of manufacturing a semiconductor device according to Claim 14, wherein forming an initial second gate on the sidewall of the first hole includes: the first hole includes first vias and second vias arranged alternately, the first vias are located in the first insulating medium layer and expose the sidewall of the first insulating medium layer, and the second vias are located in the second insulating medium layer and expose the sidewall of the second insulating medium layer; forming a third via by etching away part of the first insulating medium layer exposed by the first via in a direction parallel to the substrate through a lateral etching process, and the edge of the second via protrudes relative to the sidewall of the third via; depositing a first conductive film on the stack structure through a deposition process, at least part of the first conductive film covers the sidewall of the second via, the upper surface and the lower surface of the edge of the second via, and at least part of the first conductive film covers the sidewall of the third via; etching away the first conductive film on the sidewall of the second via and the first conductive film on the upper surface and the lower surface of the edge of the second via, and retaining the first conductive film on the sidewall of the third via to form an initial second gate.

17. The method of manufacturing a semiconductor device according to Claim 16, wherein forming a first semiconductor layer on the first gate insulating layer includes: depositing a first semiconductor film on the stack structure through a deposition process, at least part of the first semiconductor film covers the sidewall of the second via, the upper surface and the lower surface of the edge of the second via, and at least part of the first semiconductor film covers the first gate insulating layer corresponding to the sidewall of the third via; depositing a first blocking film on the stack structure through a deposition process, at least part of the first blocking film covers the first semiconductor film on the sidewall of the second via, the upper surface and the lower surface of the edge of the second via, and at least part of the first blocking film covers the first semiconductor film corresponding to the sidewall of the third via; etching away the first blocking film on the sidewall of the second via and the upper surface and the lower surface of the edge of the second via through an etching process, and retaining the first blocking film corresponding to the sidewall of the third via to form a first blocking layer; etching away the first semiconductor film on the sidewall of the second via and the upper surface and the lower surface of the edge of the second via through an etching process, and shielding the first semiconductor film corresponding to the sidewall of the third via by the first blocking layer to retain the first semiconductor film corresponding to the sidewall of the third via to form a first semiconductor layer.

18. The method of manufacturing a semiconductor device according to Claim 17, wherein etching away part of the second blocking film in the first hole to form a second hole includes: the first hole includes a first region and a second region, etching away the second blocking film in the first region to form a second hole through an etching process, retaining the second blocking film in the second region, the retained second blocking film in the second region forms a second blocking layer, the second hole exposes the second conductive film on the sidewall of the second via in the first region, and the second blocking film remains in the third via in the first region.

19. The method of manufacturing a semiconductor device according to Claim 18, wherein The etching removes the second conductive film exposed by the second hole, retains the second conductive film covered by the second shielding layer, and forms a reference signal line containing a reference electrode, comprising: The second shielding film remaining in the third via in the first region and part of the second shielding layer in the second region are removed by a lateral etching process along a direction parallel to the substrate, the second conductive film corresponding to the sidewall of the third via and the second conductive film on the upper and lower surfaces of the edge of the second via are exposed; The second conductive film on the sidewall of the second via in the first region, the second conductive film on the upper and lower surfaces of the edge of the second via and the second conductive film corresponding to the sidewall of the third via are removed by an etching process; the second conductive film in the second region is shielded by the second shielding layer, and the second conductive film in the second region is retained to form a reference signal line containing a reference electrode.

20. The method of manufacturing a semiconductor device according to Claim 19, wherein The first gate is formed in the second hole, comprising: A first insulating film is deposited on the stack structure by a deposition process, at least part of the first insulating film covers the sidewall of the second via in the first region, at least part of the first insulating film covers the upper and lower surfaces of the edge of the second via in the first region; at least part of the first insulating film covers the first semiconductor layer on the sidewall of the third via in the first region; at least part of the first insulating film covers the second shielding layer and the two end faces of the reference electrode in the second region; The first insulating film on the sidewall of the second via in the first region, the upper and lower surfaces of the edge of the second via, the sidewall of the third via and the second shielding layer in the second region is removed by an etching process; the first insulating film on the two end faces of the reference electrode in the second region is retained to form a first insulating layer; A second gate insulating layer is first deposited on the stack structure by a deposition process, at least part of the second gate insulating layer covers the sidewall of the second via in the first region, the upper and lower surfaces of the edge of the second via, the first semiconductor layer corresponding to the sidewall of the third via; at least part of the second gate insulating layer covers the second shielding layer and the first insulating layer in the second region; The second hole is filled with conductive material by a deposition process to form a first word line, and the region opposite to the first semiconductor layer forms a first gate.

21. The method of manufacturing a semiconductor device according to Claim 20, wherein The first lateral groove and the second lateral groove are formed in the stack structure, and the first lateral groove exposes at least part of the initial second gate, comprising: A mask layer is formed on the surface of the stack structure away from the substrate; The first groove and the second groove are formed in the stack structure by shielding through the mask layer, the first groove exposes the sidewall of the first insulating medium layer corresponding to one side of the first hole, and the second groove exposes the sidewall of the first insulating medium layer corresponding to the other side of the first hole; The first insulating medium layer exposed by the first groove is removed by a lateral etching process to form a first lateral groove, and the first lateral groove exposes the initial second gate; The first insulating medium layer exposed by the second groove is partially removed by a lateral etching process to form a second lateral groove.

22. The method of manufacturing a semiconductor device according to Claim 21, wherein The exposed initial second gate is removed by etching to form a second gate; exposing at least part of the first semiconductor layer, and forming a second insulating layer on the end surface of the second gate, comprising: by an etching process, etching and removing the initial second gate exposed by the first lateral trench, exposing the sidewall of the first gate insulating layer, and forming the end surface of the second gate; by a deposition process, depositing a second insulating film on the stack structure, at least part of the second insulating film covering the second gate end surface exposed by the first lateral trench and the first gate insulating layer; at least part of the second insulating film covering the sidewall, top wall and bottom wall of the second lateral trench; by an etching process, etching and removing part of the second insulating film and part of the first gate insulating layer, exposing the sidewall of the first semiconductor layer, retaining only the second insulating film on the end surface of the second gate, the retained second insulating film forming the second insulating layer.

23. The method of manufacturing a semiconductor device according to Claim 22, wherein the first bit line formed on the inner wall of the first lateral trench, and the second bit line formed on the inner wall of the second lateral trench, comprising: by a deposition process, depositing a third conductive film on the stack structure, at least part of the third conductive film covering the second insulating layer and the first semiconductor layer exposed by the first lateral trench; at least part of the third conductive film covering the sidewall, top wall and bottom wall of the second lateral trench; etching and removing the third conductive film, retaining the third conductive film on the sidewall of the first lateral trench to form the first bit line; and retaining the third conductive film on the sidewall of the second lateral trench to form the second bit line; by a deposition process, filling the isolation material in the first trench and the second trench to form a second isolation layer.

24. The method of manufacturing a semiconductor device according to Claim 14, wherein the first bit line and the second bit line are formed on the same conductive film by one patterning process.

25. An electronic device comprising the semiconductor device according to any one of claims 1 to 13.

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