Shift register, driving circuit, driving method, and display device

Abstract

A shift register, a driving circuit, a driving method, and a display device, relating to the technical field of display. The shift register comprises: a first shift register circuit configured to output a first scanning signal by means of a first output end under the control of a first power supply voltage of a first power supply, a second power supply voltage of a second power supply, and a first input signal from a first input end; a second shift register circuit configured to output a shift signal by means of a shift output end under the control of a third power supply voltage of a third power supply, a fourth power supply voltage of a fourth power supply, and a second input signal from a second output end, and to output a second scanning signal by means of the second output end under the control of the third power supply voltage and the second power supply voltage; and a third shift register circuit configured to output a third scanning signal by means of a third output end under the control of the first power supply voltage, the fourth power supply voltage, and a third input signal from the third output end.

Description

Shift register, driving circuit, driving method and display device

[0001] The present application claims priority to Chinese Patent Application No. 202410520079.4, filed on April 28, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a shift register, a driving circuit, a driving method and a display device. BACKGROUND

[0003] With the rapid development of the display industry, the requirement for low power consumption of display panels is also increasingly high. For example, the driving power consumption of a display panel can be reduced by reducing the operating voltage of a pixel circuit.

[0004] However, in order to ensure that the display panel can realize a high-brightness display mode at a lower operating voltage, it is necessary to provide the pixel circuit with driving signals having multiple voltages. This also leads to a higher requirement for the voltage of the driving signal output by the shift register. SUMMARY

[0005] The present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0006] According to a first aspect, the present disclosure provides a shift register, comprising: a first shift register circuit, electrically connected with a first power supply, a second power supply, a first input terminal and a first output terminal, the first shift register circuit being configured to output a first scan signal through the first output terminal under the control of a first power supply voltage of the first power supply, a second power supply voltage of the second power supply and a first input signal from the first input terminal; a second shift register circuit, electrically connected with the second power supply, a third power supply, a fourth power supply, a shift output terminal, a second input terminal and a second output terminal, the second shift register circuit being configured to output a shift signal through the shift output terminal under the control of a third power supply voltage of the third power supply, a fourth power supply voltage of the fourth power supply and a second input signal from the second output terminal, and output a second scan signal through the second output terminal under the control of the third power supply voltage and the second power supply voltage; and a third shift register circuit, electrically connected with the first power supply, the fourth power supply, a third input terminal and a third output terminal, the third shift register circuit being configured to output a third scan signal through the third output terminal under the control of the first power supply voltage, the fourth power supply voltage and a third input signal from the third output terminal.

[0007] For example, the first shift register circuit is further configured to output the first scan signal under the control of a first clock signal from a first clock terminal; wherein a first level of the first clock signal is equal to the first power supply voltage, and a second level of the first clock signal is equal to the second power supply voltage.

[0008] For example, the second shift register circuit is further configured to output the second scan signal under control of a second clock signal from a second clock terminal, wherein a first level of the second clock signal is equal to the third power voltage and a second level of the second clock signal is equal to the fourth power voltage.

[0009] For example, the third shift register circuit is further configured to output the third scan signal under control of a third clock signal from a third clock terminal, wherein a first level of the third clock signal is equal to the third power voltage and a second level of the third clock signal is equal to the fourth power voltage.

[0010] For example, the third shift register circuit is further configured to output the third scan signal under control of a third clock signal from a third clock terminal, wherein a first level of the third clock signal is equal to the third power voltage and a second level of the third clock signal is equal to the second power voltage.

[0011] For example, the second shift register circuit comprises a control unit configured to output a shift signal under control of the third power voltage, the fourth power voltage and a second input signal, and control potentials of the first node and the second node, and an output unit configured to output the second scan signal under control of the second power voltage, the third power voltage, the potential of the first node and the potential of the second node.

[0012] For example, the shift register further comprises a fourth shift register circuit electrically connected with the first power supply, the second power supply, a fourth input terminal and a fourth output terminal, the fourth shift register circuit being configured to output a fourth scan signal through the fourth output terminal under control of the first power voltage, the second power voltage and a fourth input signal from the fourth input terminal.

[0013] For example, the shift register further comprises a fifth shift register circuit electrically connected with the first power supply, the second power supply, a fifth input terminal and a fifth output terminal, the fifth shift register circuit being configured to output a light-emitting control signal through the fifth output terminal under control of the first power voltage, the second power voltage and a fifth input signal from the fifth input terminal.

[0014] For example, the fourth power voltage is less than the second power voltage.

[0015] According to a second aspect, the present disclosure provides a driving circuit, comprising: a first gate driving circuit comprising M first shift register circuits connected in cascade, a first input terminal of an mth first shift register circuit being electrically connected with a first output terminal of an (m-1)th first shift register circuit, 1 < m ≤ M, m and M being positive integers greater than 1; a second gate driving circuit comprising M second shift register circuits connected in cascade, a second input terminal of an mth second shift register circuit being electrically connected with a shift output terminal of an (m-1)th second shift register circuit; and a third gate driving circuit comprising M third shift register circuits connected in cascade, a third input terminal of an mth third shift register circuit being electrically connected with a third output terminal of an (m-1)th third shift register circuit.

[0016] For example, the driving circuit further comprises: a fourth gate driving circuit comprising M fourth shift register circuits connected in cascade, a fourth input terminal of an mth fourth shift register circuit being electrically connected with a fourth output terminal of an (m-1)th fourth shift register circuit; and a light-emitting control driving circuit comprising M fifth shift register circuits connected in cascade, a fifth input terminal of an mth fifth shift register circuit being electrically connected with a fifth output terminal of an (m-1)th fifth shift register circuit.

[0017] According to a third aspect, the present disclosure provides a display device, comprising: a display panel; and a driving circuit as provided in the embodiments of the present disclosure; wherein the display panel comprises a plurality of sub-pixel units, and the sub-pixel units are electrically connected with a first output terminal, a second output terminal and a third output terminal of the driving circuit.

[0018] According to a fourth aspect, the present disclosure provides a driving method applied to a shift register as provided in the embodiments of the present disclosure, comprising: a driving method applied to a shift register as provided in the embodiments of the present disclosure, comprising: outputting a first scanning signal under the control of a first power voltage, a second power voltage and a first input signal; outputting a shift signal under the control of a third power voltage, a fourth power voltage and a second input signal; outputting a second scanning signal under the control of the second power voltage and the third power voltage; and outputting a third scanning signal under the control of the first power voltage, the fourth power voltage and a third input signal.

[0019] For example, outputting the third scanning signal under the control of the first power voltage and the fourth power voltage comprises: in a first display mode, controlling the fourth power voltage to be a first voltage, so as to output the third scanning signal under the control of the first power voltage and the fourth power voltage; and in a second display mode, controlling the fourth power voltage to be a second voltage, so as to output the third scanning signal under the control of the first power voltage and the fourth power voltage; wherein the first voltage is less than the second voltage. Attached Figure Description

[0020] Figure 1A is a schematic diagram of an example pixel circuit;

[0021] Figure 1B is a signal timing diagram of an example pixel circuit;

[0022] Figure 2 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0023] Figure 3 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0024] Figure 4 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0025] Figure 5 is a schematic diagram of the structure of the second shift register circuit according to an embodiment of the present disclosure;

[0026] Figure 6A is a schematic diagram of the structure of a second shift register circuit according to another embodiment of the present disclosure;

[0027] Figure 6B is a signal timing diagram of a second shift register circuit according to an embodiment of the present disclosure;

[0028] Figure 6C is a signal timing diagram of a second shift register circuit according to another embodiment of the present disclosure;

[0029] Figure 7 is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0030] Figure 8A is a schematic diagram of the structure of a first gate driving circuit according to an embodiment of the present disclosure;

[0031] Figure 8B is a schematic diagram of the structure of a second gate driving circuit according to an embodiment of the present disclosure;

[0032] Figure 8C is a schematic diagram of the structure of a third gate driving circuit according to an embodiment of the present disclosure;

[0033] Figure 9 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure; and

[0034] Figure 10 is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0035] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be used to clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals.

[0036] In the following description, some specific embodiments are used only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it can cause confusion to the understanding of the present disclosure, the conventional structure or configuration will be omitted. It should be noted that the shape and size of each component in the drawings do not reflect the true size and ratio, but only illustrate the content of the embodiments of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by a person of ordinary skill in the art. The "first", "second" and similar words used in the embodiments of the present disclosure do not represent any order, number or importance, but are only used to distinguish different components.

[0038] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" can mean that two components are directly connected, or that two components are connected via one or more other components. In addition, the two components can be connected or coupled by wired or wireless means.

[0039] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain can be interchangeable. In the embodiments of the present disclosure, according to its function, the gate can be called the control electrode, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0040] In addition, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish the amplitudes of the two power supply voltages. For example, the following is described by taking "first power supply voltage" as a relatively high voltage and "second power supply voltage" as a relatively low voltage. Those skilled in the art can understand that the present disclosure is not limited thereto.

[0041] It should be noted that in the description of the embodiments of the present disclosure, the symbol OUT can represent both an output signal and a level of the output signal. Similarly, the symbol INPUT can represent both an input signal and a level of the input signal, the symbol CLK can represent both a clock terminal and a voltage of a clock signal, and VGH and VGL can represent both a power supply terminal and a power supply voltage provided by the power supply terminal. The same applies to the following embodiments, and similar parts will not be described again.

[0042] FIG. 1A is a structural schematic diagram of an example pixel circuit, and FIG. 1B is a signal timing diagram of the example pixel circuit. FIG. 1A shows a pixel circuit of a sub-pixel in a pixel array.

[0043] As shown in FIG. 1A, the pixel circuit 100 of the sub-pixel includes transistors M1 to M8, a capacitor CST, and a light emitting element OLED. The transistors M1, M3 to M8 are P-type transistors, and the transistor M2 is an N-type transistor.

[0044] The gate of the transistor M1 is controlled by a first reset signal Preset, the gate of the transistor M2 is controlled by a first gate drive signal Ngate, the gate of the transistor M4 is controlled by a second gate drive signal Pgate, the gates of the transistors M5 and M6 are controlled by an emission control signal EM, the gates of the transistors M7 and M8 are controlled by a second reset signal PresetH, and the transistor M3 is a drive transistor.

[0045] The pixel circuit shown in FIG. 1A is only illustrative, and the present disclosure does not limit the circuit structure of the pixel circuit.

[0046] In combination with FIG. 1B and FIG. 1A, the working process of the pixel circuit 100 is schematically described.

[0047] When the first gate drive signal Ngate is at a high level and the first reset signal Preset is at a low level, the transistors M1 and M2 are turned on. The first initialization signal Vinit1 is written to the first node Q1 through the transistors M1 and M2, and the gate voltage of the transistor M3 is initialized and the capacitor CST is charged.

[0048] When the second gate driving signal Pgate is low and the first gate driving signal Ngate is high, the transistor M4 and the transistor M2 are turned on. The capacitor CST keeps the potential of the first node Q1 as a low potential, and the transistor M3 is turned on. The data signal Data is written to the first node Q1 through the transistor M4, the transistor M3 and the transistor M2, the gate of the transistor M3 is initialized, and the capacitor CST is charged, at this time, the potential of the first node Q1 is raised. The potential of the second node Q2 keeps as the potential amplitude Vdata of the data signal Data, and according to the characteristics of the transistor M3, when the potential of the first node Q1 increases to Vdata+Vth, the charging process is completed. At this time, the potentials of the first node Q1 and the third node Q3 are both Vdata+Vth. The voltage information of the data signal Vdata and the threshold voltage Vth is stored in the storage capacitor CST for subsequent control of the gate of the transistor M3. It should be noted that Vth represents the threshold voltage of the transistor M3.

[0049] When the second reset signal PresetH is low, the transistor M7 and the transistor M8 are turned on. The first initialization signal Vinit2 is written to the fourth node Q4 through the transistor M7, so as to initialize the anode voltage of the light emitting element OLED as Vinit2. The reference voltage signal Vref is written to the third node Q3 through the transistor M8 and the transistor M3.

[0050] When the light emitting control signal EM is low, the transistor M5 and the transistor M6 are turned on, and the driving current is applied to the light emitting element OLED along the light emitting path from the power supply VDD to the light emitting element OLED via the transistor M5, the transistor M3 and the transistor M6, so as to make the light emitting element OLED emit light. At this time, the second node Q2 is connected with the power supply VDD, and the power supply voltage of the power supply VDD is applied to the second node Q2.

[0051] The first reset signal Preset, the first gate driving signal Ngate, the second gate driving signal Pgate, the light emitting control signal EM and the second reset signal PresetH can be provided by different driving circuits. For example, the first reset signal Preset, the first gate driving signal Ngate, the second gate driving signal Pgate and the second reset signal PresetH can be provided by a gate driving (Gate On Array, GOA) circuit, and the light emitting control signal EM is provided by an emission control signal driving (Emission On Array, EOA) circuit. For example, the GOA circuit can include a plurality of cascaded GOA units, and each GOA unit provides a driving signal to a row of pixel units in the pixel array. Similarly, the EOA circuit includes a plurality of cascaded EOA units, and each EOA unit provides a light emitting control signal EM to a row of pixel units in the pixel array.

[0052] For example, the pixel circuit 100 can be a pixel circuit of a sub-pixel in a tandem organic light-emitting diode (OLED) display panel (PNL). The tandem OLED device has high current efficiency, and can reduce the display power consumption of the PNL. In order to further reduce the driving power consumption, the operating power supply voltage VDD of the operating power supply VDD can be reduced. For example, the operating power supply voltage VDD is reduced from 4.6 V to 2.8 V.

[0053] For example, the display mode of the PNL includes a normal mode and a high brightness mode (HBM). For example, the display brightness of the normal mode can be less than or equal to 500 nits, and the display brightness of the high brightness mode can be greater than or equal to 2000 nits.

[0054] In the pixel circuit of the tandem OLED with the power supply voltage VDD = 2.8 V, when the display brightness is greater than 2000 nits, based on the characteristics of the large voltage across of the tandem device itself and the voltage drop of the power supply voltage VDD / VSS of the PNL in the high brightness mode, in order to ensure the quality uniformity of the high brightness display and ensure that the driving transistor (transistor M3) works in the saturation region, the power supply voltage VSS needs to be less than or equal to -9 V. For example, when the display brightness is 2000 nits, the power supply voltage VDD is 2.8 V, and the power supply voltage VSS is -9 V. When the display brightness is 2200 nits, the power supply voltage VDD is 2.8 V, and the power supply voltage VSS is -9.3 V. When the power supply voltage VSS is lower than -9 V, in order to ensure the quality of the HBM black screen and the low gray scale screen, the second initialization signal Vinit2 cannot be much higher than the power supply voltage VSS. For example, when the display brightness is 500 nits, the power supply voltage VDD is 2.8 V, and the power supply voltage VSS is -6.7 V. When the display brightness is 150 nits, the power supply voltage VDD is 2.8 V, and the power supply voltage VSS is -5.8 V.

[0055] When the operating power supply voltage VDD is reduced to 2.8 V, in order to ensure that the display panel reaches the brightness requirement of the HBM, the low level of the second reset signal PresetH needs to be lower than -12 V, so as to ensure that the transistor M7 is completely turned on at this time, and the second initialization signal Vinit2 can be normally written into the anode of the light-emitting element OLED through the transistor M7. Therefore, the transistor M7 and the transistor M8 need to be driven separately.

[0056] For example, the transistor M2 is an NMOS transistor, and the transistors M1, M3-M8 are PMOS transistors, so the transistor M2 needs to be driven separately. For example, by controlling the differential refresh of the transistor M2 in different pixel rows in the display panel, local refresh of the display panel can be realized, thereby realizing power consumption reduction.

[0057] Since the pixel circuit 100 has corresponding requirements for the voltage values of the high and low levels of the first reset signal Preset, the first gate drive signal Ngate, the second gate drive signal Pgate, the emission control signal EM, and the second reset signal PresetH, respectively, the shift register included in the driving circuit needs to work under different power supply voltages to output driving signals with corresponding voltage values.

[0058] For example, the power supply voltages required by the shift registers outputting different driving signals and the working power supply voltage of the pixel circuit 100 can be as shown in Table 1.

[0059] Table 1

[0060] The power supply voltages required by the shift registers of the first reset signal Preset, the second gate drive signal Pgate, and the emission control signal EM can be the same. Therefore, 3 groups of power supplies VGH / VGL are required to meet the independent driving of the first reset signal Preset, the first gate drive signal Ngate, the second gate drive signal Pgate, the emission control signal EM, and the second reset signal PresetH, to ensure different display requirements of the pixel circuit 100.

[0061] In the display device, multiple groups of power supplies VGH / VGL occupy a large space, which causes difficulty in narrowing the frame of the display and increases the power consumption of the display device. In addition, the number of power supplies VGH / VGL provided by the existing driving circuit is limited, and multiple shift registers cannot be driven separately by multiple power supplies VGH / VGL.

[0062] To solve the above problems, the present disclosure provides a shift register, which realizes independent driving of multiple shift registers by two groups of power supplies VGH / VGL, and reduces the power consumption of the display device.

[0063] FIG. 2 is a structural schematic diagram of a scanning shift register according to an embodiment of the present disclosure.

[0064] As shown in FIG. 2, the shift register 200 includes a first shift register circuit 210, a second shift register circuit 220, and a third shift register circuit 230.

[0065] In the embodiment of the present disclosure, the first shift register circuit 210 is electrically connected with the first power supply VGH1, the second power supply VGL1, the first input terminal INPUT1 and the first output terminal OUT1. The first shift register circuit 210 is configured to output a first scan signal OUT1 through the first output terminal OUT1 under the control of a first power supply voltage VGH1 of the first power supply VGH1, a second power supply voltage VGL1 of the second power supply VGL1 and a first input signal INPUT1 from the first input terminal INPUT1.

[0066] In the embodiment of the present disclosure, the second shift register circuit 220 is electrically connected with the second power supply VGL1, the third power supply VGH2, the fourth power supply VGL2, the shift output terminal CR, the second input terminal INPUT2 and the second output terminal OUT2. The second shift register circuit 220 is configured to output a shift signal CR through the shift output terminal CR under the control of a third power supply voltage VGH2 of the third power supply VGH2, a fourth power supply voltage VGL2 of the fourth power supply VGL2 and a second input signal INPUT2 from the second output terminal INPUT2, and output a second scan signal OUT2 through the second output terminal OUT2 under the control of the third power supply voltage VGH2 and the second power supply voltage VGL1.

[0067] In the embodiment of the present disclosure, the third shift register circuit 230 is electrically connected with the first power supply VGH1, the fourth power supply VGL2, the third input terminal INPUT3 and the third output terminal OUT3. The third shift register circuit 230 is configured to output a third scan signal OUT3 through the third output terminal OUT3 under the control of the first power supply voltage VGH1, the fourth power supply voltage VGL2 and a third input signal OUT3 from the third output terminal OUT3.

[0068] For example, the first scan signal OUT1 output by the first shift register circuit 210 can be a second gate drive signal Pgate applied in the pixel circuit 100 shown in FIG. 1A. The second scan signal OUT2 output by the second shift register circuit 220 can be a first gate drive signal Ngate applied in the pixel circuit 100 shown in FIG. 1A. The third scan signal OUT3 output by the third shift register circuit 230 can be a second reset signal PresetH applied in the pixel circuit 100 shown in FIG. 1A.

[0069] In the embodiment of the present disclosure, the first power supply VGH1 and the second power supply VGL1 are a group of power supplies VGH / VGL, and the third power supply VGH2 and the fourth power supply VGL2 are a group of power supplies VGH / VGL.

[0070] In the embodiments of the present disclosure, the fourth power voltage VGL2 is less than the second power voltage VGL1. The first power voltage VGH1 is greater than the third power voltage VGH2. For example, the first power voltage VGH1 can be 7.2V, and the second power voltage VGL1 can be -9V. The third power voltage VGH2 can be 6.4V, and the fourth power voltage VGL2 can be -12V.

[0071] It should be noted that the voltage values of the first power voltage VGH1, the second power voltage VGL1, the third power voltage VGH2 and the fourth power voltage VGL2 can be adjusted according to the actual use and demand of the shift register.

[0072] In the embodiments of the present disclosure, the first scan signal OUT1 controls the gate of the transistor M4 in the pixel circuit 100 shown in FIG. 1A. Since the transistor M4 is a PMOS tube, the transistor M4 can be turned on by setting the low level of the first scan signal OUT1. For example, in order to reduce the driving power consumption of the first shift register circuit 210, if the voltage value of the second power voltage VGL1 can control the transistor M4 to be turned on in the high-brightness mode, the low level of the first scan signal OUT1 can be -9V. In addition, through simulation, it is determined that the high power voltage applied to the first shift register circuit 210 is 7.2V. Therefore, the first power voltage VGH1 is set to 7.2V, the second power voltage VGL1 is set to -9V, and the first shift register circuit 210 outputs the first scan signal OUT1 under the control of the first power voltage VGH1 and the second power voltage VGL1, so that the high and low levels of the first scan signal OUT1 are 7.2V and -9V respectively.

[0073] In the embodiments of the present disclosure, the second scan signal OUT2 controls the gate of the transistor M2 in the pixel circuit 100 shown in FIG. 1A. Since the transistor M2 is an NMOS tube, the transistor M2 can be turned on by setting the high level of the second scan signal OUT2. For example, in order to reduce the driving power consumption of the second shift register circuit 220, if the voltage value of the third power voltage VGH2 can control the transistor M2 to be turned on in the high-brightness mode, the high level of the second scan signal OUT2 can be set to 6.4V. In order to further reduce the driving power consumption, the low level of the second scan signal OUT2 can be -9V. Therefore, the third power voltage VGH2 is set to 6.4V and the second power voltage VGL1 is set to -9V, and the second shift register circuit 220 outputs the second scan signal OUT2 under the control of the third power voltage VGH2 and the second power voltage VGL1, so that the high and low levels of the second scan signal OUT2 are 6.4V and -9V respectively.

[0074] At the same time, the levels of the second scan signal OUT2 received by different pixel rows of the display panel are different, so that the display panel can be locally refreshed. Therefore, the high and low levels of the shift signal CR output by the second shift register circuit 220 and the high and low levels of the second scan signal OUT2 are different. The shift signal CR is used for output to the next stage of the second shift register circuit cascaded with the second shift register circuit 220. In order to ensure that the next stage of the second shift register circuit can stably output the shift signal CR, the high level of the shift signal CR can be 6.4V, and the low level can be -12V.

[0075] In the embodiment of the present disclosure, the third scan signal OUT3 controls the gate of the transistor M7 in the pixel circuit 100 shown in FIG. 1A. When the low level of the third scan signal OUT3 is -12V, the gate of the transistor M7 is controlled by the third scan signal OUT3, so that the transistor M7 is completely opened, and the second initialization signal Vinit2 can be completely written. In addition, it is determined through simulation that the high power voltage applied to the third shift register circuit 230 in the highlight mode is 7.2V. Therefore, the first power voltage VGH1 and the fourth power voltage VGL2 are set, and the third shift register circuit 230 is controlled by the first power voltage VGH1 and the fourth power voltage VGL2 to output the third scan signal OUT3, so that the high and low levels of the third scan signal OUT3 are 7.2V and -12V respectively.

[0076] In the embodiment of the present disclosure, since the two groups of power supply VGH1 / VGL1 and VGH2 / VGL2 are multiplexed, three groups of power supply (VGL1 / VGH1, VGH2 / VGL1 and VGH1 / VGL2) are formed, so that the three shift register circuits are separately provided with power supply voltages, and are separately driven. In addition, by providing power supply voltages for a plurality of shift register circuits through the two groups of power supply, the occupied space of the power supply line can be reduced, which is beneficial to narrow the frame of the display device.

[0077] FIG. 3 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0078] As shown in FIG. 3, the shift register 300 includes a first shift register circuit 310, a second shift register circuit 320 and a third shift register circuit 330.

[0079] The first shift register circuit 310, the second shift register circuit 320 and the third shift register circuit 330 are similar to the first shift register circuit 210, the second shift register circuit 220 and the third shift register circuit 230 respectively, and the same parts will not be described herein for the sake of simplicity.

[0080] In the embodiment of the present disclosure, the first shift register circuit 310 outputs the first scan signal OUT1 under the control of the first clock signal CLK1 from the first clock terminal CLK1. The first level of the first clock signal CLK1 is equal to the first power voltage VGH1, and the second level of the first clock signal CLK1 is equal to the second power voltage VGL1.

[0081] In the embodiment of the present disclosure, the second shift register circuit 320 outputs the second scan signal OUT2 under the control of the second clock signal CLK2 from the second clock terminal CLK2. The first level of the second clock signal CLK2 is equal to the third power voltage VGH2, and the second level of the second clock signal CLK2 is equal to the fourth power voltage VGL2.

[0082] In the embodiment of the present disclosure, the third shift register circuit 330 outputs the third scan signal OUT3 under the control of the third clock signal CLK3 from the third clock terminal CLK3. The first level of the third clock signal CLK3 is equal to the third power voltage VGH2, and the second level of the third clock signal CLK3 is equal to the fourth power voltage VGL2.

[0083] In the embodiment of the present disclosure, the first level is high, and the second level is low. The high level of the first clock signal CLK1 is 7.2V, and the low level is -9V. The high level of the second clock signal CLK2 is 6.4V, and the low level is -12V. The high level of the third clock signal CLK3 is 6.4V, and the low level is -12V.

[0084] In the embodiment of the present disclosure, in the highlight mode, the low level of the third scan signal OUT3 needs to be -12V, so that the third scan signal OUT3 controls the transistor M7 shown in FIG. 1A to be completely opened, and the second initialization signal Vinit2 can be completely written.

[0085] Since the third scan signal OUT3 is used to control the on and off states of the PMOS tube, it is necessary to ensure that the low level of the third scan signal OUT3 remains stable. In order to ensure that the low level of the third scan signal OUT3 remains stable at -12V, the low level of the third clock signal CLK3 also needs to remain at -12V. The high and low levels of the third clock signal CLK3 need to correspond to a group of power supplies, so the high and low levels of the third clock signal CLK3 are consistent with the third power voltage VGH2 and the fourth power voltage VGL2 respectively, wherein the fourth power voltage VGL2 is -12V.

[0086] In the embodiment of the present disclosure, since the second scan signal OUT2 is used to control the on and off states of the NMOS tube, it is necessary to ensure that the high level of the second scan signal OUT2 remains stable. In order to ensure that the high level of the second scan signal OUT2 remains stable at 6.4V, the high level of the second clock signal CLK2 also needs to remain at 6.4V. The high and low levels of the second clock signal CLK2 need to correspond to a group of power supplies, so the high and low levels of the second clock signal CLK2 are consistent with the third power supply voltage VGH2 and the fourth power supply voltage VGL2 respectively, and the third power supply voltage VGH2 is 6.4V.

[0087] In the embodiment of the present disclosure, since the first scan signal OUT1 is used to control the on and off states of the PMOS tube, it is necessary to ensure that the low level of the first scan signal OUT1 remains stable. In order to ensure that the low level of the first scan signal OUT1 remains stable at -9V, the high level of the first clock signal CLK1 also needs to remain at 7.2V. The high and low levels of the first clock signal CLK1 need to correspond to a group of power supplies, so the high and low levels of the first clock signal CLK1 are consistent with the first power supply voltage VGH1 and the second power supply voltage VGL1 respectively, wherein the first power supply voltage VGH1 is 7.2V and the second power supply voltage VGL1 is -9V.

[0088] In the embodiment of the present disclosure, in the normal mode, the requirement for the low level of the third scan signal OUT3 can be reduced, thereby reducing the driving power consumption of the third shift register circuit 330. Therefore, in the normal mode, the voltage value of the fourth power supply voltage VGL2 from the fourth power supply VGL2 can be adjusted.

[0089] For example, the fourth power supply voltage VGL2 is adjusted from -12V to -9V, which makes the low level of the third scan signal OUT3 adjusted to -9V. Correspondingly, in order to ensure that the low level of the third scan signal OUT3 remains stable at -9V, the low level of the third clock signal CLK3 also needs to remain at -9V, so the high and low levels of the adjusted third clock signal CLK3 are 6.4V and -9V respectively. Therefore, in the normal mode, the first level of the third clock signal CLK3 can be set to be equal to the third power supply voltage VGH2, and the second level of the third clock signal CLK3 can be set to be equal to the second power supply voltage VGL1.

[0090] In the embodiments of the present disclosure, the high and low levels of the clock signals applied to the first shift register circuit 310, the second shift register circuit 320 and the third shift register circuit 330 can ensure that the high and low levels of the first scan signal OUT1, the second scan signal OUT2 and the third scan signal OUT3 can be stably maintained as the corresponding voltage values. In addition, according to the display mode of the display panel, the voltage values of the power supply voltages applied to the first shift register circuit 310, the second shift register circuit 320 and the third shift register circuit 330 can be adjusted, and the high and low levels of the clock signals are correspondingly adjusted to ensure the stable output of the scan signals and reduce the driving power consumption generated by the clock signals.

[0091] FIG. 4 is a structural schematic diagram of a shift register according to another embodiment of the present disclosure.

[0092] As shown in FIG. 4, the shift register 400 includes a first shift register circuit 410, a second shift register circuit 420, a third shift register circuit 430, a fourth shift register circuit 440 and a fifth shift register circuit 450.

[0093] The first shift register circuit 410, the second shift register circuit 420 and the third shift register circuit 430 are similar to the first shift register circuit 310, the second shift register circuit 320 and the third shift register circuit 330 respectively, and the same parts will not be described herein for simplicity.

[0094] In the embodiments of the present disclosure, the fourth shift register circuit 440 is electrically connected with the first power supply VGH1, the second power supply VGL1, a fourth input terminal INPUT4 and a fourth output terminal OUT4. The fourth shift register circuit 440 is configured to output a fourth scan signal OUT4 through the fourth output terminal OUT4 under the control of the first power supply voltage VGH1, the second power supply voltage VGL1 and a fourth input signal INPUT4 from the fourth input terminal INPUT4.

[0095] In the embodiments of the present disclosure, the fourth shift register circuit 440 outputs the fourth scan signal OUT4 under the control of a fourth clock signal CLK4 from a fourth clock terminal CLK4. The first level of the fourth clock signal CLK4 is equal to the first power supply voltage VGH1, and the second level of the fourth clock signal CLK4 is equal to the second power supply voltage VGL1.

[0096] In the embodiment of the present disclosure, the fifth shift register circuit 450 is electrically connected with the first power supply VGH1, the second power supply VGL1, the fifth input terminal INPUT5 and the fifth output terminal OUT5. The fifth shift register circuit 450 is configured to output a light-emitting control signal OUT5 through the fifth output terminal OUT5 under the control of the first power supply voltage VGH1, the second power supply voltage VGL1 and a fifth input signal INPUT5 from the fifth input terminal INPUT5.

[0097] In the embodiment of the present disclosure, the fifth shift register circuit 450 outputs a fifth scan signal OUT5 under the control of a fifth clock signal CLK5 from the fifth clock terminal CLK5. The first level of the fifth clock signal CLK5 is equal to the first power supply voltage VGH1, and the second level of the fifth clock signal CLK5 is equal to the second power supply voltage VGL1.

[0098] In the embodiment of the present disclosure, the power supply electrically connected with the fourth shift register circuit 440 and the fifth shift register circuit 450 is similar to the power supply electrically connected with the first shift register 410. The voltage value of the power supply voltage applied to the fourth shift register circuit 440 and the fifth shift register circuit 450 is similar to the voltage value of the power supply voltage applied to the power supply of the first shift register 410. The high and low levels of the clock signal applied to the fourth shift register circuit 440 and the fifth shift register circuit 450 are similar to the high and low levels of the clock signal applied to the first shift register 410. For the sake of simplicity, details are not described herein.

[0099] FIG. 5 is a structural schematic diagram of a second shift register circuit according to an embodiment of the present disclosure.

[0100] As shown in FIG. 5, the second shift register circuit 520 includes a control unit 521 and an output unit 522.

[0101] In the embodiment of the present disclosure, the control unit 521 outputs a shift signal CR and controls the potentials of the first node N1 and the second node N2 under the control of the third power supply voltage VGH2, the fourth power supply voltage VGL2 and the second input signal INPUT2. The output unit 522 outputs a second scan signal OUT2 under the control of the second power supply voltage VGL1, the third power supply voltage VGH2, the potential of the first node N1 and the potential of the second node N2.

[0102] In the embodiment of the present disclosure, the shift signal CR is output to the next stage of the second shift register circuit which is cascaded with the second shift register circuit 520. The high and low levels of the shift signal CR are controlled by the third power voltage VGH2 and the fourth power voltage VGL2. The second scan signal OUT2 can be output to the gate of the transistor M2 of the pixel circuit 100 shown in FIG. 1A, for example. The high and low levels of the second scan signal OUT2 are controlled by the second power voltage VGL1 and the third power voltage VGH2.

[0103] In the embodiment of the present disclosure, under the control of the high level of the second input signal INPUT2, the control unit 521 controls the fourth power VGL2 and the shift output end CR to be in the off state. Under the control of the high level of the second input signal INPUT2 and the fourth power voltage VGL2, the control unit 521 controls the third power VGH2 and the shift output end CR to be in the on state, and the shift signal CR output by the shift output end CR is high. Under the control of the low level of the second input signal INPUT2, the control unit 521 controls the fourth power VGL2 and the shift output end CR to be in the on state, and the shift signal CR output by the shift output end CR is low.

[0104] In the embodiment of the present disclosure, under the control of the low level of the first node N1 and the high level of the second node N2, the output unit 522 controls the second power VGL1 and the second output end OUT2 to be in the off state, controls the third power VGH2 and the second output end OUT2 to be in the on state, and the second scan signal OUT2 output by the second output end OUT2 is high. Under the control of the high level of the first node N1 and the low level of the second node N2, the output unit 522 controls the third power VGH2 and the second output end OUT2 to be in the off state, controls the second power VGL1 and the second output end OUT2 to be in the on state, and the second scan signal OUT2 output by the second output end OUT2 is low.

[0105] In the embodiment of the present disclosure, the control unit 521 is also electrically connected with the second clock end CLK2. Under the control of the second clock signal CLK2, the third power voltage VGH2, the fourth power voltage VGL2 and the second input signal INPUT2, the control unit 521 outputs the shift signal CR and controls the potentials of the first node N1 and the second node N2. The first level of the second clock signal CLK2 is equal to the third power voltage VGH2, and the second level of the second clock signal CLK2 is equal to the fourth power voltage VGL2.

[0106] It should be noted that the first node N1 and the second node N2 do not represent actual components, but represent the convergence points of the relevant circuit connections in the circuit diagram.

[0107] FIG. 6A is a structural schematic diagram of a second shift register circuit according to another embodiment of the present disclosure. FIG. 6B is a signal timing diagram of the second shift register circuit according to an embodiment of the present disclosure. FIG. 6C is a signal timing diagram of the second shift register circuit according to another embodiment of the present disclosure.

[0108] As shown in FIG. 6A, the second shift register circuit 620 includes a control unit 621 and an output unit 622.

[0109] In an embodiment of the present disclosure, the control unit 621 includes the first transistor T1 to the eighteenth transistor T18, the twenty-first transistor T21 to the twenty-sixth transistor T26, and the capacitor C1 to the capacitor C8. The output unit 622 includes the nineteenth transistor T19 and the twentieth transistor T20.

[0110] In an embodiment of the present disclosure, the second clock end CLK2 includes a clock end CK and a clock end CB. The level of the clock signal CK from the clock end CK is valid when it is different from the level of the clock signal CB from the clock end CB. For example, when the clock signal CK is at a low level, the clock signal CB is at a high level. When the clock signal CB is at a low level, the clock signal CK is at a high level.

[0111] For example, the second shift register circuit 620 can be an n-level second shift register circuit in a plurality of cascaded second shift register circuits, where n is a positive integer.

[0112] The control electrode of the first transistor T1 and the control electrode of the fourteenth transistor T14 are electrically connected to the clock end CK. The first electrode of the first transistor T1 and the first electrode of the fourteenth transistor T14 are electrically connected to the second input end INPUT2. The second electrode of the first transistor T1 is electrically connected to the twelfth node N12, and the second electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8.

[0113] The control electrode of the second transistor T2 is electrically connected to the twelfth node N12, the first electrode is electrically connected to the clock end CK, and the second electrode is electrically connected to the thirteenth node N13.

[0114] The control electrode of the third transistor T3 is electrically connected to the clock end CK, the first electrode is electrically connected to the fourth power supply VGL2, and the second electrode is electrically connected to the thirteenth node N13.

[0115] The control electrode of the fourth transistor T4 is electrically connected to the ninth node N9, the first electrode is electrically connected to the fifth node N5, and the second electrode is electrically connected to the clock end CB.

[0116] The control electrode of the fifth transistor T5 is electrically connected to the thirteenth node N13, the first electrode is electrically connected to the third power supply VGH2, and the second electrode is electrically connected to the fifth node N5.

[0117] The control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode is electrically connected to the clock terminal CB, and the second electrode is electrically connected to the third node N3.

[0118] The control electrode of the seventh transistor T7 is electrically connected to the clock terminal CB, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the fourth node N4.

[0119] The control electrode of the eighth transistor T8 is electrically connected to the twelfth node N12, the first electrode is electrically connected to the fourth node N4, and the second electrode is electrically connected to the third power supply VGH2.

[0120] The control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the first electrode is electrically connected to the third power supply VGH2, and the second electrode is electrically connected to the shift output terminal CR(n).

[0121] The control electrode of the tenth transistor T10 is electrically connected to the seventh node N7, the first electrode is electrically connected to the shift output terminal CR(n), and the second electrode is electrically connected to the fourth power supply VGL2.

[0122] The control electrode of the eleventh transistor T11 is electrically connected to the fourth power supply VGL2, the first electrode is electrically connected to the thirteenth node N13, and the second electrode is electrically connected to the sixth node N6.

[0123] The control electrode of the twelfth transistor T12 is electrically connected to the fourth power supply VGL2, the first electrode is electrically connected to the twelfth node N12, and the second electrode is electrically connected to the seventh node N7.

[0124] The control electrode of the thirteenth transistor T13 is electrically connected to the first control terminal NCX, the first electrode is electrically connected to the third power supply VGH2, and the second electrode is electrically connected to the twelfth node N12.

[0125] The control electrode of the fifteenth transistor T15 is electrically connected to the fourth power supply VGL2, the first electrode is electrically connected to the eighth node N8, and the second electrode is electrically connected to the ninth node N9.

[0126] The control electrode and the first electrode of the sixteenth transistor T16 are electrically connected to the ninth node N9, and the second electrode is electrically connected to the seventh node N7.

[0127] The control electrode and the first electrode of the seventeenth transistor T17 are electrically connected to the ninth node N9, and the second electrode is electrically connected to the second node N2.

[0128] The control electrode of the eighteenth transistor T18 is electrically connected to the eleventh node N11, the first electrode is electrically connected to the twelfth node N12, and the second electrode is electrically connected to the second node N2.

[0129] The control electrode of the nineteenth transistor T19 is electrically connected to the first node N1, the first electrode is electrically connected to the third power supply VGH2, and the second electrode is electrically connected to the second output terminal OUT2.

[0130] The control electrode of the twentieth transistor T20 is electrically connected to the second node N2, the first electrode is electrically connected to the second output terminal OUT2, and the second electrode is electrically connected to the second power supply VGL1.

[0131] The twenty-first transistor T21 can be a double-gate transistor, the control electrode of the twenty-first transistor T20 is electrically connected to the eleventh node N11, the first electrode is electrically connected to the fourth node N4, and the second electrode is electrically connected to the first node N1.

[0132] The control electrode of the twenty-second transistor T22 is electrically connected to the third node N3(n-1) of the second shift register circuit of the n-1th stage, the first electrode is electrically connected to the second control terminal vms, and the second electrode is electrically connected to the tenth node N10.

[0133] The control electrode of the twenty-third transistor T23 is electrically connected to the shift output terminal CR(n), the first electrode is electrically connected to the tenth node N10, and the second electrode is electrically connected to the eleventh node N11.

[0134] The control electrode of the twenty-fourth transistor T24 is electrically connected to the second node N2, the first electrode is electrically connected to the second electrode of the twenty-sixth transistor T26, and the second electrode is electrically connected to the third power supply VGH2.

[0135] The control electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5, the first electrode is electrically connected to the eleventh node N11, and the second electrode is electrically connected to the fourth power supply VGL2.

[0136] The control electrode of the twenty-sixth transistor T26 is electrically connected to the second output terminal OUT2, and the first electrode is electrically connected to the first node N1.

[0137] The first end of the first capacitor C1 is electrically connected to the sixth node N6, and the second end is electrically connected to the third node N3.

[0138] The first end of the second capacitor C2 is electrically connected to the fourth node N4, and the second end is electrically connected to the third power supply VGH2.

[0139] The first end of the third capacitor C3 is electrically connected to the fifth node N5, and the second end is electrically connected to the ninth node N9.

[0140] The first end of the fourth capacitor C4 is electrically connected to the eleventh node N11, and the second end is electrically connected to the tenth node N1.

[0141] The first end of the fifth capacitor C5 is electrically connected to the third power supply VGH2, and the second end is electrically connected to the first node N1.

[0142] The first end of the sixth capacitor C6 is electrically connected to the third power supply VGH2, and the second end is electrically connected to the shift output terminal CR(n).

[0143] A first terminal of the seventh capacitor C7 is electrically connected to the fourth power supply VGL2, and a second terminal of the seventh capacitor C7 is electrically connected to the second output terminal OUT2.

[0144] A first terminal of the eighth capacitor C8 is electrically connected to the fourth power supply VGL2, and a second terminal of the eighth capacitor C8 is electrically connected to the shift output terminal CR(n).

[0145] In the example of FIG. 6A, the first transistor T1 to the twenty-sixth transistor T26 are P-type transistors, for example, thin film transistors with an active layer of low temperature polysilicon (LTPS). Those skilled in the art can understand that, according to the embodiments of the present disclosure, the first transistor T1 to the twenty-sixth transistor T26 can also be N-type transistors, for example, thin film transistors with an active layer of indium gallium zinc oxide (IGZO), and the levels of the gate drive signals of the respective transistors can be changed accordingly.

[0146] In addition, those skilled in the art can understand that the capacitors can be respectively implemented as single capacitors or multiple capacitive units connected in parallel or in series, as long as the corresponding functions can be implemented.

[0147] It should be noted that the first node N1 to the thirteenth node N13 do not represent actual components, but represent the convergence points of the relevant circuit connections in the circuit diagram.

[0148] FIGS. 6B and 6C are signal timing diagrams of the second shift register circuit in FIG. 6A. FIGS. 6B and 6C show the timing waveforms of the respective signals.

[0149] The voltage value of the fourth power supply voltage VGL2 shown in FIG. 6B is -12V, and the voltage value of the fourth power supply voltage VGL2 shown in FIG. 6C is -9V. For example, the signal timing and the potential changes of the nodes in the second shift register circuit shown in FIG. 6B can be for a highlight mode, and the signal timing and the potential changes of the nodes in the second shift register circuit shown in FIG. 6C can be for a regular mode. For example, the signal timing shown in FIGS. 6B and 6C can be the simulation results of the potential changes of the nodes in the second shift register circuit. For example, the simulation results of the potential changes of the nodes in the second shift register circuit can be when a plurality of second shift register circuits connected in cascade are not connected to a display panel, or the simulation results of the potential changes of the nodes in the first stage second shift register circuit in a plurality of second shift register circuits connected in cascade.

[0150] The working process of the scan shift register provided by the embodiments of the present disclosure is described below with the structure of the second shift register circuit shown in FIG. 6A as an example, in combination with the signal timing diagrams shown in FIGS. 6B and 6C. The signal timing and the potential changes of the nodes in the second shift register circuit shown in FIGS. 6B and 6C are similar.

[0151] In the embodiments of the present disclosure, the eleventh transistor T11, the fifteenth transistor T15 and the twelfth transistor T12 are in the on state under the control of the fourth power supply voltage VGL2.

[0152] In the first stage S1, the second input signal INPUT2 is at a low level, the clock signal CK is at a low level, and the clock signal CB is at a high level.

[0153] The first transistor T1 and the fourteenth transistor T14 are turned on, and the second input signal INPUT2 is written to the twelfth node N12 and the seventh node N7 through the first transistor T1 and the twelfth transistor T12. At this time, the potentials of the seventh node N7 and the twelfth node N12 are at a low level. Under the control of the low level of the potential of the seventh node N7, the tenth transistor T10 is turned on.

[0154] The second input signal INPUT2 is written to the eighth node N8 and the ninth node N9 through the fourteenth transistor T14 and the fifteenth transistor T15. The potentials of the eighth node N8 and the ninth node N9 are at a low level. The sixteenth transistor T16 is turned on under the control of the low level of the ninth node N9, and the second input signal INPUT2 is written to the seventh node N7 through the sixteenth transistor T16.

[0155] The third transistor T3 is turned on, and the fourth power supply voltage VGL2 is written to the thirteenth node N13 and the sixth node N6 through the third transistor T3 and the eleventh transistor T11, and the potentials of the thirteenth node N13 and the sixth node N6 are at a low level. The sixth transistor T6 is turned on, and the clock signal CB is written to the third node N3 through the sixth transistor T6, and the third node N3 is at a high level.

[0156] The eighth transistor T8 is turned on under the control of the twelfth node N12, and the third power supply voltage VGH2 is written to the fourth node N4 through the eighth transistor T8, and the potential of the fourth node N4 is at a high level. The ninth transistor T9 is turned off under the control of the high level of the fourth node N4.

[0157] Therefore, the fourth power supply voltage VGL2 is written to the shift output end CR(n) through the tenth transistor T10, and the shift output end CR(n) outputs a low level signal.

[0158] The seventeenth transistor T17 is turned on under the control of the low level of the ninth node N9, and the low level of the ninth node N9 is written to the second node N2, and the potential of the second node N2 is at a low level, and the twentieth transistor T20 is turned on. The second power supply voltage VGL1 is written to the second output end OUT2 through the twentieth transistor T20, and the second output end OUT2 outputs a low level signal.

[0159] At this time, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are turned on, and the third power supply voltage VGH2 is written to the first node N1 through the twenty-fourth transistor T24 and the twenty-sixth transistor T26. The potential of the first node N1 is at a high level, and the nineteenth transistor T19 is turned off.

[0160] In the second stage S2, the second input signal INPUT2 is at a low level, the clock signal CK is at a high level, and the clock signal CB is at a low level.

[0161] The first transistor T1, the fourteenth transistor T14, and the third transistor T3 are turned off. The potentials of the twelfth node N12, the third node N3, the fourth node N4, the sixth node N6, the seventh node N7, the eighth node N8, the ninth node N9, the first node N1, and the second node N2 remain the same as in the previous stage.

[0162] The fourth transistor T4 is turned on, the clock signal CB is written to the fifth node N5 through the fourth transistor T4, and the potential of the fifth node N5 is at a low level. The second transistor T2 is turned on, the clock signal CK is written to the thirteenth node N13 through the second transistor T2, and the potential of the thirteenth node N13 is at a high level.

[0163] The tenth transistor T10 and the twentieth transistor T20 are turned on, and the ninth transistor T9 and the nineteenth transistor T19 are turned off. Therefore, the fourth power supply voltage VGL2 is written to the shift output terminal CR(n) through the tenth transistor T10, and the shift output terminal CR(n) outputs a low level signal. The second power supply voltage VGL1 is written to the second output terminal OUT2 through the twentieth transistor T20, and the second output terminal OUT2 outputs a low level signal.

[0164] In the third stage S3, the second input signal INPUT2 is at a high level, the clock signal CK is at a low level, and the clock signal CB is at a high level.

[0165] The first transistor T1 and the fourteenth transistor T14 are turned on, and the second input signal INPUT2 is written to the twelfth node N12 and the seventh node N7 through the first transistor T1 and the twelfth transistor T12. At this time, the potentials of the seventh node N7 and the twelfth node N12 are at a high level. Under the control of the high level of the potential of the seventh node N7, the tenth transistor T10 is turned off.

[0166] The second input signal INPUT2 is written to the eighth node N8 and the ninth node N9 through the fourteenth transistor T14 and the fifteenth transistor T15. The potentials of the eighth node N8 and the ninth node N9 are at a high level. The sixteenth transistor T16 is turned on under the control of the low level of the ninth node N9, and the second input signal INPUT2 is written to the seventh node N7 through the sixteenth transistor T16.

[0167] The third transistor T3 is turned on, the fourth power supply voltage VGL2 is written to the thirteenth node N13 and the sixth node N6 through the third transistor T3 and the eleventh transistor T11, and the potentials of the thirteenth node N13 and the sixth node N6 are low. The sixth transistor T6 is turned on, and the clock signal CB is written to the third node N3 through the sixth transistor T6, and the third node N3 is high.

[0168] The seventh transistor T7 and the eighth transistor T8 are turned off. The second capacitor C2 controls the potential of the fourth node N4 to remain high. The ninth transistor T9 is turned off under the control of the high level of the fourth node N4.

[0169] Therefore, the shift output end CR(n) maintains the output state of the previous stage, and the shift output end CR(n) outputs a low level signal.

[0170] The fourth capacitor C4 controls the potential of the eleventh node N11 to remain low. The eighteenth transistor T18 is turned on, and the high potential of the twelfth node N12 is written to the second node N2 through the eighteenth transistor T18, and the twentieth transistor T20 is turned off. The fifth capacitor C5 controls the potential of the first node N1 to remain high. The twentieth transistor T20 is turned off under the control of the high level of the first node N1.

[0171] Therefore, the second output end OUT2 maintains the output state of the previous stage, and the second output end OUT2 outputs a low level signal.

[0172] In the fourth stage S4, the second input signal INPUT2 is high.

[0173] When the clock signal CK is high and the clock signal CB is low, the first transistor T1, the fourteenth transistor T14 and the third transistor T3 are turned off.

[0174] The potentials of the seventh node N7, the twelfth node N12 and the thirteenth node N13 remain the same as the previous stage, and the tenth transistor T10 is turned off. The first capacitor C1 controls the potential of the sixth node N6 to remain low. The sixth transistor T6 and the seventh transistor T7 are turned on, and the clock signal CB is written to the fourth node N4 through the sixth transistor T6 and the seventh transistor T7, and the potential of the fourth node N4 is low, and the ninth transistor T9 is turned on. The third power supply voltage VGH2 is written to the shift output end CR(n) through the ninth transistor T9, and the shift output end CR(n) outputs a high level signal.

[0175] The potential of the second node N2 remains the same as the previous stage, and the twentieth transistor T20 is turned off.

[0176] The fourth capacitor C4 controls the potential of the eleventh node N11 to be kept at a low level. The twenty-first transistor T21 is turned on, and the low potential of the fourth node N4 is written to the first node N1 through the twenty-first transistor T21, and the potential of the first node N1 is at a low level. The nineteenth transistor T19 is turned on, and the third power supply voltage VGH2 is written to the second output terminal OUT2 through the nineteenth transistor T19, and the second output terminal OUT2 outputs a high level signal.

[0177] When the clock signal CK is at a low level and the clock signal CB is at a high level, the potentials of the twelfth node N12, the thirteenth node N13, the fourth node N4, the fifth node N5, the seventh node N7, the eighth node N8, the ninth node N9, the tenth node N10, the eleventh node N11, the first node N1 and the second node N2 are kept the same as those in the previous stage.

[0178] The tenth transistor T10 and the twentieth transistor T20 are turned off, and the ninth transistor T9 and the nineteenth transistor T19 are turned on. Therefore, the third power supply voltage VGH2 is written to the shift output terminal CR(n) through the ninth transistor T9, and the shift output terminal CR(n) outputs a high level signal. The third power supply voltage VGH2 is written to the second output terminal OUT2 through the nineteenth transistor T19, and the second output terminal OUT2 outputs a high level signal.

[0179] In the fifth stage S5, the second input signal INPUT2 is at a low level, the clock signal CK is at a high level, and the clock signal CB is at a low level.

[0180] The potentials of the fourth node N4, the seventh node N7, the first node N1 and the second node N2 are kept the same as those in the previous stage. Therefore, the second output terminal OUT2 keeps the output state of the previous stage, and the second output terminal OUT2 outputs a low level signal.

[0181] In the sixth stage S6, the second input signal INPUT2 is at a low level, the clock signal CK is at a low level, and the clock signal CB is at a high level.

[0182] The potentials of the nodes of the second shift register circuit in the sixth stage S6 are the same as those of the nodes of the second shift register circuit in the first stage S1,

[0183] Therefore, the tenth transistor T10 and the twentieth transistor T20 are turned on, and the ninth transistor T9 and the nineteenth transistor T19 are turned off. The fourth power supply voltage VGL2 is written to the shift output terminal CR(n) through the tenth transistor T10, and the shift output terminal CR(n) outputs a low level signal. The second power supply voltage VGL1 is written to the second output terminal OUT2 through the twentieth transistor T20, and the second output terminal OUT2 outputs a low level signal.

[0184] In the embodiment of the present disclosure, when the potential of the first control signal vms is low, the second output terminal OUT2 outputs a high-level signal. Under the control of the high-level, the second transistor M2 shown in FIG. 1A is turned on, and the pixel circuit 100 can refresh the data voltage. When the potential of the first control signal vms is high, the second output terminal OUT2 outputs a low-level signal. Under the control of the low-level, the second transistor M2 shown in FIG. 1A is turned off, and the data voltage cannot be refreshed, and the pixel circuit 100 will maintain the last frame of light-emitting state.

[0185] For example, when the display image of the display panel is a static image, the pixel array of the display panel is refreshed at a low frequency, the first control signal vms is high, the second output terminal OUT2 outputs a low voltage signal, and the second transistor M2 shown in FIG. 1A is turned off. When the display image of the display panel is a dynamic image, the pixel array of the display panel needs to be normally refreshed or high-frequency refreshed, the first control signal vms is low, the second output terminal OUT2 outputs a high-level signal, and the second transistor M2 shown in FIG. 1A is turned on.

[0186] In the embodiment of the present disclosure, by controlling the level of the first control signal vms received by different stages of the second shift register circuit in the cascaded multiple second shift register circuits, the level of the second scanning signal OUT can be controlled, so as to realize the local refresh of the display image in the display panel and reduce the refresh power consumption.

[0187] In the embodiment of the present disclosure, in the highlight mode, the voltage value of the third power voltage VGH2 can be 6.4V, the second power voltage VGL1 can be -9V, and the fourth power voltage VGL2 can be -12V. The high and low levels of the shift signal output by the shift output terminal CR(n) are 6.4V and -12V respectively, and the high and low levels of the second scanning signal OUT2 output by the second output terminal OUT2 are 6.4V and -9V respectively, which can meet the driving requirements of the pixel circuit shown in FIG. 1A. When the fourth power voltage VGL2 is -12V, the potential of the second node N2 is less than -23V, which can ensure that the twentieth transistor T20 can be completely opened, and is conducive to the stable output of the second output terminal OUT to the second power voltage VGL1.

[0188] FIG. 7 is a structural schematic diagram of a driving circuit according to an embodiment of the present disclosure.

[0189] As shown in FIG. 7, the driving circuit 700 includes a first gate driving circuit 710, a second gate driving circuit 720, and a third gate driving circuit 730.

[0190] In the embodiments of the present disclosure, the first gate drive circuit 710 includes M first shift register circuits connected in cascade. The M first shift register circuits include a first shift register circuit 710_1, a first shift register circuit 710_2, …, and a first shift register circuit 710_M. A first input terminal of an mth stage first shift register circuit is electrically connected with a first output terminal of an (m-1) th stage first shift register circuit, 1 < m ≤ M, m and M are positive integers greater than 1.

[0191] For example, the first output terminal OUT1 of the first shift register circuit 710_1 is electrically connected with the first input terminal INPUT1 of the first shift register circuit 710_2.

[0192] In the embodiments of the present disclosure, the second gate drive circuit 720 includes M second shift register circuits connected in cascade. The M second shift register circuits include a second shift register circuit 720_1, a second shift register circuit 720_2, …, and a second shift register circuit 720_M. A second input terminal of an mth stage second shift register circuit is electrically connected with a shift output terminal of an (m-1) th stage second shift register circuit.

[0193] For example, the shift output terminal CR of the second shift register circuit 720_1 is electrically connected with the second input terminal INPUT2 of the second shift register circuit 720_2.

[0194] In the embodiments of the present disclosure, the third gate drive circuit 730 includes M third shift register circuits connected in cascade. The M third shift register circuits include a third shift register circuit 730_1, a third shift register circuit 730_2, …, and a third shift register circuit 730_M. A third input terminal of an mth stage third shift register circuit is electrically connected with a third output terminal of an (m-1) th stage third shift register circuit.

[0195] For example, the third output terminal OUT3 of the third shift register circuit 730_1 is electrically connected with the third input terminal INPUT3 of the third shift register circuit 730_2.

[0196] In the embodiments of the present disclosure, the first shift register circuit can be any one of the first shift register circuit 210, the first shift register circuit 310, and the first shift register circuit 410 described above. The second shift register circuit can be any one of the second shift register circuit 220, the second shift register circuit 320, the second shift register circuit 420, the second shift register circuit 520, and the second shift register circuit 620 described above. The third shift register circuit can be any one of the third shift register circuit 230, the third shift register circuit 330, and the third shift register circuit 430 described above.

[0197] In the embodiments of the present disclosure, the first input end INPUT1 of the first-stage first shift register circuit 710_1 is electrically connected with the first trigger signal end STV1. The second input end INPUT2 of the first-stage second shift register circuit 720_1 is electrically connected with the second trigger signal end STV2. The third input end INPUT3 of the first-stage third shift register circuit 730_1 is electrically connected with the third trigger signal end STV3.

[0198] In the embodiments of the present disclosure, the driving circuit 700 further includes a fourth gate driving circuit. The fourth gate driving circuit includes M fourth shift register circuits connected in cascade, and the fourth input end of the mth-stage fourth shift register circuit is electrically connected with the fourth output end of the (m-1)th-stage fourth shift register circuit.

[0199] The driving circuit 700 further includes a light-emitting control driving circuit. The light-emitting control driving circuit includes M fifth shift register circuits connected in cascade, and the fifth input end of the mth-stage fifth shift register circuit is electrically connected with the fifth output end of the (m-1)th-stage fifth shift register circuit.

[0200] The fourth shift register circuit can be the fourth shift register circuit 440 described above. The fifth shift register circuit can be the fifth shift register circuit 450 described above.

[0201] In the embodiments of the present disclosure, each first shift register circuit included in the first gate driving circuit 710 can provide the second gate driving signal Pgate for a row of pixels in the pixel array. Each second shift register circuit included in the second gate driving circuit 720 can provide the first gate driving signal Ngate for a row of pixels in the pixel array. Each third shift register circuit included in the third gate driving circuit 730 can provide the second reset signal PresetH for a row of pixels in the pixel array. Each fourth shift register circuit included in the fourth gate driving circuit 740 can provide the first reset signal Preset for a row of pixels in the pixel array. Each fifth shift register circuit included in the light-emitting control driving circuit 750 can provide the light-emitting control signal EM for a row of pixels in the pixel array.

[0202] FIG. 8A is a structural schematic diagram of a first gate driving circuit according to an embodiment of the present disclosure.

[0203] As shown in FIG. 8A, the first gate driving circuit 810 includes M first shift register circuits connected in cascade.

[0204] In the embodiments of the present disclosure, the first gate driving circuit 810 can be the first gate driving circuit 710 described above.

[0205] In the embodiment of the present disclosure, the M first shift register circuits in cascade are electrically connected with the first power supply VGH1, the second power supply VGL1 and the first clock terminal CLK1 respectively.

[0206] FIG. 8B is a structural schematic diagram of a second gate drive circuit according to an embodiment of the present disclosure.

[0207] As shown in FIG. 8B, the second gate drive circuit 820 includes M second shift register circuits in cascade.

[0208] In the embodiment of the present disclosure, the second gate drive circuit 820 can be the second gate drive circuit 720 described above.

[0209] In the embodiment of the present disclosure, the M second shift register circuits in cascade are electrically connected with the second power supply VGL1, the third power supply VGH2 and the second clock terminal CLK2 respectively.

[0210] In the embodiment of the present disclosure, the shift output terminal CR of the Mth second shift register circuit 820_M can be electrically connected with the anti-static terminal ESD.

[0211] FIG. 8C is a structural schematic diagram of a third gate drive circuit according to an embodiment of the present disclosure.

[0212] As shown in FIG. 8C, the third gate drive circuit 830 includes M third shift register circuits in cascade.

[0213] In the embodiment of the present disclosure, the third gate drive circuit 830 can be the third gate drive circuit 730 described above.

[0214] In the embodiment of the present disclosure, the M third shift register circuits in cascade are electrically connected with the first power supply VGH1, the fourth power supply VGL2 and the third clock terminal CLK3 respectively.

[0215] FIG. 9 is a structural schematic diagram of a display device according to an embodiment of the present disclosure.

[0216] As shown in FIG. 9, the display device 900 includes a display panel 910 and a drive circuit 920.

[0217] In the embodiment of the present disclosure, the display panel 910 includes a plurality of pixel units arranged in an array. The circuit structure of a sub-pixel included in each pixel unit can be as shown in FIG. 1A. The pixel units are electrically connected with the first output terminal, the second output terminal and the third output terminal of the drive circuit 920.

[0218] In the embodiment of the present disclosure, the drive circuit 920 can be the drive circuit 700 described above.

[0219] FIG. 10 is a flow chart of a driving method according to an embodiment of the present disclosure.

[0220] As shown in FIG. 10, the driving method can be applied to the shift register 200, the shift register 300 and the shift register 400 described above.

[0221] In the embodiments of the present disclosure, the driving method can include operations S1010 to S1040.

[0222] In operation S1010, a first scan signal is output under the control of a first power voltage, a second power voltage and a first input signal.

[0223] In operation S1020, a shift signal is output under the control of a third power voltage, a fourth power voltage and a second input signal.

[0224] In operation S1030, a second scan signal is output under the control of the second power voltage and the third power voltage.

[0225] In operation S1040, a third scan signal is output under the control of the first power voltage, the fourth power voltage and a third input signal.

[0226] In the embodiments of the present disclosure, S1010 is similar to the operation performed by the first shift register circuit 210 described above, S1020 to S1030 are similar to the operation performed by the second shift register circuit 220 described above, and S1040 is similar to the operation performed by the third shift register circuit 230 described above, which will not be described herein again.

[0227] In the embodiments of the present disclosure, the first level is a low level and the second level is a high level. Those skilled in the art can also set the first level to be a high level and the second level to be a low level according to the type of the transistor in the shift register.

[0228] In the embodiments of the present disclosure, in the first display mode, the fourth power voltage is controlled to be a first voltage so as to output the third scan signal under the control of the first power voltage and the fourth power voltage, and in the second display mode, the fourth power voltage is controlled to be a second voltage so as to output the third scan signal under the control of the first power voltage and the fourth power voltage; wherein the first voltage is less than the second voltage.

[0229] In the embodiments of the present disclosure, the first display mode can be a highlight mode, and the second display mode can be a regular mode. The first voltage can be -12V, and the second voltage can be -9V.

[0230] The computer program product of the first aspect can include one or more non-transitory computer-readable media storing instructions that, when executed, cause one or more processors to perform the operations of the first aspect. The one or more non-transitory computer-readable media can include, for example, magnetic media such as one or more magnetic disks, magnetic tapes or cassettes; optical media such as one or more compact discs (CD), optical discs or discs (for example, DVD, Blu-ray Disc®, digital video disc, ultra density disc, ultra-compact disc, any optical media, etc.); semiconductor media such as solid state hard drives (for example, flash memory, solid state USB drives, etc.); any other suitable medium; or any suitable combination of media.

[0231] Those skilled in the art will understand that features recited in various embodiments and / or claims of the present disclosure can be combined and / or interchanged, even if this is not explicitly stated in the present disclosure. In particular, features recited in various embodiments and / or claims of the present disclosure can be combined and / or interchanged, without departing from the spirit and teachings of the present disclosure. All such combinations and / or interchanges are within the scope of the present disclosure.

[0232] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: a first shift register circuit electrically connected with a first power supply, a second power supply, a first input terminal and a first output terminal, the first shift register circuit being configured to output a first scan signal through the first output terminal under control of a first power supply voltage of the first power supply, a second power supply voltage of the second power supply and a first input signal from the first input terminal; a second shift register circuit electrically connected with the second power supply, a third power supply, a fourth power supply, a shift output terminal, a second input terminal and a second output terminal, the second shift register circuit being configured to output a shift signal through the shift output terminal under control of a third power supply voltage of the third power supply, a fourth power supply voltage of the fourth power supply and a second input signal from the second output terminal, and output a second scan signal through the second output terminal under control of the third power supply voltage and the second power supply voltage; and a third shift register circuit electrically connected with the first power supply, the fourth power supply, a third input terminal and a third output terminal, the third shift register circuit being configured to output a third scan signal through the third output terminal under control of the first power supply voltage, the fourth power supply voltage and a third input signal from the third output terminal. the first shift register circuit is further configured to:

2. The shift register of claim 1, wherein, output the first scan signal under control of a first clock signal from a first clock terminal, wherein a first level of the first clock signal is equal to the first power supply voltage and a second level of the first clock signal is equal to the second power supply voltage. the second shift register circuit is further configured to:

3. The shift register of claim 1, wherein, output the second scan signal under control of a second clock signal from a second clock terminal, wherein a first level of the second clock signal is equal to the third power supply voltage and a second level of the second clock signal is equal to the fourth power supply voltage. the third shift register circuit is further configured to:

4. The shift register of claim 1, wherein, output the third scan signal under control of a third clock signal from a third clock terminal, wherein a first level of the third clock signal is equal to the third power supply voltage and a second level of the third clock signal is equal to the fourth power supply voltage. the third shift register circuit is further configured to:

5. The shift register of claim 1, wherein, output the third scan signal under control of a third clock signal from a third clock terminal, wherein a first level of the third clock signal is equal to the third power supply voltage and a second level of the third clock signal is equal to the second power supply voltage. the second shift register circuit comprises:

6. The shift register of claim 1, wherein, a control unit configured to output the shift signal under control of the third power supply voltage, the fourth power supply voltage and the second input signal, and control potentials of a first node and a second node, and an output unit configured to output the second scan signal under control of the second power supply voltage, the third power supply voltage, the potential of the first node and the potential of the second node. the shift register further comprises:

7. The shift register of claim 1, wherein, ​ A fourth shift register circuit electrically connected with the first power supply, the second power supply, a fourth input terminal and a fourth output terminal, the fourth shift register circuit configured to output a fourth scan signal through the fourth output terminal under the control of the first power supply voltage, the second power supply voltage and a fourth input signal from the fourth input terminal.

8. The shift register of claim 1, wherein, The shift register further comprises: A fifth shift register circuit electrically connected with the first power supply, the second power supply, a fifth input terminal and a fifth output terminal, the fifth shift register circuit configured to output a light emitting control signal through the fifth output terminal under the control of the first power supply voltage, the second power supply voltage and a fifth input signal from the fifth input terminal.

9. The shift register of any of claims 1-8, wherein, The fourth power supply voltage is less than the second power supply voltage.

10. A driving circuit comprising: A first gate driving circuit comprising M first shift register circuits as claimed in any one of claims 1-9 connected in cascade, the first input terminal of the mth first shift register circuit electrically connected with the first output terminal of the (m-1)th first shift register circuit, 1 A second gate driving circuit comprising M second shift register circuits as claimed in any one of claims 1-9 connected in cascade, the second input terminal of the mth second shift register circuit electrically connected with the shift output terminal of the (m-1)th second shift register circuit; and A third gate driving circuit comprising M third shift register circuits as claimed in any one of claims 1-9 connected in cascade, the third input terminal of the mth third shift register circuit electrically connected with the third output terminal of the (m-1)th third shift register circuit.

11. The driving circuit as claimed in claim 10, further comprising: A fourth gate driving circuit comprising M fourth shift register circuits as claimed in any one of claims 1-9 connected in cascade, the fourth input terminal of the mth fourth shift register circuit electrically connected with the fourth output terminal of the (m-1)th fourth shift register circuit; and A light emitting control driving circuit comprising M fifth shift register circuits as claimed in any one of claims 1-9 connected in cascade, the fifth input terminal of the mth fifth shift register circuit electrically connected with the fifth output terminal of the (m-1)th fifth shift register circuit.

12. A display device comprising A display panel; and The driving circuit as claimed in claim 11; wherein, The display panel comprising a plurality of pixel units, the pixel units electrically connected with the first output terminal, the second output terminal, the third output terminal of the driving circuit.

13. A driving method applied to the shift register as claimed in any one of claims 1-9, comprising: outputting a first scan signal under the control of the first power supply voltage, the second power supply voltage and the first input signal; outputting a shift signal under the control of the third power supply voltage, the fourth power supply voltage and the second input signal; outputting a second scan signal under the control of the second power supply voltage and the third power supply voltage; and ​ Output a third scan signal under control of the first power supply voltage, the fourth power supply voltage and the third input signal.

14. The method of claim 13, wherein, The outputting of the third scan signal under control of the first power supply voltage and the fourth power supply voltage comprises: In the first display mode, the fourth power supply voltage is controlled to be a first voltage, so as to output the third scan signal under control of the first power supply voltage and the fourth power supply voltage; and In the second display mode, the fourth power supply voltage is controlled to be a second voltage, so as to output the third scan signal under control of the first power supply voltage and the fourth power supply voltage. The first voltage is less than the second voltage.

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