Pixel circuit, driving method and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a driving method and a display apparatus. The pixel circuit comprises: a light-emitting device; a first driving circuit, which is coupled to the light-emitting device, and is configured to provide, in response to a signal of a light emission control signal terminal, a first driving current to the light-emitting device; and a second driving circuit, which is coupled to the light-emitting device, and is configured to provide, in response to a signal of a pulse width modulation signal terminal, a second driving current to the light-emitting device, wherein the light-emitting device is configured to emit light under the control of at least one of the first driving current and the second driving current, and the current value of the first driving current is different from the current value of the second driving current.

Description

Pixel circuit, driving method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a pixel circuit, a driving method and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED), Mini Light Emitting Diode (Mini LED) and other light emitting devices have the advantages of self-luminescence, low energy consumption, etc., and are one of the hotspots in the field of application research of display devices today. Pixel circuits are used in general display devices to drive light emitting devices to emit light.

[0003] Among them, the Mini LED / Micro LED display device has the advantages of low power consumption, high brightness, high resolution, high color saturation, fast response speed, long service life, high efficiency, etc. Moreover, the Mini LED / Micro LED can realize ultra-large screen display by seamlessly splicing multiple display panels, and has broad application prospects in large-size display scenarios such as command and monitoring centers, commercial centers, high-end conferences, cinemas, and live events. At present, the Mini LED / Micro LED display device still has the problem of relatively high power consumption, and also has the problem of color cast; in terms of seamless splicing of multiple display panels, there may be a picture tearing problem between different display panels.

[0004] SUMMARY

[0005] The pixel circuit provided by the embodiments of the present disclosure comprises:

[0006] a light emitting device;

[0007] a first driving circuit coupled with the light emitting device and configured to provide a first driving current to the light emitting device in response to a signal of a light emitting control signal end;

[0008] a second driving circuit coupled with the light emitting device and configured to provide a second driving current to the light emitting device in response to a signal of a pulse width control signal end;

[0009] the light emitting device is configured to emit light under the control of at least one of the first driving current and the second driving current;

[0010] The current value of the first driving current is different from the current value of the second driving current.

[0011] In some possible implementation manners, the first driving circuit comprises:

[0012] The first driving transistor is configured to generate the first driving current for driving the light emitting device to emit light according to a data voltage signal;

[0013] The first control circuit is coupled with the first driving transistor, and is configured to turn on the gate and the second electrode of the first driving transistor and turn on the first electrode and the first node of the first driving transistor in response to a signal of a first control signal terminal;

[0014] The second control circuit is coupled with the gate of the first driving transistor and the first node, and is configured to provide a signal of a reference voltage signal terminal to a second node in response to a signal of a second control signal terminal, provide a signal of a first power supply terminal to the second node in response to a signal of a light emitting control signal terminal, store a signal of the first node, and couple a signal of the second node to the gate of the first driving transistor;

[0015] The first data writing circuit is coupled with the first node, and is configured to provide the data voltage signal of a data signal terminal to the first node in response to a signal of a first scanning signal terminal;

[0016] The first initialization circuit is coupled with the gate of the first driving transistor, and is configured to provide a signal of an initialization signal terminal to the gate of the first driving transistor in response to a signal of a third control signal terminal;

[0017] The first light emitting control circuit is coupled with the second electrode of the first driving transistor and the light emitting device, and is configured to turn on the second electrode of the first driving transistor and the light emitting device in response to a signal of the light emitting control signal terminal.

[0018] In some possible implementation manners, the first driving circuit further comprises a second driving transistor.

[0019] The gate of the second driving transistor is coupled with the gate of the first driving transistor, and the second electrode of the second driving transistor is coupled with the second electrode of the first driving transistor.

[0020] In some possible implementation manners, the first driving circuit further comprises a second light emitting control circuit.

[0021] The second light-emitting control circuit is coupled with the first electrode of the second drive transistor and is configured to provide a signal of the first power supply end to the first electrode of the second drive transistor in response to a signal of the light-emitting control signal end.

[0022] In some possible implementation manners, the second light-emitting control circuit includes a second light-emitting transistor.

[0023] The gate of the second light-emitting transistor is coupled with the light-emitting control signal end, the first electrode of the second light-emitting transistor is coupled with the first power supply end, and the second electrode of the second light-emitting transistor is coupled with the first electrode of the second drive transistor.

[0024] In some possible implementation manners, the first control circuit includes a first transistor and a second transistor.

[0025] The gate of the first transistor is coupled with the first control signal end, the first electrode of the first transistor is coupled with the gate of the first drive transistor, and the second electrode of the first transistor is coupled with the second electrode of the first drive transistor.

[0026] The gate of the second transistor is coupled with the first control signal end, the first electrode of the second transistor is coupled with the first electrode of the first drive transistor, and the second electrode of the second transistor is coupled with the first node.

[0027] In some possible implementation manners, the second control circuit includes a third transistor, a fourth transistor, a first capacitor and a second capacitor.

[0028] The gate of the third transistor is coupled with the light-emitting control signal end, the first electrode of the third transistor is coupled with the first power supply end, and the second electrode of the third transistor is coupled with the second node.

[0029] The gate of the fourth transistor is coupled with the second control signal end, the first electrode of the fourth transistor is coupled with the reference voltage signal end, and the second electrode of the fourth transistor is coupled with the second node.

[0030] The first electrode of the first capacitor is coupled with the first node, and the second electrode of the first capacitor is coupled with the reference voltage signal end.

[0031] The first electrode of the second capacitor is coupled with the second node, and the second electrode of the second capacitor is coupled with the gate of the first drive transistor.

[0032] In some possible implementation manners, the first data write circuit includes a first data transistor.

[0033] A gate of the first data transistor is coupled to the first scan signal terminal, a first electrode of the first data transistor is coupled to the first node, and a second electrode of the first data transistor is coupled to the data signal terminal.

[0034] In some possible implementations, the first initialization circuit includes a first initialization transistor.

[0035] A gate of the first initialization transistor is coupled to the third control signal terminal, a first electrode of the first initialization transistor is coupled to the gate of the first drive transistor, and a second electrode of the first initialization transistor is coupled to the initialization signal terminal.

[0036] In some possible implementations, the first light emitting control circuit includes a first light emitting transistor.

[0037] A gate of the first light emitting transistor is coupled to the light emitting control signal terminal, a first electrode of the first light emitting transistor is coupled to the second electrode of the first drive transistor, and a second electrode of the first light emitting transistor is coupled to the light emitting device.

[0038] In some possible implementations, the second drive circuit includes:

[0039] A third drive transistor configured to generate, according to a data voltage signal, the second drive current for driving the light emitting device to emit light.

[0040] A third control circuit coupled to the third drive transistor and configured to, in response to a signal of a fourth control signal terminal, turn on a gate and a second electrode of the third drive transistor, and turn on a first electrode of the third drive transistor and a third node.

[0041] A fourth control circuit coupled to the gate of the third drive transistor and the third node and configured to, in response to a signal of a second control signal terminal, provide a signal of a reference voltage signal terminal to a fourth node, in response to a signal of the light emitting control signal terminal, provide a signal of a first power supply terminal to the fourth node, store the signal of the third node, and couple the signal of the fourth node to the gate of the third drive transistor.

[0042] A second data write circuit coupled to the third node and configured to, in response to a signal of a second scan signal terminal, provide the data voltage signal of a data signal terminal to the third node.

[0043] A second initialization circuit coupled to the gate of the third drive transistor and configured to, in response to a signal of a third control signal terminal, provide a signal of an initialization signal terminal to the gate of the third drive transistor.

[0044] A third light emitting control circuit is coupled to the second electrode of the third drive transistor and the light emitting device, and is configured to turn on the second electrode of the third drive transistor and the light emitting device in response to a signal of the pulse width modulation signal terminal.

[0045] In some possible implementation manners, the third control circuit includes a fifth transistor and a sixth transistor.

[0046] The gate electrode of the fifth transistor is coupled to the fourth control signal terminal, the first electrode of the fifth transistor is coupled to the gate electrode of the third drive transistor, and the second electrode of the fifth transistor is coupled to the second electrode of the third drive transistor.

[0047] The gate electrode of the sixth transistor is coupled to the fourth control signal terminal, the first electrode of the sixth transistor is coupled to the first electrode of the third drive transistor, and the second electrode of the sixth transistor is coupled to the third node.

[0048] In some possible implementation manners, the fourth control circuit includes a seventh transistor, an eighth transistor, a third capacitor and a fourth capacitor.

[0049] The gate electrode of the seventh transistor is coupled to the light emitting control signal terminal, the first electrode of the seventh transistor is coupled to the first power supply terminal, and the second electrode of the seventh transistor is coupled to the fourth node.

[0050] The gate electrode of the eighth transistor is coupled to the second control signal terminal, the first electrode of the eighth transistor is coupled to the reference voltage signal terminal, and the second electrode of the eighth transistor is coupled to the fourth node.

[0051] The first electrode of the third capacitor is coupled to the third node, and the second electrode of the third capacitor is coupled to the reference voltage signal terminal.

[0052] The first electrode of the fourth capacitor is coupled to the fourth node, and the second electrode of the fourth capacitor is coupled to the gate electrode of the third drive transistor.

[0053] In some possible implementation manners, the second data writing circuit includes a second data transistor.

[0054] The gate electrode of the second data transistor is coupled to the second scan signal terminal, the first electrode of the second data transistor is coupled to the third node, and the second electrode of the second data transistor is coupled to the data signal terminal.

[0055] In some possible implementation manners, the second initialization circuit includes a second initialization transistor.

[0056] A gate of the second initialization transistor is coupled with the third control signal terminal, a first electrode of the second initialization transistor is coupled with a gate of the third drive transistor, and a second electrode of the second initialization transistor is coupled with the initialization signal terminal.

[0057] In some possible implementation manners, the third light emitting control circuit includes a third light emitting transistor.

[0058] A gate of the third light emitting transistor is coupled with the pulse width control signal terminal, a first electrode of the third light emitting transistor is coupled with a second electrode of the third drive transistor, and a second electrode of the third light emitting transistor is coupled with the light emitting device.

[0059] In some possible implementation manners, the display device further includes a reset circuit coupled with the light emitting device and configured to provide a signal of the initialization signal terminal to the light emitting device in response to a signal of the third control signal terminal.

[0060] In some possible implementation manners, the reset circuit includes a reset transistor.

[0061] A gate of the reset transistor is coupled with the third control signal terminal, a first electrode of the reset transistor is coupled with the light emitting device, and a second electrode of the reset transistor is coupled with the initialization signal terminal.

[0062] The display device provided by the embodiments of the present disclosure includes the pixel circuit.

[0063] The driving method of the pixel circuit provided by the embodiments of the present disclosure includes:

[0064] In the light emitting stage, the first drive circuit provides a first drive current to the light emitting device in response to a signal of the light emitting control signal terminal, and the second drive circuit provides a second drive current to the light emitting device in response to a signal of the pulse width control signal terminal.

[0065] The light emitting device is configured to emit light under control of at least one of the first drive current and the second drive current. BRIEF DESCRIPTION OF DRAWINGS

[0066] FIG. 1 is a structural schematic diagram of a pixel circuit provided by the embodiments of the present disclosure;

[0067] FIG. 2 is another structural schematic diagram of a pixel circuit provided by the embodiments of the present disclosure;

[0068] FIG. 3 is still another structural schematic diagram of a pixel circuit provided by the embodiments of the present disclosure;

[0069] FIG. 4 is still another structural schematic diagram of a pixel circuit provided by the embodiments of the present disclosure;

[0070] FIG. 5 is a timing diagram of some signals according to an embodiment of the present disclosure;

[0071] FIG. 6 is a schematic diagram of an operation according to an embodiment of the present disclosure;

[0072] FIG. 7 is a simulation diagram according to an embodiment of the present disclosure;

[0073] FIG. 8 is another simulation diagram according to an embodiment of the present disclosure;

[0074] FIG. 9 is a diagram of some brightness adjustment according to an embodiment of the present disclosure;

[0075] FIG. 10 is another diagram of some brightness adjustment according to an embodiment of the present disclosure;

[0076] FIG. 11 is yet another diagram of some brightness adjustment according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict, if necessary. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0078] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0079] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the content of the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0080] The display device provided by the embodiments of the present disclosure comprises: a display panel, the display area of the display panel comprises a plurality of pixel units arranged in an array, and each pixel unit comprises a plurality of sub-pixels. For example, each pixel unit comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to realize color display. Alternatively, each pixel unit can comprise a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to realize color display. Of course, the light-emitting color of the sub-pixel in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0081] The pixel circuit provided by the embodiments of the present disclosure comprises:

[0082] a light-emitting device L;

[0083] a first driving circuit 100 coupled to the light-emitting device L and configured to provide a first driving current to the light-emitting device L in response to a signal of a light-emitting control signal end EM;

[0084] a second driving circuit 200 coupled to the light-emitting device L and configured to provide a second driving current to the light-emitting device L in response to a signal of a pulse width control signal end HF;

[0085] the light-emitting device L is configured to emit light under the control of at least one of the first driving current and the second driving current;

[0086] the current value of the first driving current is different from the current value of the second driving current.

[0087] The embodiments of the present disclosure control the light-emitting device to emit light through the cooperation of the first driving circuit and the second driving circuit. That is, the first driving circuit provides a first driving current to the light-emitting device in response to a signal of a light-emitting control signal end EM, the second driving circuit provides a second driving current to the light-emitting device in response to a signal of a pulse width control signal end HF, and the light-emitting device emits light under the control of at least one of the first driving current and the second driving current. The current value of the first driving current is different from the current value of the second driving current. In this way, the current value of the driving current can be controlled by controlling at least one of the signals of the light-emitting control signal end EM and the pulse width control signal end HF, so as to control the brightness of the light-emitting device. Therefore, more accurate Gamma curve and more fine gray scale value can be obtained, so as to avoid color deviation and improve the display quality of the display panel.

[0088] Exemplarily, as shown in FIG. 1, the second electrode of the light emitting device L is coupled with the second power supply end VSS; exemplarily, the light emitting device L can be an electroluminescent diode. For example, the light emitting device L can include at least one of an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), and the like. Exemplarily, the light emitting device L can include an anode, a light emitting layer, and a cathode which are arranged in a stack. Further, the light emitting layer can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. Of course, in actual applications, the specific structure of the light emitting device L can be determined according to the requirements of actual applications, which is not limited herein.

[0089] In some embodiments of the present disclosure, as shown in FIGS. 2 and 3, the first driving circuit 100 includes:

[0090] The first driving transistor T01 is configured to generate a first driving current for driving the light emitting device L to emit light according to a data voltage signal;

[0091] The first control circuit 110 is coupled with the first driving transistor T01 and is configured to turn on the gate and the second electrode of the first driving transistor T01 and turn on the first electrode of the first driving transistor T01 and the first node A in response to a signal of the first control signal end SC1;

[0092] The second control circuit 120 is coupled with the gate of the first driving transistor T01 and the first node A and is configured to provide a signal of the reference voltage signal end Vgh to the second node K1 in response to a signal of the second control signal end SC2, provide a signal of the first power supply end VDD to the second node K1 in response to a signal of the light emitting control signal end EM, store a signal of the first node A, and couple a signal of the second node K1 to the gate of the first driving transistor T01;

[0093] The first data writing circuit 130 is coupled with the first node A and is configured to provide a data voltage signal of the data signal end DA to the first node A in response to a signal of the first scanning signal end SS1;

[0094] The first initialization circuit 140 is coupled with the gate of the first driving transistor T01 and is configured to provide a signal of the initialization signal end Vint to the gate of the first driving transistor T01 in response to a signal of the third control signal end SC3;

[0095] The first light-emitting control circuit 150 is coupled with the second electrode of the first drive transistor T01 and the light-emitting device L, and is configured to turn on the second electrode of the first drive transistor T01 and the light-emitting device L in response to a signal of the light-emitting control signal end EM.

[0096] In some embodiments of the present disclosure, as shown in FIGS. 2 and 3, the first drive circuit 100 further comprises a second drive transistor T02; wherein the gate electrode of the second drive transistor T02 is coupled with the gate electrode of the first drive transistor T01, and the second electrode of the second drive transistor T02 is coupled with the second electrode of the first drive transistor T01.

[0097] The present disclosure can improve the stability of the circuit and reduce the power consumption of the circuit by setting the first drive transistor and the second drive transistor in the first drive circuit to cooperate with each other, and coupling the gate electrode of the second drive transistor with the gate electrode of the first drive transistor, and coupling the second electrode of the second drive transistor with the second electrode of the first drive transistor.

[0098] It should be noted that if a current with a current value of I needs to be output, when two drive transistors are used, the two drive transistors can output currents with a current value of 0.5I respectively, and the channel width-length ratio of the two drive transistors is 5 / 5; but when one drive transistor is used, the drive transistor outputs a current with a current value of I, and the channel width-length ratio of the drive transistor is 10 / 5. Due to the short channel effect of the drive transistor, the drive transistor with a smaller channel width-length ratio W / L has better stability, and therefore, the stability of the drive transistor with a channel width-length ratio of 5 / 5 is better than that of the drive transistor with a channel width-length ratio of 10 / 5. Moreover, the power consumption of the circuit is related to the voltage difference Vds between the source and the drain of the drive transistor, and the greater the voltage difference Vds between the source and the drain of the drive transistor, the greater the power consumption of the circuit. Simulation results prove that the power consumption of the circuit using two parallel drive transistors is less than that of the circuit using one drive transistor, and the power consumption can be reduced by about 16.6%.

[0099] For example, the first drive circuit can not only include two parallel drive transistors, but also include three parallel drive transistors, four parallel drive transistors, five parallel drive transistors, etc., which are not limited herein, and only two parallel drive transistors are taken as an example for description below.

[0100] In some embodiments of the present disclosure, as shown in FIGS. 2 and 3, the first drive circuit 100 further comprises a second light-emitting control circuit 160;

[0101] The second light-emitting control circuit 160 is coupled to the first electrode of the second drive transistor T02 and configured to provide a signal of the first power supply terminal VDD to the first electrode of the second drive transistor T02 in response to a signal of the light-emitting control signal terminal EM.

[0102] In some embodiments of the present disclosure, as shown in FIGS. 2 and 3, the second light-emitting control circuit 160 includes a second light-emitting transistor Tf2, wherein the gate electrode of the second light-emitting transistor Tf2 is coupled to the light-emitting control signal terminal EM, the first electrode of the second light-emitting transistor Tf2 is coupled to the first power supply terminal VDD, and the second electrode of the second light-emitting transistor Tf2 is coupled to the first electrode of the second drive transistor T02.

[0103] For example, the second light-emitting transistor Tf2 can be configured as an N-type transistor, and the active level of the light-emitting control signal is high level and the inactive level of the light-emitting control signal is low level. Alternatively, the second light-emitting transistor Tf2 can be configured as a P-type transistor, and the active level of the light-emitting control signal is low level and the inactive level of the light-emitting control signal is high level.

[0104] In some embodiments of the present disclosure, as shown in FIGS. 2 and 3, the first control circuit 110 includes a first transistor T1 and a second transistor T2, wherein the gate electrode of the first transistor T1 is coupled to the first control signal terminal SC1, the first electrode of the first transistor T1 is coupled to the gate electrode of the first drive transistor T01, the second electrode of the first transistor T1 is coupled to the second electrode of the first drive transistor T01, the gate electrode of the second transistor T2 is coupled to the first control signal terminal SC1, the first electrode of the second transistor T2 is coupled to the first electrode of the first drive transistor T01, and the second electrode of the second transistor T2 is coupled to the first node A.

[0105] For example, the first transistor T1 and the second transistor T2 can be configured as N-type transistors, and the active level of the first control signal is high level and the inactive level of the first control signal is low level. Alternatively, the first transistor T1 and the second transistor T2 can be configured as P-type transistors, and the active level of the first control signal is low level and the inactive level of the first control signal is high level.

[0106] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 3, the second control circuit 120 comprises a third transistor T3, a fourth transistor T4, a first capacitor C1 and a second capacitor C2; a gate of the third transistor T3 is coupled with the light-emitting control signal end EM, a first electrode of the third transistor T3 is coupled with the first power supply end VDD, and a second electrode of the third transistor T3 is coupled with the second node K1; a gate of the fourth transistor T4 is coupled with the second control signal end SC2, a first electrode of the fourth transistor T4 is coupled with the reference voltage signal end Vgh, and a second electrode of the fourth transistor T4 is coupled with the second node K1; a first electrode of the first capacitor C1 is coupled with the first node A, and a second electrode of the first capacitor C1 is coupled with the reference voltage signal end Vgh; a first electrode of the second capacitor C2 is coupled with the second node K1, and a second electrode of the second capacitor C2 is coupled with the gate of the first driving transistor T01.

[0107] Exemplarily, the third transistor T3 can be turned on under the control of the active level of the light-emitting control signal transmitted on the light-emitting control signal end EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the third transistor T3 can be set as an N-type transistor, and the active level of the light-emitting control signal is high level and the inactive level of the light-emitting control signal is low level. Alternatively, the third transistor T3 can be set as a P-type transistor, and the active level of the light-emitting control signal is low level and the inactive level of the light-emitting control signal is high level.

[0108] Exemplarily, the fourth transistor T4 can be turned on under the control of the active level of the second control signal transmitted on the second control signal end SC2, and can be turned off under the control of the inactive level of the second control signal. For example, the fourth transistor T4 can be set as an N-type transistor, and the active level of the second control signal is high level and the inactive level of the second control signal is low level. Alternatively, the fourth transistor T4 can be set as a P-type transistor, and the active level of the second control signal is low level and the inactive level of the second control signal is high level.

[0109] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 3, the first data writing circuit 130 comprises a first data transistor Ts1; a gate of the first data transistor Ts1 is coupled with the first scanning signal end SS1, a first electrode of the first data transistor Ts1 is coupled with the first node A, and a second electrode of the first data transistor Ts1 is coupled with the data signal end DA.

[0110] Exemplarily, the first data transistor Ts1 can be turned on under the control of an effective level of the first scan signal transmitted on the first scan signal end SS1, and can be turned off under the control of an ineffective level of the first scan signal. For example, the first data transistor Ts1 can be set as an N-type transistor, and the effective level of the first scan signal is high level and the ineffective level of the first scan signal is low level. Alternatively, the first data transistor Ts1 can be set as a P-type transistor, and the effective level of the first scan signal is low level and the ineffective level of the first scan signal is high level.

[0111] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 3, the first initialization circuit 140 includes a first initialization transistor Tc1; wherein a gate of the first initialization transistor Tc1 is coupled with the third control signal end SC3, a first pole of the first initialization transistor Tc1 is coupled with the gate of the first drive transistor T01, and a second pole of the first initialization transistor Tc1 is coupled with the initialization signal end Vint.

[0112] Exemplarily, the first initialization transistor Tc1 can be turned on under the control of an effective level of the third control signal transmitted on the third control signal end SC3, and can be turned off under the control of an ineffective level of the third control signal. For example, the first initialization transistor Tc1 can be set as an N-type transistor, and the effective level of the third control signal is high level and the ineffective level of the third control signal is low level. Alternatively, the first initialization transistor Tc1 can be set as a P-type transistor, and the effective level of the third control signal is low level and the ineffective level of the third control signal is high level.

[0113] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 3, the first light-emitting control circuit 150 includes a first light-emitting transistor Tf1; wherein a gate of the first light-emitting transistor Tf1 is coupled with the light-emitting control signal end EM, a first pole of the first light-emitting transistor Tf1 is coupled with the second pole of the first drive transistor T01, and a second pole of the first light-emitting transistor Tf1 is coupled with the light-emitting device L.

[0114] Exemplarily, the first light-emitting transistor Tf1 can be turned on under the control of an effective level of the light-emitting control signal transmitted on the light-emitting control signal end EM, and can be turned off under the control of an ineffective level of the light-emitting control signal. For example, the first light-emitting transistor Tf1 can be set as an N-type transistor, and the effective level of the light-emitting control signal is high level and the ineffective level of the light-emitting control signal is low level. Alternatively, the first light-emitting transistor Tf1 can be set as a P-type transistor, and the effective level of the light-emitting control signal is low level and the ineffective level of the light-emitting control signal is high level.

[0115] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4, the second drive circuit 200 includes:

[0116] The third drive transistor M03 is configured to generate a second drive current for driving the light emitting device L to emit light according to a data voltage signal;

[0117] The third control circuit 210 is coupled to the third drive transistor M03 and configured to turn on the gate and the second electrode of the third drive transistor M03 and turn on the first electrode and the third node B of the third drive transistor M03 in response to a signal of the fourth control signal terminal SC4.

[0118] The fourth control circuit 220 is coupled to the gate of the third drive transistor M03 and the third node B and configured to provide a signal of the reference voltage signal terminal Vgh to the fourth node K2, provide a signal of the first power supply terminal VDD to the fourth node K2 in response to a signal of the light emitting control signal terminal EM, store a signal of the third node B, and couple a signal of the fourth node K2 to the gate of the third drive transistor M03.

[0119] The second data writing circuit 230 is coupled to the third node B and configured to provide a data voltage signal of the data signal terminal DA to the third node B in response to a signal of the second scan signal terminal SS2.

[0120] The second initialization circuit 240 is coupled to the gate of the third drive transistor M03 and configured to provide a signal of the initialization signal terminal Vint to the gate of the third drive transistor M03 in response to a signal of the third control signal terminal SC3.

[0121] The third light emitting control circuit 250 is coupled to the second electrode of the third drive transistor M03 and the light emitting device L and configured to turn on the second electrode of the third drive transistor M03 and the light emitting device L in response to a signal of the pulse width modulation signal terminal HF.

[0122] In some embodiments of the present disclosure, as shown in FIGS. 2 and 4, the third control circuit 210 includes a fifth transistor T5 and a sixth transistor T6; the gate of the fifth transistor T5 is coupled to the fourth control signal terminal SC4, the first electrode of the fifth transistor T5 is coupled to the gate of the third drive transistor M03, and the second electrode of the fifth transistor T5 is coupled to the second electrode of the third drive transistor M03; the gate of the sixth transistor T6 is coupled to the fourth control signal terminal SC4, the first electrode of the sixth transistor T6 is coupled to the first electrode of the third drive transistor M03, and the second electrode of the sixth transistor T6 is coupled to the third node B.

[0123] Exemplarily, the fifth transistor T5 and the sixth transistor T6 can be turned on under the control of the active level of the fourth control signal transmitted on the fourth control signal end SC4, and can be turned off under the control of the inactive level of the fourth control signal. For example, the fifth transistor T5 and the sixth transistor T6 can be set as N-type transistors, and the active level of the fourth control signal is high level and the inactive level of the fourth control signal is low level. Alternatively, the fifth transistor T5 and the sixth transistor T6 can be set as P-type transistors, and the active level of the fourth control signal is low level and the inactive level of the fourth control signal is high level.

[0124] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4, the fourth control circuit 220 includes a seventh transistor T7, an eighth transistor T8, a third capacitor C3 and a fourth capacitor C4. The gate of the seventh transistor T7 is coupled with the light-emitting control signal end EM, the first pole of the seventh transistor T7 is coupled with the first power supply end VDD, and the second pole of the seventh transistor T7 is coupled with the fourth node K2. The gate of the eighth transistor T8 is coupled with the second control signal end SC2, the first pole of the eighth transistor T8 is coupled with the reference voltage signal end Vgh, and the second pole of the eighth transistor T8 is coupled with the fourth node K2. The first electrode of the third capacitor C3 is coupled with the third node B, and the second electrode of the third capacitor C3 is coupled with the reference voltage signal end Vgh. The first electrode of the fourth capacitor C4 is coupled with the fourth node K2, and the second electrode of the fourth capacitor C4 is coupled with the gate of the third driving transistor M03.

[0125] Exemplarily, the seventh transistor T7 can be turned on under the control of the active level of the light-emitting control signal transmitted on the light-emitting control signal end EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the seventh transistor T7 can be set as an N-type transistor, and the active level of the light-emitting control signal is high level and the inactive level of the light-emitting control signal is low level. Alternatively, the seventh transistor T7 can be set as a P-type transistor, and the active level of the light-emitting control signal is low level and the inactive level of the light-emitting control signal is high level.

[0126] Exemplarily, the eighth transistor T8 can be turned on under the control of the active level of the second control signal transmitted on the second control signal end SC2, and can be turned off under the control of the inactive level of the second control signal. For example, the eighth transistor T8 can be set as an N-type transistor, and the active level of the second control signal is high level and the inactive level of the second control signal is low level. Alternatively, the eighth transistor T8 can be set as a P-type transistor, and the active level of the second control signal is low level and the inactive level of the second control signal is high level.

[0127] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4, the second data writing circuit 230 includes a second data transistor Ts2; wherein a gate of the second data transistor Ts2 is coupled with the second scan signal terminal SS2, a first pole of the second data transistor Ts2 is coupled with the third node B, and a second pole of the second data transistor Ts2 is coupled with the data signal terminal DA.

[0128] For example, the second data transistor Ts2 can be set as an N-type transistor, and the effective level of the second scan signal is high level and the ineffective level of the second scan signal is low level. Alternatively, the second data transistor Ts2 can be set as a P-type transistor, and the effective level of the second scan signal is low level and the ineffective level of the second scan signal is high level.

[0129] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4, the second initialization circuit 240 includes a second initialization transistor Tc2; wherein a gate of the second initialization transistor Tc2 is coupled with the third control signal terminal SC3, a first pole of the second initialization transistor Tc2 is coupled with the gate of the third driving transistor M03, and a second pole of the second initialization transistor Tc2 is coupled with the initialization signal terminal Vint.

[0130] For example, the second initialization transistor Tc2 can be set as an N-type transistor, and the effective level of the third control signal is high level and the ineffective level of the third control signal is low level. Alternatively, the second initialization transistor Tc2 can be set as a P-type transistor, and the effective level of the third control signal is low level and the ineffective level of the third control signal is high level.

[0131] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4, the third light emitting control circuit 250 includes a third light emitting transistor Tf3; wherein a gate of the third light emitting transistor Tf3 is coupled with the pulse width control signal terminal HF, a first pole of the third light emitting transistor Tf3 is coupled with the second pole of the third driving transistor M03, and a second pole of the third light emitting transistor Tf3 is coupled with the light emitting device L.

[0132] Exemplarily, the third light-emitting transistor Tf3 can be turned on under the control of the active level of the pulse-width modulation signal transmitted on the pulse-width modulation signal end HF, and can be turned off under the control of the inactive level of the pulse-width modulation signal. For example, the third light-emitting transistor Tf3 can be set as an N-type transistor, and the active level of the pulse-width modulation signal is high level and the inactive level of the pulse-width modulation signal is low level. Alternatively, the third light-emitting transistor Tf3 can be set as a P-type transistor, and the active level of the pulse-width modulation signal is low level and the inactive level of the pulse-width modulation signal is high level.

[0133] In some embodiments of the present disclosure, as shown in FIG. 2, the reset circuit 300 is further coupled with the light-emitting device L and configured to provide the signal of the initialization signal end Vint to the light-emitting device L in response to the signal of the third control signal end SC3.

[0134] In some embodiments of the present disclosure, as shown in FIG. 2, the reset circuit 300 includes a reset transistor T9, wherein the gate of the reset transistor T9 is coupled with the third control signal end SC3, the first pole of the reset transistor T9 is coupled with the light-emitting device L, and the second pole of the reset transistor T9 is coupled with the initialization signal end Vint.

[0135] Exemplarily, the reset transistor T9 can be turned on under the control of the active level of the third control signal transmitted on the third control signal end SC3, and can be turned off under the control of the inactive level of the third control signal. For example, the reset transistor T9 can be set as an N-type transistor, and the active level of the third control signal is high level and the inactive level of the third control signal is low level. Alternatively, the reset transistor T9 can be set as a P-type transistor, and the active level of the third control signal is low level and the inactive level of the third control signal is high level.

[0136] Exemplarily, the first pole of the above-mentioned transistor can be its source pole, and the second pole can be its drain pole. Alternatively, the first pole is its drain pole, and the second pole is its source pole. This is not limited herein.

[0137] Generally, the mobility of the transistor with low temperature poly-silicon (LTPS) material as the active layer is high, and the transistor can be made thinner, smaller and lower in power consumption, etc. In the specific implementation, the material of the active layer of the above-mentioned at least one transistor can be set as low temperature poly-silicon material. In this way, the above-mentioned transistor can be set as an LTPS transistor, so that the pixel circuit can be made with high mobility, thinner, smaller and lower in power consumption, etc.

[0138] Generally, the leakage current of the transistor using metal oxide semiconductor material as the active layer is small, and therefore, in some embodiments of the present disclosure, the material of the active layer of the at least one transistor can also include metal oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide), and of course, other metal oxide semiconductor materials are also possible, which are not limited herein. In this way, the transistor can be configured as an oxide transistor (Oxide Thin Film Transistor), so as to reduce the leakage current of the pixel circuit.

[0139] For example, all the transistors can be configured as LTPS transistors. Alternatively, all the transistors can be configured as oxide transistors. Alternatively, part of the transistors can be configured as oxide transistors, and the remaining transistors can be configured as LTPS transistors. By combining the processes of manufacturing LTPS transistors and oxide transistors, the LTPO pixel circuit of low-temperature polysilicon oxide can be manufactured, so as to reduce the leakage current of the gate of the driving transistor M0 and reduce the power consumption. Therefore, when the pixel circuit is applied to the display panel, the uniformity of the display can be ensured when the display panel displays at a reduced refresh frequency.

[0140] For example, the first power supply end VDD can be configured to load a constant first power supply voltage Vdd, and the first power supply voltage Vdd is generally positive, and the second power supply end VSS can load a constant second power supply voltage Vss, and the second power supply voltage Vss can be a ground voltage or a negative value. In actual applications, the specific values of the first power supply voltage Vdd and the second power supply voltage Vss can be designed and determined according to the actual application environment, which are not limited herein.

[0141] The embodiment of the present disclosure provides a driving method of a pixel circuit, including: a light emitting stage, a first driving circuit provides a first driving current to a light emitting device in response to a signal of a light emitting control signal end; a second driving circuit provides a second driving current to the light emitting device in response to a signal of a pulse width control signal end; and the light emitting device is configured to emit light under the control of at least one of the first driving current and the second driving current.

[0142] For example, as shown in FIG. 5, before the light emitting stage F4, the reset stage F1, the first compensation stage F2 and the second compensation stage F3 are further included.

[0143] The working process of the pixel circuit provided by the embodiment of the present disclosure is described below by taking the pixel circuit shown in FIG. 2 as an example in combination with the signal timing diagram shown in FIG. 5. The working process of the pixel circuit in one display frame 1H is taken as an example for description, wherein one display frame 1H can include a reset stage F1, a first compensation stage F2, a second compensation stage F3, and an emitting stage F4.

[0144] As shown in FIG. 5, sc1 represents a first control signal of a first control signal end SC1, sc2 represents a second control signal of a second control signal end SC2, sc3 represents a third control signal of a third control signal end SC3, sc4 represents a fourth control signal of a fourth control signal end SC4, em represents an emitting control signal of an emitting control signal end EM, hf represents a pulse width modulation signal of a pulse width modulation signal end HF, ss1(1) represents a first scanning signal of a first scanning signal end SS1 of the 1st row, ss2(1) represents a second scanning signal of a second scanning signal end SS2 of the 1st row, ss1(n) represents a first scanning signal of a first scanning signal end SS1 of the n th row, ss2(n) represents a second scanning signal of a second scanning signal end SS2 of the n th row, and da represents a data voltage signal of a data signal end.

[0145] In the reset stage F1, the first transistor T1 is turned off under the control of the high level of the first control signal sc1, the second transistor T2 is turned off under the control of the high level of the first control signal sc1, the third transistor T3 is turned off under the control of the high level of the light emitting control signal em, the fourth transistor T4 is turned on under the control of the low level of the second control signal sc2, the fifth transistor T5 is turned off under the control of the high level of the fourth control signal sc4, the sixth transistor T6 is turned off under the control of the high level of the fourth control signal sc4, the seventh transistor T7 is turned off under the control of the high level of the light emitting control signal em, the eighth transistor T8 is turned on under the control of the low level of the second control signal sc2, the reset transistor T9 is turned on under the control of the low level of the third control signal sc3, the first initialization transistor Tc1 is turned on under the control of the low level of the third control signal sc3, the second initialization transistor Tc2 is turned on under the control of the low level of the third control signal sc3, the first light emitting transistor Tf1 is turned off under the control of the high level of the light emitting control signal em, the second light emitting transistor Tf2 is turned off under the control of the high level of the light emitting control signal em, the third light emitting transistor Tf3 is turned off under the control of the high level of the pulse width modulation signal hf, the first data transistor Ts1 is turned off under the control of the high level of the first scanning signal, and the second data transistor Ts2 is turned off under the control of the high level of the second scanning signal. The fourth transistor T4 that is turned on provides the signal of the reference voltage signal end Vgh to the second node K1, and thus the voltage value Vk1 of the second node K1 is vgh, where vgh represents the voltage value of the signal of the reference voltage signal end Vgh. The eighth transistor T8 that is turned on provides the signal of the reference voltage signal end Vgh to the fourth node K2, and thus the voltage value Vk2 of the fourth node K2 is vgh. The ninth transistor T9 that is turned on provides the signal of the initialization signal end Vint to the anode (for example, the node C in the figure) of the light emitting device L, and thus the voltage value Vc of the anode of the light emitting device L is vint, where vint represents the voltage value of the signal of the initialization signal end Vint. The first initialization transistor Tc1 that is turned on provides the signal of the reference voltage signal end Vgh to the gate (for example, the node G1 in the figure) of the first drive transistor T01, and thus the voltage value Vg1 of the gate of the first drive transistor T01 is vint. The second initialization transistor Tc2 that is turned on provides the signal of the reference voltage signal end Vgh to the gate (for example, the node G2 in the figure) of the third drive transistor T03, and thus the voltage value Vg2 of the gate of the third drive transistor T03 is vint.

[0146] In the first compensation stage F2, the first transistor T1 is turned on under the control of the low level of the first control signal sc1, the second transistor T2 is turned on under the control of the low level of the first control signal sc1, the third transistor T3 is turned off under the control of the high level of the light emitting control signal em, the fourth transistor T4 is turned on under the control of the low level of the second control signal sc2, the fifth transistor T5 is turned off under the control of the high level of the fourth control signal sc4, the sixth transistor T6 is turned off under the control of the high level of the fourth control signal sc4, the seventh transistor T7 is turned off under the control of the high level of the light emitting control signal em, the eighth transistor T8 is turned on under the control of the low level of the second control signal sc2, the reset transistor T9 is turned off under the control of the high level of the third control signal sc3, the first initialization transistor Tc1 is turned off under the control of the high level of the third control signal sc3, the second initialization transistor Tc2 is turned off under the control of the high level of the third control signal sc3, the first light emitting transistor Tf1 is turned off under the control of the high level of the light emitting control signal em, the second light emitting transistor Tf2 is turned off under the control of the high level of the light emitting control signal em, the third light emitting transistor Tf3 is turned off under the control of the high level of the pulse width modulation signal hf, the first data transistor Ts1 is turned off under the control of the high level of the first scanning signal, and the second data transistor Ts2 is turned off under the control of the high level of the second scanning signal. The first capacitor C1 stores the data voltage signal da written to the first node A in the last frame, the turned-on second transistor T2 turns on the first node A and the first electrode (for example, the node S1 in the figure) of the first driving transistor T01, so that the voltage value Vs1 of the first electrode of the first driving transistor T01 is Vda1, wherein Vda1 represents the voltage value of the data voltage signal da; the turned-on first transistor T1 turns on the gate (for example, the node G1 in the figure) and the second electrode (for example, the node D1 in the figure) of the first driving transistor T01, so as to compensate the threshold voltage Vth of the gate of the first driving transistor T01, and the voltage value Vd1 of the second electrode of the first driving transistor T01 is Vda1+Vth, and the voltage value Vg1 of the gate of the first driving transistor T01 is Vda1+Vth; the turned-on fourth transistor T4 provides the signal of the reference voltage signal end Vgh to the second node K1, so that the voltage value Vk1 of the second node K1 is vgh; since the first electrode (for example, the node S2 in the figure) of the third driving transistor T03 is coupled with the first electrode (for example, the node S1 in the figure) of the first driving transistor T01, the voltage value Vs2 of the first electrode of the third driving transistor T03 is vda1; the turned-on eighth transistor T8 provides the signal of the reference voltage signal end Vgh to the fourth node K2, and the voltage value Vk2 of the fourth node K2 is vgh; the voltage value Vg2 of the gate of the third driving transistor T03 still remains vint; and the voltage value Vc of the anode of the light emitting device L still remains vint.

[0147] In the second compensation stage F3, the first transistor T1 is turned off under the control of the high level of the first control signal sc1, the second transistor T2 is turned off under the control of the high level of the first control signal sc1, the third transistor T3 is turned off under the control of the high level of the light-emitting control signal em, the fourth transistor T4 is turned on under the control of the low level of the second control signal sc2, the fifth transistor T5 is turned on under the control of the low level of the fourth control signal sc4, the sixth transistor T6 is turned on under the control of the low level of the fourth control signal sc4, the seventh transistor T7 is turned off under the control of the high level of the light-emitting control signal em, the eighth transistor T8 is turned on under the control of the low level of the second control signal sc2, the reset transistor T9 is turned off under the control of the high level of the third control signal sc3, the first initialization transistor Tc1 is turned off under the control of the high level of the third control signal sc3, the second initialization transistor Tc2 is turned off under the control of the high level of the third control signal sc3, the first light-emitting transistor Tf1 is turned off under the control of the high level of the light-emitting control signal em, the second light-emitting transistor Tf2 is turned off under the control of the high level of the light-emitting control signal em, the third light-emitting transistor Tf3 is turned off under the control of the high level of the pulse width modulation signal hf, the first data transistor Ts1 is turned off under the control of the high level of the first scanning signal, and the second data transistor Ts2 is turned off under the control of the high level of the second scanning signal.The third capacitor C3 stores the data voltage signal da written to the third node B in the last frame. The turned-on sixth transistor T6 connects the first electrode (e.g., node S2 in the figure) of the third driving transistor T03 to the third node B, so that the voltage value Vs2 of the first electrode of the third driving transistor T03 is equal to Vda2, where Vda2 represents the voltage value of the data voltage signal da. The turned-on fifth transistor T5 connects the gate (e.g., node G2 in the figure) of the third driving transistor T03 to the second electrode (e.g., node D2 in the figure), so as to compensate the threshold voltage Vth of the gate of the third driving transistor T03, and thus the voltage value Vd2 of the second electrode of the third driving transistor T03 is equal to Vda2+Vth, and the voltage value Vg2 of the gate of the third driving transistor T03 is equal to Vda2+Vth. The turned-on eighth transistor T8 provides the signal of the reference voltage signal end Vgh to the fourth node K2, so that the voltage value Vk2 of the fourth node K2 is equal to vgh. Since the first electrode (e.g., node S2 in the figure) of the third driving transistor T03 is coupled to the first electrode (e.g., node S1 in the figure) of the first driving transistor T01, the voltage value Vs1 of the first electrode of the first driving transistor T01 is equal to vda2. The turned-on fourth transistor T4 provides the signal of the reference voltage signal end Vgh to the second node K1, and the voltage value Vk1 of the second node K1 is equal to vgh. The voltage value Vg1 of the gate of the first driving transistor T01 remains Vda1+Vth. The voltage value Vd1 of the second electrode of the first driving transistor T01 remains Vda1+Vth. The voltage value Vc of the anode of the light emitting device L remains vint.

[0148] In the light emitting stage F4, the first transistor T1 is turned off under the control of the high level of the first control signal sc1, the second transistor T2 is turned off under the control of the high level of the first control signal sc1, the third transistor T3 is turned on under the control of the low level of the light emitting control signal em, the fourth transistor T4 is turned off under the control of the high level of the second control signal sc2, the fifth transistor T5 is turned off under the control of the high level of the fourth control signal sc4, the sixth transistor T6 is turned off under the control of the high level of the fourth control signal sc4, the seventh transistor T7 is turned on under the control of the low level of the light emitting control signal em, the eighth transistor T8 is turned off under the control of the high level of the second control signal sc2, the reset transistor T9 is turned off under the control of the high level of the third control signal sc3, the first initialization transistor Tc1 is turned off under the control of the high level of the third control signal sc3, the second initialization transistor Tc2 is turned off under the control of the high level of the third control signal sc3, the first light emitting transistor Tf1 is turned on under the control of the low level of the light emitting control signal em, the second light emitting transistor Tf2 is turned on under the control of the low level of the light emitting control signal em, the third light emitting transistor Tf3 is turned on under the control of the low level of the pulse width modulation signal hf, the first data transistor Ts1 is turned on under the control of the low level of the first scanning signal, and the second data transistor Ts2 is turned on under the control of the low level of the second scanning signal.The first data transistor Ts1 in conduction provides the data voltage signal of the data signal terminal DA to the first node A, and the first capacitor C1 stores the signal of the first node A; the second data transistor Ts2 in conduction provides the data voltage signal of the data signal terminal DA to the third node B, and the third capacitor C3 stores the signal of the third node B; the third transistor T3 in conduction provides the signal of the first power supply terminal VDD to the second node K1, and the voltage value Vk1 of the second node K1 is Vdd, wherein Vdd represents the voltage value of the signal of the first power supply terminal VDD; the second capacitor C2 couples the signal of the second node K1 to the gate of the first driving transistor T01 (for example, the node G1 in the figure), and the voltage value Vg1 of the gate of the first driving transistor T01 is vda1+Vth-vgh+Vdd; the seventh transistor T7 in conduction provides the signal of the first power supply terminal VDD to the fourth node K2, and the voltage value Vk2 of the fourth node K2 is Vdd; the fourth capacitor C4 couples the signal of the fourth node K2 to the gate of the third driving transistor M03 (for example, the node G2 in the figure), and the voltage value Vg2 of the gate of the third driving transistor M03 is vda2+Vth-vgh+Vdd; the second light-emitting transistor Tf2 in conduction provides the signal of the first power supply terminal VDD to the first electrode of the second driving transistor T02, and the first light-emitting transistor Tf1 in conduction connects the second electrodes of the first driving transistor T01 and the second driving transistor T02 with the light-emitting device L, that is, provides the first driving current to the light-emitting device L, and drives the light-emitting device L to emit light, and the voltage value Vs1 of the first electrode of the first driving transistor T01 is Vdd, and the voltage value Vd1 of the second electrode of the first driving transistor T01 is Vss+VL+Vem, wherein Vss represents the voltage value of the signal of the second power supply terminal VSS, VL represents the voltage value of the light-emitting device L, and Vem represents the voltage value of the signal of the light-emitting control signal terminal EM; the second light-emitting transistor Tf2 in conduction connects the second electrode of the third driving transistor T03 with the light-emitting device L, that is, provides the second driving current to the light-emitting device L, and drives the light-emitting device L to emit light, and the voltage value Vs2 of the first electrode of the third driving transistor T03 is Vdd, and the voltage value Vd2 of the second electrode of the third driving transistor T03 is Vss+VL+Vhf, wherein Vhf represents the voltage value of the signal of the pulse width control signal terminal HF; the voltage value Vc of the anode of the light-emitting device L is Vss+VL; the first driving transistor T01, the second driving transistor T02 and the third driving transistor T03 all work in the saturation region, and the first driving current generated by the first driving circuit 100. The second driving current generated by the second driving circuit 200 The total driving current finally received by the light-emitting device L Wherein, μ represents the mobility of the driving transistor, Cox represents the unit area capacitance of the gate insulating layer of the driving transistor, and W / L represents the channel width-length ratio of the driving transistor.

[0149] It should be noted that the pixel circuit in the embodiment of the present disclosure shares the same light-emitting control signal end, that is, the entire display panel can emit light at the same time, further avoiding the picture tearing problem between multiple seamlessly spliced display panels, and as shown in FIG. 6, in the light-emitting stage, the light-emitting device emits light at the same time, the scan signal is loaded to each row of scan signal ends, scanning (Scan) is performed, data signal voltage writing (Ddta Writing) is performed, and then the black insertion time can be minimized to avoid flicker.

[0150] In addition, the pixel circuit of the embodiment of the present disclosure realizes compensation of the signal of the first power supply end VDD, and the final driving current Ids is not related to the voltage value Vdd of the signal of the first power supply end VDD, so that the pixel circuit can solve the seamless splicing of multiple display panels, avoid the picture tearing problem between different display panels caused by the difference of the signal of the first power supply end VDD, and avoid the problem of uneven and inconsistent brightness.

[0151] For example, as shown in the simulation curve diagram of FIG. 7, the abscissa V represents the voltage value of the signal of the first power supply end VDD, the ordinate R represents the change rate of brightness, h1 represents the curve obtained by not compensating the signal of the first power supply end VDD, and h2 represents the curve obtained by compensating the signal of the first power supply end VDD. As can be seen from the figure, when the signal of the first power supply end VDD is not compensated, the change rate of brightness is large; when the signal of the first power supply end VDD is compensated, the change rate of brightness is small; that is, by compensating the signal of the first power supply end VDD, the influence of the change of the signal of the first power supply end VDD on the brightness can be avoided.

[0152] For example, as shown in FIG. 8, when the gray scale is low, the signal of the pulse width control signal end HF in the pixel circuit of the embodiment of the present disclosure can be adjusted to control the current value of the second driving current, and then the brightness of the light-emitting device is adjusted; when the gray scale is medium, the signal of the pulse width control signal end HF and the signal of the light-emitting control signal end EM in the pixel circuit of the embodiment of the present disclosure can be adjusted to control the current value of the first driving current and the current value of the second driving current, and then the brightness of the light-emitting device is adjusted; when the gray scale is high, the signal of the pulse width control signal end HF and the signal of the light-emitting control signal end EM in the pixel circuit of the embodiment of the present disclosure can be adjusted to control the current value of the first driving current and the current value of the second driving current, or the signal of the light-emitting control signal end EM can be adjusted to control the current value of the first driving current, and then the brightness of the light-emitting device is adjusted.

[0153] It should be noted that the high gray scale, the middle gray scale and the low gray scale divided according to the Gamma value of different display products are not the same, and the actual display effect needs to be seen, for example, 1-64 is a low gray scale range, 65-128 is a middle gray scale range, and 129-255 is a high gray scale range, which is not limited here.

[0154] For example, by adjusting the signals of the pulse width control signal end HF and the light emitting control signal end EM in the pixel circuit of the embodiment of the present disclosure, the luminance adjustment diagram shown in FIG. 9 can be obtained, L1 and L2 represent different luminance values respectively, t1, t2, t3 and t4 represent different time values respectively, and it can be seen that adjusting the signals of the pulse width control signal end HF and the light emitting control signal end EM at the same time can more finely adjust the luminance change, which is more conducive to the switching of the gray scale. And the overall luminance change value AL satisfies the following formula: AL=L'+L". As shown in the luminance adjustment diagram in FIG. 10, L' represents the luminance change value that can be adjusted by adjusting the signal of the light emitting control signal end EM. As shown in the luminance adjustment diagram in FIG. 11, L" represents the luminance change value that can be adjusted by adjusting the signal of the pulse width control signal end.

[0155] Based on the same disclosure concept, the embodiment of the present disclosure also provides a display device comprising the pixel circuit provided by the embodiment of the present disclosure. The principle of solving the problem of the display device is similar to that of the pixel circuit, and therefore the implementation of the display device can be referred to the implementation of the pixel circuit, and the repeated parts will not be described here.

[0156] In specific implementation, in the embodiment of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those skilled in the art, and will not be described here, nor should they be regarded as a limitation on the present disclosure.

[0157] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0158] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A pixel circuit, wherein, include: Light-emitting devices; A first driving circuit, coupled to the light-emitting device, is configured to provide a first driving current to the light-emitting device in response to a signal at the light-emitting control signal terminal. The second driving circuit, coupled to the light-emitting device, is configured to provide a second driving current to the light-emitting device in response to a signal at the pulse width modulation signal terminal. The light-emitting device is configured to emit light under the control of at least one of the first driving current and the second driving current; The current value of the first driving current is different from the current value of the second driving current.

2. The pixel circuit of claim 1, wherein, The first driving circuit includes: The first driving transistor is configured to generate a first driving current that drives the light-emitting device to emit light according to a data voltage signal; A first control circuit, coupled to the first driving transistor, is configured to, in response to a signal at a first control signal terminal, turn on the gate and second terminal of the first driving transistor, and turn on the first terminal and first node of the first driving transistor. The second control circuit, coupled to the gate of the first driving transistor and the first node, is configured to provide a signal from the reference voltage signal terminal to the second node in response to a signal from the second control signal terminal, provide a signal from the first power supply terminal to the second node in response to a signal from the light emission control signal terminal, store the signal of the first node, and couple the signal of the second node to the gate of the first driving transistor. A first data writing circuit, coupled to the first node, is configured to provide the data voltage signal from the data signal terminal to the first node in response to a signal from the first scan signal terminal. A first initialization circuit, coupled to the gate of the first driving transistor, is configured to provide an initialization signal to the gate of the first driving transistor in response to a signal from a third control signal terminal. A first light-emitting control circuit, coupled to the second terminal of the first driving transistor and the light-emitting device, is configured to conduct the second terminal of the first driving transistor and the light-emitting device in response to a signal at the light-emitting control signal terminal.

3. The pixel circuit of claim 2, wherein, The first driving circuit further includes: a second driving transistor; The gate of the second driving transistor is coupled to the gate of the first driving transistor, and the second terminal of the second driving transistor is coupled to the second terminal of the first driving transistor.

4. The pixel circuit of claim 3, wherein, The first driving circuit further includes: a second light-emitting control circuit; The second light-emitting control circuit, coupled to the first terminal of the second driving transistor, is configured to provide a signal from the first power supply terminal to the first terminal of the second driving transistor in response to a signal from the light-emitting control signal terminal.

5. The pixel circuit of claim 4, wherein, The second light-emitting control circuit includes: a second light-emitting transistor; The gate of the second light-emitting transistor is coupled to the light-emitting control signal terminal, the first terminal of the second light-emitting transistor is coupled to the first power supply terminal, and the second terminal of the second light-emitting transistor is coupled to the first terminal of the second driving transistor.

6. The pixel circuit of any one of claims 2-5, wherein, The first control circuit includes: a first transistor and a second transistor; A gate of the first transistor is coupled with the first control signal terminal, a first electrode of the first transistor is coupled with a gate of the first drive transistor, and a second electrode of the first transistor is coupled with a second electrode of the first drive transistor. A gate of the second transistor is coupled with the first control signal terminal, a first electrode of the second transistor is coupled with the first electrode of the first drive transistor, and a second electrode of the second transistor is coupled with the first node.

7. The pixel circuit of any one of claims 2-6, wherein, The second control circuit includes a third transistor, a fourth transistor, a first capacitor, and a second capacitor. A gate of the third transistor is coupled with the light-emitting control signal terminal, a first electrode of the third transistor is coupled with the first power supply terminal, and a second electrode of the third transistor is coupled with the second node. A gate of the fourth transistor is coupled with the second control signal terminal, a first electrode of the fourth transistor is coupled with the reference voltage signal terminal, and a second electrode of the fourth transistor is coupled with the second node. A first electrode of the first capacitor is coupled with the first node, and a second electrode of the first capacitor is coupled with the reference voltage signal terminal. A first electrode of the second capacitor is coupled with the second node, and a second electrode of the second capacitor is coupled with the gate of the first drive transistor.

8. The pixel circuit of any one of claims 2-7, wherein, The first data write circuit includes a first data transistor. A gate of the first data transistor is coupled with the first scan signal terminal, a first electrode of the first data transistor is coupled with the first node, and a second electrode of the first data transistor is coupled with the data signal terminal.

9. The pixel circuit of any of claims 2-8, wherein, The first initialization circuit includes a first initialization transistor. A gate of the first initialization transistor is coupled with the third control signal terminal, a first electrode of the first initialization transistor is coupled with the gate of the first drive transistor, and a second electrode of the first initialization transistor is coupled with the initialization signal terminal.

10. The pixel circuit of any one of claims 2-9, wherein, The first light-emitting control circuit includes a first light-emitting transistor. A gate of the first light-emitting transistor is coupled with the light-emitting control signal terminal, a first electrode of the first light-emitting transistor is coupled with the second electrode of the first drive transistor, and a second electrode of the first light-emitting transistor is coupled with the light-emitting device.

11. The pixel circuit of any one of claims 1-10, wherein, The second drive circuit includes: a third drive transistor configured to generate, according to a data voltage signal, the second drive current for driving the light-emitting device to emit light; a third control circuit coupled with the third drive transistor and configured to, in response to a signal of a fourth control signal terminal, turn on a gate and a second electrode of the third drive transistor, and turn on a first electrode of the third drive transistor and a third node; a fourth control circuit coupled with the gate of the third drive transistor and the third node and configured to, in response to a signal of a second control signal terminal, provide a signal of a reference voltage signal terminal to a fourth node, in response to a signal of a light-emitting control signal terminal, provide a signal of a first power supply terminal to the fourth node, store a signal of the third node, and couple a signal of the fourth node to the gate of the third drive transistor. The second data writing circuit is coupled with the third node and configured to provide the data voltage signal of the data signal terminal to the third node in response to a signal of a second scan signal terminal; The second initialization circuit is coupled with the gate of the third driving transistor and configured to provide a signal of an initialization signal terminal to the gate of the third driving transistor in response to a signal of a third control signal terminal; The third light emitting control circuit is coupled with the second electrode of the third driving transistor and the light emitting device and configured to turn on the second electrode of the third driving transistor and the light emitting device in response to a signal of the pulse width control signal terminal.

12. The pixel circuit of claim 11, wherein, The third control circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is coupled with the fourth control signal terminal, the first electrode of the fifth transistor is coupled with the gate of the third driving transistor, and the second electrode of the fifth transistor is coupled with the second electrode of the third driving transistor; The gate of the sixth transistor is coupled with the fourth control signal terminal, the first electrode of the sixth transistor is coupled with the first electrode of the third driving transistor, and the second electrode of the sixth transistor is coupled with the third node.

13. The pixel circuit of claim 11 or 12, wherein, The fourth control circuit includes a seventh transistor, an eighth transistor, a third capacitor, and a fourth capacitor; The gate of the seventh transistor is coupled with the light emitting control signal terminal, the first electrode of the seventh transistor is coupled with the first power supply terminal, and the second electrode of the seventh transistor is coupled with the fourth node; The gate of the eighth transistor is coupled with the second control signal terminal, the first electrode of the eighth transistor is coupled with the reference voltage signal terminal, and the second electrode of the eighth transistor is coupled with the fourth node; The first electrode of the third capacitor is coupled with the third node, and the second electrode of the third capacitor is coupled with the reference voltage signal terminal; The first electrode of the fourth capacitor is coupled with the fourth node, and the second electrode of the fourth capacitor is coupled with the gate of the third driving transistor.

14. The pixel circuit of any of claims 11-13, wherein, The second data writing circuit includes a second data transistor; The gate of the second data transistor is coupled with the second scan signal terminal, the first electrode of the second data transistor is coupled with the third node, and the second electrode of the second data transistor is coupled with the data signal terminal.

15. The pixel circuit of any of claims 11-14, wherein, The second initialization circuit includes a second initialization transistor; The gate of the second initialization transistor is coupled with the third control signal terminal, the first electrode of the second initialization transistor is coupled with the gate of the third driving transistor, and the second electrode of the second initialization transistor is coupled with the initialization signal terminal.

16. The pixel circuit of any of claims 11-15, wherein, The third light emitting control circuit includes a third light emitting transistor; The gate of the third light emitting transistor is coupled with the pulse width control signal terminal, the first electrode of the third light emitting transistor is coupled with the second electrode of the third driving transistor, and the second electrode of the third light emitting transistor is coupled with the light emitting device.

17. The pixel circuit of any of claims 1-16, wherein, Further comprising: A reset circuit is coupled with the light emitting device and configured to provide a signal of an initialization signal terminal to the light emitting device in response to a signal of a third control signal terminal.

18. The pixel circuit of claim 17, wherein, The reset circuit comprises a reset transistor; a gate of the reset transistor is coupled with the third control signal terminal, a first pole of the reset transistor is coupled with the light emitting device, and a second pole of the reset transistor is coupled with the initialization signal terminal.

19. A display device comprising: The pixel circuit according to any one of claims 1-18.

20. A driving method of a pixel circuit according to any one of claims 1 to 18, wherein, comprising: a light emitting stage, the first driving circuit providing the first driving current to the light emitting device in response to a signal of the light emitting control signal terminal; the second driving circuit providing the second driving current to the light emitting device in response to a signal of the pulse width modulation signal terminal; the light emitting device is configured to emit light under control of at least one of the first driving current and the second driving current.

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