Link training method, chip, apparatus, and system

Abstract

Embodiments of the present application provide a link training method, a chip, an apparatus, and a system. In the method, a sending end device generates and sends a first link training request to a receiving end PHY chip, the first link training request being used for indicating that the receiving end PHY chip performs link training of a first parameter, the first parameter comprising at least a parameter of a receiving end module, and the parameter of the receiving end module being an optical module parameter; and the sending end device receives first state information, the first state information indicating a state after link training of the first parameter is performed on the basis of the first link training request. Thus, even if the receiving end module in a communication system does not comprise an oDSP chip, the receiving end PHY chip can still implement link training of the parameter in the receiving end module connected to the receiving end PHY chip by means of the interaction of end-to-end link training requests and state information between the sending end device and the receiving end PHY chip, so that the working performance of the communication system is guaranteed.

Description

A link training method, chip, device and system

[0001] The present application claims priority to the Chinese patent application No. 202410601108.X, filed on May 14, 2024, and entitled "A link training method, chip, device and system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, and in particular, to a link training method, chip, device and system. BACKGROUND

[0003] For some high-speed interconnection scenarios, a communication system usually needs to guarantee the working performance of the communication system through link training. The link training needs to be performed on a loop of electrical signals formed in the communication system. For example, for a communication system in which a first network device is connected to a second network device through a first conventional optical module and a second conventional optical module in sequence, since the first conventional optical module and the second conventional optical module each include an optical digital signal processing (oDSP) chip, the oDSP chip has a transmitting end of electrical signals and a receiving end of electrical signals, so the link training can be performed between the first network device and the first conventional optical module in the communication system, and the link training can be performed between the second network device and the second conventional optical module.

[0004] However, in order to reduce the cost and power consumption of the modules connected to the network device, the oDSP chip in the module is removed or part of the oDSP chip in the module is omitted to obtain an improved module. For a communication system including the improved module, since the network device and the module cannot form a loop of electrical signals, the link training currently applicable to the loop of electrical signals cannot be applied.

[0005] Therefore, there is an urgent need to provide a link training scheme applicable to a communication system including an improved module to guarantee the working performance of the communication system. SUMMARY

[0006] Therefore, the present application provides a link training method, chip, device and system, which can perform link training on a communication system including an improved module to improve the performance of the improved module, thereby guaranteeing the working performance of the communication system including the improved module.

[0007] In a first aspect, the application provides a link training method, which is applied to a transmitting end device. The method may, for example, comprise the following steps. First, the transmitting end device generates a first link training request. Next, the transmitting end device sends the first link training request to a receiving end physical layer (Physical, PHY) chip, where the first link training request is used to instruct the receiving end PHY chip to perform link training on a first parameter, and the first parameter may at least include a parameter of a receiving end module, which is an optical module parameter. Then, the transmitting end device receives first status information, which indicates the status of the first parameter after link training based on the first link training request. In this way, even if the receiving end module does not include an oDSP chip, the link training on the parameter in the receiving end module connected to the receiving end PHY chip can be realized through the interaction between the transmitting end device and the receiving end PHY chip in terms of the link training request and the status information. For a communication system that cannot be applied to the current link training (i.e., a communication system including an improved module), effective link training can be realized, so that the working performance of the communication system can be guaranteed.

[0008] It can be understood that the communication system to which the application is directed may include a transmitting end PHY chip, a transmitting end module, a receiving end module and a receiving end PHY chip, where the transmitting end PHY chip is connected to the receiving end PHY chip through the transmitting end module and the receiving end module in sequence. At least one of the transmitting end module and the receiving end module is the improved module mentioned in the application. According to the difference between the transmitting end module and the receiving end module, the communication system has different architectures, and in the communication system with different architectures, the transmitting end device may correspond to the transmitting end PHY chip or the transmitting end module. The transmitting end and the receiving end in the application are described with reference to the direction of the interactive link training request, i.e., the transmitting end device sends a link training request to the receiving end PHY chip, but the link to be trained is the link from the receiving end PHY chip to the transmitting end device.

[0009] In some possible implementations, in one case, the receiving-end module can include an optical module, and the optical module parameter is a parameter in the optical module. For example, the receiving-end module is a linear-drive pluggable optics (LPO, also referred to as a linear direct-drive optical module, or linear optical module), and the optical module parameter can be a parameter in a driver continuous time linear equalizer (DRV_CTLE) in the LPO. In another case, the receiving-end module can also include an active copper cable linear (ACC-Linear) module, and the optical module parameter is a parameter in the ACC-Linear module. It should be noted that the structure of the ACC-Linear module is of the same type as that of the LPO, except that the ACC-Linear module does not include components (such as a laser) for converting an electrical signal into an optical signal and components (such as a photo-diode (PD)) for converting an optical signal into an electrical signal, which are included in the LPO.

[0010] In some possible implementations, for the case where the receiving-end module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the sending-end module connected to the sending-end PHY chip is an LPO, and then the sending-end device can refer to the sending-end PHY chip. As another example, the communication system can be an LPO-retimed optical module (also referred to as a retimed optical module) architecture, that is, the sending-end module connected to the sending-end PHY chip is a retimed optical module, and then the sending-end device can refer to the sending-end PHY chip or the sending-end module. As yet another example, the communication system can be an LPO-LRO architecture, that is, the sending-end module connected to the sending-end PHY chip is an LRO, and then the sending-end device can refer to the sending-end PHY chip or the sending-end module. For the last two examples, whether the sending-end device is the sending-end PHY chip or the sending-end module can depend on whether the oDSP chip in the sending-end module has the capability of receiving and analyzing a training frame. If the oDSP chip has the capability, the sending-end device can be the sending-end module. If the oDSP chip does not have the capability, the sending-end device can be the sending-end PHY chip.

[0011] In some possible implementation, for the case that the receiving end module is LRO, as an example, the communication system can be LRO-LPO architecture, i.e., the transmitting end module connected by the transmitting end PHY chip is LPO, then the transmitting end device is the transmitting end PHY chip; as another example, the communication system can be LRO-retimed architecture, i.e., the transmitting end module connected by the transmitting end PHY chip is retimed optical module, then the transmitting end device is the transmitting end PHY chip or the transmitting end module; as yet another example, the communication system can be LRO-LRO architecture, i.e., the transmitting end module connected by the transmitting end PHY chip is LRO, then the transmitting end device is the transmitting end PHY chip or the transmitting end module. For the last two examples, whether the transmitting end device is the transmitting end PHY chip or the transmitting end module can depend on whether the oDSP chip in the transmitting end module has the capability of transceiving and analyzing training frames, if yes, the transmitting end device can be the transmitting end module, if not, the transmitting end device can be the transmitting end PHY chip.

[0012] In this application, the LRO can include an oDSP chip, the transmitter (TX) of the receiving end PHY chip is connected to the oDSP chip of the LRO, and the receiver (RX) of the transmitting end PHY chip is not connected to the oDSP chip of the LRO.

[0013] In some possible implementation, if the first parameter only includes the parameter of the receiving end module and does not include the parameter of the receiving end PHY chip, as an example, if in the link training process, the transmitting end device not only needs the receiving end PHY chip to perform link training on the parameter of the receiving end module, but also needs the receiving end PHY chip to perform link training on its own parameter, then the method can further include: first, the transmitting end device generates a second link training request, the second link training request is used to instruct the receiving end PHY chip to perform link training on a second parameter, the second parameter includes the parameter of the receiving end PHY chip; then, the transmitting end device sends the second link training request to the receiving end PHY chip; so that after the receiving end PHY chip performs link training on the second parameter according to the second link training request, the transmitting end device receives the second state information sent by the receiving end PHY chip, the second state information indicates the state after the link training on the second parameter based on the second link training request. For example, the parameter of the receiving end PHY chip can include the tap coefficient in the TX-FFE (Forward Feedback Equalizer) of the receiving end PHY chip. In this way, the transmitting end device can instruct the receiving end PHY chip to perform link training on its own parameter and the parameter of the receiving end module respectively through two link training requests.

[0014] In some possible implementation, the first parameter can include parameters of the receiving end module. In this way, the first link training request can indicate the receiving end PHY chip to perform link training on the parameters of the receiving end module.

[0015] In some possible implementation, the sending end device can receive not only the first status information but also test information. In this way, the sending end device can test the link quality of the link from the receiving end PHY chip to the sending end device based on the test information and obtain a test result. In this way, after the link training on the first parameter of the link from the receiving end PHY chip to the sending end device based on the first link training request, the sending end device can accurately know the link quality of the link, which provides a reliable data basis for the next decision of the link training of the link.

[0016] As an example, if the sending-end device determines that the test result does not satisfy the first condition, the method can further include that the sending-end device continues to instruct the receiving-end PHY chip to perform link training on the first parameter. For example, first, the sending-end device generates a third link training request, the third link training request being used to instruct the receiving-end PHY chip to continue to perform link training on the first parameter; then, the sending-end device sends the third link training request to the receiving-end PHY chip; and finally, the sending-end device receives third state information, the third state information indicating a state after the first parameter is subjected to link training based on the third link training request. The first parameter can include a parameter of the receiving-end module and / or a parameter of the receiving-end PHY chip. The first parameter in this case can be the same as or different from the first parameter indicated in the first link training request. Even if the first parameter indicated in the first link training request is the same as that indicated in the third link training request, the adjustment manner of the first parameter indicated in the third link training request can be different from that indicated in the first link training request. The first condition can include any one of the following conditions: a variation of a value of a first quality index is less than or equal to a first threshold, the first quality index being used to represent a link quality of a link from the receiving-end PHY chip to the sending-end device, and a smaller value of the first quality index representing a better link quality, for example, the first quality index being a bit error rate (BER); a variation of a value of a second quality index is greater than or equal to a second threshold, the second quality index being used to represent a link quality of a link from the receiving-end PHY chip to the sending-end device, and a larger value of the second quality index representing a better link quality, for example, the second quality index being a signal-to-noise ratio (SNR). In this way, the sending-end device continues to adjust the receiving-end PHY chip and / or the receiving-end module to implement link training on the link from the receiving-end PHY chip to the sending-end device in the case where it is determined that the test result does not satisfy the first condition (i.e., the parameter adjusted in the current link training is not adjusted to a better state, and the parameter adjusted in the current link training can be continuously optimized).

[0017] As another example, if the sending-end device determines that the test result satisfies the first condition, the method can further include: the sending-end device continues to determine whether the test result satisfies a preset second condition, if yes, it can be considered that the link training this time makes the link from the receiving-end PHY chip to the sending-end device satisfy the expected performance requirement, and there is no need to continue to perform link training on the link from the receiving-end PHY chip to the sending-end device, in this case, the sending-end device can generate local receiving-end preparation information, which is used to indicate that the link training from the receiving-end PHY chip to the sending-end device is completed. In this way, whether the link training of a certain direction of the link is completed can be identified through the second condition, which provides a reliable basis for judging the progress of the link training of the communication system. If not, it can be considered that the link training this time does not make the link from the receiving-end PHY chip to the sending-end device satisfy the expected performance requirement, and it is necessary to continue to perform link training on other parameters of other parts of the link from the receiving-end PHY chip to the sending-end device, in this case, the sending-end device can perform link training on a third parameter, which includes a parameter of a sending-end module, and the parameter of the sending-end module is an optical module parameter. In this way, by performing link training on the parameters of the receiving-end PHY chip and / or the parameters of the receiving-end module first, and then performing link training on the parameters of the sending-end module after the test result satisfies the first condition, and then performing link training on the parameters of the sending-end module until the test result satisfies the second condition, effective link training can be performed on the link from the receiving-end PHY chip to the sending-end device in the communication system. The second condition can include any one of the following conditions: the value of the first quality index is less than or equal to a third threshold value, or the value of the second quality index is greater than or equal to a fourth threshold value, for example, the first quality index is BER, and the second quality index is SNR.

[0018] In some possible implementation manners, the first link training request can be a training frame, and the training frame can include a control field, which is used to indicate that the link training is performed on the first parameter. As an example, the link training performed on the first parameter can be indicated by a plurality of reserved bits in the control field; as another example, the link training performed on the first parameter can also be indicated by a reserved bit in the control field and a coefficient select (coef_sel) field; as yet another example, the link training performed on the first parameter can also be indicated by a reserved value combination of the coefficient select field in the control field.

[0019] In a second aspect, the application further provides a link training method applied to a receiving end PHY chip. The method may, for example, comprise the following steps. First, the receiving end PHY chip receives a first link training request sent by a sending end device, the first link training request being used to instruct the receiving end PHY chip to perform link training on a first parameter, the first parameter comprising a parameter of a receiving end module, and the parameter of the receiving end module being an optical module parameter. The receiving end PHY chip performs link training on the first parameter according to the first link training request. The receiving end PHY chip sends first status information to the sending end device, the first status information indicating a status after the link training on the first parameter based on the first link training request. In this way, even if the oDSP chip is not included in the receiving end module in the communication system, the link training request and the status information can be exchanged between the sending end device and the receiving end PHY chip in an end-to-end manner, so as to realize the link training on the parameter in the receiving end module connected to the receiving end PHY chip. For the communication system (i.e., the communication system including the improved module) that cannot be applied to the current link training, the effective link training can be realized, so as to guarantee the working performance of the communication system.

[0020] In some possible implementation manners, the receiving end module comprises an optical module, and the optical module parameter is a parameter in the optical module; or the receiving end module comprises an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module.

[0021] In some possible implementation manners, for the case where the receiving end module is an LPO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0022] In some possible implementation manners, for the case where the receiving end module is an LRO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0023] In the embodiment of the application, the LRO comprises an optical digital signal processor oDSP chip, the sending end TX of the receiving end PHY chip is connected to the oDSP chip, and the receiving end RX of the receiving end PHY chip is not connected to the oDSP chip.

[0024] In some possible implementation manners, the link training on the first parameter according to the first link training request can include: in response to the first link training request, the receiving end PHY chip performing the link training on the parameter of the receiving end module through an Inter-Integrated Circuit (IIC or I2C) bus.

[0025] In some possible implementation manners, the method can further include: receiving, by the receiving end PHY chip, a second link training request sent by the sending end device, the second link training request being used to instruct the receiving end PHY chip to perform link training on a second parameter, the second parameter including a parameter of the receiving end PHY chip; performing, by the receiving end PHY chip, link training on the second parameter according to the second link training request; and sending, by the receiving end PHY chip, second state information to the sending end device, the second state information being used to indicate a state after the link training on the second parameter based on the second link training request.

[0026] In some possible implementation manners, the first parameter can further include a parameter of the receiving end PHY chip.

[0027] In some possible implementation manners, the first link training request is a training frame, and the training frame includes a control field, the control field being used to instruct the link training on the first parameter. The link training on the first parameter can be instructed through a plurality of reserved bits in the control field, or the link training on the first parameter can be instructed through a reserved bit and a parameter selection field in the control field, or the link training on the first parameter can be instructed through a reserved value combination of the parameter selection field in the control field.

[0028] It should be noted that the related description of the second aspect can be referred to the corresponding description of the first aspect.

[0029] In a third aspect, the present application further provides a chip, which includes an interface circuit and a processing circuit. The processing circuit is configured to generate a first link training request. The interface circuit is configured to send the first link training request to a receiving end PHY chip, the first link training request being used to instruct the receiving end PHY chip to perform link training on a first parameter, the first parameter at least including a parameter of a receiving end module, the parameter of the receiving end module being an optical module parameter. The interface circuit is further configured to receive first state information, the first state information being used to indicate a state after the link training on the first parameter based on the first link training request.

[0030] In some possible implementation manners, in one case, the receiving end module can include an optical module, and the optical module parameter is a parameter in the optical module. For example, the receiving end module is an LPO, and the optical module parameter can be a parameter in DRV_CTLE in the LPO. In another case, the receiving end module can also include an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module.

[0031] In some possible implementation manners, for the case that the receiving end module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the chip protected in the present application is a sending end PHY chip, and the sending end module connected to the sending end PHY chip is an LPO, and then the sending end device can refer to the sending end PHY chip. As another example, the communication system can be an LPO-retimed architecture, that is, the chip protected in the present application is a sending end PHY chip or a chip in a sending end module, and the sending end module connected to the sending end PHY chip is a retimed optical module, and then the sending end device can refer to the sending end PHY chip or the sending end module. As yet another example, the communication system can be an LPO-LRO architecture, that is, the chip protected in the present application is a sending end PHY chip or a chip in a sending end module, and the sending end module connected to the sending end PHY chip is an LRO, and then the sending end device can refer to the sending end PHY chip or the sending end module.

[0032] In some possible implementation manners, for the case that the receiving end module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the chip protected in the present application is a sending end PHY chip, and the sending end module connected to the sending end PHY chip is an LPO, and then the sending end device can refer to the sending end PHY chip. As another example, the communication system can be an LPO-retimed architecture, that is, the chip protected in the present application is a sending end PHY chip or a chip in a sending end module, and the sending end module connected to the sending end PHY chip is a retimed optical module, and then the sending end device can refer to the sending end PHY chip or the sending end module. As yet another example, the communication system can be an LPO-LRO architecture, that is, the chip protected in the present application is a sending end PHY chip or a chip in a sending end module, and the sending end module connected to the sending end PHY chip is an LRO, and then the sending end device can refer to the sending end PHY chip or the sending end module.

[0033] In the present application, the LRO can include an oDSP chip, the TX of the receiving end PHY chip is connected to the oDSP chip of the LRO, and the RX of the sending end PHY chip is not connected to the oDSP chip of the LRO.

[0034] In some possible implementation, the processing circuitry is further configured to generate a second link training request, the second link training request being used to instruct the receiving-end PHY chip to perform link training on a second parameter, the second parameter comprising a parameter of the receiving-end PHY chip; the interface circuitry is further configured to send the second link training request to the receiving-end PHY chip; and the interface circuitry is further configured to receive second status information sent by the receiving-end PHY chip, the second status information indicating a status after the second parameter is subjected to link training based on the second link training request.

[0035] In some possible implementation, the first parameter further comprises a parameter of the receiving-end PHY chip.

[0036] In some possible implementation, the interface circuitry is further configured to receive test information; and the processing circuitry is further configured to test a link quality of a link from the receiving-end PHY chip to the sending-end device based on the test information, and obtain a test result.

[0037] In some possible implementation, the processing circuitry is further configured to, if it is determined that the test result does not satisfy the first condition, generate a third link training request, the third link training request being used to instruct the receiving-end PHY chip to continue performing link training on the first parameter; the interface circuitry is further configured to send the third link training request to the receiving-end PHY chip; and the interface circuitry is further configured to receive third status information, the third status information indicating a status after the first parameter is subjected to link training based on the third link training request.

[0038] As an example, the first condition can comprise any one of the following conditions: a variation of a value of a first quality indicator is less than or equal to a first threshold, the first quality indicator being used to represent a link quality of the link from the receiving-end PHY chip to the sending-end device, and a smaller value of the first quality indicator representing a better link quality; a variation of a value of a second quality indicator is greater than or equal to a second threshold, the second quality indicator being used to represent a link quality of the link from the receiving-end PHY chip to the sending-end device, and a larger value of the second quality indicator representing a better link quality.

[0039] In some possible implementation, the processing circuitry is further configured to, if it is determined that the test result satisfies the first condition but does not satisfy the second condition, perform link training on a third parameter, the third parameter comprising a parameter of a sending-end module, and the parameter of the sending-end module being an optical module parameter.

[0040] As an example, the second condition can include any one of the following conditions: a value of a first quality indicator is less than or equal to a third threshold, the first quality indicator is used to represent a link quality of a link from the receiving-end PHY chip to the sending-end device, and a smaller value of the first quality indicator represents a better corresponding link quality; a value of a second quality indicator is greater than or equal to a fourth threshold, the second quality indicator is used to represent a link quality of a link from the receiving-end PHY chip to the sending-end device, and a greater value of the second quality indicator represents a better corresponding link quality.

[0041] In some possible implementation manners, the first link training request is a training frame, and the training frame includes a control field, the control field being used to indicate that the first parameter is subjected to link training. For example, the first parameter can be indicated to be subjected to link training by a plurality of reserved bits in the control field, or the first parameter can be indicated to be subjected to link training by a reserved bit and a parameter selection field in the control field, or the first parameter can be indicated to be subjected to link training by a reserved value combination of the parameter selection field in the control field.

[0042] It should be noted that the related description of the third aspect can be referred to the corresponding description of the first aspect.

[0043] In a fourth aspect, the present application further provides a chip, which should be a receiving-end PHY chip. The chip includes an interface circuit and a processing circuit. The interface circuit is configured to receive a first link training request sent by a sending-end device, the first link training request being used to indicate that the receiving-end PHY chip performs link training on a first parameter, the first parameter including a parameter of a receiving-end module, and the parameter of the receiving-end module being an optical module parameter. The processing circuit is configured to perform link training on the first parameter according to the first link training request. The interface circuit is further configured to send first state information to the sending-end device, the first state information indicating a state after the link training on the first parameter based on the first link training request.

[0044] In some possible implementation manners, the receiving-end module includes an optical module, and the optical module parameter is a parameter in the optical module; or the receiving-end module includes an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module.

[0045] In some possible implementation manners, for a case where the receiving-end module is an LPO, if the sending-end device is a sending-end PHY chip, the sending-end module connected to the sending-end PHY chip is an LPO; or if the sending-end device is a sending-end PHY chip or a sending-end module, the sending-end module is a traditional optical module or an LRO.

[0046] In another possible implementation, for the case that the receiving end module is an LRO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0047] In the embodiments of the present application, the LRO includes an optical digital signal processor oDSP chip, the sending end TX of the receiving end PHY chip is connected to the oDSP chip, and the receiving end RX of the sending end PHY chip is not connected to the oDSP chip.

[0048] In some possible implementation, the processing circuitry is specifically configured to: in response to the first link training request, perform link training on the parameters of the receiving end module through the IIC bus.

[0049] In some possible implementation, the interface circuitry is further configured to receive a second link training request sent by the sending end device, the second link training request being used to instruct the receiving end PHY chip to perform link training on second parameters, the second parameters including the parameters of the receiving end PHY chip; the processing circuitry is further configured to perform link training on the second parameters according to the second link training request; and the interface circuitry is further configured to send second state information to the sending end device, the second state information indicating a state after the link training on the second parameters based on the second link training request.

[0050] In another possible implementation, the first parameters further include the parameters of the receiving end PHY chip.

[0051] In some possible implementation, the first link training request is a training frame, and the training frame includes a control field, the control field being used to instruct to perform link training on the first parameters. For example, the link training on the first parameters can be instructed through a plurality of reserved bits in the control field; or the link training on the first parameters can be instructed through a reserved bit and a parameter selection field in the control field; or the link training on the first parameters can be instructed through a reserved value combination of the parameter selection field in the control field.

[0052] It should be noted that the related description of the fourth aspect can be referred to the corresponding description of the second aspect.

[0053] In a fifth aspect, the present application also provides a link training apparatus, which is applied to a sending end device. The apparatus may, for example, include a processing unit, a sending unit and a receiving unit. The processing unit is configured to generate a first link training request. The sending unit is configured to send the first link training request to a receiving end PHY chip, where the first link training request is used to instruct the receiving end PHY chip to perform link training on a first parameter. The first parameter may, for example, include a parameter of a receiving end module, and the receiving end module may, for example, be an optical module. The receiving unit is configured to receive first status information, where the first status information is used to indicate a status of the first parameter after the link training based on the first link training request.

[0054] In some possible implementation manners, in one case, the receiving end module may, for example, include an optical module, and the optical module parameter may, for example, be a parameter in the optical module. For example, the receiving end module may, for example, be an LPO, and the optical module parameter may, for example, be a parameter in a DRV_CTLE in the LPO. In another case, the receiving end module may, for example, include an ACC-Linear module, and the optical module parameter may, for example, be a parameter in the ACC-Linear module.

[0055] In some possible implementation manners, for the case where the receiving end module is an LPO, as an example, the communication system may, for example, be an LPO-LPO architecture, where the sending end module connected to the sending end PHY chip is an LPO. In this case, the sending end device may, for example, be the sending end PHY chip. As another example, the communication system may, for example, be an LPO-retimed architecture, where the sending end module connected to the sending end PHY chip is a retimed optical module. In this case, the sending end device may, for example, be the sending end PHY chip or the sending end module. As yet another example, the communication system may, for example, be an LPO-LRO architecture, where the sending end module connected to the sending end PHY chip is an LRO. In this case, the sending end device may, for example, be the sending end PHY chip or the sending end module.

[0056] In some possible implementation manners, for the case where the receiving end module is an LRO, as an example, the communication system may, for example, be an LRO-LPO architecture, where the sending end module connected to the sending end PHY chip is an LPO. In this case, the sending end device may, for example, be the sending end PHY chip. As another example, the communication system may, for example, be an LRO-retimed architecture, where the sending end module connected to the sending end PHY chip is a retimed optical module. In this case, the sending end device may, for example, be the sending end PHY chip or the sending end module. As yet another example, the communication system may, for example, be an LRO-LRO architecture, where the sending end module connected to the sending end PHY chip is an LRO. In this case, the sending end device may, for example, be the sending end PHY chip or the sending end module.

[0057] In the present application, the LRO can include an oDSP chip, the TX of the receiving end PHY chip is connected to the oDSP chip of the LRO, and the RX of the sending end PHY chip is not connected to the oDSP chip of the LRO.

[0058] In some possible implementation ways, the processing unit is further configured to generate a second link training request, the second link training request being used to instruct the receiving end PHY chip to perform link training on a second parameter, the second parameter including a parameter of the receiving end PHY chip; the sending unit is further configured to send the second link training request to the receiving end PHY chip; and the receiving unit is further configured to receive second state information sent by the receiving end PHY chip, the second state information indicating a state after the second parameter is subjected to link training based on the second link training request.

[0059] In some possible implementation ways, the first parameter further includes a parameter of the receiving end PHY chip.

[0060] In some possible implementation ways, the receiving unit is further configured to receive test information; and the processing unit is further configured to test a link quality of a link from the receiving end PHY chip to the sending end device based on the test information, and obtain a test result.

[0061] In some possible implementation ways, the processing unit is further configured to generate a third link training request if it is determined that the test result does not satisfy the first condition, the third link training request being used to instruct the receiving end PHY chip to continue to perform link training on the first parameter; the sending unit is further configured to send the third link training request to the receiving end PHY chip; and the receiving unit is further configured to receive third state information, the third state information indicating a state after the first parameter is subjected to link training based on the third link training request.

[0062] As an example, the first condition can include any one of the following conditions: a variation of a value of a first quality index is less than or equal to a first threshold, the first quality index being used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and the smaller the value of the first quality index, the better the corresponding link quality; a variation of a value of a second quality index is greater than or equal to a second threshold, the second quality index being used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and the greater the value of the second quality index, the better the corresponding link quality.

[0063] In some possible implementation ways, the processing unit is further configured to perform link training on a third parameter if it is determined that the test result satisfies the first condition but does not satisfy the second condition, the third parameter including a parameter of a sending end module, and the parameter of the sending end module being an optical module parameter.

[0064] As an example, the second condition can include any one of the following conditions: a value of the first quality indicator is less than or equal to a third threshold, the first quality indicator is used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and the smaller the value of the first quality indicator, the better the corresponding link quality is represented; a value of the second quality indicator is greater than or equal to a fourth threshold, the second quality indicator is used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and the greater the value of the second quality indicator, the better the corresponding link quality is represented.

[0065] In some possible implementation manners, the first link training request is a training frame, and the training frame includes a control field, the control field being used to indicate that the first parameter is subjected to link training. For example, the first parameter subjected to link training can be indicated by a plurality of reserved bits in the control field, or the first parameter subjected to link training can be indicated by a reserved bit and a parameter selection field in the control field, or the first parameter subjected to link training can be indicated by a reserved value combination of the parameter selection field in the control field.

[0066] It should be noted that the related description of the fifth aspect can be referred to the corresponding description of the first aspect.

[0067] In a sixth aspect, the present application further provides a link training apparatus, which should be a receiving end PHY chip. The apparatus can at least include a receiving unit, a sending unit and a processing unit. The receiving unit is used to receive a first link training request sent by a sending end device, the first link training request being used to instruct the receiving end PHY chip to perform link training on a first parameter, the first parameter including a parameter of a receiving end module, and the parameter of the receiving end module being an optical module parameter; the processing unit is used to perform link training on the first parameter according to the first link training request; and the sending unit is used to send first state information to the sending end device, the first state information indicating a state after the first parameter is subjected to link training based on the first link training request.

[0068] In some possible implementation manners, the receiving end module includes an optical module, and the optical module parameter is a parameter in the optical module; or the receiving end module includes an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module.

[0069] In some possible implementation manners, for a case where the receiving end module is an LPO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; or if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0070] In another possible implementation, for the case that the receiving end module is an LRO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0071] In the embodiment of the application, the LRO includes an optical digital signal processor oDSP chip, the sending end TX of the receiving end PHY chip is connected to the oDSP chip, and the receiving end RX of the sending end PHY chip is not connected to the oDSP chip.

[0072] In some possible implementation, the processing unit is specifically configured to: in response to the first link training request, perform link training on the parameters of the receiving end module through the IIC bus.

[0073] In some possible implementation, the receiving unit is further configured to receive a second link training request sent by the sending end device, the second link training request being used to instruct the receiving end PHY chip to perform link training on second parameters, the second parameters including the parameters of the receiving end PHY chip; the processing unit is further configured to perform link training on the second parameters according to the second link training request; and the sending unit is configured to send second state information to the sending end device, the second state information being used to indicate a state after the link training on the second parameters based on the second link training request.

[0074] In another possible implementation, the first parameters further include the parameters of the receiving end PHY chip.

[0075] In some possible implementation, the first link training request is a training frame, and the training frame includes a control field, the control field being used to instruct to perform link training on the first parameters. For example, the link training on the first parameters can be instructed through a plurality of reserved bits in the control field; or the link training on the first parameters can be instructed through a reserved bit and a parameter selection field in the control field; or the link training on the first parameters can be instructed through a reserved value combination of the parameter selection field in the control field.

[0076] It should be noted that the related description of the sixth aspect can be referred to the corresponding description of the second aspect.

[0077] In a seventh aspect, the application provides a communication device, the communication device including an interface and a processor. The interface is configured to receive an instruction and transmit the instruction to the processor; and the processor is configured to execute the method of the first aspect, the second aspect and the possible implementation manners thereof.

[0078] In an eighth aspect, the present application provides a communication system, which comprises a sending device and a receiving PHY chip. The sending device is configured to perform the method of the first aspect and possible implementation manners thereof. The receiving PHY chip is configured to perform the method of the second aspect and possible implementation manners thereof.

[0079] In the eighth aspect, the present application further provides a storage medium, which stores instructions, and when the instructions are run on a processor, the method of the first aspect, the second aspect and possible implementation manners thereof is implemented.

[0080] In the ninth aspect, the present application further provides a program product, which comprises a program, and when the program is run on a processor, the method of the first aspect, the second aspect and possible implementation manners thereof is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0081] FIG. 1 is a structural schematic diagram of a communication system with a retimed-retimed architecture according to an embodiment of the present application;

[0082] FIG. 2a is a structural schematic diagram of a communication system with an LPO-LPO architecture according to an embodiment of the present application;

[0083] FIG. 2b is a structural schematic diagram of a communication system with an LRO-LRO architecture according to an embodiment of the present application;

[0084] FIG. 3 is a structural schematic diagram of a communication system with a C2C architecture according to an embodiment of the present application;

[0085] FIG. 4 is a schematic diagram of a general structure of a communication system according to an embodiment of the present application;

[0086] FIG. 5 is a flow schematic diagram of a link training method 100 according to an embodiment of the present application;

[0087] FIG. 6 is a flow schematic diagram of an example of a link training method according to an embodiment of the present application;

[0088] FIG. 7 is a structural schematic diagram of a communication system with a retimed-LPO architecture according to an embodiment of the present application;

[0089] FIG. 8 is a structural schematic diagram of a communication system with a retimed-LRO architecture according to an embodiment of the present application;

[0090] FIG. 9 is a structural schematic diagram of a communication system with an LRO-LPO architecture according to an embodiment of the present application;

[0091] FIG. 10 is a structural schematic diagram of a chip 1000 according to an embodiment of the present application;

[0092] FIG. 11 is a schematic diagram of a structure of a communication device 1100 according to an embodiment of the present application;

[0093] FIG. 12 is a schematic diagram of a structure of a communication device 1200 according to an embodiment of the present application;

[0094] FIG. 13 is a schematic diagram of a structure of a communication system 1300 according to an embodiment of the present application. DETAILED DESCRIPTION

[0095] In order to ensure the working performance of a communication system, a communication standard (for example, Institute of Electrical and Electronics Engineers (IEEE) 802.3 CL72, CL136 and CL162, and for example, Common Management Interface Specification (CMIS) protocol of Optical Internetworking Forum (OIF)) defines the related content of link training. Link training can be understood as an important stage for preparing the running of a communication system, which is used to complete the tuning and configuration of to-be-configured parameters including equalization parameters for a telecommunication signal loop constituted in the communication system before the communication system is running. The standard is called link training (LT). Link training can be divided into three steps: first, frame locking, which can be understood as the identification of a training frame; second, training process, which is used to complete the interaction and negotiation of parameters; and third, the update of parameters. It should be noted that the embodiments of the present application do not involve the improvement of the above three steps of link training, so the three steps will not be described.

[0096] Currently, in some communication scenarios, the architecture of a communication system is usually as shown in FIG. 1. The communication system can include a network device 1, a traditional optical module (also referred to as a retimed optical module) 1, a traditional optical module 2, and a network device 2. The traditional optical module 1 can at least include an oDSP chip 11, a laser driver (Laser DRV) 12, a laser 13, a PD 14, and a trans-impedance amplifier (TIA) 15. Similarly, the traditional optical module 2 can at least include an oDSP chip 21, a Laser DRV 22, a laser 23, a PD 24, and a TIA 25. Link training for the communication system of FIG. 1 (which can be referred to as a retimed-retimed architecture communication system) can include link training for an electrical signal loop 1 between the network device 1 and the traditional optical module 1, and link training for an electrical signal loop 2 between the network device 2 and the traditional optical module 2. The electrical signal loop 1 can refer to a loop from a TX 1 of a PHY chip 1 of the network device 1, through an RX 11 of the oDSP chip 11 of the traditional optical module 1 close to the network device 1 and a TX 14 of the oDSP chip 11 of the traditional optical module 1 close to the network device 1 in sequence, to an RX 2 of the PHY chip 1 of the network device 1. Similarly, the electrical signal loop 2 can refer to a loop from a TX 3 of a PHY chip 2 of the network device 2, through an RX 21 of the oDSP chip 21 of the traditional optical module 2 close to the network device 2 and a TX 24 of the oDSP chip 21 of the traditional optical module 2 close to the network device 2 in sequence, to an RX 4 of the PHY chip 2 of the network device 2. The oDSP chip 11 can further include a TX 12 and an RX 13 close to the traditional optical module 2, and the oDSP chip 21 can further include a TX 22 and an RX 23 close to the traditional optical module 1. Taking the electrical signal loop 1 as an example, data interaction between the network device 1 and the oDSP chip 11 of the traditional optical module 1 can be implemented through different buses under different standards. For example, for relevant provisions in IEEE 802.3, data interaction between the network device 1 and the oDSP chip 11 of the traditional optical module 1 can be implemented through a chip-to-module (C2M) bus; for example, for relevant provisions of the CMIS protocol of OIF, data interaction between the network device 1 and the oDSP chip 11 of the traditional optical module 1 can be implemented through a two-wire interface (TWI, also referred to as an Inter-Integrated Circuit (IIC or I2C)) bus in an out-of-band manner.

[0097] It should be noted that for the retimed-retimed architecture communication system, the link training can be performed on the electrical signal loop 1 and the electrical signal loop 2 respectively, because the oDSP chip is included in the traditional optical module 1 and the traditional optical module 2, so that the electrical signal loop can be formed between the network device and the oDSP chip of the traditional optical module. However, considering that the oDSP chip in the traditional optical module has high power consumption, accounting for more than 50% of the power consumption of the traditional optical module, and the cost of the oDSP chip is also high, therefore, the LPO is born. Since the LPO adopts a linear optical engine interface to connect with the network device, and the linear optical engine interface has significant advantages in power consumption, cost, delay and the like, therefore, the LPO is likely to be widely used in future high-speed interconnected communication systems.

[0098] The LPO can at least include a Laser DRV, a Laser, a PD and a TIA. Compared with the traditional optical module, the oDSP chip in the traditional optical module is removed, and the equalization capability of the oDSP chip is offloaded to the SerDes on the ASIC side of the network device to which the LPO is connected. The LPO can integrate a CTLE to compensate for channel impairment, and the SerDes on the ASIC side of the network device to which the LPO is connected includes an FFE to reduce the BER of the link through stronger equalization performance. The equalization parameters to be configured are more and are coupled with each other, and the influence of each equalization parameter on the end-to-end communication link needs to be considered.

[0099] If the traditional optical module in the communication system shown in FIG. 1 is replaced by the LPO, then the communication system can refer to FIG. 2a (which can be referred to as an LPO-LPO architecture communication system). Since the LPO 1 does not include an oDSP chip, the electrical signal from the network device 1 to the LPO 1 will be converted into an optical signal through the Laser DRV 12 and the Laser 13, and cannot be directly converted back to the network device 1 in the form of an electrical signal, so that the electrical signal loop cannot be formed between the network device and the LPO 1. Therefore, the link training scheme for the retimed-retimed architecture communication system cannot be applied to the link training of the LPO-LPO architecture communication system.

[0100] In addition, in some current communication scenarios, a communication system from network device 1 to network device 2 (which can be referred to as a chip to chip (C2C) communication system) can also be included, as shown in FIG. 3. For the C2C communication system, link training can be directly performed on the electrical signal loop 3 between network device 1 and network device 2. However, since the C2C communication system does not involve an optical module, the link training for the C2C communication system does not include a training process for equalization parameters in the optical module, and for a communication system of an LPO-LPO architecture, it is equivalent to not considering the influence of the equalization parameters in the line LPO on the entire communication system, so the link training for the C2C communication system cannot be applied to the link training for the communication system of the LPO-LPO architecture.

[0101] Since the oDSP chip is not included in the LPO, the performance of the sending end of the communication system including the LPO (such as the communication system of the LPO-LPO architecture) (such as the performance of the Testpoint (TP) 2 point) is not ideal. Based on this, the embodiments of the present application provide a link training method, which is at least applicable to a communication system including an LPO (such as a communication system of an LPO-LPO architecture), so that the communication system including the LPO performs link training through the link training method provided by the embodiments of the present application. In the communication system in which the link training is completed, the performance of the LPO is improved, thereby improving the working performance of the communication system including the LPO, so that the communication system including the LPO can be widely used in future high-speed interconnection communication systems. Wherein, the TP2 point refers to the light output point of the optical module defined in IEEE 802.3. Taking FIG. 2a as an example, in the link from network device 1 to network device 2 through LPO 1 and LPO 2, the TP2 point can refer to the position of the light output point of Laser 13; in the link from network device 2 to network device 1 through LPO 2 and LPO 1, the TP2 point can refer to the position of the light output point of Laser 23. In IEEE 802.3, not only is the TP2 point defined, but also requirements for the TP2 point are proposed as a basis for judging whether the performance of the communication system (such as the performance of the sending end of the communication system) is ideal.

[0102] The communication system architecture to which the link training method provided in the embodiments of the present application is applicable can be referred to FIG. 4. Referring to FIG. 4, the communication system can include a network device A (which can also be referred to as a host A, hereinafter referred to as HA), a module A (which can also be referred to as a Module A, hereinafter referred to as MA), a module B (which can also be referred to as a Module B, hereinafter referred to as MB), and a network device B (which can also be referred to as a Host B, hereinafter referred to as HB), wherein the HA is connected to the HB through the MA and the MB in sequence. The HA can be connected to the MA through an IIC bus, or can be connected to the MA through a bidirectional data interface. The IIC bus can be used to implement parameter configuration of the HA to the MA, and the data interface can be used to implement sending and receiving of service data between the HA and the MA. Similarly, the HB can also be connected to the MB through an IIC bus, or can be connected to the MB through a bidirectional data interface. It should be noted that at least one of the MA and the MB is an improved optical module (such as an LPO) obtained by improving a traditional optical module. It should be noted that the network device can be referred to as a host. From the hardware implementation, it can be understood that the network device can be implemented through a PHY chip, and therefore the network device can also be a PHY chip.

[0103] The implementation of the link training method provided in the embodiments of the present application will be described below in combination with FIG. 4.

[0104] It should be noted that the link training process of the link from the HB to the HA in FIG. 4 is taken as an example for description in the following, the sending end device corresponds to the PHY chip of the HA or the MA, and the receiving end PHY chip corresponds to the PHY chip of the HB. The link training method provided in the embodiments of the present application can include, for example: first, the HA generates a link training request 1 and sends the link training request 1 to the PHY chip of the HB, the link training request 1 is used to instruct the PHY chip of the HB to perform link training on a first parameter, the first parameter can include at least a parameter of the MB, and the parameter of the MB is an optical module parameter; then, the PHY chip of the HB performs link training on the first parameter based on the received link training request 1, and obtains state information 1, the state information 1 indicates a state after the link training on the first parameter based on the link training request 1; and then, the HA receives the state information 1. In this way, even if the receiving end module in the communication system does not include an oDSP chip, the link training of the receiving end PHY chip on the parameters in the receiving end module connected to the receiving end PHY chip can also be implemented through the interaction of the end-to-end link training request and the state information, for example, the PHY chip of the HB performs link training on the parameters of the end-to-end link from the HB to the HA including the parameter of the MB based on the instruction of the HA. In this way, for the communication system which cannot be applied to the current link training, effective link training can be implemented, so that the working performance of the communication system is guaranteed.

[0105] The optical module parameters can refer to parameters used in the optical module or the ACC-Linear module. It should be noted that the ACC-Linear module is different from the LPO in that there is no device (such as a laser and a PD) for converting an electrical signal into an optical signal, and the ACC-Linear module can include, for example, a linear equalization chip for improving the equalization performance of a signal. If the MA is an ACC-Linear module and the MB is also an ACC-Linear module, the optical module parameters can be parameters of a CTLE in a Laser DRV in the LPO when the receiving end module is an LPO. For example, when the receiving end module is an ACC-Linear module, the optical module parameters can be equalizer parameters in a linear equalization chip in the ACC-Linear module. Hereinafter, the receiving end module is taken as an example to describe the ACC-Linear module, and the ACC-Linear module is replaced by the LPO, which does not affect the description of the link training process of the communication system.

[0106] The parameters of the MB can include parameters of the MB that need to be subjected to link training. For example, the MB can be the LPO 2 shown in FIG. 2a, and the parameters of the MB can include equalizer parameters in the Laser DRV 22 of the LPO 2. The state information 1 can be used to indicate the result of the link training of the first parameters by the HB. For example, the state information 1 can include specific parameters modified by the HB for the MB and the degree of modification when the HB performs link training on the first parameters.

[0107] It should be noted that the HA sends a link training request 1 to the PHY chip of the HB to instruct the PHY chip of the HB to perform link training on the first parameters. In response to the link training request 1, the PHY chip of the HB performs link training on the first parameters on the TX side, and the first parameters include parameters on the TX side of the MB. Through the link training on the first parameters, the link quality from the PHY chip of the HB to the HA is improved. Therefore, the link training on the first parameters is essentially link training on the link from the PHY chip of the HB to the HA. Based on this, it can be understood that the link training on the first parameters by the receiving end PHY chip is essentially link training on the link from the receiving end PHY chip to the sending end device.

[0108] For the link training request, it can include but is not limited to: parameter adjustment type, specific parameter to be adjusted, and adjustment value. For the case of the training frame corresponding to the link training request, the content included in the above link training request can be embodied by the control field in the training frame. For example, the parameter adjustment type can indicate individual coefficient control, and when the initial condition request (ic_req) field in the control field = 00, it indicates that the parameter adjustment type is individual coefficient control. The specific parameter to be adjusted can be indicated by the coefficient selection (coef_sel) field. By different values of the coef_sel field, different parameters are adjusted. The adjustment value can be understood as the adjustment step (or step value), which can be +3, -2, etc. The adjustment value will affect the performance of the equalizer in the receiving end module, so as to change the performance curve of the equalizer by the adjustment value of the equalizer parameter.

[0109] For the state information, it can include but is not limited to: adjustment result corresponding to the link training, specific parameter to be adjusted, and state of the specific parameter to be adjusted. For the case of the training frame corresponding to the state information, the content included in the above state information can be embodied by the status field in the training frame. Among them, the adjustment result corresponding to the link training can indicate whether the parameter to be adjusted corresponding to a certain link training request is completed, the specific parameter to be adjusted can indicate the parameter actually adjusted in the process of responding to a certain link training request for link training, and the state of the specific parameter to be adjusted can indicate whether the parameter to be adjusted is adjusted to the limit (i.e. the boundary or boundary range of the possible value of the parameter). It should be noted that in addition to receiving the state information, the training frame corresponding to the state information can also include test information. The test information can be the training pattern field in the training frame. The training pattern field can be understood as a test sequence, which is used by the sending end device to test the link quality of the link transmitting the training frame. Since the link is in the state after responding to the link training request and adjusting the first parameter, testing the link quality of the link is equivalent to obtaining the training effect of this link training, which can provide reliable data basis for the next decision of the link training of the link.

[0110] It should be noted that the communication system mentioned above including the LPO can refer to at least one module connected with the PHY chip in the communication system, and is an improved optical module obtained by improving the traditional optical module. Compared with the traditional optical module, the improved optical module cancels the oDSP chip in the traditional optical module or omits part of the oDSP chip in the traditional optical module. The optical module canceling the oDSP chip can be the LPO, such as the LPO 1 or the LPO 2 shown in FIG. 2a; the optical module omitting part of the oDSP chip can be a transmit retimed optics (TRO, also referred to as a Tx-retimed optical module or an LRO, which is explained below as an LRO). The LRO can also be understood as: an optical module including an oDSP chip, a network device connected with the optical module including a TX and a RX, the TX of the network device being connected with the oDSP chip of the optical module, and the RX of the network device not being connected with the oDSP chip of the optical module, such as the LRO 1 or the LRO 2 shown in FIG. 2b. In some other cases, the LRO can also include a complete oDSP chip, and the structure can refer to the traditional optical module 1 or the traditional optical module 2 shown in FIG. 1, but in some cases, such as when the end-to-end link training process provided in the present application is implemented, the oDSP chip connected with the RX of the network device is closed, and the actual working structure can refer to the LRO 1 or the LRO 2 shown in FIG. 2b.

[0111] FIG. 2b shows a communication system of an LRO-LRO architecture, in which the LPO in FIG. 2a can be replaced by an LRO. The LRO 1 includes an oDSP chip 11, and compared with the oDSP chip 11 shown in FIG. 1, only includes the RX 11 close to the network device 1 and the TX 12 close to the LRO 2. Similarly, the LRO 2 includes an oDSP chip 21, and compared with the oDSP chip 21 shown in FIG. 1, only includes the RX 21 close to the network device 2 and the TX 22 close to the LRO 1.

[0112] It should be noted that in the communication system to which the embodiments of the present application are applicable, both ends can be improved optical modules (LPO or LRO), which can be specifically referred to the related descriptions of FIG. 2a, FIG. 2b and FIG. 9; or one end can be an improved optical module and the other end can be a traditional optical module, which can be specifically referred to the related descriptions of FIG. 7 or FIG. 8 below.

[0113] It should be noted that in the communication system of the embodiments of the present application, the receiving end can include a receiving end PHY chip and a receiving end module, and the sending end can include a sending end PHY chip and a sending end module. Taking FIG. 4 as an example, if the link to be trained is the HB to HA link, then the sending end PHY chip can correspond to the PHY chip in the HA, the receiving end PHY chip can correspond to the PHY chip in the HB, the sending end module can correspond to the MA, and the receiving end module can correspond to the MB. If the link to be trained is the HA to HB link, then the sending end PHY chip can correspond to the PHY chip in the HB, the receiving end PHY chip can correspond to the PHY chip in the HA, the sending end module can correspond to the MB, and the receiving end module can correspond to the MA. For the sending end device mentioned in the embodiments of the present application, for the scenario where the sending end module is LPO, the sending end device can be understood as the sending end PHY chip; for the scenario where the sending end module is LRO, the sending end device can be the oDSP chip in the LRO (i.e., the oDSP chip connected with the TX of the sending end PHY chip), or can be the sending end PHY chip.

[0114] It should be noted that the PHY chip can be implemented by an ASIC chip, and can also be referred to as an electrical chip. The SerDes on the ASIC side in the above can be integrated with the ASIC chip, or can be set independently of the ASIC chip.

[0115] It should be noted that in the embodiments of the present application, the network device is a general term for devices that can exist in a network, and can be a switch, a router, a firewall, or other network devices in the conventional sense, or can be a user host or a vehicle host, etc. The PHY chip in the network device can include firmware (Firmware) or mainboard control software, wherein the Firmware can be understood as an operating system of the SerDes, and the Firmware is a control software in the PHY chip, which can be deployed in the microcontroller unit (MCU) of the SerDes, and the functions include: controlling the registers in the equalizer of the SerDes, and the Firmware can execute the method provided in the embodiments of the present application; the network device where the PHY chip is located can include a mainboard and a plurality of line cards, and the mainboard is used to control each line card, and the mainboard control software can execute the method provided in the embodiments of the present application, and the obtained parameter values of the link training are issued through the mainboard, and the PMD layer (i.e., the registers of the SerDes, etc.) is controlled by means of a protocol or other channels, to realize the downward configuration of the parameter values of the link training.

[0116] It should be noted that the method provided in the embodiments of the present application can be applied to link training in various data transmission scenarios, including but not limited to: data center, supercomputing node, artificial intelligence data center network (AI DCN) and the like, and can also be applied to a bearer network of a 5G wireless network, such as a front-haul bearer scenario.

[0117] It should be noted that for a communication system, end-to-end link training can be performed in two directions at the same time, and when link training in both directions is completed, link training of a bidirectional link of the communication system is completed. When link training in a certain direction fails, it is considered that link training for the bidirectional link of the communication system fails, and link training in both directions needs to be restarted.

[0118] It should be noted that in the embodiments of the present application, the link from the receiving end PHY chip to the sending end device is a link in a specified direction, and the direction of the link is from the receiving end PHY chip to the sending end device. Hereinafter, the "link from the receiving end PHY chip to the sending end device" can be understood as "link in the direction from the receiving end PHY chip to the sending end device".

[0119] In the embodiments of the present application, the maximum allowed time (such as max-timer) or the maximum training times can be set for the whole link training process. Then, the link training failure can refer to that the link training is not completed within the max-timer, and once the duration of the link training exceeds the limit of the max-timer, the link training is considered to fail, and the whole link training process can be restarted by resetting the link training. Alternatively, the link training failure can refer to that the link training is not completed although the number of the link training times reaches the maximum training times. At this time, the link training is considered to fail, and the whole link training process can be restarted by resetting the link training. In the whole link training process, one link training can be understood as the process that the HB performs the link training on its own parameters and / or the parameters of the MB based on the link training request sent by the HA. Alternatively, one link training can be understood as the process that the HB performs the link training on its own parameters and / or the parameters of the MB based on the link training request sent by the HA, and then the HA performs the link training on the parameters of the MA. For the case of setting the maximum training times, the number of the link training times is increased by one after each link training is implemented. If the number of the link training times does not reach the maximum training times and the link training is not completed, the next link training is continued. If the number of the link training times does not reach the maximum training times but the link training is completed, the link training in the present direction is ended, and the link training of the communication system is completed after the link training in the opposite direction is completed. If the number of the link training times reaches the maximum training times and the link training is not completed, the link training is considered to fail. The completion of the link training can refer to that the link quality reaches the expected effect after the link training, and the value of the index representing the link quality meets the preset threshold, for example, the BER is less than or equal to the preset BER threshold, or for example, the SNR of the link is greater than or equal to the preset SNR threshold.

[0120] In order to more clearly introduce the embodiments of the present application, the method provided by the embodiments of the present application is described below with reference to the accompanying drawings.

[0121] FIG. 5 is a flow diagram of a link training method 100 according to an embodiment of the present application. The method 100 is introduced in the way of the interaction between the transmitting end device and the receiving end PHY chip in the link training process in a communication system. The communication system can correspond to the communication system shown in FIG. 2a, FIG. 2b or FIG. 4, or can correspond to the communication system shown in FIG. 7, FIG. 8 or FIG. 9. The steps performed by the transmitting end device in the method 100 can be understood as being implemented by the transmitting end PHY chip, specifically, can be implemented by the Firmware or the main control board control software in the transmitting end PHY chip, or can be understood as being implemented by the oDSP chip of the LRO as the transmitting end module (the oDSP chip of the LRO needs to have the capability of receiving and analyzing the training frame); similarly, the steps performed by the receiving end PHY chip in the method 100 can be understood as being implemented by the Firmware or the main control board control software in the receiving end PHY chip.

[0122] As shown in FIG. 5, the method 100 can include the following S101-S106, for example:

[0123] S101, the transmitting end device generates a first link training request, the first link training request being used to instruct the receiving end PHY chip to perform link training on a first parameter, the first parameter including a parameter of a receiving end module, the parameter of the receiving end module being an optical module parameter.

[0124] In the communication system, if it is needed to perform link training on the link from the receiving end PHY chip to the transmitting end device, the transmitting end device can generate a first link training request and send the first link training request to the receiving end PHY chip as an instruction to trigger the receiving end PHY chip to perform link training on the link from the receiving end PHY chip to the transmitting end device.

[0125] The first link training request can be a training frame in the link training, and the training frame can include a frame marker field, a control field, a status field and a training mode field. The control field is used to instruct to perform link training on the first parameter. The bits in the control field and the status field in the training frame can be encoded in the Differential Manchester Encoding (DME) mode, for example.

[0126] It can be understood that the receiving end PHY chip receiving the training frame can determine the first parameter needed to be trained based on the control field in the training frame and perform link training on the first parameter.

[0127] The first parameter can include a parameter of a receiving end module. The parameter of the receiving end module can refer to a parameter in a receiving end module connected to a receiving end PHY chip that needs to be trained. The receiving end module can be an optical module such as an LPO or an LRO, and the parameter of the receiving end module can refer to an equalizer parameter of a DRV in the LPO or the LRO. Alternatively, the receiving end module can be an ACC-Linear module, and the parameter of the receiving end module can refer to an equalizer parameter of a DRV in the ACC-Linear module.

[0128] The examples in the method 100 are described by taking the link training of a link from the HB to the HA in the communication system shown in FIG. 4 as an example, that is, the sending end corresponds to the HA and the MA, the receiving end corresponds to the HB and the MB, the receiving end PHY chip corresponds to the PHY chip of the HB, and the receiving end module corresponds to the MB.

[0129] In this case, the parameter of the receiving end module can refer to a parameter in the MB that needs to be trained, for example, can be an equalization parameter of a DRV_CTLE (i.e., a CTLE on the DRV) in the MB, and specifically can be at least one of dc_gain, boost0, or boost1 of the DRV_CTLE in the MB.

[0130] The control field of the training frame can include 16 bits from the 0th bit to the 15th bit, and the following description is taken as an example of the definition of the control field in the training frame in IEEE 802.3CL136. Four known value combinations of the 2nd bit, the 3rd bit, and the 4th bit of the control field of the training frame are used to indicate the link training of the PHY chip link training parameter, respectively. The 5th bit, the 6th bit, the 7th bit, the 10th bit, the 11th bit, the 14th bit, and the 15th bit are reserved (Reserved) bits.

[0131] For example, in the communication system shown in FIG. 4, the parameters of the receiving end PHY chip can refer to the parameters in the HB that need to be subjected to link training, for example, can be the equalization parameters of the TX-FFE in the HB (i.e., the FFE on the TX of the SerDes of the HB), can be at least one of pre2, pre1, post1 or post2 of the TX-FFE in the HB. For the control field of the training frame, when the known value combination of the 2nd, 3rd and 4th bits is 011, it can be used to instruct the HB to perform link training on pre2 of the TX-FFE in the HB; when the known value combination of the 2nd, 3rd and 4th bits is 111, it can be used to instruct the HB to perform link training on pre1 of the TX-FFE in the HB; when the known value combination of the 2nd, 3rd and 4th bits is 000, it can be used to instruct the HB to perform link training on post2 of the TX-FFE in the HB; and when the known value combination of the 2nd, 3rd and 4th bits is 100, it can be used to instruct the HB to perform link training on post1 of the TX-FFE in the HB.

[0132] In the embodiments of the present application, the control field in the training frame can not only instruct the receiving end PHY chip to perform link training on its own parameters according to the known definition, but also can instruct the receiving end PHY chip to perform link training on the parameters of the receiving end module connected to it by extending and defining the control field in the training frame.

[0133] As an example, the first link training request can instruct the receiving end PHY chip to perform link training on the first parameters through the multiple reserved bits of the control field. The number of bits of the reserved bits used to instruct the receiving end PHY chip to perform link training on the first parameters can be determined based on the number of parameters included in the first parameters, as long as the number of parameters included in the first parameters is less than or equal to the number of bits of the reserved bits raised to the power of 2. For example, when the number of parameters included in the first parameters is 3, at least 2 reserved bits are required, and the 2 reserved bits can be at least two of the 5th, 6th, 7th, 10th, 11th, 14th and 15th bits; for another example, when the number of parameters included in the first parameters is 9, at least 4 reserved bits are required, and the 4 reserved bits can be at least four of the 5th, 6th, 7th, 10th, 11th, 14th and 15th bits.

[0134] Taking the parameters of the receiving end module including the dc_gain, boost0 and boost1 of the DRV_CTLE in the MB as an example, the 3 value combinations of the 5th bit and the 6th bit in the DME code block can be used to instruct the HB to perform link training on the dc_gain, boost0 and boost1 in the MB, for example, the value combination of the 5th bit and the 6th bit being 00 can be used to instruct the HB to perform link training on the dc_gain in the MB; the value combination of the 5th bit and the 6th bit being 01 can be used to instruct the HB to perform link training on the boost0 in the MB; the value combination of the 5th bit and the 6th bit being 10 can be used to instruct the HB to perform link training on the boost1 in the MB.

[0135] As another example, the first link training request can also use one reserved bit in the control field and the parameter selection field to instruct the receiving end PHY chip to perform link training on the first parameters. For example, a first value of the reserved bit is used to instruct the receiving end PHY chip to perform link training on the parameters of the receiving end module, a second value of the reserved bit is used to instruct the receiving end PHY chip to perform link training on the parameters of the receiving end PHY chip, and the first value is different from the second value. The value combinations of the parameter selection field are used to indicate the specific parameters that need to be link trained by the reserved bit in different values. For example, the parameter selection field can be the 2nd bit, the 3rd bit and the 4th bit, and the reserved bit can be any one of the 5th bit, the 6th bit, the 7th bit, the 10th bit, the 11th bit, the 14th bit and the 15th bit. Taking the 5th bit as the reserved bit as an example, when the value of the 5th bit is 0 (i.e. the second value), it is used to instruct the receiving end PHY chip to perform link training on its own parameters, and then the meanings of the known value combinations of the 2nd bit, the 3rd bit and the 4th bit remain the same as defined in the current standard; when the value of the 5th bit is 1 (i.e. the first value), it is used to instruct the receiving end PHY chip to perform link training on the parameters of the receiving end module, and then the meanings of the value combinations of the 2nd bit, the 3rd bit and the 4th bit can be flexibly defined.

[0136] For example, the first parameter only includes the parameters of the receiving end module, and the parameters of the receiving end module include dc_gain, boost0 and boost1 of the DRV_CTLE in the MB. Then, the different values of the 5th bit in the control field can be used to indicate that the HB performs link training on its own or on the parameters in the MB. The parameter selection field can include the 2nd bit, the 3rd bit and the 4th bit in the control field. For example, when the value of the 5th bit is 1, and the value combination of the 2nd bit, the 3rd bit and the 4th bit is 100, it is used to indicate that the HB performs link training on dc_gain in the MB; when the value of the 5th bit is 1, and the value combination of the 2nd bit, the 3rd bit and the 4th bit is 111, it is used to indicate that the HB performs link training on boost0 in the MB; when the value of the 5th bit is 1, and the value combination of the 2nd bit, the 3rd bit and the 4th bit is 110, it is used to indicate that the HB performs link training on boost1 in the MB; when the value of the 5th bit is 0, and the known value combination of the 2nd bit, the 3rd bit and the 4th bit is referred to the current definition, it is used to indicate that the HB performs link training on the PHY chip link training parameters in the HB.

[0137] As another example, the first link training request can also indicate that the receiving end PHY chip performs link training on the first parameter through the reserved value combination of the parameter selection field in the control field. The known value combination of the parameter selection field is used to indicate the parameters of the receiving end PHY chip that need to be link trained, and the known value combination is different from the reserved value combination. For example, the parameter selection field can include the 2nd bit, the 3rd bit and the 4th bit, the known value combination can be 100, 000, 111 and 011, and the reserved value combination can include 001, 010, 101 and 110, and at most 4 receiving end module parameters can be defined for link training. The meaning of the reserved value combination of the 2nd bit, the 3rd bit and the 4th bit can be flexibly defined.

[0138] In the case that the first parameter only includes the parameters of the receiving end module, the parameters of the receiving end module include dc_gain, boost0 and boost1 of the DRV_CTLE in the MB, the HB can be instructed to perform link training on its own or on the parameters in the MB by different reserved value combinations of the 2nd, 3rd and 4th bits in the control field. For example, when the value combination of the 2nd, 3rd and 4th bits is 001, it is used to instruct the HB to perform link training on dc_gain in the MB; when the value combination of the 2nd, 3rd and 4th bits is 101, it is used to instruct the HB to perform link training on boost0 in the MB; when the value combination of the 2nd, 3rd and 4th bits is 110, it is used to instruct the HB to perform link training on boost1 in the MB; and the known value combination of the 2nd, 3rd and 4th bits is used to instruct the HB to perform link training on the parameters of the PHY chip in the HB according to the current standard definition.

[0139] In the case that the first parameter only includes the parameters of the receiving end module, the parameters of the receiving end module include dc_gain, boost0 and boost1 of the DRV_CTLE in the MB, the HB can be instructed to perform link training on its own or on the parameters in the MB by different reserved value combinations of the 2nd, 3rd and 4th bits in the control field. For example, when the value combination of the 2nd, 3rd and 4th bits is 001, it is used to instruct the HB to perform link training on dc_gain in the MB; when the value combination of the 2nd, 3rd and 4th bits is 101, it is used to instruct the HB to perform link training on boost0 in the MB; when the value combination of the 2nd, 3rd and 4th bits is 110, it is used to instruct the HB to perform link training on boost1 in the MB; and the known value combination of the 2nd, 3rd and 4th bits is used to instruct the HB to perform link training on the parameters of the PHY chip in the HB according to the current standard definition.

[0140] In some possible implementations, the first link training request can indicate that the receiving-end PHY chip performs link training on the parameters of the receiving-end module. In this implementation, the first parameters can further include parameters of the receiving-end PHY chip. As an example, the first link training request can indicate, through a combination of values of a plurality of reserved bits in the control field, that the receiving-end PHY chip performs link training on the parameters of the receiving-end module in the first parameters.

[0141] Taking the communication system shown in FIG. 4 as an example, the parameters of the receiving end PHY chip in the first parameter can include at least one of pre2, pre1, post1 and post2 of the TX-FFE in the HB, the parameters of the receiving end module in the first parameter include at least one of dc_gain, boost0 and boost1 of the DRV_CTLE in the MB, and it is assumed that the reserved bit positions are the 5th and 6th bits in the control field. Then, in the first link training request, when the known value combination of the 2nd, 3rd and 4th bits in the control field is 011 and the value combination of the 5th and 6th bits is 00, it is used to instruct the HB to perform link training on pre2 of the TX-FFE in the HB and dc_gain in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 111 and the value combination of the 5th and 6th bits is 00, it is used to instruct the HB to perform link training on pre1 of the TX-FFE in the HB and dc_gain in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 000 and the value combination of the 5th and 6th bits is 00, it is used to instruct the HB to perform link training on post2 of the TX-FFE in the HB and dc_gain in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 100 and the value combination of the 5th and 6th bits is 00, it is used to instruct the HB to perform link training on post1 of the TX-FFE in the HB and dc_gain in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 011 and the value combination of the 5th and 6th bits is 01, it is used to instruct the HB to perform link training on pre2 of the TX-FFE in the HB and boost0 in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 111 and the value combination of the 5th and 6th bits is 01, it is used to instruct the HB to perform link training on pre1 of the TX-FFE in the HB and boost0 in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 000 and the value combination of the 5th and 6th bits is 01, it is used to instruct the HB to perform link training on post2 of the TX-FFE in the HB and boost0 in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 100 and the value combination of the 5th and 6th bits is 01, it is used to instruct the HB to perform link training on post1 of the TX-FFE in the HB and boost0 in the MB; when the known value combination of the 2nd, 3rd and 4th bits is 011 and the value combination of the 5th and 6th bits is 10, it is used to instruct the HB to perform link training on pre2 of the TX-FFE in the HB and boost1 in the MB;When the known value combination of the 2nd bit, the 3rd bit and the 4th bit is 111 and the value combination of the 5th bit and the 6th bit is 10, it is used to instruct the HB to perform link training on the pre1 of the TX-FFE in the HB and the boost1 in the MB; when the known value combination of the 2nd bit, the 3rd bit and the 4th bit is 000 and the value combination of the 5th bit and the 6th bit is 10, it is used to instruct the HB to perform link training on the post2 of the TX-FFE in the HB and the boost1 in the MB; when the known value combination of the 2nd bit, the 3rd bit and the 4th bit is 100 and the value combination of the 5th bit and the 6th bit is 10, it is used to instruct the HB to perform link training on the post1 of the TX-FFE in the HB and the boost1 in the MB. In this way, the sending end device can instruct the receiving end PHY chip to perform link training on the parameters of itself and the module connected thereto respectively through one link training request, which can accelerate the convergence speed of link training and improve the efficiency of link training in many scenarios. For example, the parameters involved in link training can be decoupled and grouped according to experience or experiment, and the grouping basis can be, for example, that the parameters having the same influence trend on the same performance (such as equalization performance) of the receiving end PHY chip and the receiving end module are divided into the same group, and the parameters of the same group are instructed to perform link training together in the same link training request, which can effectively improve the efficiency of link training.

[0142] In the embodiments of the application, the receiving end module can refer to the LPO, LRO or ACC-Linear module, and the receiving end PHY chip can refer to the PHY chip in the network device connected with the receiving end module. When the receiving end module is the LPO, the sending end device can refer to the sending end PHY chip, and when the receiving end module is the traditional optical module or the LRO, the sending end device can refer to the sending end PHY chip or the sending end module, which refers to the traditional optical module, the LPO, the LRO or the ACC-Linear module connected with the sending end PHY chip.

[0143] It should be noted that before S101, the method 100 can further include that the receiving end PHY chip performs initialization configuration between the receiving end PHY chip and the receiving end module, and the sending end PHY chip performs initialization configuration between the sending end PHY chip and the sending end module.

[0144] With the communication system in FIG. 4 as an example, the initialization configuration performed by the receiving-end PHY chip can be understood as the HB initializing the HB and the MB, and the initialization configuration of the sending-end device can be understood as the HA initializing the HA and the MA. With the HB initializing the HB and the MB as an example, the parameters of the initialization configuration can include: the tap coefficient of the TX-FFE of the HB, the equalization parameters (for example, boost1, boost0 and dc_gain) of the DRV_CTLE of the MB, and the TIA output amplitude (TIA_OA) of the MB. As an example, the HB can pre-acquire preset values of the parameters to be subjected to the link training, and then the HB can directly configure the parameters in the HB and the MB as the preset values. As another example, the MB can be connected with a self-loopback device such as a loopback cap before the MB is connected with the MA, and the optical signal emitted by the HB through the MB is looped back to the HB in a self-loopback manner. The HB can configure the parameters in the HB and the MB based on the quality of the electrical signal looped back to the HB. In this way, the initialization configuration makes the communication system subjected to the link training have a more reasonable starting condition, provides a better data basis for the link training, and to a certain extent, can improve the success rate and efficiency of the link training.

[0145] It can be seen that the sending-end device generates the first link training request in S101, and the sending-end device sends the first link training request to the receiving-end PHY chip, and instructs the receiving-end PHY chip to perform link training on the first parameters based on the first link training request, so that the preparation work is completed, and the implementation of the method 100 provided in the embodiments of the present application becomes possible.

[0146] S102, the sending-end device sends the first link training request to the receiving-end PHY chip.

[0147] S103, the receiving-end PHY chip receives the first link training request sent by the sending-end device.

[0148] As an example, the channel for the sending-end device to interact with the receiving-end PHY chip can include a data channel for transmitting service data, and then S102 can include: the sending-end device sends the first link training request to the receiving-end PHY chip through the data channel between the sending-end device and the receiving-end PHY chip; and S103 can include: the receiving-end PHY chip receives the first link training request from the sending-end device through the data channel.

[0149] Taking the communication system shown in FIG. 4 as an example, S102-S103 can include: S11, the RX of the HA determines a first parameter that needs to be subjected to link training, and transmits indication information of the first parameter and related information such as a link training manner of the first parameter to the TX of the HA; S12, the TX of the HA generates a first link training request according to the related information obtained from the RX of the HA; S13, the TX of the HA sends the first link training request to the RX of the HB through path 1; S14, the RX of the HB parses the received first link training request to obtain the related information; and S15, the RX of the HB transmits the parsed related information to the TX of the HB. In this way, the TX of the HB can perform S104 to perform link training on the first parameter based on the related information obtained from the RX of the HB. The path 1 can refer to a transmission path of service data of the TX of the HA to the RX of the HB through the MA and the MB in sequence, and the path 1 can be understood as a data channel from the HA to the HB.

[0150] It can be understood that the sending end device can send the first link training request to the receiving end PHY chip through any channel capable of interacting with the receiving end PHY chip, and the receiving end PHY chip receives the first link training request, thereby preparing for link training on the first parameter by the receiving end PHY chip.

[0151] S104, the receiving end PHY chip performs link training on the first parameter according to the first link training request, and generates first state information.

[0152] The first state information corresponds to the first link training request. The first state information can be used to indicate a state of the receiving end PHY chip after performing link training on the first parameter based on the first link training request. The first state information can include specific parameters participating in the link training and specific link training performed by each specific parameter when the receiving end PHY chip performs link training on the first parameter, so as to let the opposite end know the specific content of the link training.

[0153] The first state information can be carried in a training frame generated after the receiving end PHY chip performs link training on the first parameter. The first state information can be carried in a state field of the training frame, and a value of the state field is used to indicate which parameter is modified in this link training and to what extent (such as whether the modification reaches a limit value of the corresponding parameter) and the like.

[0154] In some possible implementation manners, the training frame generated by the receiving-end PHY chip after the link training on the first parameter can further include test information in addition to the first status information, and the test information is used by the sending-end device to test the link quality of the link from the receiving-end PHY chip to the sending-end device after the current link training, so that the sending-end device makes a next-step decision on the link training of the link from the receiving-end PHY chip to the sending-end device. The test information can be embodied by a training mode field in the training frame.

[0155] Thus, when the sending-end device receives the training frame, the specific situation of the current link training can be known from the status field of the training frame, and the link quality of the link after the current link training can be tested based on the training mode field of the training frame, to obtain a value of at least one quality index capable of representing the quality of the link, so as to guide the following link training.

[0156] As an example, the first parameter includes a parameter of the receiving-end module, and S104 can at least include: the receiving-end PHY chip performing link training on the parameter of the receiving-end module. The receiving-end PHY chip performing link training on the parameter of the receiving-end module needs to consider an interaction channel between the receiving-end PHY chip and the receiving-end module.

[0157] It can be understood that there can be various possible interaction channels between the receiving-end PHY chip and the receiving-end module, for example, an IIC bus, for another example, a data channel, and for still another example, other management register channels. Thus, the receiving-end PHY chip performing link training on the parameter of the receiving-end module in S104 can include: the receiving-end PHY chip performing link training on the parameter of the receiving-end module in the receiving-end module through any possible interaction channel. For example, S104 can include: in response to the first link training request, the receiving-end PHY chip performing link training on the parameter of the receiving-end module in the receiving-end module through the IIC bus.

[0158] As another example, the first parameter can include a parameter of the receiving-end module and a parameter of the receiving-end PHY chip, and S104 can include: the receiving-end PHY chip performing link training on the parameter of the receiving-end module and the parameter of the receiving-end PHY chip. The parameter of the receiving-end PHY chip can be understood as a parameter of the receiving-end PHY chip participating in the current link training. In this example, S104 can include, for example: in response to the first link training request, the receiving-end PHY chip performing link training on the parameter of the receiving-end module through the IIC bus, and the receiving-end PHY chip performing link training on the parameter of the receiving-end PHY chip.

[0159] If the receiving end module is an LPO, the parameters of the receiving end module can include equalization parameters in a DRV_CTLE of the LPO, and the parameters of the receiving end PHY chip can include tap coefficients in a TX-FFE of the receiving end PHY chip.

[0160] It should be noted that the link training can be understood as a process of adjusting the values of corresponding parameters, and the specific parameters and adjustment manners can be carried in the first link training request.

[0161] It can be seen that, through S104, the receiving end PHY chip generates first state information capable of reflecting the state of the link training after performing the link training on the first parameters, thereby making preparations for subsequent feedback of the state of the link training to the sending end device and guiding subsequent link training.

[0162] S105, the receiving end PHY chip sends the first state information to the sending end device.

[0163] S106, the sending end device receives the first state information.

[0164] In order to feed back the state of the link training to the sending end device instructing the link training, the method 100 needs to pass the first state information to the sending end device through S105-S106.

[0165] In some possible implementation manners, the method 100 can further include: the sending end device tests a link quality of a link from the receiving end PHY chip to the sending end device based on the test information, and obtains a test result. Thus, the sending end device judges whether the link training in the direction from the receiving end PHY chip to the sending end device satisfies a preset first condition based on the test result. If the first condition is satisfied, it can be considered that the parameter adjusted by the link training has been adjusted to a better state, and it is not necessary to improve the link quality of the trained link by continuing to adjust the parameter. If the first condition is not satisfied, it can be considered that the parameter adjusted by the link training can be continuously optimized. In a case where it is determined that the link training from the receiving end PHY chip to the sending end device satisfies the preset first condition, the sending end device can further judge whether the link training in the direction from the receiving end PHY chip to the sending end device satisfies a preset second condition. If the second condition is satisfied, it can be considered that the link training makes the link from the receiving end PHY chip to the sending end device satisfy an expected performance requirement, and it is not necessary to continue the link training on the link in the direction from the receiving end PHY chip to the sending end device. If the second condition is not satisfied, it can be considered that the link training does not make the link from the receiving end PHY chip to the sending end device satisfy the expected performance requirement, and it is necessary to continue the link training on parameters of other parts of the link from the receiving end PHY chip to the sending end device.

[0166] The first condition and the second condition can be flexibly set based on actual situations of the link training.

[0167] The first condition is used to indicate whether the adjustment of the same parameter can still continue to improve the link quality of the trained link. As an example, the first condition can include any one of the following conditions: condition 1, a variation of a value of a first quality index is less than or equal to a first threshold, the first quality index is used to represent the link quality of the link from the receiving end PHY chip to the sending end device, and the smaller the value of the first quality index, the better the corresponding link quality; condition 2, a variation of a value of a second quality index is greater than or equal to a second threshold, the second quality index is used to represent the link quality of the link from the receiving end PHY chip to the sending end device, and the greater the value of the second quality index, the better the corresponding link quality. The first quality index may, for example, be a BER, and the second quality index may, for example, be an SNR.

[0168] The second condition is used to determine whether the link training makes the performance of the link meet the requirements of the service data transmission, so as to determine whether the link training is completed. As an example, the second condition can include any one of the following conditions: condition 3, the value of the first quality index is less than or equal to a third threshold; condition 4, the value of the second quality index is greater than or equal to a fourth threshold. The first quality index may, for example, be a BER, and the second quality index may, for example, be an SNR.

[0169] Taking condition 1 as the first condition, condition 3 as the second condition, and the BER as the first quality index as an example, the method 100 may, for example, include the following steps: after S106, the sending end device performs link quality testing on the link from the receiving end PHY chip to the sending end device according to the test information, to obtain a value of the BER representing the link quality of the link from the receiving end PHY chip to the sending end device; the sending end device calculates the difference between the value of the BER obtained this time and the value of the BER obtained after the last link training on the link from the receiving end PHY chip to the sending end device, and determines whether the difference of the BER is less than or equal to the first threshold. If yes, it is considered that the link training from the receiving end PHY chip to the sending end device meets the first condition. If no, it is considered that the link training from the receiving end PHY chip to the sending end device does not meet the first condition. For the case where the link training from the receiving end PHY chip to the sending end device meets the first condition, the sending end device can continue to determine whether the value of the BER obtained this time is less than or equal to the third threshold. If yes, it is considered that the link training from the receiving end PHY chip to the sending end device meets the second condition. If no, it is considered that the link training from the receiving end PHY chip to the sending end device does not meet the second condition.

[0170] As an example, if the sending-end device determines that the link training from the receiving-end PHY chip to the sending-end device satisfies the first condition and satisfies the second condition, the method 100 can further include that the sending-end device can generate a local receiving-end ready (local_rx_ready) information, the local receiving-end ready information being used to indicate that the link training from the receiving-end PHY chip to the sending-end device is completed. In this way, it can be identified through the second condition whether the link training of a link in a certain direction is completed, and a reliable judgment basis of the progress of the link training of the communication system is provided.

[0171] As another example, if the sending-end device determines that the link training from the receiving-end PHY chip to the sending-end device does not satisfy the second condition, the method 100 can further include that the sending-end device continues to perform the link training on the link from the receiving-end PHY chip to the sending-end device.

[0172] In one case, if the sending-end device determines that the link training from the receiving-end PHY chip to the sending-end device does not satisfy the first condition, the sending-end device can continue to instruct the receiving-end PHY chip to perform the link training on itself or the receiving-end module, for example, the sending-end device generates a third link training request, the third link training request being used to instruct the receiving-end PHY chip to continue to perform the link training on the first parameter; the sending-end device sends the third link training request to the receiving-end PHY chip; the receiving-end PHY chip performs the link training on the first parameter based on the received third link training request, generates third state information of the link training; and the receiving-end PHY chip sends the third state information corresponding to the third link training request to the sending-end device. In this case, the first parameter can include a parameter of the receiving-end module and / or a parameter of the receiving-end PHY chip, and the first parameter in this case can be the same as or different from the first parameter in S101; even if the first parameter in this case is the same as the first parameter in S101, the adjustment manner of the first parameter indicated by the third link training request can be different from the adjustment manner of the first parameter indicated by the first link training request.

[0173] In another case, if the sending end device determines that the link training from the receiving end PHY chip to the sending end device satisfies the first condition but does not satisfy the second condition, it can be considered that the link training of the receiving end PHY chip to itself and to the receiving end module has been unable to further improve the link quality of the link from the receiving end PHY chip to the sending end device, or it is determined that the result of the link training obtained by instructing the receiving end PHY chip to perform link training on the first parameter satisfies the expected effect of the receiving end PHY chip performing link training on the first parameter. In this case, in the process of continuing to perform link training on the link from the receiving end PHY chip to the sending end device, the method 100 can further include: the sending end device performing link training on a third parameter, the third parameter including a parameter of the sending end module. The parameter of the sending end module can be understood as a parameter of the sending end module participating in the link training. After the sending end device performs link training on the third parameter, if it is determined that the link training on the link from the receiving end PHY chip to the sending end device satisfies the preset second condition, it is considered that the sending end device does not need to continue to perform link training on the third parameter, at which time, according to needs, the link training on the link from the receiving end PHY chip to the sending end device can be ended; or, if it is determined that the link training on the link from the receiving end PHY chip to the sending end device again satisfies the preset first condition but still does not satisfy the second condition, the sending end device can automatically start link training on its own parameter until the link training from the receiving end PHY chip to the sending end device satisfies the second condition; if it is determined that the link training on the link from the receiving end PHY chip to the sending end device does not satisfy the preset first condition and the second condition, the sending end device can continue to perform link training on the third parameter. It should be noted that the third parameter involved in each time the sending end device performs link training on the third parameter can be the same or different.

[0174] Taking the communication system shown in FIG. 4 as an example, the sending end device performing link training on the third parameter can include: the HA performing link training on a parameter in the MA. Taking the sending end module as an LPO as an example, the parameter of the sending end module can include an equalization parameter in the TIA_OA of the LPO.

[0175] For the sending end device to determine that the link training of the receiving end PHY chip to itself and to the receiving end module has failed to further improve the link quality of the link from the receiving end PHY chip to the sending end device, or to determine that the result of the link training obtained by instructing the receiving end PHY chip to perform link training on the first parameter meets the expected effect of the receiving end PHY chip performing link training on the first parameter, a preset first condition can be implemented, for example, when the sending end device determines that the result of the link training meets the first condition after the receiving end PHY chip performs link training on the first parameter, it is considered that the link training of the receiving end PHY chip to itself and to the receiving end module has failed to further improve the link quality of the link from the receiving end PHY chip to the sending end device, or it is considered that the result of the link training obtained by instructing the receiving end PHY chip to perform link training on the first parameter meets the expected effect of the receiving end PHY chip performing link training on the first parameter. At this time, the sending end device can continue to perform link training on the link from the receiving end PHY chip to the sending end device by adjusting the sending end module.

[0176] It should be noted that during the process of the sending end device performing link training on the third parameter of the sending end module, the sending end device can continue to send a link training request to the receiving end PHY chip, and the receiving end PHY chip can not process the received link training request by default.

[0177] It should be noted that after the sending end device performs link training on the third parameter of the sending end module, the method 100 can further include that the sending end device continues to instruct the receiving end PHY chip to perform link training on itself or the receiving end module. For example, after the sending end device performs link training on the third parameter of the module connected to itself, if the sending end device determines that the link training from the receiving end PHY chip to the sending end device does not meet the second condition, or if the sending end device determines that the link training from the receiving end PHY chip to the sending end device does not meet the second condition but meets the first condition, the sending end device can continue to instruct the receiving end PHY chip to continue link training on itself or the receiving end module.

[0178] It should be noted that in the above various possible link training processes, it is necessary to complete within the set maximum allowed time and / or maximum training times. Once the implementation time of the link training reaches the maximum allowed time or the number of link training reaches the maximum training times, it is considered that the entire link training process fails.

[0179] Thus, by the method 100, even if the receiving end module and / or the sending end module in the communication system does not include an oDSP chip, the receiving end PHY chip can perform link training on the first parameter including the parameters of the receiving end module through the interaction of the end-to-end link training request and the state information, and for the communication system which cannot be applied to the current link training, the effective link training can be realized, so that the working performance of the communication system is guaranteed.

[0180] In order to make the link training method provided by the embodiments of the present application more easily understood, a possible link training process is described below in combination with FIG. 6.

[0181] As shown in FIG. 6, assuming that the maximum allowed time of the link training is preset, one possible example of the link training method provided by the embodiments of the present application may, for example, include S601-S610:

[0182] S601, the local network device and the module connected to the local network device (hereinafter referred to as the local module) are initialized and configured, and the peer network device and the module connected to the peer network device (hereinafter referred to as the peer module) are initialized and configured.

[0183] S602, if the implementation time of the link training is within the maximum allowed time, the local network device judges whether the link quality 1 of the link from the peer network device to the local network device meets the requirement of the service data transmission, if yes, S610 is executed; if not, S603 is executed.

[0184] The requirement of the service data transmission in S602 can be understood as the second condition in the above.

[0185] S603, the local network device instructs the peer network device to perform link training on the parameters of the PHY chip of the peer network device and / or the parameters of the peer module, so that the local network device obtains the link quality 2 of the link from the peer network device to the local network device.

[0186] S604, if the implementation time of the link training is within the maximum allowed time, the local network device judges whether the difference between the link quality 2 and the link quality 2' obtained in the previous link training is less than the first preset value, if yes, S605 is executed; if not, S603 is returned.

[0187] The difference between the link quality 2 and the link quality 2' obtained in the previous link training is less than the first preset value can be understood as the first condition in the above.

[0188] The specific value of the first preset value can be flexibly set based on actual requirements. The difference between the link quality 2 and the link quality 2' obtained in the previous link training is less than the first preset value, which is used to represent that the link quality of the link is basically unchanged or changes little after two adjacent link trainings, that is, the effect of the link training corresponding to the link quality 2 is not significant enough, and thus it is not necessary to continue to optimize the same content.

[0189] S605, the local network device performs link training on the parameters of the local module to obtain the link quality 3 of the link from the opposite network device to the local network device;

[0190] S606, if the implementation time of the link training is within the maximum allowed time, the local network device judges whether the link quality 3 meets the requirement of the service data transmission, if yes, it is considered that the link training is completed, and S610 is executed, otherwise, S607 is executed;

[0191] The requirement of the service data transmission in S606 can be understood as the second condition in the above.

[0192] S607, the local network device judges whether the implementation time of the link training is within the maximum allowed time, if yes, S608 is executed, otherwise, S609 is executed;

[0193] S608, the local network device judges whether the difference between the link quality 3 and the link quality 3' obtained in the previous link training is less than the second preset value, if yes, S603 is returned to be executed, if not, S605 is returned to be executed;

[0194] The specific value of the second preset value can be flexibly set based on actual requirements, and the second preset value can be the same as or different from the first preset value. The difference between the link quality 3 and the link quality 3' obtained in the previous link training is less than the second preset value, which is used to represent that the link quality of the trained link is basically unchanged or changes little after two adjacent link trainings, that is, the effect of the link training corresponding to the link quality 3 is not significant enough, and thus it is not necessary to continue to optimize the same content.

[0195] S609, the local network device determines that the overall link training process fails, and restarts the process of the link training;

[0196] S610, the link from the opposite network device to the local network device is used for the transmission of service data.

[0197] Thus, it can be known from the embodiment shown in FIG. 6 that the link training method provided by the embodiment of the present application no longer depends on the oDSP chip in the module connected with the network device, and the network device does not need to form an electrical signal loop with the module connected with itself, and can realize the end-to-end link training of the communication system based on the indication of the end-to-end link training of the communication system and the timely feedback of the link quality. For the communication system that the current link training cannot be applied to, the effective link training can be realized, and the working performance of the communication system can be guaranteed.

[0198] The communication system to which the embodiment of the present application is applicable can also be applicable to the retimed-LPO architecture communication system shown in FIG. 7, the retimed-LRO architecture communication system shown in FIG. 8 and the LRO-LPO architecture communication system shown in FIG. 9 in addition to the LPO-LPO architecture communication system shown in FIG. 2a and the LRO-LRO architecture communication system shown in FIG. 2b. The communication systems of various architectures and the processes of performing the link training of the method provided by the embodiment of the present application on the corresponding communication systems will be introduced respectively.

[0199] Scenario one, for the LPO-LPO architecture communication system shown in FIG. 2a, the link training process can refer to the related description in the embodiment shown in FIG. 5 or FIG. 6.

[0200] Scenario two, for the retimed-LPO architecture communication system, as shown in FIG. 7, the LPO 1 in FIG. 2a is replaced by the traditional optical module 1 shown in FIG. 1 compared with the communication system shown in FIG. 2a.

[0201] For the communication system shown in FIG. 7, initialization configuration can be performed between the network device 1 and the traditional optical module 1 and between the network device 2 and the LPO 2 before the link training starts. For example, the initialization configuration between the network device 1 and the traditional optical module 1 can be completed before the factory, and the initialization configuration between the network device 2 and the LPO 2 can be completed before the factory or through the self-loop mode.

[0202] For the link training of the link 1 from the network device 1 to the network device 2, the link training can include:

[0203] The first step, the link training between the network device 1 and the traditional optical module 1 in the link 1 can refer to the link training scheme of the electrical signal loop 1 in FIG. 1, for example, the link training mechanism of CL136 or CL162 in IEEE 802.3 can be referred to, which is not described here. After the link training of the electrical signal loop 1 is completed, the value of the equalization parameter (such as the tap coefficient of TX-FFE) of the TX in the network device 1 no longer changes. It should be noted that a bit (such as the 15th bit of the control field of the training frame) can be used in the training frame to indicate whether the link training between the network device 1 and the traditional optical module 1 is completed, for example, the value of the bit is 0, which indicates that the link training between the network device 1 and the traditional optical module 1 is not completed; the value of the bit is 1, which indicates that the link training between the network device 1 and the traditional optical module 1 is completed.

[0204] The second step, after the link training between the network device 1 and the traditional optical module 1 in the link 1 is completed, the subsequent link training between the traditional optical module 1 and the network device 2 is started.

[0205] As an example, the equalization parameter (such as the tap coefficient of TX-FFE in the oDSP chip 11) in the oDSP chip 11 of the traditional optical module 1 has been configured before the traditional optical module 1 is shipped, and the index of the output port TP2 point meets the protocol requirements, so the traditional optical module 1 can participate in the link training, and the network device 1 or the traditional optical module 1 can default not to perform the link training after receiving the link training request sent by the network device 2. In this example, the network device 2 can perform link training on the equalization parameter (such as TIA_OA in the LPO 2) in the LPO 2 through the IIC bus or other management register channel. If it is determined that the link training from the network device 1 to the network device 2 meets the second condition within the maximum allowed time or the maximum number of training times, it is determined that the link training from the network device 1 to the network device 2 is completed.

[0206] As another example, when adjusting the equalization parameters within LPO 2 (such as TIA OA in LPO 2) alone cannot complete the link training, the equalization parameters within the oDSP chip 11 of the conventional optical module 1 (such as the tap coefficients of TX-FFE within the oDSP chip 11) can also be targeted for link training. Next, case one, the network device 1 receives the link training request sent by the network device 2, and the network device 1 can adjust the equalization parameters within the oDSP chip 11 of the conventional optical module 1 according to the link training request, and send the obtained state information and test information to the network device 2, and the network device 2 can determine the effect of the current link training based on the received test information; case two, when the network device 2 determines that the effect of the current link training meets the first condition, for example, the change amount of the BER of the link is less than or equal to the threshold D, the network device 2 continues to perform link training on the equalization parameters within LPO 2 (such as TIA OA in LPO 2) through the IIC bus or other management register channel, at this time, the network device 1 or the conventional optical module 1 can default not to perform link training after receiving the link training request sent by the network device 2; case three, when the network device 2 performs link training on the equalization parameters within LPO 2, the network device 2 determines that the effect of the current link training meets the first condition, for example, the change amount of the BER of the link is less than or equal to the threshold D, the network device 2 can stop training the equalization parameters within LPO 2, and actively start link training on the equalization parameters within the oDSP chip 11 of the conventional optical module 1 (such as the tap coefficients of TX-FFE within the oDSP chip 11). In the iteration of the above case one, case two and case three, if within the limit of the maximum allowed time or the maximum number of training times, the network device 2 determines that the effect of the current link training meets the second condition, for example, the value of the BER of the link 1 is less than or equal to the threshold T, it is determined that the link training from the network device 1 to the network device 2 is completed.

[0207] The RX of the network device 2 can pass the link training related information to the TX of the network device 2, the TX of the network device 2 carries the link training related information in a training frame and sends the training frame to the RX of the network device 1 or the RX of the conventional optical module 1, the RX of the network device 1 or the RX of the conventional optical module 1 parses the received training frame to obtain the link training related information, and passes the link training related information to the TX of the network device 1 or the TX of the conventional optical module 1, and the TX of the network device 1 or the TX of the conventional optical module 1 adjusts the equalization parameters (such as the tap coefficients of the TX-FFE in the oDSP chip 11) in the oDSP chip 11 of the conventional optical module 1 according to the obtained link training related information. If the oDSP chip 11 of the conventional optical module 1 close to the TX 12 and the RX 12 of the LPO 2 side has the functions of receiving and parsing the training frame (such as the DME code block in the training frame), the TX of the network device 2 sends the training frame carrying the link training related information to the RX 12 of the conventional optical module 1, and the network device 1 does not participate in the transmission and parsing of the training frame. If the oDSP chip 11 of the conventional optical module 1 close to the TX 12 and the RX 12 of the LPO 2 side does not have the functions of receiving and parsing the training frame (such as the DME code block in the training frame), the TX of the network device 2 sends the training frame carrying the link training related information to the RX of the network device 1, the RX of the network device 1 obtains the link training related information after parsing the training frame, and passes the link training related information to the TX of the network device 1, and the TX of the network device 1 adjusts the equalization parameters in the oDSP chip 11 of the conventional optical module 1 based on the link training related information through the IIC bus, other management register channel or data channel.

[0208] For the link training of the link 2 from the network device 2 to the network device 1, the network device 1 can send a link training request to the network device 2, the network device 2 adjusts its own equalization parameters (such as the tap coefficients of the TX-FFE) and / or adjusts the equalization parameters of the LPO 2 (such as the equalization parameters of the DRV_CTLE) through the IIC bus, other management register channel or data channel according to the indication of the received link training request, the network device 2 sends the corresponding state information and test information of the link training to the network device 1, and if the link training from the network device 2 to the network device 1 satisfies the second condition based on the test information within the maximum allowed time or the maximum number of training, it is determined that the link training from the network device 2 to the network device 1 is completed. Wherein, the network device 1 determines that the effect of the current link training satisfies the second condition, for example, the value of the BER of the link 2 is less than or equal to a threshold T.

[0209] The RX of the network device 1 or the RX of the conventional optical module 1 can pass the link training related information to the TX of the network device 1 or the TX of the conventional optical module 1, the TX of the network device 1 or the TX of the conventional optical module 1 carries the link training related information in a training frame and sends the training frame to the RX of the network device 2, the RX of the network device 2 parses the received training frame to obtain the link training related information, and passes the link training related information to the TX of the network device 2, and the TX of the network device 2 adjusts the equalization parameters in the LPO 2 (such as the equalization parameters of the DRV_CTLE in the LPO 2) according to the obtained link training related information. If the oDSP chip 11 of the conventional optical module 1 close to the TX 12 and the RX 12 of the LPO 2 side has the functions of transmitting and parsing the training frame (such as the DME code block in the training frame), then the TX 12 of the conventional optical module 1 sends the training frame carrying the link training related information to the RX of the network device 2, and the network device 1 does not participate in the transmission and parsing of the training frame. If the oDSP chip 11 of the conventional optical module 1 close to the TX 12 and the RX 12 of the LPO 2 side does not have the functions of transmitting and parsing the training frame (such as the DME code block in the training frame), then the TX of the network device 1 sends the training frame carrying the link training related information to the RX of the network device 2.

[0210] It should be noted that the link training of the link 1 and the link training of the link 2 can be considered as two parts of the entire link training process of the communication system shown in FIG. 7, and the maximum allowed time and the maximum number of training can be the same. The failure of the link training of the link 1 or the failure of the link training of the link 2 can cause the entire link training process to fail, and a new link training process needs to be restarted to prepare the communication system for transmitting service data.

[0211] It should be noted that for the link training from the network device 1 to the network device 2, the transmission path of the link training request can be the data channel used for service data transmission.

[0212] Scenario three, for the communication system of the LRO-LRO architecture shown in FIG. 2b, initialization configuration can be performed between the network device 1 and the LRO 1, and between the network device 2 and the LRO 2 before the link training starts. For example, the initialization configuration between the network device 1 and the LRO 1 can be completed before the factory, and the initialization configuration between the network device 2 and the LRO 2 can be completed before the factory or through a self-loopback manner.

[0213] As an example, the LRO can internally include a complete oDSP chip, and the oDSP RX in the oDSP chip is in an open state during the process of link training between the network device 1 and the LRO 1 and between the network device 2 and the LRO 2, referring to the current link training scheme, and is closed once the corresponding link training is completed. For example, the RX of the oDSP chip 11 in the LRO 1 is closed after the link training between the network device 1 and the LRO 1 is completed; similarly, the RX of the oDSP chip 21 in the LRO 2 is closed after the link training between the network device 2 and the LRO 2 is completed.

[0214] As another example, as shown in FIG. 2b, only the TX part is made inside the LRO. In the first case, the equalization parameters of the TX of the network device 1 can be configured before leaving the factory, and link training between the network device 1 and the LRO 1 is no longer needed. In the second case, the equalization parameters of the TX of the network device 1 need to be link trained, for example, a bidirectional feedback channel for information involved in link training can be constructed between the network device 1 and the LRO 1 by means of an out-of-band channel (such as an IIC bus), and the feedback information of the oDSP chip 11 in the LRO 1 is transmitted to the network device 1 to adjust the equalization parameters of the network device 1 to achieve link training between the network device 1 and the LRO 1. It should be noted that in the above two cases, the link between the network device 1 and the LRO 1 has been supplemented, and the subsequent link training process between the LRO 1 and the network device 2 can refer to the description of the second step of link training of link 1 in FIG. 7. In the third case, the equalization parameters of the TX of the network device 1 can participate in the link training of the end-to-end equalization parameters, that is, the equalization parameters of the TX of the network device 1 are adjusted based on the indication of the link training request sent by the network device 2, and the link training between the network device 1 and the LRO 1 is no longer considered separately. The flow of link training is basically the same as that shown in FIG. 2a, and the main differences include the following two points: first, the LRO internally adjusts the equalization parameters of the oDSP chip (such as the tap coefficients of TX_FFE of the oDSP chip); second, the network device can configure the equalization parameters of the oDSP chip in the LRO through the IIC bus, other management register channels or data channels.

[0215] It should be noted that the training frame used to carry the relevant information of link training can be transmitted in the communication system through a data channel.

[0216] Scenario four, for a communication system of a retimed-LRO architecture, as shown in FIG. 8, compared with the communication system shown in FIG. 7, the LPO 2 in FIG. 7 is replaced by the LRO 2 shown in FIG. 2b. For the link training of the link 3 from the network device 1 to the network device 2, please refer to the relevant description of the link training of the link 1 in FIG. 7, or refer to the relevant description of the link training of any one direction in FIG. 2b. For the link training of the link 4 from the network device 2 to the network device 1, please refer to the relevant description of the link training of the communication system of the retimed-retimed architecture in FIG. 1 using the current link training method.

[0217] Scenario five, for a communication system of an LRO-LPO architecture, as shown in FIG. 9, compared with the communication system shown in FIG. 2b, the LRO 2 in FIG. 2b is replaced by the LPO 2 shown in FIG. 2a. For the link training of the link 5 from the network device 1 to the network device 2, please refer to the relevant description of the link training of the link 1 in FIG. 7, or refer to the relevant description of the link training of any one direction in FIG. 2b, or refer to the relevant description of the link training of the link 3 in FIG. 8. For the link training of the link 6 from the network device 2 to the network device 1, please refer to the relevant description of the link training of any one direction of the communication system of the LPO-LPO architecture in FIG. 2a.

[0218] It can be seen that the method provided by the embodiments of the present application can realize end-to-end link training of a communication system in a communication system involving multiple links, through the indication of end-to-end link training of the communication system and the timely feedback of link quality, and is suitable for multiple possible scenarios in which at least one network device connected to the module of the communication system is an improved module. For the communication system that cannot be adapted to the current link training, effective link training can be realized, so that the working performance of the communication system can be guaranteed.

[0219] Correspondingly, the embodiments of the present application also provide a chip 1000, as shown in FIG. 10. The chip 1000 can include an interface circuit 1001 and a processing circuit 1002.

[0220] If the chip 1000 corresponds to a chip in a sending end device, the functions of the structures in the chip 1000 are as follows:

[0221] The processing circuit 1002 is configured to generate a first link training request, and the first link training request is used to instruct a receiving end PHY chip to perform link training on a first parameter. The first parameter can include at least a parameter of a receiving end module, and the parameter of the receiving end module is an optical module parameter. The function of the processing circuit 1002 can correspond to the relevant description of S101 in FIG. 5.

[0222] The interface circuit 1001 is configured to send the first link training request to a receiving end PHY chip. The function of the interface circuit 1001 can correspond to S102 in FIG. 5.

[0223] The interface circuit 1001 is further configured to receive first state information, the first state information indicating a state after link training of the first parameter based on the first link training request. The function of the interface circuit 1001 can correspond to S106 in FIG. 5.

[0224] In some possible implementation manners, in one case, the receiving end module can include an optical module, and the optical module parameter is a parameter in the optical module. For example, the receiving end module is an LPO, and the optical module parameter can be a parameter in DRV_CTLE in the LPO. In another case, the receiving end module can also include an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module.

[0225] In some possible implementation manners, for the case that the receiving end module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, the chip 1000 protected by the embodiment of the present application is a transmitting end PHY chip, and the transmitting end module connected to the transmitting end PHY chip is an LPO. Therefore, the transmitting end device can refer to the transmitting end PHY chip. As another example, the communication system can be an LPO-retimed architecture, that is, the chip 1000 protected by the embodiment of the present application is a transmitting end PHY chip or a chip in a transmitting end module, and the transmitting end module connected to the transmitting end PHY chip is a retimed optical module. Therefore, the transmitting end device can refer to the transmitting end PHY chip or the transmitting end module. As yet another example, the communication system can be an LPO-LRO architecture, that is, the chip 1000 protected by the embodiment of the present application is a transmitting end PHY chip or a chip in a transmitting end module, and the transmitting end module connected to the transmitting end PHY chip is an LRO. Therefore, the transmitting end device can refer to the transmitting end PHY chip or the transmitting end module.

[0226] In some possible implementation ways, for the case that the receiving-end module is an LRO, as an example, the communication system can be an LRO-LPO architecture, that is, the chip 1000 protected by the embodiment of the application is a transmitting-end PHY chip, the transmitting-end module connected to the transmitting-end PHY chip is an LPO, and then the transmitting-end device is the transmitting-end PHY chip; as another example, the communication system can be an LRO-retimed architecture, that is, the chip 1000 protected by the embodiment of the application is a transmitting-end PHY chip or a chip in a transmitting-end module, the transmitting-end module connected to the transmitting-end PHY chip is a retimed optical module, and then the transmitting-end device is the transmitting-end PHY chip or the transmitting-end module; as yet another example, the communication system can be an LRO-LRO architecture, that is, the chip 1000 protected by the embodiment of the application is a transmitting-end PHY chip or a chip in a transmitting-end module, the transmitting-end module connected to the transmitting-end PHY chip is an LRO, and then the transmitting-end device is the transmitting-end PHY chip or the transmitting-end module.

[0227] In the application, the LRO can include an oDSP chip, the oDSP chip of the LRO is connected to the TX of the receiving-end PHY chip, and the oDSP chip of the LRO is not connected to the RX of the transmitting-end PHY chip.

[0228] In some possible implementation ways, the processing circuit 1002 is further configured to generate a second link training request, the second link training request being used to instruct the receiving-end PHY chip to perform link training on a second parameter, the second parameter including a parameter of the receiving-end PHY chip; the interface circuit 1001 is further configured to send the second link training request to the receiving-end PHY chip; and the interface circuit 1001 is further configured to receive second state information sent by the receiving-end PHY chip, the second state information indicating a state after the second parameter is subjected to link training based on the second link training request.

[0229] In some possible implementation ways, the first parameter further includes a parameter of the receiving-end PHY chip.

[0230] In some possible implementation ways, the interface circuit 1001 is further configured to receive test information; and the processing circuit 1002 is further configured to test a link quality of a link from the receiving-end PHY chip to the transmitting-end device based on the test information, and obtain a test result.

[0231] In some possible implementation, the processing circuit 1002 is further configured to generate a third link training request if it is determined that the test result does not satisfy the first condition, the third link training request being used to instruct the receiving-end PHY chip to continue link training on the first parameter; the interface circuit 1001 is further configured to send the third link training request to the receiving-end PHY chip; and the interface circuit 1001 is further configured to receive third status information, the third status information indicating a status of link training on the first parameter based on the third link training request.

[0232] As an example, the first condition can include any one of the following conditions: a variation of a value of a first quality indicator is less than or equal to a first threshold, the first quality indicator being used to represent a link quality of a link from the receiving-end PHY chip to the sending-end device, and a smaller value of the first quality indicator representing a better link quality; a variation of a value of a second quality indicator is greater than or equal to a second threshold, the second quality indicator being used to represent a link quality of the link from the receiving-end PHY chip to the sending-end device, and a larger value of the second quality indicator representing a better link quality.

[0233] In some possible implementation, the processing circuit 1002 is further configured to perform link training on a third parameter if it is determined that the test result satisfies the first condition but does not satisfy the second condition, the third parameter including a parameter of a sending-end module, and the parameter of the sending-end module being an optical module parameter.

[0234] As an example, the second condition can include any one of the following conditions: a value of the first quality indicator is less than or equal to a third threshold, the first quality indicator being used to represent a link quality of a link from the receiving-end PHY chip to the sending-end device, and a smaller value of the first quality indicator representing a better link quality; a value of the second quality indicator is greater than or equal to a fourth threshold, the second quality indicator being used to represent a link quality of the link from the receiving-end PHY chip to the sending-end device, and a larger value of the second quality indicator representing a better link quality.

[0235] In some possible implementation, the first link training request is a training frame, and the training frame includes a control field, the control field being used to instruct link training on the first parameter. For example, the link training on the first parameter can be instructed by a plurality of reserved bits in the control field; or the link training on the first parameter can be instructed by a reserved bit and a parameter selection field in the control field; or the link training on the first parameter can be instructed by a reserved value combination of the parameter selection field in the control field.

[0236] It should be noted that the chip 1000 can be referred to the description of the related operations performed by the sending-end device in the method 100.

[0237] If the chip 1000 corresponds to a receiving end PHY chip, the functions of the structures in the chip 1000 are as follows:

[0238] The interface circuit 1001 is configured to receive a first link training request sent by a sending end device, and the first link training request is used to instruct the receiving end PHY chip to perform link training on a first parameter, and the first parameter includes a parameter of a receiving end module, and the parameter of the receiving end module is a parameter of an optical module. The function of the interface circuit 1001 can correspond to the related description of S103 in FIG. 5.

[0239] The processing circuit 1002 is configured to perform link training on the first parameter according to the first link training request. The function of the processing circuit 1002 can correspond to the related description of S104 in FIG. 5.

[0240] The interface circuit 1001 is further configured to send first state information to the sending end device, and the first state information indicates a state after the link training on the first parameter based on the first link training request. The function of the interface circuit 1001 can correspond to the related description of S105 in FIG. 5.

[0241] In some possible implementation manners, the receiving end module includes an optical module, and the parameter of the optical module is a parameter in the optical module; or the receiving end module includes an ACC-Linear module, and the parameter of the optical module is a parameter in the ACC-Linear module.

[0242] In some possible implementation manners, for a case where the receiving end module is an LPO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; or if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0243] In some possible implementation manners, for a case where the receiving end module is an LRO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; or if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0244] In the embodiment of the application, the LRO includes an optical digital signal processor oDSP chip, the sending end TX of the receiving end PHY chip is connected to the oDSP chip, and the receiving end RX of the receiving end PHY chip is not connected to the oDSP chip.

[0245] In some possible implementation manners, the processing circuit 1002 is specifically configured to perform link training on the parameter of the receiving end module through an IIC bus in response to the first link training request.

[0246] In some possible implementation manners, the interface circuit 1001 is further configured to receive a second link training request sent by the sending-end device, the second link training request being used to instruct the receiving-end PHY chip to perform link training on a second parameter, the second parameter comprising a parameter of the receiving-end PHY chip; the processing circuit 1002 is further configured to perform link training on the second parameter according to the second link training request; and the interface circuit 1001 is further configured to send second status information to the sending-end device, the second status information indicating a status after the link training on the second parameter based on the second link training request.

[0247] In some possible implementation manners, the first parameter further comprises a parameter of the receiving-end PHY chip.

[0248] In some possible implementation manners, the first link training request is a training frame, and the training frame comprises a control field, the control field being used to instruct to perform link training on the first parameter. For example, the link training on the first parameter can be instructed by a plurality of reserved bits in the control field; or the link training on the first parameter can be instructed by a reserved bit and a parameter selection field in the control field; or the link training on the first parameter can be instructed by a reserved value combination of the parameter selection field in the control field.

[0249] It should be noted that the related description of the chip 1000 can refer to the description of the related operation performed by the receiving-end PHY chip in the method 100.

[0250] Correspondingly, the embodiment of the present application further provides a communication apparatus 1100, as shown in FIG. 11, which can comprise a processing unit 1101, a sending unit 1102 and a receiving unit 1103. The receiving unit 1103 and the sending unit 1102 can correspond to the interface circuit 1001 in the chip 1000 or the interface 1201 in the communication apparatus 1200 described below; and the processing unit 1101 can correspond to the processing circuit 1002 in the chip 1000 or the processor 1202 in the communication apparatus 1200 described below.

[0251] If the communication apparatus 1100 is applied to a sending-end device, the functions of the structures in the communication apparatus 1100 are as follows:

[0252] The processing unit 1101 is configured to generate a first link training request; the sending unit 1102 is configured to send the first link training request to a receiving end PHY chip, the first link training request being used to instruct the receiving end PHY chip to perform link training on a first parameter, the first parameter at least including a parameter of a receiving end module, and the parameter of the receiving end module being a parameter of an optical module; and the receiving unit 1103 is configured to receive first state information, the first state information indicating a state after the link training on the first parameter based on the first link training request.

[0253] In some possible implementation manners, in one case, the receiving end module can include an optical module, and the parameter of the optical module is a parameter in the optical module. For example, the receiving end module is an LPO, and the parameter of the optical module is a parameter in DRV_CTLE in the LPO. In another case, the receiving end module can also include an ACC-Linear module, and the parameter of the optical module is a parameter in the ACC-Linear module.

[0254] In some possible implementation manners, for the case that the receiving end module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, a sending end module connected to the sending end PHY chip is an LPO, and the sending end device refers to the sending end PHY chip. As another example, the communication system can be an LPO-retimed architecture, that is, a sending end module connected to the sending end PHY chip is a retimed optical module, and the sending end device refers to the sending end PHY chip or the sending end module. As yet another example, the communication system can be an LPO-LRO architecture, that is, a sending end module connected to the sending end PHY chip is an LRO, and the sending end device refers to the sending end PHY chip or the sending end module.

[0255] In some possible implementation manners, for the case that the receiving end module is an LPO, as an example, the communication system can be an LPO-LPO architecture, that is, a sending end module connected to the sending end PHY chip is an LPO, and the sending end device refers to the sending end PHY chip. As another example, the communication system can be an LPO-retimed architecture, that is, a sending end module connected to the sending end PHY chip is a retimed optical module, and the sending end device refers to the sending end PHY chip or the sending end module. As yet another example, the communication system can be an LPO-LRO architecture, that is, a sending end module connected to the sending end PHY chip is an LRO, and the sending end device refers to the sending end PHY chip or the sending end module.

[0256] In the present application, the LRO can include an oDSP chip, and the TX of the receiving end PHY chip is connected to the oDSP chip of the LRO, and the RX of the sending end PHY chip is not connected to the oDSP chip of the LRO.

[0257] In some possible implementation, the processing unit 1101 is further configured to generate a second link training request, the second link training request being used to instruct the receiving-end PHY chip to perform link training on a second parameter, the second parameter comprising a parameter of the receiving-end PHY chip; the sending unit 1102 is further configured to send the second link training request to the receiving-end PHY chip; and the receiving unit 1103 is further configured to receive second state information sent by the receiving-end PHY chip, the second state information indicating a state after the second parameter is subjected to link training based on the second link training request.

[0258] In some other possible implementation, the first parameter further comprises a parameter of the receiving-end PHY chip.

[0259] In some possible implementation, the receiving unit 1103 is further configured to receive test information; and the processing unit 1101 is further configured to test a link quality of a link from the receiving-end PHY chip to the sending-end device based on the test information, and obtain a test result.

[0260] In some possible implementation, the processing unit 1101 is further configured to, if it is determined that the test result does not satisfy the first condition, generate a third link training request, the third link training request being used to instruct the receiving-end PHY chip to continue performing link training on the first parameter; the sending unit 1102 is further configured to send the third link training request to the receiving-end PHY chip; and the receiving unit 1103 is further configured to receive third state information, the third state information indicating a state after the first parameter is subjected to link training based on the third link training request.

[0261] As an example, the first condition can comprise any one of the following conditions: a variation of a value of a first quality indicator is less than or equal to a first threshold, the first quality indicator being used to represent a link quality of the link from the receiving-end PHY chip to the sending-end device, and the smaller the value of the first quality indicator, the better the corresponding link quality; a variation of a value of a second quality indicator is greater than or equal to a second threshold, the second quality indicator being used to represent a link quality of the link from the receiving-end PHY chip to the sending-end device, and the greater the value of the second quality indicator, the better the corresponding link quality.

[0262] In some possible implementation, the processing unit 1101 is further configured to, if it is determined that the test result satisfies the first condition but does not satisfy the second condition, perform link training on a third parameter, the third parameter comprising a parameter of a sending-end module, and the parameter of the sending-end module being an optical module parameter.

[0263] As an example, the second condition can include any one of the following conditions: a value of a first quality indicator is less than or equal to a third threshold, the first quality indicator is used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and a smaller value of the first quality indicator represents a better corresponding link quality; a value of a second quality indicator is greater than or equal to a fourth threshold, the second quality indicator is used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and a greater value of the second quality indicator represents a better corresponding link quality.

[0264] In some possible implementation manners, the first link training request is a training frame, and the training frame includes a control field, the control field being used to indicate that the first parameter is subjected to link training. For example, the first parameter can be indicated to be subjected to link training by a plurality of reserved bits in the control field, or the first parameter can be indicated to be subjected to link training by a reserved bit and a parameter selection field in the control field, or the first parameter can be indicated to be subjected to link training by a reserved value combination of the parameter selection field in the control field.

[0265] It should be noted that the related description of the communication apparatus 1100 can refer to the description of the related operations performed by the sending end device in the method 100.

[0266] If the communication apparatus 1100 is applied to the receiving end PHY chip, the functions of the structures in the communication apparatus 1100 are as follows.

[0267] The receiving unit 1103 is configured to receive a first link training request sent by a sending end device, the first link training request being used to indicate that the receiving end PHY chip performs link training on a first parameter, the first parameter including a parameter of a receiving end module, and the parameter of the receiving end module being a parameter of an optical module; the processing unit 1101 is configured to perform link training on the first parameter according to the first link training request; and the sending unit 1102 is configured to send first state information to the sending end device, the first state information indicating a state after the link training on the first parameter based on the first link training request.

[0268] In some possible implementation manners, the receiving end module includes an optical module, and the parameter of the optical module is a parameter in the optical module; or the receiving end module includes an ACC-Linear module, and the parameter of the optical module is a parameter in the ACC-Linear module.

[0269] In some possible implementation manners, for a case where the receiving end module is an LPO, if the sending end device is a sending end PHY chip, the sending end module connected to the sending end PHY chip is an LPO; or if the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO.

[0270] In some possible implementation manners, the first parameter further includes a parameter of the receiving-end PHY chip.

[0271] In the embodiment, the LRO includes an optical digital signal processor oDSP chip, and the transmitting end TX of the receiving-end PHY chip is connected to the oDSP chip, and the receiving end RX of the receiving-end PHY chip is not connected to the oDSP chip.

[0272] In some possible implementation manners, the processing unit 1101 is specifically configured to perform link training on the parameters of the receiving-end module through the IIC bus in response to the first link training request.

[0273] In some possible implementation manners, the receiving unit 1103 is further configured to receive a second link training request sent by the transmitting-end device, the second link training request being used to instruct the receiving-end PHY chip to perform link training on a second parameter, and the second parameter including a parameter of the receiving-end PHY chip; the processing unit 1101 is further configured to perform link training on the second parameter according to the second link training request; and the sending unit 1102 is configured to send second state information to the transmitting-end device, the second state information being used to indicate a state after the link training on the second parameter based on the second link training request.

[0274] In some possible implementation manners, the first parameter further includes a parameter of the receiving-end PHY chip.

[0275] In some possible implementation manners, the first link training request is a training frame, and the training frame includes a control field, and the control field is used to instruct to perform link training on the first parameter. For example, the link training on the first parameter can be instructed through a plurality of reserved bits in the control field; or the link training on the first parameter can be instructed through a reserved bit and a parameter selection field in the control field; or the link training on the first parameter can be instructed through a reserved value combination of the parameter selection field in the control field.

[0276] It should be noted that the related description of the communication apparatus 1100 can be referred to the description corresponding to the related operations performed by the receiving-end PHY chip in the method 100.

[0277] Correspondingly, the embodiment of the present application further provides a communication device 1200, as shown in FIG. 12. The communication device 1200 can include an interface 1201 and a processor 1202. Wherein, the interface 1201 can correspond to the interface circuit 1001 in the chip 1000 or the receiving unit 1103 and the sending unit 1102 in the communication device 1100; the processor 1202 can correspond to the processing circuit 1002 in the chip 1000 or the processing unit 1101 in the communication device 1100.

[0278] The interface 1201 is configured to receive an instruction and transmit the instruction to the processor 1202.

[0279] The processor 1202 is configured to execute the method 100 shown in FIG. 5 or the embodiment shown in FIG. 6.

[0280] In addition, the embodiment of the present application further provides a communication system 1300, as shown in FIG. 13. The communication system 1300 can include a sending end device 1301 and a receiving end PHY chip 1302.

[0281] Wherein, the sending end device 1301 is configured to execute the steps performed by the sending end device in the method 100 or the embodiment shown in FIG. 6.

[0282] The receiving end PHY chip 1302 is configured to execute the steps performed by the receiving end PHY chip in the method 100 or the embodiment shown in FIG. 6.

[0283] In addition, the embodiment of the present application further provides a storage medium, and the storage medium stores program codes or instructions, when the program codes or instructions are executed on a processor, the processor executes the method in any one of the implementation manners in the above embodiments.

[0284] In addition, the embodiment of the present application further provides a program product, when the program product is executed on a processor, the processor executes the method in any one of the implementation manners in the above embodiments.

[0285] It should be understood that the "determining B according to A" mentioned in the embodiment of the present application does not mean that B is determined only according to A, but also can be determined according to A and / or other information.

[0286] It should be understood that the network architecture and the business scenario described in the embodiment of the present application are for more clearly illustrating the technical solutions of the embodiment of the present application, and do not constitute a limitation on the technical solutions provided by the embodiment of the present application. It is known to those skilled in the art that, with the evolution of network architecture and the appearance of new business scenarios, the technical solutions provided by the embodiment of the present application are also applicable to similar technical problems.

[0287] The ordinal numbers "1", "2", "3", "first", "second", "third" and the like in the present application are used to distinguish a plurality of objects, and are not used to limit the order of the plurality of objects.

[0288] The "A and / or B" mentioned in the present application should be understood as including the following cases: only A, only B, or both A and B.

[0289] From the description of the above embodiments, a person skilled in the art can clearly understand that all or part of the steps of the above-mentioned embodiment methods can be implemented by means of software plus a general hardware platform. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as a read-only memory (English: read-only memory, ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network communication device such as a router) execute the methods described in various embodiments or some parts of the embodiments.

[0290] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for system embodiments and device embodiments, since they are basically similar to method embodiments, they are described more simply, and the relevant parts can be referred to the part of the method embodiments. The above-described device and system embodiments are only illustrative, and the modules described as separate components can be or can not be physically separated, and the components shown as modules can be or can not be physical modules, i.e., they can be located in one place or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment according to actual needs. A person of ordinary skill in the art can understand and implement it without creative labor.

[0291] The above is only the preferred embodiment of the present application, and is not used to limit the protection scope of the present application. It should be noted that, for those skilled in the art, without departing from the present application, a number of improvements and refinements can also be made, which should also be considered as the protection scope of the present application.

Claims

A link training method, characterized in that, The method comprises: A sending end device generates a first link training request, the first link training request being used to instruct a receiving end PHY chip to perform link training on a first parameter, the first parameter comprising a parameter of a receiving end module, the parameter of the receiving end module being an optical module parameter; The sending end device sends the first link training request to the receiving end PHY chip; The sending end device receives first state information, the first state information indicating a state after the first parameter is subjected to link training based on the first link training request. The method of claim 1, wherein The method further comprises: The sending end device generates a second link training request, the second link training request being used to instruct the receiving end PHY chip to perform link training on a second parameter, the second parameter comprising a parameter of the receiving end PHY chip; The sending end device sends the second link training request to the receiving end PHY chip; The sending end device receives second state information sent by the receiving end PHY chip, the second state information indicating a state after the second parameter is subjected to link training based on the second link training request. The method of claim 1, wherein The first parameter further comprises a parameter of the receiving end PHY chip. The method according to any one of claims 1 to 3, characterized in that The method further comprises: The sending end device receives test information; The sending end device tests a link quality of a link from the receiving end PHY chip to the sending end device based on the test information, and obtains a test result. The method according to claim 4, characterized in that The method further comprises: If the sending end device determines that the test result does not satisfy a first condition, the sending end device generates a third link training request, the third link training request being used to instruct the receiving end PHY chip to continue performing link training on the first parameter; The sending end device sends the third link training request to the receiving end PHY chip; The sending end device receives third state information, the third state information indicating a state after the first parameter is subjected to link training based on the third link training request. The method according to claim 5, characterized in that The first condition comprises any one of the following conditions: A variation of a value of a first quality index is less than or equal to a first threshold, the first quality index being used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and the smaller the value of the first quality index, the better the corresponding link quality; A variation of a value of a second quality index is greater than or equal to a second threshold, the second quality index being used to represent a link quality of a link from the receiving end PHY chip to the sending end device, and the greater the value of the second quality index, the better the corresponding link quality. The method according to claim 5 or 6, characterized in that The method further comprises: If the sending end device determines that the test result satisfies the first condition but does not satisfy a second condition, the sending end device performs link training on a third parameter, the third parameter comprising a parameter of a sending end module, the parameter of the sending end module being an optical module parameter. The method of claim 7, wherein The second condition comprises any one of the following conditions: The first quality index is less than or equal to a third threshold, and the first quality index is used to represent the link quality of the link from the receiving end PHY chip to the sending end device, and the smaller the value of the first quality index, the better the corresponding link quality; The second quality index is greater than or equal to a fourth threshold, and the second quality index is used to represent the link quality of the link from the receiving end PHY chip to the sending end device, and the greater the value of the second quality index, the better the corresponding link quality. The method according to any one of claims 1 to 8, characterized in that The first link training request is a training frame, and the training frame includes a control field, and the control field is used to indicate that the first parameter is subjected to link training. The method of claim 9, wherein The first parameter is subjected to link training through a plurality of reserved bits in the control field; Or, the first parameter is subjected to link training through a reserved bit and a parameter selection field in the control field; Or, the first parameter is subjected to link training through a reserved value combination of the parameter selection field in the control field. The method of any one of claims 1-10, wherein The receiving end module includes an optical module, and the optical module parameter is a parameter in the optical module; Or, the receiving end module includes an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module. The method according to any one of claims 1 to 10, characterized in that The receiving end module is an LPO, the sending end device is a sending end PHY chip, and the sending end module connected to the sending end PHY chip is an LPO; Or, the receiving end module is an LPO, the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO, the LRO includes an oDSP chip, the TX of the receiving end PHY chip is connected to the oDSP chip, and the RX of the receiving end PHY chip is not connected to the oDSP chip. The method according to any one of claims 1 to 10, characterized in that The receiving end module is an LRO, the sending end device is a sending end PHY chip, and the sending end module connected to the sending end PHY chip is an LPO; Or, the receiving end module is an LRO, the sending end device is a sending end PHY chip or a sending end module, and the sending end module is a traditional optical module or an LRO; The LRO includes an oDSP chip, the TX of the receiving end PHY chip is connected to the oDSP chip, and the RX of the receiving end PHY chip is not connected to the oDSP chip. A link training method, characterized in that, The method comprises: The receiving end PHY chip receives a first link training request sent by the sending end device, the first link training request is used to instruct the receiving end PHY chip to perform link training on a first parameter, the first parameter includes a parameter of a receiving end module, and the parameter of the receiving end module is an optical module parameter; The receiving end PHY chip performs link training on the first parameter according to the first link training request; and The receiving end PHY chip performs link training on the first parameter according to the first link training request. The receiving end PHY chip sends first status information to the sending end device, and the first status information indicates a state after link training of the first parameter based on the first link training request. The method of claim 14, wherein The receiving end PHY chip performs link training on the first parameter according to the first link training request, including: In response to the first link training request, the receiving end PHY chip performs link training on the parameter of the receiving end module through an internal integrated circuit (IIC) bus. The method according to claim 14 or 15, characterized in that The method further includes: The receiving end PHY chip receives a second link training request sent by the sending end device, and the second link training request is used to instruct the receiving end PHY chip to perform link training on a second parameter, and the second parameter includes a parameter of the receiving end PHY chip; The receiving end PHY chip performs link training on the second parameter according to the second link training request; The receiving end PHY chip sends second status information to the sending end device, and the second status information indicates a state after link training of the second parameter based on the second link training request. The method according to claim 14 or 15, characterized in that The first parameter further includes a parameter of the receiving end PHY chip. The method according to any one of claims 14-17, characterized in that The first link training request is a training frame, and the training frame includes a control field used to instruct link training on the first parameter. The method according to claim 18, characterized in that, link training on the first parameter is instructed through a plurality of reserved bits in the control field; or link training on the first parameter is instructed through a reserved bit and a parameter selection field in the control field; or link training on the first parameter is instructed through a reserved value combination of the parameter selection field in the control field. The method according to any one of claims 14-19, characterized in that, the receiving end module includes an optical module, and the optical module parameter is a parameter in the optical module; or the receiving end module includes an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module. The method according to any one of claims 14-19, characterized in that The receiving end module is an LPO, the sending end device is a sending end PHY chip, and a sending end module connected to the sending end PHY chip is an LPO; or the receiving end module is an LPO, the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO, the LRO includes an oDSP chip, a sending end TX of the receiving end PHY chip is connected to the oDSP chip, and a receiving end RX of the receiving end PHY chip is not connected to the oDSP chip. The method according to any one of claims 14-19, characterized in that The receiving end module is an LPO, the sending end device is a sending end PHY chip, and a sending end module connected to the sending end PHY chip is an LPO; or the receiving end module is an LPO, the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO; The LRO includes an optical digital signal processor (oDSP) chip, a transmitting end TX of the receiving end PHY chip is connected to the oDSP chip, and a receiving end RX of the transmitting end PHY chip is not connected to the oDSP chip. A communication device, characterized by The communication device includes an interface and a processor; The interface is configured to receive an instruction and transmit the instruction to the processor; The processor is configured to execute the method in any one of claims 1-22. A chip characterized by The chip includes an interface circuit and a processing circuit; The processing circuit is configured to generate a first link training request, the first link training request being used to instruct a receiving end PHY chip to perform link training on a first parameter, the first parameter including a parameter of a receiving end module, and the parameter of the receiving end module being an optical module parameter; The interface circuit is configured to send the first link training request to the receiving end PHY chip; The interface circuit is further configured to receive first state information, the first state information indicating a state after the first parameter is subjected to link training based on the first link training request. The chip according to claim 24, wherein The processing circuit is further configured to generate a second link training request, the second link training request being used to instruct the receiving end PHY chip to perform link training on a second parameter, the second parameter including a parameter of the receiving end PHY chip; The interface circuit is further configured to send the second link training request to the receiving end PHY chip; The interface circuit is further configured to receive second state information sent by the receiving end PHY chip, the second state information indicating a state after the second parameter is subjected to link training based on the second link training request. The chip according to claim 24, wherein The first parameter further includes the parameter of the receiving end PHY chip. The chip according to any one of claims 24-26, wherein The interface circuit is further configured to receive test information; The processing circuit is further configured to test a link quality of a link from the receiving end PHY chip to the transmitting end device based on the test information, and obtain a test result. The chip according to claim 27, wherein The processing circuit is further configured to generate a third link training request if it is determined that the test result does not satisfy a first condition, the third link training request being used to instruct the receiving end PHY chip to continue performing link training on the first parameter; The interface circuit is further configured to send the third link training request to the receiving end PHY chip; The interface circuit is further configured to receive third state information, the third state information indicating a state after the first parameter is subjected to link training based on the third link training request. The chip according to claim 28, characterized in that The first condition includes any one of the following conditions: A variation of a value of a first quality index is less than or equal to a first threshold, the first quality index being used to represent a link quality of a link from the receiving end PHY chip to the transmitting end device, and the smaller the value of the first quality index, the better the corresponding link quality. The second quality index is used to represent the link quality of the link from the receiving end PHY chip to the sending end device, and the greater the value of the second quality index represents the better the corresponding link quality. The chip according to any one of claims 28-33, wherein The processing circuit is further configured to perform link training on a third parameter if it is determined that the test result satisfies the first condition but does not satisfy a second condition, wherein the third parameter comprises a parameter of a sending end module, and the parameter of the sending end module is an optical module parameter. The chip according to claim 30, wherein The second condition comprises any one of the following conditions: The first quality index is used to represent the link quality of the link from the receiving end PHY chip to the sending end device, and the smaller the value of the first quality index represents the better the corresponding link quality; The second quality index is used to represent the link quality of the link from the receiving end PHY chip to the sending end device, and the greater the value of the second quality index represents the better the corresponding link quality. The chip according to any one of claims 24-31, wherein The first link training request is a training frame, and the training frame comprises a control field, and the control field is used to indicate that the first parameter is subjected to link training. The chip according to claim 32, wherein The control field comprises a plurality of reserved bits, and the plurality of reserved bits are used to indicate that the first parameter is subjected to link training. Alternatively, the control field comprises one reserved bit and a parameter selection field, and the one reserved bit and the parameter selection field are used to indicate that the first parameter is subjected to link training. Alternatively, the parameter selection field of the control field comprises a reserved value combination, and the reserved value combination is used to indicate that the first parameter is subjected to link training. The chip according to any one of claims 24-33, wherein The receiving end module comprises an optical module, and the optical module parameter is a parameter in the optical module. Alternatively, the receiving end module comprises an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module. The chip according to any one of claims 24-33, wherein The receiving end module is an LPO, and the chip is a sending end PHY chip, and the sending end module connected to the sending end PHY chip is the LPO. Alternatively, the receiving end module is the LPO, the chip is a sending end PHY chip or a chip in a sending end module, the sending end module is a traditional optical module or an LRO, the LRO comprises an oDSP chip, a sending end TX of the receiving end PHY chip is connected to the oDSP chip, and a receiving end RX of the receiving end PHY chip is not connected to the oDSP chip. The chip according to any one of claims 24-33, wherein The receiving end module is the LRO, and the chip is a sending end PHY chip, and the sending end module connected to the sending end PHY chip is the LPO. Alternatively, the receiving end module is the LRO, and the chip is a sending end PHY chip or a chip in a sending end module, and the sending end module is a traditional optical module or an LRO. The LRO includes an optical digital signal processor oDSP chip, a transmitting end TX of the receiving end PHY chip is connected to the oDSP chip, and a receiving end RX of the transmitting end PHY chip is not connected to the oDSP chip. A chip characterized by The chip is a receiving end PHY chip, and the chip includes an interface circuit and a processing circuit; The interface circuit is configured to receive a first link training request sent by a transmitting end device, and the first link training request is used to instruct the receiving end PHY chip to perform link training on a first parameter, the first parameter including a parameter of a receiving end module, and the parameter of the receiving end module being an optical module parameter; The processing circuit is configured to perform link training on the first parameter according to the first link training request; The interface circuit is further configured to send first state information to the transmitting end device, the first state information indicating a state after the link training on the first parameter based on the first link training request. The chip according to claim 37, wherein The processing circuit is specifically configured to: In response to the first link training request, perform link training on the parameter of the receiving end module through an internal integrated circuit IIC bus. The chip according to any one of claims 37 or 38, The interface circuit is further configured to receive a second link training request sent by the transmitting end device, and the second link training request is used to instruct the receiving end PHY chip to perform link training on a second parameter, the second parameter including a parameter of the receiving end PHY chip; The processing circuit is further configured to perform link training on the second parameter according to the second link training request; The interface circuit is further configured to send second state information to the transmitting end device, the second state information indicating a state after the link training on the second parameter based on the second link training request. Chip according to claim 37 or 38, characterized in that The first parameter further includes the parameter of the receiving end PHY chip. The chip according to any one of claims 37-40, wherein The first link training request is a training frame, and the training frame includes a control field, and the control field is used to instruct the link training on the first parameter. The chip according to claim 41, The link training on the first parameter is instructed through a plurality of reserved bit positions in the control field; or the link training on the first parameter is instructed through a reserved bit position and a parameter selection field in the control field; or the link training on the first parameter is instructed through a reserved value combination of the parameter selection field in the control field. The chip according to any one of claims 37-42, The receiving end module includes an optical module, and the optical module parameter is a parameter in the optical module; or the receiving end module includes an ACC-Linear module, and the optical module parameter is a parameter in the ACC-Linear module. The chip according to any one of claims 37-42, wherein The receiving end module is an LPO, and the transmitting end device is a transmitting end PHY chip, and a transmitting end module connected to the transmitting end PHY chip is the LPO; Or, the receiving end module is an LPO, the sending end device is a sending end PHY chip or a sending end module, the sending end module is a traditional optical module or an LRO, the LRO includes an optical digital signal processor oDSP chip, a sending end TX of the receiving end PHY chip is connected to the oDSP chip, and a receiving end RX of the sending end PHY chip is not connected to the oDSP chip. The chip according to any one of claims 37-42, wherein The receiving end module is an LRO, the sending end device is a sending end PHY chip, and a sending end module connected to the sending end PHY chip is an LPO; Or, the receiving end module is an LRO, the sending end device is a sending end PHY chip or a sending end module, and the sending end module is a traditional optical module or an LRO. The LRO includes an optical digital signal processor oDSP chip, a sending end TX of the receiving end PHY chip is connected to the oDSP chip, and a receiving end RX of the sending end PHY chip is not connected to the oDSP chip. A communication system characterized by The communication system includes a receiving end PHY chip and a sending end device; The sending end device is configured to perform the method in any one of claims 1-13; The receiving end PHY chip is configured to perform the method in any one of claims 14-22.

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