Processing apparatus, storage management method, and related device

Abstract

Disclosed in embodiments of the present application are a processing apparatus, a storage management method, and a related device. The apparatus may comprise a processor core, a last-stage cache LLC, and a memory controller. The memory controller is used for: receiving a first memory access request sent by the processor core and used for reading first data, the first memory access request carrying a first memory access address; on the basis of the first memory access address, reading memory access data from a memory coupled to the processing apparatus; and if the memory access data comprises the first data and second data in a compressed state, in response to the first memory access request, sending the first data to the processor core by means of the LLC, and caching the second data in the compressed state to the LLC. The processing apparatus of the present application can reduce the overhead of storage resources on the basis of memory bandwidth compression technology.

Description

Processing device, storage management method and related equipment

[0001] The present application claims priority to the Chinese patent application No. 202410608522.3, filed on May 15, 2024, entitled "Processing device, storage management method and related equipment", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of memory access technology, and in particular to a processing device, a storage management method and related equipment. BACKGROUND

[0003] Memory is one of the important components in a computer, which is a bridge for communication with the central processing unit (CPU). The running of all programs in the computer is carried out in the memory, so the performance of the memory has a great influence on the computer. The memory is also called internal storage, which is used to temporarily store the operation data in the CPU and exchange data with external storage such as hard disk. When the computer is running, the CPU will transfer the data needed for operation to the memory for operation, and then the CPU will transfer the result after the operation is completed. The running of the memory also determines the stable operation of the computer.

[0004] In the conventional technology, the system increases the frequency or the number of pins of the memory interface to improve the bandwidth between the system on chip (SoC) and the memory, but these technologies often bring energy consumption and area cost. In addition, the interface change is often slow because a new memory standard needs a long cycle to be proposed once. With the rapid increase in the number of cores of mainstream server processors, the memory wall is becoming increasingly prominent, for example, the bandwidth between the level 3 cache (L3) capacity on the SoC side and the double data rate synchronous dynamic random access memory (DDR) becomes a significant performance bottleneck.

[0005] The memory bandwidth compression technology is a technology for improving the memory bandwidth of a computer system, and is an effective method for solving the SoC bottleneck of a system. Specifically, the memory bandwidth compression technology stores compressed data into a memory, so that the memory system can transmit data through fewer pins, thereby improving the effective bandwidth. However, in the prior art, the memory bandwidth compression technology itself has overhead, including caching of data prefetched due to compression. For example, when the address length of a memory access request is less than the actual length of the compressed data stored at the address (or a related address), additional data other than the request will be moved to the on-chip space. Due to the characteristics of program locality, this type of data may be accessed soon, so additional cache space is needed to store the data. However, when these data are not used, the space used to store the data will be wasted, unnecessarily occupying on-chip space. SUMMARY

[0006] Embodiments of the present application provide a storage management method and device and related equipment, which can save memory bandwidth and reduce the overhead of storage resources.

[0007] In a first aspect, embodiments of the present application provide a processing device, which can include a processor core, a last level cache (LLC) and a memory controller. The memory controller is configured to receive a first memory access request for reading first data sent by the processor core, the first memory access request carrying a first memory access address; read memory access data from a memory coupled to the processing device based on the first memory access address; and if the memory access data includes the first data and second data in a compressed state, send the first data to the processor core through the LLC and cache the second data in the compressed state to the LLC in response to the first memory access request.

[0008] The embodiments of the present application increase the compression mechanism on the side of the on-chip cache on the basis of the memory bandwidth compression technology, that is, in addition to storing compressed data in the memory concerned, the compressed data is also cached in the last level cache (LLC) of the processing device to save the on-chip storage resources. Specifically, the embodiments of the present application provide a processing device, when additional compressed data is read out from the memory due to the memory bandwidth compression mechanism, the original compressed state of the additional compressed data is still maintained for caching (that is, stored in the last level cache in the compressed state), thereby effectively reducing the overhead of the on-chip storage resources on the basis of saving the memory bandwidth. Unlike the prior art, after the compressed data is read from the memory, it needs to be cached on the chip in the uncompressed state, the embodiments of the present application take out the additional compressed data from the memory without decompressing the additional compressed data but caching it in the original compressed state in the LLC, and if the additional compressed data in the compressed state needs to be read out from the LLC to the upper level cache, it can be read out and decompressed. On the one hand, since the additional data is compressed, the bandwidth between the on-chip and off-chip is saved in the process of reading from the memory (such as DDR) to the last level cache (such as L3) compared with the uncompressed data; on the other hand, since the additional compressed data is cached in the LLC in the form of maintaining its original compressed state, the storage space of the LLC (such as L3) can be saved, and the larger the amount of additional data read, the greater the benefit. For example, in some cases, when the read memory data includes additional data other than the first memory request and the additional data is in the compressed state, not only the memory bandwidth and the storage overhead of the on-chip memory data can be saved, but also considering the characteristics of program locality, the pre-fetched additional compressed data is likely to be accessed soon, so that the probability and efficiency of the subsequent data hit on the chip can be improved, the number of memory access can be reduced, and the overall performance of memory access can be improved. In summary, the present application sets a joint compression mechanism between the LLC and the memory, stores the compressed data in the cache and the memory by using the same preset compression rule, realizes the effect of once compression and twice storage, further reduces the data storage overhead of the on-chip system (SoC) on the basis of reducing the bandwidth between the on-chip system and the off-chip storage system, and solves the technical problems of low compression rate and low space utilization rate when the cache and the memory are compressed separately. In addition, the embodiments of the present application do not need a separate on-chip storage space, that is, the resources of the LLC on the chip are reused, and the chip area on the chip is effectively reduced.

[0009] In a possible implementation, the memory data further includes a compression identifier for indicating whether the second data is in the compressed state; and the memory controller is further configured to cache the compression identifier to the LLC.

[0010] In the embodiments of the present application, if the compressed data stored in the memory carries a compression identifier indicating whether the data is in a compressed state, the compression identifier can be cached into the LLC together with the data. In this way, the compression state of the data in a certain address can be determined based on the compression identifier, regardless of whether the data is on-chip or in the memory. When the compression identifier is cached into the LLC together with the data, the compression state of the corresponding data can be determined based on the compression identifier cached in the LLC, thereby facilitating relevant read / write operations. For example, if a certain data needs to be read from the memory, the compression identifier can be used to determine whether the data needs to be decompressed or compressed.

[0011] In a possible implementation, if the first data is in a compressed state, the memory controller is specifically configured to: in response to the first memory access request, send the first data in a compressed state to the LLC; the LLC is configured to: receive and cache the first data in the compressed state, read and decompress the cached first data in the compressed state, and send the decompressed data to the processor core; the LLC is configured to: decompress the received first data in the compressed state and send the decompressed data to the processor core; wherein the first data in the compressed state is obtained by compressing part or all of the original data corresponding to the first memory access address, and the second data in the compressed state is obtained by compressing part or all of the original data corresponding to the second memory access address in the memory.

[0012] When the access data read from the memory by the access request contains additional data other than the requested access address, and the additional data is compressed data, the embodiments of the present application will read the redundant compressed data and store it in the LLC in the original compressed state. Among them, the additional data read from the access address is mainly due to the compressed state of the data stored in the memory. For example, when the length of the access request (requesting 64B original data, compressed to 32B) is less than the actual length of the compressed data (such as storing two adjacent 64B compressed data as two 32B in the same memory cell), due to the granularity of the access (i.e. the minimum size of data taken out by one access request, such as 64B), the additional data will be moved to the on-chip space, or due to the prediction error of the data compression state (the original prediction is that the 64B data is non-compressed data, but in fact the 64B data is compressed data), which causes the redundant 32B compressed data to be read to the on-chip. Based on the above reasons, when the additional access data (such as adjacent data or adjacent compressed data) is read from the memory, the embodiments of the present application will read the redundant compressed data and store it in the L3 in the original compressed state. In this way, since the data reading usually has a certain continuity, when the next time the additional access data needs to be read, it can be read from the on-chip LLC (such as L3) without reading from the off-chip memory (DDR) again. On the one hand, it saves the memory access times (the same size of data needs two access times before, now only one access time is needed), that is, when the next time the additional data needs to be accessed, there is no need to access the memory, so the hit efficiency is higher. On the other hand, when the read data is also in the compressed state (i.e. the first data is in the compressed state, which can also be referred to as the first compressed data), the actual data and the additional data (i.e. the second data in the compressed state, which can also be referred to as the second compressed data) are all cached in the LLC in the original compressed state, so the storage overhead of the on-chip cache is greatly saved. Further, since the read data is compressed, the memory bandwidth is saved compared with non-compressed data during the process of reading from the memory to the LLC.

[0013] In a possible implementation, if the first data is in the compressed state, the memory controller is specifically configured to: in response to the first access request, send the first data in the compressed state to the LLC; and the LLC is configured to send the first data in the compressed state received to the processor core after decompression.

[0014] When the access data read out from the memory by the access request contains extra data other than the requested access address, and the extra data is compressed data, the embodiments of the present application will store the redundant compressed data in this readout and keep the original compressed state in the LLC. However, in different cache mechanisms, mutual exclusion mechanisms may be set between different levels of caches. When there is a mutual exclusion mechanism between the LLC and its upper level cache, the data actually requested by the access (i.e. the first data in the compressed state, which can also be referred to as the first compressed data) can not be cached to the LLC, but directly cached to the upper level cache of the LLC after being read out from the memory. Since the first data read out in the embodiments of the present application is in a compressed state, the decompressed data can be cached to the upper level cache of the LLC (i.e. without being cached to the LLC) after being decompressed by the LLC. For example, the LLC is L3, and it is assumed that there is a mutual exclusion mechanism between L3 and L2. Therefore, only one copy of the data is retained between the two, and the other copy is not retained in the corresponding cache. That is, after the data is read out from L3 and written to L2, the data does not need to be retained in L3. Conversely, when the data is read out from L2 and written to L3, the data does not need to be retained in L2. Therefore, after the access data is read out from the memory, it is assumed that the first compressed data is the data actually needed to be read in the access request, and since the data requested by the processor core to access is ultimately needed to be read into the processor core, i.e. the first compressed data needs to be read out from the memory and cached to L2→L1→the processor core. Therefore, if L3 and L2 are mutually exclusive, the first compressed data does not need to be cached to L3, but can be decompressed by the LLC and then cached to L2 in a non-compressed state.

[0015] In a possible implementation, if the access data includes the first data and the first data is in a compressed state, the memory controller is further configured to: in response to the first access request, send the first data in a compressed state to the LLC; and the LLC is configured to: receive and cache the first data in a compressed state, read and decompress the cached first data in a compressed state, and send the decompressed data to the processor core; or the LLC is configured to: decompress the received first data in a compressed state, and send the decompressed data to the processor core.

[0016] In the embodiments of the present application, when the read access data includes the compressed state first data (which can also be referred to as first compressed data) stored in the partial address in the first access address, the read first compressed data is equivalent to the original data (i.e., the first data) corresponding to the first access address compressed by the preset compression rule. In this case, the first compressed data is stored in the LLC in the compressed state, and further, in response to the first access request, the LLC reads the first compressed data cached in the LLC, then decompresses and writes to the upper cache, and finally sends to the processor core. For example, the CPU core requests to read the original data (i.e., 128B uncompressed data) corresponding to the first access address. If the original data is compressed to 64B compressed data and actually stored in the lower 64B address in the 128B address, the partial access address (i.e., the address of the lower 64B actually stored data in the 128B address) in the first access address is read, and the first compressed data is cached in the LLC in the original compressed state. Subsequently, if the processor core needs to read the data, the data needs to be written to the upper cache, i.e., the 64B compressed data is decompressed and written to the upper cache.

[0017] In a possible implementation, if the access data includes the first data, and the first data is in the uncompressed state, the memory controller is further configured to: in response to the first access request, send the first data in the uncompressed state to the LLC; and the LLC is configured to receive and cache the first data in the uncompressed state and send to the processor core; or the LLC is configured to send the received first data in the uncompressed state to the processor core.

[0018] In the embodiments of the present application, when the read access data includes the non-compressed data originally stored in the memory in the uncompressed state, in a possible implementation, the non-compressed data can be directly stored in the LLC in the non-compressed state. The reason is that, considering that in some scenarios, the compressed data or non-compressed data stored in the memory is written from the on-chip to the memory, i.e., when a certain data can be compressed, it has been compressed on-chip (LLC or memory controller) and written to the memory, and when a certain data cannot be compressed, it is written to the memory in the uncompressed state. Therefore, the compressed or uncompressed state data stored in the memory can indicate whether the data can be compressed. Therefore, when reading a certain data from the memory, it can no longer be necessary to determine whether it can be compressed, because its current compression state already indicates whether the data can be compressed. Therefore, in the embodiments of the present application, it can no longer be necessary to re-determine, but can be directly written to the LLC in the non-compressed state or compressed state of the data originally in the memory.

[0019] In a possible implementation, if the access data includes the first data, and the first data is in a non-compressed state; the memory controller is further configured to: in response to the first access request, send the first data in the non-compressed state to the LLC; and the LLC is configured to: if the first data in the non-compressed state is compressible, compress and cache the received first data in the non-compressed state, and send the first data in the non-compressed state to the processor core; if the first data in the non-compressed state is not compressible, receive and cache the first data in the non-compressed state, and send the first data in the non-compressed state to the processor core.

[0020] In the embodiment of the application, when the read access data includes non-compressed data originally stored in the memory in a non-compressed state, in another possible implementation, it can be determined whether the data can be compressed first. If the data can be compressed, the data is compressed and then stored in the LLC, and the compression rule is consistent with the compression rule of the compressed data in the memory, so that subsequent transmission between the memory and the LLC can be performed according to the original compression state of the data, that is, the data is compressed once in the LLC (such as L3) and the memory (such as DDR), and the storage effect in the two places is achieved. If the data cannot be compressed, the data is stored in the LLC in a non-compressed state, and then the data is directly written into the cache of the upper level of the LLC to be finally sent to the processor core. That is, it is considered that in some cases, some data is not compressed when written from the LLC into the memory, but when written from the memory into the LLC, it may be compressed again due to the current bandwidth requirement or the change of the attribute of the data, resulting in the case that the data is not compressed when stored in the memory, but needs to be compressed again when taken out from the memory and stored in the cache. Therefore, in the embodiment of the application, the non-compressed data in the memory can be compressed as much as possible according to the requirement, so as to improve the data compression rate in the storage system as much as possible, and reduce the bandwidth and storage overhead.

[0021] In a possible implementation, the memory controller stores a mapping relationship between address information and data compression information; and the memory controller is specifically configured to: determine the data compression information corresponding to the first access address based on the mapping relationship; and read the access data from the memory based on the first access address and the corresponding data compression information.

[0022] In the embodiments of the present application, the memory access system stores the mapping relationship between the address information and the data compression information, for example, whether a certain address is a high-order address or a low-order address in a compression unit, and the data compression information includes whether the data is compressed data, uncompressed data, or non-stored data, etc. Based on the address information of the first memory access address and the data compression information corresponding to the first memory access address, it can be determined which data needs to be read out for the first memory access address in the memory access request. It should be noted that, originally in the memory access process, only the data stored in the memory access address needs to be read out, but since the present application is based on the memory bandwidth compression mechanism, there are some cases where the memory access address and the stored data are not strictly matched, because the addresses occupied by some compressed data will change to a certain extent, and this change is related to the preset compression mechanism used in the present application, that is, different compression algorithms may lead to different accurate correspondence between the memory access address and the data.

[0023] In a possible implementation, the storage granularity of the LLC is a cache line; and the memory controller is specifically configured to: if it is determined that the first memory access address belongs to a first type of address, read the memory access data stored in the first memory access address; the first type of address includes an address whose address length is less than or equal to the cache line and that stores data, or an address whose address length is greater than the cache line and that stores original data; or, if it is determined that the first memory access address belongs to a second type of address, read the memory access data stored in a second memory access address; the second type includes an address whose address length is less than or equal to the cache line and whose corresponding original data compression data is stored in the second memory access address; or, if it is determined that the first memory access address belongs to a third type of address, read the memory access data stored in part of the memory access addresses in the first memory access address; the third type of address includes an address whose address length is greater than the cache line and whose corresponding original data compression data is stored in the part of the memory access addresses.

[0024] In the embodiments of the present application, since it is based on the memory bandwidth compression mechanism, in some cases, the actual data stored in the first memory access address may not be the original data corresponding to the address, or in other words, the original data originally requested by the first memory access request is not stored in the first memory access address, therefore, the data requested by the first memory access request may be to read part or all of the first memory access address, or it may be to read data in other addresses other than the first memory access address. In the embodiments of the present application, based on the different final addresses from which the memory access data is read, the types of the first memory access address are divided into three different cases:

[0025] In the first case, the access data is stored in the first access address, for example including: 1, requesting to read data in the low 64B, whether the data is compressed or not, directly reading the data in the first access address; 2, requesting to read data in the high 64B, if the data is not compressed, directly reading the data in the first access address; 3, requesting to read 128B data, if the data is non-compressed data, directly reading the data in the first access address; in the above case 1, the first access address stores the corresponding original data (i.e. the first data in the non-compressed state) or the compressed data of the original data corresponding to the first access address and the second access address (i.e. the first data in the compressed state and the second data in the compressed state); in the above cases 2 and 3, the first access address stores the corresponding original data (i.e. the first data in the non-compressed state);

[0026] In the second case, the first access address does not store data, and the access data is stored in the second access address, for example including: 4, requesting to read data in the high 64B, if the data is compressed, there is no data stored in the high 64B, and the compressed data needs to be read from the low 64B (i.e. the second access address); in the above case 4, that is, the original data that should be stored in the first access address is stored in other access addresses (such as the second access address) due to the memory bandwidth compression mechanism, so that the original data corresponding to the first access address needs to be read from the second access address, and usually in this case, the second access address also stores the original data corresponding to the second access address, that is, the second access address stores the compressed data of the original data corresponding to the first access address and the second access address (i.e. the first data in the compressed state and the second data in the compressed state);

[0027] In the third case, the access data is stored in part of the first access address, for example including: 5, requesting to read 128B data, if the data is compressed, reading the data in part of the first access address; in the above case 5, the original data corresponding to the first access address is actually stored in part of the first access address, that is, the original data corresponding to the first access address (i.e. the first data in the non-compressed state) is stored in part of the first access address after compression, so that reading the original data in the first access address only needs to read the corresponding address in the first access address.

[0028] In a possible implementation, the apparatus further includes a cache or a multi-level cache of the LLC; the first access request further includes a third access address; and the memory controller is further configured to: before reading the access data from the memory based on the first access address, hit the data corresponding to the third access address from the LLC or the cache or the multi-level cache of the LLC.

[0029] In the embodiments of the present application, when the processor (specifically, the processor core) initiates a first memory access request, in some possible cases, the first memory access request can contain a longer address than the first memory access address (i.e., an address containing the first memory access address and a third memory access address), and only because the data corresponding to the third memory access address has been hit in the L1, L2 or L3, it is necessary to find the data of the remaining first memory access address in the memory.

[0030] In a possible implementation, the apparatus further includes a next-level cache of the LLC; and the memory controller is further configured to: receive a second memory access request of writing third data cached in the LLC to the next-level cache, and determine whether the third data is compressed data; and the LLC is further configured to: if the third data is in a compressed state, decompress the third data in the compressed state, and write the decompressed third data to the next-level cache; or if the third data is in a non-compressed state, write the third data in the non-compressed state to the next-level cache.

[0031] In the embodiments of the present application, when it is necessary to request writing data in the LLC (such as L3) to the next-level cache or the cache above the next-level cache, it is necessary to read the data from the LLC, and because the LLC in the embodiments of the present application stores compressed data or non-compressed data compressed according to a preset compression rule, it is necessary to first determine whether the data is compressed data, if the data is compressed data, then it is necessary to first decompress the compressed data and then write the decompressed data to the next-level cache (because the CPU core finally needs to read non-compressed original data), if the data is non-compressed data, the non-compressed data is directly read and written to the next-level cache and then sent to the processor core.

[0032] In a possible implementation, the apparatus further includes a next-level cache of the LLC; and the memory controller is further configured to: receive a second memory access request of writing third data cached in the LLC to the next-level cache, and determine whether the third data is compressed data; and the LLC is further configured to: if the third data is in a compressed state, decompress the third data in the compressed state, and write the decompressed third data to the next-level cache; or if the third data is in a non-compressed state, write the third data in the non-compressed state to the next-level cache.

[0033] In the embodiments of the present application, when data needs to be written (kicked out or evicted) from the upper-level cache to the LLC cache, it is necessary to first determine whether the data can be compressed. If the data can be compressed, the data is compressed first and then cached in the LLC. If the data cannot be compressed, the data is cached in the non-compressed state, so that the data can be directly stored in the memory in the compressed state or the non-compressed state subsequently. That is, for a certain data, when the data can be compressed, the data is preferentially compressed in the LLC, and when the data is written into the memory subsequently, the data does not need to be determined and compressed again, but can be directly written into the memory in the compressed state. When a certain data cannot be compressed, the data is stored in the LLC in the non-compressed state, and when the data is written into the memory subsequently, the data can be directly written into the memory in the non-compressed state without the need for determination and compression again.

[0034] In a possible implementation, the memory controller is further configured to receive a third memory access request for writing fifth data cached in the LLC to the memory; and the LLC is further configured to write the fifth data in the compressed state to the memory if the fifth data is in the compressed state.

[0035] In the embodiments of the present application, when data cached in the last-level cache LLC needs to be written into the memory, it is necessary to first determine whether the data is compressed data. If the data is compressed data, the data is also written into the memory in the original compressed state, thereby realizing the function of compressing data in one place and storing data in multiple places. Not only is the bandwidth between the on-chip (that is, the cache) and the off-chip (that is, the memory) saved, but repeated compression is also unnecessary, because the same compression mechanism is set between the LLC and the memory, or the compression mechanism of the memory covers the compression mechanism of the cache. Therefore, repeated compression is not necessary, and the efficiency of storing compressed data is further improved.

[0036] In a possible implementation, the LLC is further configured to compress the fifth data and write the fifth data in the compressed state to the memory if the fifth data is in the non-compressed state, or write the fifth data in the compressed state to the memory if the fifth data is in the non-compressed state.

[0037] In the embodiments of the present application, when data cached in the last level cache (LLC) needs to be written into the memory, it can be determined first whether the data is compressed data. If the data is uncompressed data, the uncompressed data can be compressed and then sent to the memory for storage. In this way, the bandwidth in the system on chip (SoC) and the bandwidth between the on-chip and off-chip transmission can be reduced. For example, in some possible embodiments, when the data to be written into the memory is cached in the LLC in an uncompressed state, it can be further determined whether the data can be compressed. If the data can be compressed, the data can be compressed in the memory controller on the chip and then stored in the memory. That is, there can be a case that the data cannot be compressed in the LLC, but can be compressed in the memory controller before being written into the memory. Alternatively, in another possible implementation, the uncompressed data can be directly written into the memory, because before the fifth data is cached in the LLC, it can be determined whether the data can be compressed. If the data can be compressed, the data can be compressed. If the data cannot be compressed, it can be compressed due to other reasons. Therefore, it is not necessary to determine again and compress again, so as to improve the efficiency of storage into the memory.

[0038] In a possible implementation, the apparatus further includes another LLC, and the memory controller is further configured to: receive a request for reading and rewriting sixth data in the LLC; if the sixth data satisfies a preset condition, determine whether seventh data is in the LLC or the other LLC, the seventh data being data adjacent to the sixth data in the physical address in the memory; if the seventh data is in a target LLC, obtain the seventh data from the target LLC; determine a compression state of the sixth data and the seventh data when written into the memory based on a compression state of the seventh data; and write the sixth data and the seventh data into the memory based on the determined compression state.

[0039] When the memory access system receives a request to read and write a certain data (i.e., the sixth data) in the LLC to the memory, it is necessary to determine whether the sixth data meets the preset condition first. Optionally, the determination of whether the sixth data meets the preset condition can be performed by querying relevant information, which can include the following aspects, such as the compression state of the sixth data itself, the length and position (such as the high bit or the low bit) of the address corresponding to the sixth data, and the like. When it is determined based on the above relevant information that the length of the original address corresponding to the sixth data is less than or equal to the minimum unit of compressed storage (such as 64B), for example, the sixth data is 64B non-compressed data or 32B compressed data, in some cases, whether the sixth data is read and written in a compressed state or a non-compressed state, and the address written after the sixth data is read and written, can depend on the data (i.e., the seventh data) adjacent to the physical address of the sixth data in the memory. For example, if the sixth data is the high 64B data in 128B alignment, it can need to be stored together with the low 64B seventh data in the physical address of the seventh data after compression. If the seventh data cannot be compressed, the sixth data cannot be compressed either, that is, it is necessary to refer to whether the seventh data associated with the sixth data can be compressed. For another example, if the sixth data is the low 64B data in 128B alignment, it is currently determined to be non-compressible, but the address written back in the non-compressed state has already stored the seventh data (the original high 64B data) in the compressed state. At this time, if the seventh data is not obtained first and the compression state of the seventh data is not known, the sixth data cannot be written back in the non-compressed state either, that is, in this case, it is necessary to refer to the compression state and the storage address of the seventh data associated with the sixth data. However, if the seventh data is stored in the memory, it is necessary to read the data from the memory, which not only increases the on-chip and off-chip bandwidth, but also reduces the data storage efficiency. Therefore, in the embodiment of the present application, the eighth data in other LLCs in the processing device is processed first. The reason is that in the processing device of the embodiment of the present application, the last level cache corresponding to different processor cores is shared with the memory, so the seventh data can be cached in other LLCs. If the seventh data can be obtained from other LLCs, the additional memory bandwidth overhead caused by reading and writing can be reduced, and the reading and writing efficiency can be improved.

[0040] In a possible implementation, the memory controller comprises a first compression module and a first decompression module; the LLC comprises a second compression module and a second decompression module; the first compression module is configured to compress uncompressed data that needs to be compressed and is stored into the memory; the second decompression module is configured to decompress compressed data that needs to be decompressed and is fetched from the memory; the second compression module is configured to compress uncompressed data that needs to be compressed and is cached into the LLC; and the second decompression module is configured to decompress compressed data that needs to be decompressed and is fetched from the LLC.

[0041] In the embodiments of the present application, the memory controller and the LLC can each comprise a corresponding compression module and a decompression module, which can be used to compress or decompress relevant data in different processes, different memory access stages (for example, reading data, writing data, and reading and writing data), or different compression granularity requirements.

[0042] In a possible implementation, the first compression module and the second compression module use the same preset compression rule to compress data.

[0043] In the embodiments of the present application, the compression modules in the memory controller and the LLC use the same compression algorithm, that is, the same compression mechanism to compress data. Correspondingly, the decompression modules in the memory controller and the LLC also use the same decompression algorithm, that is, the same decompression mechanism to decompress data. Optionally, the preset compression rule in the memory controller can include but is not limited to the preset compression rule in the LLC, that is, the compression and decompression modules in the memory controller can have more possible compression modes and compression granularities and corresponding decompression modes and decompression granularities than the LLC.

[0044] In a second aspect, the embodiments of the present application provide a storage management method, which can include: receiving a first memory access request for reading first data sent by a processor core, the first memory access request carrying a first memory access address; reading memory access data from a memory coupled to the processor core based on the first memory access address; if the memory access data comprises the first data and second data in a compressed state, sending the first data to the processor core and caching the second data in the compressed state to the LLC in response to the first memory access request.

[0045] In a possible implementation, the memory access data further comprises a compression identifier for indicating whether the second data is in a compressed state; and the method further comprises: caching the compression identifier to the LLC.

[0046] In a possible implementation, if the first data is in a compressed state, the sending the first data to the processor core comprises: in response to the first memory access request, sending the first data in a compressed state to the LLC; receiving and caching, by the LLC, the first data in the compressed state, reading the cached first data in the compressed state and sending the first data in the compressed state to the processor core after decompression; or sending, by the LLC, the received first data in the compressed state to the processor core after decompression. The first data in the compressed state is obtained by compressing part or all of the original data corresponding to the first memory access address, and the second data in the compressed state is obtained by compressing part or all of the original data corresponding to the second memory access address in the memory.

[0047] In a possible implementation, if the memory access data includes the first data and the first data is in a compressed state, the method further comprises: in response to the first memory access request, sending the first data in a compressed state to the LLC; receiving and caching, by the LLC, the first data in the compressed state, reading the cached first data in the compressed state and sending the first data in the compressed state to the processor core after decompression; or sending, by the LLC, the received first data in the compressed state to the processor core after decompression.

[0048] In a possible implementation, if the memory access data includes the first data and the first data is in a non-compressed state, the method further comprises: in response to the first memory access request, sending the first data in a non-compressed state to the LLC; receiving and caching, by the LLC, the first data in the non-compressed state and sending the first data in the non-compressed state to the processor core; or sending, by the LLC, the received first data in the non-compressed state to the processor core.

[0049] In a possible implementation, if the memory access data includes the first data and the first data is in a non-compressed state, the method further comprises: in response to the first memory access request, sending the first data in a non-compressed state to the LLC; if the first data in the non-compressed state is compressible, compressing, by the LLC, the received first data in the non-compressed state and caching the first data in the non-compressed state, and sending the first data in the non-compressed state to the processor core; if the first data in the non-compressed state is not compressible, receiving and caching, by the LLC, the first data in the non-compressed state, and sending the first data in the non-compressed state to the processor core.

[0050] In a possible implementation, the reading of the memory access data from the memory coupled to the processor core based on the first memory access address comprises: determining data compression information corresponding to the first memory access address based on a pre-stored mapping relationship; the mapping relationship comprises a mapping relationship between address information and data compression information; and reading the memory access data from the memory based on the first memory access address and the corresponding data compression information.

[0051] In a possible implementation, the storage granularity of the LLC is a cache line; and the reading of the memory access data from the memory based on the first memory access address and the corresponding data compression information comprises: if it is determined that the first memory access address belongs to a first type of address, reading the memory access data stored in the first memory access address; the first type of address comprises an address whose address length is less than or equal to the cache line and that stores data, or an address whose address length is greater than the cache line and that stores original data; or, if it is determined that the first memory access address belongs to a second type of address, reading the memory access data stored in a second memory access address; the second type of address comprises an address whose address length is less than or equal to the cache line and that stores compressed data of corresponding original data in the second memory access address; or, if it is determined that the first memory access address belongs to a third type of address, reading the memory access data stored in part of the memory access addresses in the first memory access address; the third type of address comprises an address whose address length is greater than the cache line and that stores compressed data of corresponding original data in the part of the memory access addresses.

[0052] In a possible implementation, the first memory access request further comprises a third memory access address; and the method further comprises: before the reading of the memory access data from the memory based on the first memory access address, hitting data corresponding to the third memory access address from the LLC or a cache at one or more levels above the LLC.

[0053] In a possible implementation, the method further comprises: receiving a second memory access request of writing third data cached in the LLC to the cache at the one or more levels above; determining whether the third data is compressed data; if the third data is in a compressed state, decompressing, by the LLC, the third data in the compressed state, and writing the decompressed third data to the cache at the one or more levels above; and if the third data is in a non-compressed state, writing, by the LLC, the third data in the non-compressed state to the cache at the one or more levels above.

[0054] In a possible implementation, the method further includes: receiving a write-back request for caching fourth data in the upper-level cache to the LLC; if the fourth data is compressible, compressing the fourth data by the LLC and caching the compressed fourth data to the LLC; and if the fourth data is not compressible, caching the fourth data to the LLC by the LLC.

[0055] In a possible implementation, the method further includes: receiving a third memory access request for writing fifth data cached in the LLC to the memory; and if the fifth data is in a compressed state, writing the fifth data in the compressed state to the memory by the LLC.

[0056] In a possible implementation, the method further includes: if the fifth data is in a non-compressed state, compressing the fifth data by the LLC and writing the fifth data in the compressed state to the memory; or if the fifth data is in the non-compressed state, writing the fifth data in the compressed state to the memory by the LLC.

[0057] In a possible implementation, the method further includes: receiving a request for read-modify-write on sixth data in the LLC; if the sixth data meets a preset condition, determining whether seventh data is in the LLC or the other LLC, the seventh data being data physically adjacent to the sixth data in the memory; if the seventh data is in a target LLC, obtaining the seventh data from the target LLC; determining a compression state of the sixth data and the seventh data written to the memory based on a compression state of the seventh data; and writing the sixth data and the seventh data to the memory based on the determined compression state.

[0058] In a third aspect, an embodiment of the present application provides a system on chip (SOC), which can include the processing apparatus provided in any of the implementation manners of the first aspect.

[0059] In a fourth aspect, the present application provides a semiconductor chip, which can include the processing apparatus provided in any of the implementation manners of the first aspect.

[0060] In a fifth aspect, the present application provides a chip system, which includes the processing apparatus provided in any of the implementation manners of the first aspect. In a possible design, the chip system further includes a memory, configured to store program instructions and data necessary or related to running of the chip system. The chip system can be composed of a chip, or can include the chip and other discrete devices.

[0061] In a sixth aspect, an electronic device is provided, which has a function of implementing any one of the storage management methods in the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the function.

[0062] In a seventh aspect, an electronic device is provided, which includes the processing device provided in any one of the implementation manners of the first aspect. In a possible design, the electronic device further includes a memory, configured to store program instructions and data necessary or related to the operation of the electronic device. The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0063] In an eighth aspect, a processing device is provided, which has a function of implementing any one of the storage management methods in the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the function.

[0064] In a ninth aspect, a terminal device is provided, which includes the processing device provided in any one of the implementation manners of the first aspect. The terminal device can further include a memory, coupled to the processing device, configured to store program instructions and data necessary to the terminal device. The terminal device can further include a communication interface, configured to enable the terminal device to communicate with other devices or a communication network.

[0065] In a tenth aspect, a computer readable storage medium is provided, which stores a computer program. When the computer program is executed by a plurality of electronic devices, the storage management method flow in any one of the second aspect is implemented.

[0066] In an eleventh aspect, a computer program is provided, which includes instructions. When the computer program is executed by an electronic device, the electronic device can execute the storage management method flow in any one of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0067] FIG. 1A is a schematic diagram of a system architecture of a multi-level management scheme.

[0068] FIG. 1B is a schematic diagram of a system architecture of an on-chip cache compression scheme.

[0069] FIG. 2A is a schematic diagram of a structure of a processing device according to an embodiment of the present application.

[0070] FIG. 2B is a schematic diagram of a structure of an electronic device according to an embodiment of the present application.

[0071] FIG. 2C is a structural schematic diagram of another electronic device according to an embodiment of the present application.

[0072] FIG. 2D is a schematic diagram of a cache line compression example according to an embodiment of the present application.

[0073] FIG. 3A is a schematic diagram of a physical memory space division according to an embodiment of the present application.

[0074] FIG. 3B is a schematic diagram of a physical page address division according to an embodiment of the present application.

[0075] FIG. 3C is a schematic diagram of 128B alignment high 64B, low 64B according to an embodiment of the present application.

[0076] FIG. 4A is a schematic diagram of a mapping relationship between data and addresses before and after compression according to an embodiment of the present application.

[0077] FIG. 4B is a schematic diagram of a mapping relationship between data and addresses before and after compression according to another embodiment of the present application.

[0078] FIG. 4C is a schematic diagram of a mapping relationship between data and addresses before and after compression according to yet another embodiment of the present application.

[0079] FIG. 4D is a schematic diagram of a mapping relationship between data and addresses before and after compression according to yet another embodiment of the present application.

[0080] FIG. 5A is a flowchart of a process of processing a 128B read request according to an embodiment of the present application.

[0081] FIG. 5B is a flowchart of a process of processing a 64B read request according to an embodiment of the present application.

[0082] FIG. 5C is a flowchart of a process of processing a 128B write request according to an embodiment of the present application.

[0083] FIG. 5D is a flowchart of a process of processing a 64B write request according to an embodiment of the present application.

[0084] FIG. 6 is a flowchart of a storage management method according to an embodiment of the present application. DETAILED DESCRIPTION

[0085] The embodiments of the present application will be described below with reference to drawings. The terms "first", "second", "third", and "fourth" and the like in the description and the claims of the present specification and the drawings are intended to distinguish different objects, and are not intended to describe a particular sequence. In addition, the terms "include" and "have" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, a method, a system, a product, or an apparatus including a series of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed or can optionally further include other steps or units inherent to such processes, methods, products, or apparatuses. In this context, referring to "embodiments" means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it necessarily independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0086] The terms "component", "module", "system", and the like used in the present specification are used to represent computer-related entities, hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or an execution thread, and a component can be located on one computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes, for example, according to a signal having one or more data packets (e.g., data from a component that is transmitted to another component, for example, via the Internet, from a local system, a distributed system, and / or a network).

[0087] First, some terms in the present application are explained and described to facilitate understanding by those skilled in the art.

[0088] (1) Integrated Circuit (IC) is a kind of micro electronic device or component. A certain process is used to interconnect the transistors, resistors, capacitors and inductors required in a circuit and other elements and wiring together on a small piece or several pieces of semiconductor wafer or dielectric substrate, and then packaged in a tube shell to become a micro structure with required circuit function; that is, the IC chip is to form an integrated circuit of a large number of microelectronic components (transistors, resistors, capacitors, etc.) on a plastic base to make a chip.

[0089] (2) Read Modify Write (RMW), a basic operation on memory, which can include a read operation, a write operation, or a read-modify-write operation, i.e., first reading out data in the memory, modifying the data, and then writing the data into the memory.

[0090] (3) Double Data Rate (DDR), i.e., DDR SDRAM = Double Data Rate Synchronous Dynamic Random Access Memory, commonly referred to as DDR, where SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory. The "synchronous" refers to the fact that the memory operates in synchronization with the clock. Internal commands are sent and data is transferred in synchronization with the clock. DDR is a memory device that loses data when power is removed and requires a timed refresh to maintain data integrity. A DDR SDRAM subsystem consists of a DDR controller, a DDR PHY, and DRAM memory chips.

[0091] (4) Static Random-Access Memory (SRAM) is a type of random-access memory. The "static" refers to the fact that the memory retains its stored data as long as power is applied. In contrast, the data stored in dynamic random-access memory (DRAM) needs to be periodically refreshed. However, when power is removed, the data stored in SRAM is also lost (referred to as volatile memory), which is different from ROM or flash memory that can store data after power is removed.

[0092] (5) Nand-flash memory is a type of non-volatile memory based on NAND technology. Compared with traditional flash memory, NAND Flash has higher storage density, lower power consumption, and longer life.

[0093] (6) Metadata, also known as intermediary data or relay data, is data about data, mainly information describing data properties, used to support functions such as indicating storage location, historical data, resource search, file recording, etc. Metadata is a kind of electronic catalog. In order to achieve the purpose of cataloging, the content or characteristics of the data must be described and collected, and the purpose of assisting data retrieval must be achieved. The metadata in the embodiments of the present application can be used to record information related to whether the data is compressed, for example, metadata records that a certain data is compressed data or non-compressed data.

[0094] (7) bit: A computer can convert 0 and 1 into signals in a circuit for calculation. A bit is the smallest unit for storing and moving data in a computer. It has only two values, 0 and 1. Its abbreviation is the lowercase letter "b".

[0095] (8) Byte. Byte is the English word for byte. Its abbreviation is the uppercase letter "B". English characters usually take one byte, which is 1B. Chinese characters usually take more than 2 bytes due to character set limitations. Conversion relationship: 8 bits equals 1 byte. One byte equals eight bits.

[0096] (9) The memory wall refers to the phenomenon where memory performance severely limits CPU performance. The main performance indicators of memory are "bandwidth" and "latency".

[0097] First, to facilitate understanding of the embodiments of this application, the specific technical problem to be solved by this application is further analyzed and proposed. Currently, there are various technical solutions for implementing bandwidth compression technology; two examples are listed below:

[0098] Option 1: Multi-level Management Solution

[0099] As shown in Figure 1A, Figure 1A is a schematic diagram of the system architecture of a multi-level management scheme, which includes the following parts:

[0100] (1) Compress the prefetched data using an additional prefetch buffer.

[0101] (2) Supports compression with multiple granularities.

[0102] The disadvantages of Option 1:

[0103] (1) Compression of DDR bandwidth specifically for memory.

[0104] (2) Additional prefetch buffer space is required.

[0105] (3) A lot of read-modify-write operations are required to update the compressed state, which becomes particularly noticeable in multi-granularity compression.

[0106] Option 2: Compression caching scheme

[0107] As shown in FIG. 1B, FIG. 1B is a schematic diagram of a system architecture of an on-chip cache compression scheme. The scheme explores various forms of cache compression, including supporting more data by increasing the block tag, and superblock to avoid increasing additional tags.

[0108] Disadvantages of the second scheme:

[0109] (1) Compression is performed separately for the cache.

[0110] (2) Without DDR compression, the superblock has low overhead, but the compression rate of the L3 is low, and the performance benefit is limited.

[0111] In summary, the above two compression technologies in the prior art each have defects and cannot balance the bandwidth and storage space overhead, for example, there is a problem of excessive space overhead. Therefore, the present application comprehensively considers the deficiencies of the existing methods, and provides a joint optimization mechanism for LLC cache and memory compression to solve the above technical problems. Specifically, the technical problems to be solved by the present application include one or more of the following aspects: providing a memory management scheme to improve the effective bandwidth between the on-chip system and the memory, while minimizing the storage space (such as on-chip storage space) overhead, and improving the efficient management of compressed data.

[0112] Based on the above, please refer to FIG. 2A, which is a structural schematic diagram of a processing device provided in an embodiment of the present application. The processing device 10 can be a system on chip (SoC), and specifically can include a processor core 101, a last-level cache 104, and a memory controller 105. Please refer to FIG. 2B, which is a structural schematic diagram of an electronic device provided in an embodiment of the present application. The electronic device 001 can include the processing device 10 described above, and optionally can further include a memory 20. The processing device 10 or the electronic device 001 described above can be located in any electronic device, such as a computer, a mobile phone, a tablet, a smart wearable device, and the like. Specifically, the processing device 10 or the electronic device 001 can also be a chip or a chip set or a circuit board carrying a chip or a chip set, which can work under necessary software drivers. The processing device 10 or the electronic device 001 containing the processing device 10 in the embodiments of the present application can be applied in a memory system, including a general server, a high-performance (HPC) server, an artificial intelligence (AI) server, a mobile device, a terminal device, or a memory control module of a terminal device, and the like. The processing device 10 or the electronic device 001 in the embodiments of the present application is deployed in a related scenario, and can achieve a substantial reduction in memory access bandwidth and a substantial reduction in on-chip storage resource overhead. It should be noted that the processing device 10 in the present application can be a system on chip (SoC), or a module in the electronic device 001 described above. Hereinafter, the processing device 10 is taken as an SoC 10 for example.

[0113] Further, please refer to FIG. 2C, which is a structural schematic diagram of another electronic device provided in an embodiment of the present application. The electronic device 001 includes an SoC 10 (taken as the processing device 10 for example), a memory 20, and an external storage 30. The SoC 10 includes a multi-core CPU 100 and a memory controller 105 as shown in FIG. 2C. Specifically, the multi-core CPU 100 includes a plurality of CPU cores (for example, CPU Core 101-1, CPU Core 101-2, …, CPU Core 101-N), a first-level cache (L1 Cache 102-1, L1 Cache 102-2, …, L1 Cache 102-N) corresponding to each CPU core, a second-level cache (L2 Cache 103-1, L2 Cache 103-2, …, L2 Cache 103-N) corresponding to each CPU core, and an L3 Cache 104 shared by the plurality of processor cores.

[0114] The SoC 10 in FIG. 2A, FIG. 2B, or FIG. 2C can be an integrated circuit with a dedicated target, which contains a complete system and all contents of embedded software. Specifically, the functional modules included in the SoC 10 in the embodiments of the present application are described as follows:

[0115] Multiple CPU cores: can include CPU Core 101-1, CPU Core 101-2, …, CPU Core 101-N. The multiple CPU cores are the core part of the SoC, responsible for performing various computing and control tasks. Illustratively, CPU Core 101-1 can run an operating system or an application program to control a plurality of hardware or software elements connected to CPU Core 101-1, and can process various data and perform operations; further, CPU Core 101-1 can load instructions or data from external memory 30 into memory 20 (see FIG. 2C), and initiate various memory access requests to memory 20 as needed (e.g., issue read data requests, write data requests, read-modify-write requests, etc. to memory 20). Alternatively, different CPU Cores in a multi-core CPU can be used to perform different functions or the same function, for example, the multiple CPU Cores can be one or more of a central processing unit (CPU), an application processor (AP), a modem processing unit, a graphics processing unit (GPU), an image signal processor (ISP), a video codec unit, a digital signal processor (DSP), a baseband processing unit, and a neural-network processing unit (NPU), etc. Alternatively, registers can also be provided in each CPU core for storing instructions and data.

[0116] Level 1 cache (L1) corresponding to each CPU core: as shown in FIG. 2C, can include L1 Cache 102-1, L1 Cache 102-2, …, L1 Cache 102-N. In FIG. 2C, the level 1 cache is the closest cache to the CPU core, and the L1 Cache is exclusive to each CPU core (also referred to as a core, CPU Core, etc.) on the CPU. Illustratively, the L1 can be logically divided, for example, into two parts, data and instruction cache, i.e., one part stores data and the other part stores instructions.

[0117] Level 2 cache (L2) corresponding to each CPU core: as shown in FIG. 2C, can include L2 Cache 103-1, L2 Cache 103-2, …, L2 Cache 103-N. In FIG. 2C, the level 2 cache is also exclusive to each core (CPU Core) on the CPU. Alternatively, in some processor architectures, the CPU cores can also share the L2 cache.

[0118] Last Level Cache (LLC) 104, which is behind the LLC and the memory, is a cache located between the processor core and the memory and closest to the memory, and is used to improve the performance of the memory hierarchy. Optionally, the LLC 104 in the embodiment of the present application also has the functions of compressing non-compressed data and decompressing compressed data. Specifically, a first compression module 1041 and a first decompression module 1042 are arranged in the LLC, and are used to compress or decompress data cached in or read out from the LLC. In the example shown in FIG. 2C, the LLC is a Level 3 Cache (L3), and it can be understood that in different processor architectures, the specific cache level corresponding to the LLC can be different (according to the difference of the system cache architecture, the LLC can be a Level 2 Cache, a Level 3 Cache, a Level 4 Cache, etc., which is not limited in the present application). For the convenience of description, the functions of the LLC will be mainly described below by taking the L3 as an example, but this does not constitute a limitation on the LLC. As shown in FIG. 2C, the L3 can be shared by all CPU cores (such as CPU Core 101-1, CPU Core 101-2, …, CPU Core 101-N) on the entire SoC 10, and the L3 in the embodiment of the present application can act as a prefetch buffer of the memory 20 (such as DDR). For example, the L3 can be used to store the additional data obtained due to compression. For example, if the memory access request hits in the L3, the data is directly read from the L3 and returned to the request. If it is assumed that the original memory access request is 64 bytes, and the compressed data read from the memory is 64 bytes, the data corresponding to the memory access and the additional data read can be cached in the L3 Cache 104 in the original compressed state. Optionally, the compression algorithm and data format of the compressed data in the L3 are the same as those of the memory, and the L3 is used as the prefetch buffer of the DDR. When the data in the DDR needs to be read, the data in the compressed state can be directly obtained from the L3. Wherein,

[0119] The first compression module (Compression Engine, CE) 1041 can be used to compress data cached in the LLC and requiring compression. The LLC (e.g., L3) in the embodiment of the present application supports compressing the high 64B and the low 64B of 128B alignment respectively, and then merging them into one 64B. Alternatively, when the compression range is constrained to 128B alignment, the L3 cache does not need to store additional tag markers due to the equivalent capacity expansion, but only needs an additional 2-bit overhead to record the compression state and markers. Please refer to FIG. 2D, which is a schematic diagram of a cache line compression example provided by the embodiment of the present application. For example, the cache line Way1 in the L3 stores compressed data A and compressed data A+1, the cache line Way2 stores compressed data C, the cache line Way3 stores uncompressed data E, and the cache line Way4 stores compressed data D. Assuming that the cache line size is 64B, A and A+1 can be 32B data compressed from 64B data, C and D can also be 32B data compressed from 64B data, and E is 64B uncompressed data. Alternatively, the first compression module 1041 in the embodiment of the present application can support mixed granularity compression, effectively increasing the compression rate. For example, the mixed granularity includes compressing 128B data to 64B, and compressing two 64B data to 32B respectively. Correspondingly, the decompression supports decompressing 64B to 128B, and decompressing two independent 32B to 64B respectively.

[0120] The first decompression module (Decompression Engine, DCE) 1042 is used to decompress compressed data read from the L3 and requiring decompression. Alternatively, the decompression can support decompressing 64B to 128B, and also can support decompressing two independent 32B to 64B respectively.

[0121] Alternatively, the first compression module 1041 and the first decompression module 1042 can also be arranged in the cache above the LLC, or between the LLC and the cache above the LLC, which is not limited in the embodiment of the present application.

[0122] The L1 cache, L2 cache, and L3 cache described above belong to a cache, which is a cache memory integrated in the CPU. According to whether the cache stores instructions or data, the cache can be divided into an I-cache and a D-cache. For example, the cache can store instructions or data that have just been used or are frequently used by the CPU. If the CPU needs to use the instructions or data again, the instructions or data can be directly called from the cache, avoiding repeated access and reducing the waiting time of the CPU, thereby improving the efficiency of the system. Alternatively, each CPU core can also have a unique register inside it. This register can only be accessed by its own CPU core and cannot be accessed by other CPU cores.

[0123] The memory (Memory) 20, also known as the internal memory, main memory, or main storage, is an internal memory that directly exchanges data with the CPU. The memory can be said to be a transit station between the external memory (such as a hard disk) and the CPU. The memory 20 is usually a power-off volatile memory that loses the data stored thereon when power is off. The memory 20 in the embodiment of the present application refers to a readable and writable running memory. Its function can be to temporarily store operation data in the multi-core CPU 100 and exchange data with the external memory 30 or other external memories, and can be used as a temporary data storage medium for the operating system or other programs running. For example, the operating system running on the CPU Core 101-1 calls the data to be operated from the memory 20 to the CPU Core 101-1 for operation, and then the CPU Core 101-1 transmits the result when the operation is completed. Since the running of all programs needs to be loaded into the memory 20 first, and then the CPU Core 101-1 can be loaded and run, optionally, in addition to the multi-core CPU 100 that can read and write the memory 20, other accelerators (not shown in FIG. 2C, such as AI processors, graphics processors, etc.) can also share the memory 20, but not the L3 cache 104, that is, the accelerator can directly access the memory 20 without first accessing the L3, but directly accessing the memory 20 (such as DDR). Therefore, the compression mechanism in the DDR can be greater than the compression mechanism of the L3, because the compression granularity of the L3 can only be the cache line, but the memory can have the cache line granularity, and can also have the multiple cache line granularity. That is, the L3 only supports cache line granularity compression, while the memory can support cache line granularity compression and multiple cache line granularity compression.

[0124] The memory 20 can specifically be one or more of a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a Synchronous Dynamic Random Access Memory (SDRAM), and the like. Among them, the DRAM further includes a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) for short, a DDR2, a DDR3, a Low Power Double Data Rate 4 (LPDDR4), or a Low Power Double Data Rate 5 (LPDDR5), and the like.

[0125] As shown in FIG. 2C, the distance from the data to the CPU core and the transmission speed size are generally: register in CPU > L1 > L2 > L3 > memory, and the storage space size is generally: memory > L3 > L2 > L1 > register. For example, the process of reading data by the multi-core CPU 100 in the embodiment of the present application is as follows: taking the CPU Core 101-1 as an example, the CPU Core 101-1 first searches in the L1 Cache 102-1, if not found, searches in the L2 Cache 103-1, if not found, searches in the L3 Cache 104, and if not found, searches in the memory. Further, the read data cannot be immediately stored in the register, but is first stored in the L3 Cache 104, then copied to the L2 Cache 103-1 and the L1 Cache 102-1, and then read into the register of the CPU Core 101-1. That is, the data read from the memory is first stored in the L3, then the data in the L3 is copied to the L2, then the data in the L2 is copied to the L1, and then the data in the L1 is copied to the register of the CPU, and the storage space finally accessed by the CPU is the register. It should be noted that in different cache mechanisms, there can be mutual exclusion mechanisms between the L3 and the L2, or between the L3 and the memory. Assuming that the above mutual exclusion mechanisms exist, based on the above data reading order, only one copy is retained in the mutually exclusive cache or memory, or between the mutually exclusive caches, and the other copy is not retained in the corresponding cache. For example, when the data is read from the L3 and written into the DDR, the data is not retained in the L3. For another example, if the L3 and the L2 are mutually exclusive, when the data is read from the L3 and written into the L2, the data does not need to be retained in the L3, and vice versa, when the data is read from the L2 and written into the L3, the data does not need to be retained in the L2. In actual embodiments, whether the read data is retained in the original cache or not varies according to different cache mechanisms, which is not limited in the embodiment of the present application.

[0126] Memory controller (Controller, DMC) 105: can be used to manage various types of memory in electronic device 001, such as memory 20, cache (L1 cache, L2 cache, L3 cache), etc., and is responsible for data exchange between CPU core and memory 20, data read and write, memory allocation and management. Optionally, the memory controller 105 can be a logical functional module with corresponding functions, such as a logic state machine, or a corresponding software implementation on related hardware. For example, the memory controller 105 receives and parses the read command, write command or read-modify-write command sent by the CPU, and according to the logical address of the data carried in the related command, the logical address of the data is parsed into a physical address according to the fixed address mapping relationship, and then the position of the data to be read or written is found, and finally the control signal corresponding to the command is sent to the memory 20. Further, since the scheme of the present application is based on memory bandwidth compression technology, and there is usually no compression function in the off-chip memory 20, therefore, the compressed data stored in the off-chip memory 20 is because it has been compressed into compressed data on-chip before being written into the memory 20, that is, the memory controller (Controller) 105 in the embodiment of the present application has the function of compressing or decompressing data. From the perspective of bandwidth, reading 128B data, if it is compressed data, then 64B of bandwidth is consumed, if it is uncompressed, then 128B of bandwidth is consumed. Optionally, the memory controller 105 can include a second compression module 1051, a second decompression module 1052, a compression state management submodule 1053, a read-modify-write submodule 1054, and a memory read-write submodule 1055. Among them,

[0127] Second compression module (Compression Engine, CE) 1051 and second decompression module (Decompression Engine, DCE) 1052: the embodiments of the present application adopt the same compression algorithm and compression granularity for LLC and memory (such as DDR). For example, the compression algorithm compresses 64B into 32B, and the corresponding decompression algorithm decompresses 32B into 64B respectively. Among them,

[0128] Second compression module 1051: can have the same function as the first compression module 1041 in the LLC (such as L3), and the second compression module 1051 in the memory controller 105 can be used to compress the uncompressed data to be written into the memory 20 and needing compression. Optionally, the second compression module 1051 in the memory controller 105 supports the overall compression of 128B, and supports the compression of high 64B and low 64B aligned with 128B respectively.

[0129] The second decompression module 1052 can have the same function as the first decompression module 1042 in the LLC (e.g., L3). The second decompression module 1052 in the memory controller 105 can be used to decompress compressed data read from the memory 20 and requiring decompression. Optionally, the decompression supports decompression of 64B into 128B, and decompression of two independent 32B into 64B respectively.

[0130] The compression state management submodule 1053: the embodiments of the present application do not have special assumptions about the function of compression state management. For the convenience of description, the embodiments of the present application can use metadata cache to manage the compression state. It can be understood that the embodiments of the present application can also be combined with a compression state prediction mechanism, which is not described in detail here. Unlike the LLC, since it is necessary to record the compression state of the off-chip space on-chip to complete the conversion of the address and the length, an additional structure is required to manage the compression state of the off-chip data, that is, the compression state management submodule 1053 in the embodiments of the present application can be used to manage the compression state of the data in the memory.

[0131] The read-write submodule 1054: combined with the LLC (e.g., L3), the path to the LLC requesting data is opened. If it is found that the data is on-chip (including other LLCs in the memory system), the corresponding LLC (e.g., L3) is requested to avoid increasing the bandwidth burden of the memory (e.g., DDR).

[0132] The memory read-write submodule 1055: if the memory (e.g., DDR) returns data in the compressed state, it keeps the compressed state and is transmitted to the LLC (e.g., L3) for storage. If the LLC (e.g., L3) is replaced by the compressed state data, it keeps the compressed state and is transmitted to the memory (e.g., DDR).

[0133] Since the LLC and the memory controller 105 both have compression / decompression functions, when the LLC performs compression or decompression, and when the memory controller 105 performs compression or decompression, are independent of each other. However, in some possible cases, such as the need to compress 128B into 64B, which may not be supported by the LLC, the second compression module / second decompression module in the memory controller 105 can be used for corresponding compression or decompression, so the range of the compression mechanism in the memory controller 105 can cover and be greater than the range of the compression mechanism in the LLC. For example, writing from the outside to L3 can be compressed by L3, and writing from the cache to DDR can also be compressed by the memory controller. The specific functions of the memory controller 105 involved in the embodiments of the present application will be introduced in subsequent embodiments.

[0134] It can be understood that, in addition to the above main functional modules, the SoC 10 can also include other accelerators, security modules, power management units, touch controllers, and various interface controllers, and other functional modules. These modules cooperate with each other to provide the functions and performance of the SoC, which will not be listed one by one here. In summary, the SoC in the embodiments of the present application is a chip that integrates multiple functional modules, which cooperate with each other to provide the SoC with various functions such as computing, graphics, communication, multimedia, and sensing. It can be understood that the internal structure and functions of the SoC in different application scenarios or different electronic devices can be different, and the embodiments of the present application do not make specific limitations thereto.

[0135] Further, please refer to FIG. 2C, the electronic device 001 can also include an external storage 30, wherein,

[0136] The external storage 30 is usually a non-volatile memory, and the content stored therein will not be lost after power off. The external storage 30 in the present application can include a read-only memory (ROM) for storing system information and a startup program, and an external storage (such as a Flash) for storing programs and data. Its function is to store instructions and data for a long time. For example, the system information includes system files such as Linux kernel and Android operating system; the programs can include system built-in application programs (such as application market, wallet application, security center, etc.) that the electronic device 001 comes with and user-subsequently-downloaded and installed application programs (such as social application, video application, mobile payment application, game application, etc.); the data can include system data related to system running (such as configuration file data, log file data, cache data, etc.), and data generated in the use process of the user (such as fingerprint data, chat history data, photo and video data, etc.). It can be understood that the data access to the external storage 30 (such as a disk) is not directly from the disk to the CPU, but through the memory as a bridge to achieve fast access.

[0137] The external storage 30 can include one or more of a one-time programmable read-only memory (OTPROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a mask read-only memory, a flash read-only memory, a universal flash memory (UFS), a Flash memory (for example, a NAND flash memory, a NOR flash memory, etc.), a hard disk drive, or a solid state drive (SSD), etc.

[0138] It can be understood that the structure of the embodiments of the present application does not constitute a specific limitation on the processing device (such as the SoC 10) or the electronic device 001. In other embodiments of the present application, the SoC 10 or the electronic device 001 can include more or fewer components than the illustration, or combine certain components, or split certain components, or different component arrangements. The components illustrated can be implemented in hardware, software, or a combination of software and hardware.

[0139] Based on the structure of any one of the possible SoC 10 or electronic device 001 in FIGS. 2A-2D described above, the memory management function implemented by the SoC 10 or the electronic device 001 in the embodiments of the present application can include the following:

[0140] The memory controller 105 is configured to receive a first memory access request for reading first data sent by the processor core, the first memory access request carrying a first memory access address; read memory access data from a memory coupled to the processing device based on the first memory access address; if the memory access data includes the first data and compressed second data, send the first data to the processor core through the LLC and cache the compressed second data to the LLC in response to the first memory access request.

[0141] The LLC 104 is configured to send the first data to the processor under the instruction of the memory controller 105, and receive and cache the compressed second data.

[0142] Specifically, when the memory controller 105 receives a first memory access request of the multi-core CPU 100 (for example, any one of the CPU cores), the process of the CPU reading data is: first looking in the L1 cache, if not found, then looking in the L2 cache, if not found, then looking in the L3 cache, and if not found, then looking in the memory. Therefore, in the embodiment of the present application, the first memory access request issued by the processor needs to find part or all of the data in the memory in the case of not all hits in the cache (including partial hits and no hits at all). Again, since the embodiment of the present application is implemented based on the memory bandwidth compression mechanism, it involves that the memory 20 may store compressed data and uncompressed data compressed according to the preset compression rule, so the data read from the memory in response to the first memory access request is not necessarily the original data corresponding to the first memory access address, it may read out the original data (i.e. the first data) corresponding to the first memory access address, or it may read out the original data (i.e. the first data) and additional data (i.e. the second data), that is, the memory access data read in response to the first memory access request may be different according to the first memory access address, whether the corresponding data is compressed, and the different preset compression mechanism. In other words, the memory access data at least contains the original data corresponding to the first memory access address in the first memory access request (i.e. the original data corresponding to the address), which may be in a compressed state or in an uncompressed state. Further, the read memory access data may not be read from the first memory access address, it may be read from the first memory access address, it may be an address associated with the first memory access address, or it may be part of the first memory access address, because the memory in the embodiment of the present application involves storing compressed data in the memory, so in some cases, the data may be stored in other addresses due to the reason that the storage address occupied by the compressed data is smaller.

[0143] Further, after reading the access data, it is needed to determine the compression state of the access data. If the read access data contains extra data in compressed state, the extra data is directly kept in original compressed state and cached in LLC. Alternatively, since the final purpose of the first access request is to write the requested data into CPU, after reading the access data from memory, the data really requested by the first access request needs to be further copied into L2 in uncompressed state, then copied into L1, and finally written into CPU to complete the response to the first access request. Therefore, as to the data really requested by the first access request in the access data (i.e. the original data corresponding to the first access address), it can be cached in LLC and then read out to the cache at the upper level of LLC, or directly written into the cache at the upper level of LLC (without being cached in LLC first). Here, it depends on whether there is a mutual exclusion mechanism between caches at different levels, and therefore, the processing mode of the data really requested by the first access request is not limited in the embodiments of the present application. Alternatively, if the data really requested by the first access request is also in compressed state, it can be cached in LLC in compressed state, or directly decompressed and cached in the cache at the upper level of LLC. From the reading process, in the prior art, L3 based on the memory bandwidth compression mechanism can only store uncompressed data, but in the embodiments of the present application, L3 can store compressed data, i.e. the compressed data read from memory such as DDR after the processor issues a read request, can not be decompressed as in the prior art and then stored in the cache or prefetch cache, but can be directly stored in L3 in original compressed format. In this way, the storage capacity of L3 is increased, the amount of data stored in the system on chip is effectively improved, and the cache data hit rate is improved.

[0144] On the basis of the memory bandwidth compression technology, the embodiment of the present application adds a compression mechanism on the cache side on chip, that is, in addition to storing compressed data in the memory involved, the compressed data is also cached in the last level cache (LLC) of the processing device to save the on-chip storage resources. Specifically, the embodiment of the present application provides a processing device, when additional compressed data is read out from the memory due to the memory bandwidth compression mechanism, the original compressed state of the additional compressed data is still maintained for caching (that is, stored in the last level cache in the compressed state), thereby effectively reducing the overhead of on-chip storage resources on the basis of saving memory bandwidth. Unlike the prior art, after the compressed data is read from the memory, it needs to be cached on chip in the uncompressed state, the embodiment of the present application takes out the additional compressed data from the memory without decompressing the additional compressed data but caching it in the original compressed state in the LLC, and if the additional data in the compressed state needs to be read out from the LLC to the upper level cache, it can be read out and decompressed. On the one hand, since the additional data is compressed, the bandwidth between on-chip and off-chip is saved in the process of reading from the memory (such as DDR) to the last level cache (such as L3) compared with non-compressed data. On the other hand, since the additional compressed data is cached in the form of LLC, the original compressed state is still maintained, thereby saving the storage space of LLC (such as L3), and the larger the amount of additional data read, the greater the benefit. For example, in some cases, when the read memory data contains additional data other than the first memory request and the additional data is in the compressed state, not only the memory bandwidth and the storage overhead of the memory data on chip can be saved, but also considering the characteristics of program locality, the pre-fetched additional compressed data is likely to be accessed soon, thereby improving the probability and efficiency of subsequent data hits on chip, reducing the number of memory accesses, and thereby improving the overall performance of memory access. In summary, the present application sets up a joint compression mechanism between LLC and memory, by using the same preset compression rule to store compressed data between cache and memory, the effect of one compression and two storage is achieved, on the basis of reducing the bandwidth between the on-chip system and the off-chip storage system, the data storage overhead of the on-chip system (SoC) is further reduced, and the technical problems of low compression rate and low space utilization when the cache and memory are compressed separately are solved. In addition, the embodiment of the present application does not need a separate on-chip storage space, that is, the resources of the LLC on chip are reused, thereby effectively reducing the chip area on chip.

[0145] The reason why the compression rate is low when the cache and the memory are compressed separately is that, in some cases, data that can be compressed originally can be determined as unable to be compressed, and thus is stored in the memory in a non-compressed state. However, by using the joint compression based on the LLC and the memory in the present application, the state of some data can be more clearly and easily obtained, and thus the probability of the data being finally compressed is higher. For example, if some data is stored in the LLC in a compressed state, then it is only necessary to determine whether the other half of the data can be compressed, and the two pieces of data can be compressed. However, if the cache and the memory are separately compressed according to the prior art, the complexity of determining whether the two pieces of data can be compressed at the same time is increased, and in some cases, the two pieces of data can be determined as unable to be compressed, and thus the compression rate of the data in the memory or the LLC is low.

[0146] In some possible implementation manners, the memory access data further includes a compression identifier for indicating whether the second data is in a compressed state; and the memory controller is further configured to cache the compression identifier to the LLC. Optionally, all data cached in the L3 of the embodiment of the present application carries its own identifier of whether the data is compressed data, and it is known that the data is compressed data or non-compressed data at the same time of the hit. If the data is compressed data, the compressed data is decompressed by the first decompression module in the L3. Exemplarily, the hit refers to that an address segment is matched, and the address segment has a record of related identifiers of whether each cacheline is compressed or uncompressed. The hit process (and the determination of whether the data is compressed data) is determined by the memory controller, and the decompressed data can be sent to the L2. In the embodiment of the present application, if the compressed data stored in the memory carries a compression identifier of whether the data is in a compressed state, the compression identifier can be cached into the LLC together with the data. In this way, whether the data is on the chip or in the memory, the compression state of the data in a certain address can be determined based on the compression identifier. When the compression identifier is cached into the LLC together with the data, the compression state of the corresponding data can be determined based on the compression identifier cached in the LLC, so as to facilitate the related read and write operations. For example, if a certain data needs to be read from the memory, whether the data needs to be decompressed or compressed can be determined based on the compression identifier.

[0147] In some possible implementation manners, when the memory access data includes compressed data, reading the memory access data in the memory and caching the memory access data into the LLC can include one or more of the following two cases:

[0148] (1) The memory access data includes compressed data, and the memory access data includes compressed data other than the current memory access request:

[0149] (1) In a possible implementation, it is assumed that the LLC and its upper-level cache are not mutually exclusive:

[0150] When it is determined that the memory access data includes first data in a compressed state (for ease of description, which can also be referred to as first compressed data in the following) and second data in a compressed state (for ease of description, which can also be referred to as second compressed data in the following), the memory controller is specifically configured to: in response to the first memory access request, send the first data in a compressed state to the LLC; and the LLC is configured to receive and cache the first data in a compressed state, read the cached first data in a compressed state, and send the first data in a compressed state to the processor core after decompression.

[0151] Specifically, the first data is original uncompressed data corresponding to a first memory access address, and the second data is original uncompressed data corresponding to a second memory access address, and the first memory access address and the second memory access address are different addresses in the memory. The first memory access address and the second memory access address in the embodiment of the application are physical addresses. Alternatively, the first memory access address and the second memory access address can be adjacent physical addresses in the memory. Illustratively, the cache of the compressed pre-fetched data can be because when the length of the memory access request is less than the actual length of the stored compressed data, additional data outside the request can be moved to the on-chip space. Due to the characteristics of program locality, this type of data can be accessed soon, so additional cache space is needed for storage. However, when these data are not used, the space used to store the data will be wasted, unnecessarily occupying on-chip space. Therefore, in the embodiment of the application, the pre-fetched data is kept in its original compressed state for caching, so as to reduce the waste of on-chip storage space. For example, when the memory controller determines that the memory access data read from the memory (such as DDR) is 64B compressed data, that is, it includes two compressed data A1+A2, if the cache mechanism is that L3 and L2 are not mutually exclusive (that is, L2 has data, and L3 must have data), then the entire compressed data (A1+A2) can be cached in L3, and A1 can be read out from L3, decompressed and written to L2. Alternatively, the decompression module in L3 can be used for decompression, or the decompression module in L2 can be used for decompression, so as to save the bandwidth between the paths on the chip. When the processor reads the second data subsequently, the second data can be directly obtained from L3, avoiding DDR access, and improving the hit efficiency without increasing the on-chip storage overhead.

[0152] When the access data read from the memory by the access request contains additional data other than the requested access address, and the additional data is compressed data, the embodiments of the present application will store the redundant compressed data in the readout and maintain the original compressed state in the LLC. Among them, the additional data other than the requested access address is mainly due to the compressed state of the data stored in the memory. For example, when the length of the access request (requesting 64B original data, compressed to 32B) is less than the actual length of the compressed data (such as actually storing two adjacent 64B compressed to two 32B in the same memory cell), at this time, due to the granularity of access (i.e. the minimum size of data taken out by one access request, such as 64B), the additional data outside the request will be moved to the on-chip space, or due to the prediction error of the data compression state (the original prediction is that the 64B data is non-compressed data, but in fact the 64B is compressed data), resulting in redundant 32B compressed data being read to the on-chip. Based on the above reasons, when the additional access data (such as adjacent data, or adjacent compressed data, etc.) is read from the memory, the embodiments of the present application will read out the redundant compressed data and store it in the L3 in the original compressed state. In this way, since the data reading usually has a certain continuity, when the next time the additional access data needs to be read, it can be read from the on-chip LLC (such as L3) without reading from the off-chip memory (DDR) again, and the compressed data can be successfully hit by reading and decompressing. On the one hand, the number of memory accesses is saved (the same size of data needs two accesses before, now only one access is needed), that is, when the next time the additional data needs to be accessed, the memory does not need to be accessed, so the hit efficiency is higher, on the other hand, when the readout data that needs to be accessed is also in the compressed state (i.e. the first data is in the compressed state, which can also be referred to as the first compressed data), the actual data and the additional data (i.e. the second data in the compressed state, which can also be referred to as the second compressed data) are all cached in the LLC in the original compressed state, so the storage overhead of the on-chip cache is greatly saved; further, since the readout data is compressed, the memory bandwidth is saved compared with non-compressed data during the process of reading from the memory to the LLC.

[0153] (2) In another possible implementation, it is assumed that the LLC and its upper level cache are mutually exclusive:

[0154] The memory controller is specifically configured to: in response to the first access request, send the first data in the compressed state to the LLC; and the LLC is configured to send the first data in the compressed state received to the processor core after decompression.

[0155] For example, when the memory controller determines that the read data from the memory (such as DDR) is 64B compressed data, that is, includes two compressed data A1+A2, if the cache mechanism is L3 and L2 are mutually exclusive (the data in L2 cannot be in L3), then L3 caches A1 and directly writes A1 into L2 after decompression (Bypass) and does not save itself. Optionally, the decompression module in L3 can decompress or the decompression module in L2 can decompress. In this way, the bandwidth between the paths on the chip can be saved. When the processor needs to read the second data, it can be directly obtained from L3 to avoid DDR access, thereby improving the hit efficiency without increasing the on-chip storage overhead.

[0156] When the read data from the memory through the access request includes additional data other than the requested data, and the additional data is compressed data, the embodiment of the present application stores the redundant compressed data in the LLC in the read state. However, in different cache mechanisms, different levels of caches can be set with a mutual exclusion mechanism. When the LLC and the cache above it have a mutual exclusion mechanism, the data actually requested by the access (that is, the first data in the compressed state, which can also be referred to as the first compressed data) can be read from the memory and then cached to the cache above the LLC. Since the first data read in the embodiment of the present application is in a compressed state, the decompressed data can be cached to the cache above the LLC after being decompressed by the LLC (that is, without being cached to the LLC). For example, the LLC is L3, and it is assumed that there is a mutual exclusion mechanism between L3 and L2. Therefore, only one copy of the data is retained between the two, and the other copy is not retained in the corresponding cache. That is, after the data is read from L3 and written to L2, the data does not need to be retained in L3. Conversely, when the data is read from L2 and written to L3, the data does not need to be retained in L2. Therefore, after the read data is read from the memory, it is assumed that the first compressed data is the data actually requested by the access request. Since the data requested by the processor core is ultimately read into the processor core, that is, the first compressed data needs to be read from the memory and cached to L2→L1→the processor core, if L3 and L2 are mutually exclusive, the first compressed data does not need to be cached to L3, but can be decompressed by the LLC and then cached to L2 in a non-compressed state.

[0157] (II) The access data includes compressed data, but the access data only includes the original data actually requested by the access request:

[0158] In a possible implementation, if the access data includes the first data and the first data is in a compressed state, the memory controller is further configured to: in response to the first access request, send the first data in the compressed state to the LLC; and the LLC is configured to: receive and cache the first data in the compressed state, read the cached first data in the compressed state and send the first data in the compressed state to the processor core after decompression; or the LLC is configured to: decompress the received first data in the compressed state and send the first data in the compressed state to the processor core.

[0159] In the embodiments of the present application, when the read access data includes the first data in the compressed state stored in the partial address in the first access address (which can also be referred to as the first compressed data), the read first compressed data is equivalent to the data compressed by the preset compression rule from the original data (i.e., the first data) corresponding to the first access address, in this case, the first compressed data is stored in the LLC in the compressed state, further, in response to the first access request, the LLC reads the first compressed data cached in the LLC, then decompresses and writes to the upper cache, and finally sends to the processor core. For example, the CPU core requests to read the original data corresponding to the first access address (i.e., 128B uncompressed data), if the original data is compressed to 64B compressed data and actually stored in the low 64B address in the 128B address, the first access address is read in the partial access address (i.e., the address of the low 64B actually stored data in the 128B address), and the first compressed data is cached in the LLC in the original compressed state, and the subsequent processor core needs to read the data, which needs to be written to the upper cache, i.e., the 64B compressed data is decompressed and written to the upper cache.

[0160] In some possible implementations, when the access data includes uncompressed data, the read-out of the access data in the memory and the caching of the access data to the LLC can include one or more of the following two cases:

[0161] (I) When the access data includes uncompressed data, it is further judged whether the data can be compressed based on the data:

[0162] In a possible implementation, if the access data includes the first data, and the first data is in a non-compressed state; the memory controller is further configured to: in response to the first access request, send the first data in the non-compressed state to the LLC; optionally, further determine whether the first data is compressible; and the LLC is configured to: if the first data in the non-compressed state is compressible, compress and cache the received first data in the non-compressed state, and send the first data in the non-compressed state to the processor core; if the first data in the non-compressed state is not compressible, receive and cache the first data in the non-compressed state, and send the first data in the non-compressed state to the processor core.

[0163] For example, when the first access address belongs to the first type of address, and the first type of address includes an address corresponding to 64B non-compressed data or an address corresponding to 128B non-compressed data. When reading data from the DDR, if the data is in a non-compressed state, it is necessary to determine whether the data can be compressed. If the data can be compressed, the data can be compressed according to a preset compression rule, and stored in the LLC. The preset compression rule is consistent with the compression rule in the memory, so that subsequent data transmission can be performed according to the preset compression rule. That is, the data needs to be compressed only once according to a unified standard between the L3 and the DDR, and does not need to be compressed multiple times, thereby achieving the effect of once compression and general use in two places.

[0164] In the embodiment of the application, when the read access data includes non-compressed data originally stored in the memory in a non-compressed state, in another possible implementation, it can be determined whether the data can be compressed first. If the data can be compressed, the data is compressed and then stored in the LLC, and the compression rule is consistent with the compression rule of the compressed data in the memory, so that subsequent transmission between the memory and the LLC can be performed according to the original compression state of the data. That is, the data is compressed only once in the LLC (such as L3) and the memory (such as DDR), and the effect of storage in two places. If the data cannot be compressed, the data is stored in the LLC in a non-compressed state, and then the data is directly written into the cache of the upper level of the LLC to be finally sent to the processor core. That is, in some cases, some data is not compressed when written from the LLC into the memory, but when taken out from the memory and written into the LLC, it may be compressed again due to the demand for current bandwidth or the change of data properties, resulting in the case that the data is not compressed when stored in the memory, but needs to be compressed again when taken out from the memory and stored in the cache. Therefore, in the embodiment of the application, the non-compressed data in the memory can be compressed as much as possible according to the demand, so as to improve the data compression rate in the storage system as much as possible, and reduce the bandwidth and storage overhead.

[0165] (ii) If the accessed data includes uncompressed data, the cache is directly performed according to the original state of the data:

[0166] In a possible implementation, if the accessed data includes the first data and the first data is in the uncompressed state, the memory controller is further configured to: in response to the first access request, send the first data in the uncompressed state to the LLC; the LLC is configured to receive and cache the first data in the uncompressed state and send the first data in the uncompressed state to the processor core; or the LLC is configured to send the received first data in the uncompressed state to the processor core.

[0167] Specifically, in the embodiment of the present application, for the case that the accessed data is uncompressed data, if the data can be compressed, it has been compressed when written into the DDR. If a data is stored in the uncompressed state in the off-chip DDR, that is, it has not been compressed, it is considered that the data is probably not compressible. Therefore, when the accessed data is uncompressed data, and after the data is read out from the memory, it can not be necessary to judge and operate whether the data is compressible.

[0168] In the embodiment of the present application, when the accessed data includes uncompressed data originally stored in the memory in the uncompressed state, in a possible implementation, the data in the uncompressed state can be directly stored in the LLC in the uncompressed state. The reason is that, considering that in some scenarios, the compressed data or uncompressed data stored in the memory is written into the memory from the on-chip, that is, when a data is compressible, it has been compressed on-chip (LLC or memory controller) and then written into the memory, and when a data is not compressible, it is written into the memory in the uncompressed state. Therefore, the compressed or uncompressed data stored in the memory can indicate whether the data is compressible. Therefore, when a data is read from the memory, it can not be necessary to judge whether the data is compressible, because the current compression state of the data indicates whether the data is compressible. Therefore, in the embodiment of the present application, it can not be necessary to rejudge, but can be directly written into the LLC according to the original uncompressed state or compressed state of the data in the memory.

[0169] As to how to read the accessed data corresponding to the first access request from the memory based on the first access address, in a possible implementation, the memory controller stores a mapping relationship between address information and data compression information; the memory controller is specifically configured to: determine the data compression information corresponding to the first access address based on the mapping relationship; and read the accessed data from the memory based on the first access address and the corresponding data compression information.

[0170] Specifically, the memory controller 105 determines the data compression information corresponding to the first memory access address based on the mapping relationship between the address information and the data compression information stored in the compression state management submodule 1053. For example, the address information of the first memory access address includes the address length, whether the address is a high address or a low address, and the data compression information corresponding to the first memory access address includes whether the address corresponds to compressed data or uncompressed data, etc. For example, when the first memory access address is a certain 128B length address, and the corresponding data compression state is a compression state, then according to the preset compression mechanism in the embodiment of the present application (for example, the preset compression mechanism includes compressing data to the low bit instead of the high bit according to a compression rate of one half), it can be determined that the memory access data corresponding to the 128B length needs to be read from the low 64B position in the 128B address. For another example, when the first memory access address is a certain 64B length address, and the corresponding data compression state is a non-compression state, then according to the preset compression mechanism in the embodiment of the present application, it can be determined that the memory access data corresponding to the 64B length is directly read from the 64B position. For another example, when the first memory access address is a certain 64B length address, the corresponding data compression state is a compression state, and the 64B is the low bit in the compression unit, then according to the preset compression mechanism in the embodiment of the present application, it can be determined that the memory access data corresponding to the 64B length is directly read from the 64B position, and at this time, the additional data stored in the address due to compression will be read out.

[0171] In the embodiment of the present application, the mapping relationship between the address information and the data compression information is stored in the memory access system, for example, whether a certain address is a high address or a low address in the compression unit, and the data compression information includes whether the data is compressed data, uncompressed data, or not stored data, etc. Based on the address information of the first memory access address and the data compression information corresponding to the first memory access address, it can be determined which data needs to be read out for the first memory access address in the memory access request. It should be noted that originally in the memory access process, only the data stored in the memory access address needs to be read out, but since the present application is based on the memory bandwidth compression mechanism, there are some cases where the memory access address and the stored data are not strictly matched, because the address occupied by some compressed data will change to a certain extent, and this change is related to the preset compression mechanism used in the present application, that is, different compression algorithms may lead to different accurate corresponding relationship between the memory access address and the data.

[0172] Since the application is based on the memory bandwidth compression mechanism, in some cases, the actual data stored in the first access address may not be the original data corresponding to the address, or in other words, the original data originally requested by the first access request is not stored in the first access address, therefore, for the data requested by the first access request, it may be to read part or all of the first access address, and it may also be to read data in other addresses other than the first access address. In the embodiments of the present application, based on the different addresses of the final read access data, the types of the first access address are divided into three different cases based on the preset compression mechanism. That is, the memory controller 105 reads the access data corresponding to the first access address from the memory based on the first access address and the corresponding data compression information, which can specifically include one or more of the following three cases:

[0173] (I) In one possible implementation, the storage granularity of the LLC is a cache line; the memory controller is specifically configured to:

[0174] If it is determined that the first access address belongs to the first type of address, the access data stored in the first access address is read; the first type of address includes an address whose length is less than or equal to the cache line and which stores data, or an address whose length is greater than the cache line and which stores original data.

[0175] Specifically, in the above first case, the access data is stored in the first access address, for example, including: 1, requesting to read data in the low 64B, whether the data is compressed or not, the data in the first access address is directly read; 2, requesting to read data in the high 64B, if the data is not compressed, the data in the first access address is directly read; 3, requesting to read 128B of data, if the data is uncompressed data, the data in the first access address is directly read; in the above case 1, the first access address stores the original data corresponding thereto (i.e. the first data in the non-compressed state) or the compressed data of the original data corresponding to the first access address and the second access address (i.e. the first data in the compressed state and the second data in the compressed state); in the above cases 2 and 3, the first access address stores the original data corresponding thereto (i.e. the first data in the non-compressed state);

[0176] (II) In one possible implementation, the storage granularity of the LLC is a cache line; the memory controller is specifically configured to:

[0177] If it is determined that the first access address belongs to the second type of address, the access data stored in the second access address is read; the second type includes an address whose length is less than or equal to the cache line and whose compressed data corresponding to the original data is stored in the second access address.

[0178] Specifically, in the above-mentioned case in the second type, the data is not stored in the first access address, and the access data is stored in the second access address, for example, including: 4, requesting to read the data in the high 64B, if the data is compressed, there is no data stored in the high 64B, and the compressed data needs to be read from the low 64B (i.e., the second access address); in the above-mentioned case 4, that is, the original data that should be stored in the first access address is stored in other access addresses (such as the second access address) due to the memory bandwidth compression mechanism, so that the original data corresponding to the first access address needs to be read from the second access address at this time, and generally in this case, the second access address also stores the original data corresponding to the second access address, that is, the second access address stores the compressed data of the original data corresponding to the first access address and the second access address (i.e., the compressed first data and the compressed second data);

[0179] In a possible implementation, the storage granularity of the LLC is a cache line; and the memory controller is specifically configured to:

[0180] If it is determined that the first access address belongs to a third type of address, the access data stored in part of the access addresses in the first access address is read; the third type of address includes an address whose length is greater than the cache line and whose compressed data of the original data is stored in the part of the access addresses.

[0181] Specifically, in the above-mentioned case in the third type, the access data is stored in part of the addresses in the first access address, for example, including: 5, requesting to read the data in 128B, if the data is compressed, the data in part of the access addresses in the first access address is read; in the above-mentioned case 5, the original data corresponding to the first access address is actually stored in part of the addresses in the first access address, that is, the original data corresponding to the first access address (i.e., the first data in the uncompressed state) is stored in part of the address segments in the first access address after compression, so that the original data in the first access address only needs to be read by reading the corresponding address in the first access address.

[0182] In the embodiments of the present application, since it is based on the memory bandwidth compression mechanism, in some cases, the data actually stored in the first access address may not be the original data corresponding to the address, or in other words, the original data originally requested by the first access request is not stored in the first access address, therefore, for the data requested by the first access request, it may be to read part or all of the first access address, or it may be to read the data in other addresses other than the first access address.

[0183] In a possible implementation, the apparatus further includes a cache or a multi-level cache of the LLC; the first memory access request further includes a third memory access address; and the memory controller is further configured to: before reading the memory access data from the memory based on the first memory access address, hit the data corresponding to the third memory access address from the LLC or the cache or the multi-level cache of the LLC.

[0184] Although the data requested to be accessed exists partially in the on-chip cache and partially in the off-chip memory, from the perspective of the memory controller, it is still one memory access request, if part of the data is hit in the on-chip cache, the hit is marked as 64B (i.e., the third memory access address), and the remaining data that is not hit (i.e., the first memory access address) is continuously searched.

[0185] In the embodiment of the application, when the processor (specifically, a processor core) initiates a first memory access request, in some possible cases, the first memory access request can include a longer address than the first memory access address (i.e., an address including the first memory access address and the third memory access address), but because the data corresponding to the third memory access address has been hit in the L1, the L2, or the L3, the remaining data of the first memory access address needs to be searched in the memory.

[0186] In a possible implementation, the apparatus further includes a cache or a multi-level cache of the LLC; the memory controller is further configured to: receive a second memory access request of writing third data cached in the LLC to the cache or the multi-level cache of the LLC, and determine whether the third data is compressed data; and the LLC is further configured to: if the third data is in a compressed state, decompress the third data in the compressed state, and write the decompressed third data to the cache or the multi-level cache of the LLC; or if the third data is in a non-compressed state, write the third data in the non-compressed state to the cache or the multi-level cache of the LLC.

[0187] In the embodiment of the application, when it is necessary to request to write data in the LLC (such as the L3) to the cache or the multi-level cache of the LLC, the data needs to be read out from the LLC, and because the compressed data or the non-compressed data compressed according to a preset compression rule is stored in the LLC in the embodiment of the application, it is necessary to first determine whether the data is compressed data, if the data is compressed data, the compressed data needs to be first decompressed and then written to the cache or the multi-level cache (because the CPU core needs to read the non-compressed original data in the end), and if the data is non-compressed data, the non-compressed data is directly read and written to the cache or the multi-level cache and then sent to the processor core.

[0188] In a possible implementation, the apparatus further includes a cache at a level above the LLC; and the memory controller is further configured to: receive a write-back request for caching fourth data in the cache at the level above the LLC to the LLC; and the LLC is further configured to: if the fourth data is compressible, compress the fourth data and cache the compressed fourth data to the LLC; and if the fourth data is not compressible, cache the fourth data to the LLC.

[0189] In the embodiments of the present application, when data needs to be written (kicked out or evicted) from the cache at the level above the LLC to the LLC, it is first determined whether the data is compressible. If the data is compressible, the data is compressed first and then cached to the LLC. If the data is not compressible, the data is cached to the LLC in a non-compressed state, so that the data can be directly stored in the memory in a compressed state or a non-compressed state subsequently. That is, for a certain data, when the data is compressible, the data is preferentially compressed in the LLC, and when the data is written to the memory subsequently, the data does not need to be determined and compressed again, but can be directly written to the memory in the compressed state. When a certain data is not compressible, the data is stored in the LLC in a non-compressed state, and when the data is written to the memory subsequently, the data can be directly written to the memory in a non-compressed state without the need for determination and compression again.

[0190] The following describes embodiments related to write requests (that is, writing data to the memory):

[0191] In a possible implementation, the memory controller is further configured to: receive a third memory access request for writing fifth data cached in the LLC to the memory; and the LLC is further configured to: if the fifth data is in a compressed state, write the fifth data in the compressed state to the memory.

[0192] For example, if there is compressed data in the L3, the data can be directly transmitted to the memory. For the reverse case, if the DDR reads data to the L3, the data does not need to be compressed again, but can be directly read out in a compressed form and cached to the L3.

[0193] In the embodiments of the present application, when data cached in the last level cache LLC needs to be written to the memory, it is first determined whether the data is compressed data. If the data is compressed data, the data is also written to the memory in the original compressed state, thereby realizing the function of compressing data in one place and storing data in multiple places. Not only is the bandwidth between the on-chip (that is, the cache) and the off-chip (that is, the memory) saved, but repeated compression is also not needed, because the compression mechanism of the LLC and the memory is the same, or the compression mechanism of the memory covers the compression mechanism of the cache. Therefore, repeated compression is not needed, and the efficiency of storing compressed data is further improved.

[0194] In a possible implementation, the LLC is further configured to: if the fifth data is in a non-compressed state, compress the fifth data and write the compressed fifth data into the memory; or if the fifth data is in a non-compressed state, write the compressed fifth data into the memory.

[0195] In the embodiments of the present application, when data cached in the last level cache LLC needs to be written into the memory, it can be determined first whether the data is compressed data. If the data is non-compressed data, the non-compressed data can be compressed, and then sent to the memory for storage. In this way, the bandwidth in the system on chip and the bandwidth between the on-chip and off-chip transmission can be reduced. For example, in some possible embodiments, when the data to be written into the memory is cached in the LLC in a non-compressed state, it can be further determined whether the data can be compressed. If the data can be compressed, the data can be compressed in the memory controller on the chip and then stored in the memory. That is, there can be a case that the data cannot be compressed in the LLC, but can be compressed in the memory controller before being written into the memory. Alternatively, in another possible implementation, the non-compressed data can be directly written into the memory, because before the fifth data is cached in the LLC, it can be determined whether the data can be compressed. If the data can be compressed, the data can be compressed. If the data cannot be compressed, it can be compressed due to other reasons. Therefore, it is not necessary to determine again and compress again, so as to improve the efficiency of storage in the memory.

[0196] Compared with the write request process in the prior art, the embodiments of the present application mainly have the following differences. On the one hand, in the write request in the prior art, there is no concept of prefetch cache, because in the prior art, there is only the concept of prefetch cache for the read request process, and there is no prefetch cache for the write request process. However, the LLC (such as L3) in the embodiments of the present application can serve as a prefetch cache for the read process and a prefetch cache for the write process.

[0197] From the write process, in the prior art, the L3 can only store non-compressed data, so that the non-compressed data can be read out from the L3 and compressed by the memory controller, and then written into the DDR. In the embodiments of the present application, the data is compressed in the L3, or the compressed data in the L3 is transmitted to the DDR in a compressed state, which is beneficial to improving the bandwidth between the internal paths on the chip and the bandwidth between the on-chip and off-chip.

[0198] From the reading process, the prior art L3 reads non-compressed data directly from the DDR or the prefetch cache, that is, the prior art L3 does not store compressed data, that is, the data read from the DDR or the prefetch cache into the L3 is non-compressed data stored by the prior art L3. In the present application, the L3 can not only be used as a prefetch cache, but also store compressed data, and by setting the data compression format and granularity in the L3 to be the same as that in the memory, the L3 can store compressed data in cooperation with the DDR.

[0199] In the following, embodiments related to read-modify-write requests (that is, first reading data from the memory or the cache, then modifying the data, and finally writing the modified data to the memory or the cache) are described:

[0200] In a possible implementation, the apparatus further includes another LLC; and the memory controller is further configured to: receive a request for reading and modifying the sixth data; if the sixth data meets a preset condition, determine whether the seventh data is in the LLC or the other LLC, the seventh data being data adjacent to the sixth data in the physical address in the memory; if the seventh data is in a target LLC, obtain the seventh data from the target LLC; determine a compression state of the sixth data and the seventh data when written into the memory based on a compression state of the seventh data; and write the sixth data and the seventh data into the memory based on the determined compression state.

[0201] In the aspect of read-modify-write (RWM), when the processor writes data to the memory, if the length of the data is less than the basic length of compression, the data of the remaining part needs to be referred to in order to determine the compression state of the data written to the memory, which introduces additional memory read operations. For example, when the processor initiates a request to read-modify-write 64 KB data (e.g., first data) in the memory, and the basic length of data compression in the memory is to compress 128 KB data into 64 KB, that is, the first data is originally compressed with the second data into the memory data (i.e., 64 KB in the compressed state), that is, two 64 KB (total 128 KB) are compressed into 64 KB, when the processor needs to read-modify-write 64 KB of the first data, the memory data (i.e., the compressed first data + the second data) needs to be read out first, then modified and written back to the memory, thereby completing the read-modify-write process. In this read-modify-write process, the processor only needs to read-modify-write the first data, but because the first data is compressed and stored with the second data in the memory, in the read-modify-write process, the second data that does not need to be read-modified-written is read out from the memory and stored in the cache. Alternatively, when the data in a certain target unit of the memory is read-modified-written, because the length of the data is 64, which is less than the basic compression unit 128 KB, because the data in the adjacent unit to the target unit needs to be referred to, additional data needs to be read, that is, additional memory read operations are introduced.

[0202] Based on the above, in the embodiment of the present application, when the memory access system receives a request to read and rewrite a certain data (i.e., the sixth data) in the LLC to the memory, it is necessary to first determine whether the sixth data meets the preset condition. Optionally, the determination of whether the sixth data meets the preset condition can be made by querying relevant information, which can include the following aspects, such as the compression state of the sixth data itself, and the length, position (such as high or low) of the address corresponding to the sixth data. When it is determined based on the above relevant information that the length of the original address corresponding to the sixth data is less than or equal to the minimum unit of compressed storage (such as 64B), such as the sixth data being 64B of non-compressed data or 32B of compressed data, in some cases, whether the sixth data is read and rewritten in a compressed state or in a non-compressed state, and the address written after the sixth data is read and rewritten, can depend on the data (i.e., the seventh data) adjacent to the physical address of the sixth data in the memory. For example, if the sixth data is the high 64B data in 128B alignment, it may need to be stored together with the low 64B seventh data in the physical address of the seventh data after compression. If the seventh data cannot be compressed, the sixth data cannot be compressed either, that is, it is necessary to refer to whether the seventh data associated with the sixth data can be compressed. For example, if the sixth data is the low 64B data in 128B alignment, it is currently determined to be non-compressible, but the address written back in the non-compressed state has already stored the seventh data (the original high 64B data) in the compressed state. At this time, if the seventh data is not obtained first and the compression state of the seventh data is not known, the sixth data cannot be written back in the non-compressed state either, that is, in this case, the compression state and storage address of the seventh data associated with the sixth data need to be referred to. However, if the seventh data is stored in the memory, it needs to be read out from the memory, which not only increases the on-chip and off-chip bandwidth, but also reduces the efficiency of data storage. Therefore, in the embodiment of the present application, the eighth data in other LLCs in the processing device is preferentially processed, because in the processing device of the embodiment of the present application, the last level caches corresponding to different processor cores are interconnected and shared with the memory, so the seventh data can be cached in other LLCs. If the seventh data can be obtained from other LLCs, the additional memory bandwidth overhead caused by reading and rewriting can be reduced, and the reading and rewriting efficiency can be improved.

[0203] In a possible implementation, the memory controller comprises a first compression module and a first decompression module; the LLC comprises a second compression module and a second decompression module; the first compression module is configured to compress uncompressed data that needs to be compressed and is stored into the memory; the second decompression module is configured to decompress compressed data that needs to be decompressed and is fetched from the memory; the second compression module is configured to compress uncompressed data that needs to be compressed and is cached into the LLC; and the second decompression module is configured to decompress compressed data that needs to be decompressed and is fetched from the LLC. In the embodiment of the present application, the memory controller and the LLC can each comprise a corresponding compression module and a decompression module, which can be used to compress or decompress relevant data in different processes, different memory access stages (for example, reading data, writing data, and reading and writing data), or different compression granularity requirements.

[0204] It should be noted that the specific compression rules for compressed data stored in the cache or the memory in the embodiment of the present application can be set differently according to different application scenarios. For example, the compression mode, compression algorithm, compression granularity, and storage address of compressed data can be different according to different application requirements. The compression rules between the LLC and the memory can be completely the same or not completely the same, and the embodiment of the present application does not make a specific limitation in this regard.

[0205] In a possible implementation, the first compression module and the second compression module use the same preset compression rule to compress data.

[0206] In the embodiment of the present application, the compression modules in the memory controller and the LLC use the same compression algorithm, that is, the same compression mechanism to compress data. Correspondingly, the decompression modules in the memory controller and the LLC also use the same decompression algorithm, that is, the same decompression mechanism to decompress data. Optionally, the preset compression rule in the memory controller can include but is not limited to the preset compression rule in the LLC, that is, the compression and decompression modules in the memory controller can have more possible compression modes and compression granularities and corresponding decompression modes and decompression granularities than the LLC.

[0207] Exemplarily, refer to FIG. 3A, which is a schematic diagram of physical memory space division provided in an embodiment of the present application. Since physical memory is usually managed in units of pages, and virtual memory is finally mapped to physical memory, there is also a concept of virtual page corresponding to the physical page in the virtual memory space, and the mapping of memory is usually in units of pages. The continuous virtual memory seen by a process (a process of a system or an application) can be discontinuous in physical memory. For example, in FIG. 3A, virtual page 2 and virtual page 3 in process 1 are continuous in the virtual memory space of process 1, but the physical memory pages to which they are mapped are discontinuous (corresponding to physical page 1 and physical page 3 respectively). For another example, in process 2, virtual page 5 is mapped to physical page 5, and virtual page 6 is mapped to physical page 7. Physical page 1, physical page 2 and physical page 3 in the physical memory space are the memory being used by process 1, and physical page 5 and physical page 7 are the memory being used by process 2. These complex and specific memory mapping details can be managed by a memory management subsystem running on a processor or a memory controller.

[0208] Exemplarily, refer to FIG. 3B, which is a schematic diagram of address division of a physical page provided in an embodiment of the present application. For example, in FIG. 3B, when the granularity size of CacheLine of a cache (Cache) in a system on chip (SOC) 10 is 64 bytes, and the size of a physical page is 4K (KB), at this time, the physical page can be divided into 64 memory units of 64 bytes, 1KB = 1024B, and 4KB / 64B = 64 memory units, that is, one memory region (4K in size) includes 64 memory units. The Cache Line is the minimum unit of data transmission between a processor (CPU) and a memory (main memory), that is, the minimum access granularity. For example, when the size of Cache Line is 64 bytes (64 bytes), the CPU will continuously take 64 bytes of data from the memory when transmitting data.

[0209] Exemplarily, refer to FIG. 3C, which is a schematic diagram of high 64B and low 64B of 128B alignment provided in an embodiment of the present application. For example, in FIG. 3C, a 4K memory page can include 32 memory units with cacheLine as the granularity, each memory unit is 64 bytes, and the high 64 bits and the low 64 bits of 128 bytes of data can be respectively stored between two adjacent memory units. It can be understood that other alignment sizes can also be used as compression granularity in the present application, for example, 256B of data can be compressed to 64B, or 256B of data can be compressed to 128B, and the present application does not make specific limitations on this.

[0210] Exemplarily, based on the above-mentioned physical address division schematic diagram, in a possible embodiment, referring to FIG. 4A, which is a schematic diagram of mapping relationship between data and address before and after compression provided by an embodiment of the present application, in FIG. 4A, it is assumed that the first memory access address and the second memory access address in the embodiment of the present application are two adjacent 64B of 128B alignment, wherein the first memory access address is the high 64B, the second memory access address is the low 64B, and the original data corresponding to the first memory access address is the first data (i.e. if not compressed, the first data should be stored in the first memory access address), the original data corresponding to the second memory access address is the second data (i.e. if not compressed, the second data should be stored in the second memory access address); when the first data and the second data are compressed based on the memory bandwidth compression technology respectively, and it is assumed that the 128B data is stored in the low 64B address after compression, then the first compressed data and the second compressed data stored in the second memory access address. For example, the high 64B data and the low 64B data are compressed into high 32B data and low 32B data according to a preset compression rule respectively, and the compressed 32B high data and 32B low data are stored in the second memory access address (the address length of the low 64B), so that the first memory access address is empty, and the first data and the second data originally stored in the first memory access address and the second memory access address are stored in the second memory access address. Therefore, when the processor requests to read the first memory access address (i.e. the original purpose is to request the first data), it is actually necessary to read from the second memory access address, and due to the size of the memory access granularity, it is assumed that the minimum memory access granularity is 64B, so the memory access data read out this time includes the first compressed data and the second compressed data, i.e. the compressed high 32B data + low 32B data, in this case, the extra data read out is the second compressed data.

[0211] In another possible embodiment, referring to FIG. 4B, which is a schematic diagram of mapping relationship between data and address before and after compression provided by an embodiment of the present application, in FIG. 4B, it is assumed that the first memory access address and the second memory access address in the embodiment of the present application are two adjacent 64B of 128B alignment, wherein the first memory access address is the low 64B and the second memory access address is the high 64B, and the original data corresponding to the first memory access address is the first data (i.e. if no compression is performed, the first data should be stored in the first memory access address), and the original data corresponding to the second memory access address is the second data (i.e. if no compression is performed, the second data should be stored in the second memory access address); when the first data and the second data are compressed based on the memory bandwidth compression technology respectively, and it is assumed that the 128B data is stored in the low 64B address after compression, then the first compressed data and the second compressed data are stored in the first memory access address. For example, the high 64B data and the low 64B data are compressed into high 32B data and low 32B data respectively according to a preset compression rule, and the compressed 32B high data and 32B low data are stored in the first memory access address (the address length is 64B), so the second memory access address is empty, and the first memory access address stores the first data and the second data which should be stored in the first memory access address and the second memory access address respectively. Therefore, when the processor requests to read the first memory access address (i.e. the original purpose is to request the first data), the first memory access address is read, but due to the memory access granularity, it is assumed that the minimum memory access granularity is 64B, so the memory access data read out this time includes the first compressed data and the second compressed data, i.e. the compressed high 32B data + low 32B data, and in this case, the extra data read out is the second compressed data.

[0212] In yet another possible embodiment, referring to FIG. 4C, which is a schematic diagram of mapping relationship between data and address before and after compression provided by an embodiment of the present application, in FIG. 4C, it is assumed that the first memory access address in the embodiment of the present application is a 128B-aligned address, wherein the 128B of the first memory access address can be divided into high 64B and low 64B, and the original data corresponding to the first memory access address is first data (i.e. if no compression is performed, the first data should be stored in the first memory access address); when the first data is compressed based on the memory bandwidth compression technology (it can be directly compressed from 128B to 64B, or two 64B are respectively compressed to 32B), and it is assumed that the 128B of data after compression is stored in the low 64B, then the first compressed data (i.e. the first data in the compressed state) is stored in the low 64B of the first memory access address. For example, the high 64B data and the low 64B data are respectively compressed to high 32B data and low 32B data according to a preset compression rule, and the compressed 32B high data and 32B low data are stored in the low 64B position (64B address length) in the first memory access address, so the high 64B position in the first memory access address is empty, and the low 64B position in the first memory access address stores the first data which should be respectively stored in the high 64B position and the low 64B position in the first memory access address. Therefore, when the processor requests to read the first memory access address, the first compressed data, i.e. the compressed high 32B data + low 32B data, is read from the low 64B position in the first memory access address, and in this case, no extra data is read out.

[0213] In yet another possible embodiment, please refer to FIG. 4D, which is a schematic diagram of mapping relationship between data and address before and after compression provided by an embodiment of the present application. In FIG. 4D, it is assumed that the first memory access address in the embodiment of the present application is a non-128B-aligned address, wherein the first memory access address spans the low 64B-01 and the high 64B-02 in two 128B-aligned addresses. When the two pieces of data are compressed based on the memory bandwidth compression technology, and it is assumed that the 128B data is stored in the low 64B address after compression, for example, the high 64B-01 data and the low 64B-01 data are compressed and stored in the low 64B-01 address, and the high 64B-02 data and the low 64B-02 data are not compressed and still stored in the original position, therefore the first memory access address contains the original high 64B-01 data, the low 64B-01 data and the high 64B-02 data, and the original high 64B-01 data and the low 64B-01 data are both compressed data. Therefore, when the processor requests to read the first memory access address, three pieces of data, i.e. the compressed high 32B-01 data + low 32B-01 data + high 64B-02 data, will be read from the first memory access address. In this case, the extra data read is the high 32B-01 data.

[0214] The following takes the processor issuing a DDR memory access request and supporting 64B and 128B lengths as an example to exemplarily describe the related memory access process of reading data. Please refer to FIG. 5A and FIG. 5B, FIG. 5A is a flowchart of processing a 128B read request provided by an embodiment of the present application, and FIG. 5B is a flowchart of processing a 64B read request provided by an embodiment of the present application. The following takes the read request as 128B granularity or 64B granularity as an example to exemplarily describe the specific process of processing the 128B and 64B read requests in the embodiment of the present application:

[0215] The following takes the read request as 128B granularity or 64B granularity as an example to exemplarily describe the specific process of processing the 128B and 64B read requests in the embodiment of the present application:

[0216] Scenario one: 128B read process

[0217] The processor issues a 128B DDR request, and after the memory controller 105 receives the 128B read request, it first checks whether there is complete 128B data in each level of cache. If there is in the L1, it is directly read out from the L1; if there is in the L2, it is copied from the L2 to the L1 and then read. It is assumed that there is no hit in the L1 and the L2, and there is complete 128B data in the L3, which is directly read from the L3.

[0218] (1) L1 miss→L2 miss→L3 has complete 128B data→directly read from L3;

[0219] (2) L1 miss -> L2 miss -> L3 has partial 64B data -> then read the remaining 64B data from the request in DDR (at this time, the compression state of the data also needs to be judged first, so as to read out from the corresponding address);

[0220] (3) L1 miss -> L2 miss -> L3 miss -> judge the compression state of the data to be read -> if it is compressed data -> access the address position of the low 64B in DDR according to the length of 64B;

[0221] (4) L1 miss -> L2 miss -> L3 miss -> if it is uncompressed data -> access the address position of the complete 128B in DDR according to the length of 128B.

[0222] Scenario two: 64B read flow

[0223] The processor issues a 64B DDR request, and after the memory controller 105 receives the 64B read request, it first checks whether there is complete 64B data in each level of cache. If there is in L1, it is directly read out from L1. If there is in L2, it is copied to L1 for reading. Assuming that L1 and L2 are both missed, it can include the following several cases:

[0224] (1) L1 miss -> L2 miss -> L3 has the 64B data -> directly read;

[0225] (2) L1 miss -> L2 miss -> L3 miss (query missing) and the memory access address is to read the low 64B -> directly access the address position of the low 64B in DDR -> if it is compressed data -> store the redundant data in L3;

[0226] (3) L1 miss -> L2 miss -> L3 miss (i.e. query missing) and the memory access address is to read the high 64B -> judge the compression state of the data to be read -> if it is compressed data -> access the address position of the low 64B in DDR according to the length of 64B -> if it is uncompressed data -> access the address position of the high 64B in DDR according to the length of 64B.

[0227] The following takes the processor issuing a DDR memory access request as an example, and supports 64B and 128B lengths, to exemplarily describe the related memory access flow of writing data. Please refer to FIG. 5C and FIG. 5D, FIG. 5C is a flowchart of processing a 128B write request according to an embodiment of the present application, and FIG. 5D is a flowchart of processing a 64B write request according to an embodiment of the present application. The following takes the write request as 128B granularity or 64B granularity as an example to exemplarily describe the specific flow of processing 128B and 64B write requests in the embodiment of the present application:

[0228] Scenario one: 128B write process

[0229] The processor issues a DDR request of 128B, and after the memory controller 105 receives the write request of 128B, the following cases can be included:

[0230] (1) The data to be written is compressed data cached in L3 → the compressed data is directly written from L3 in the original compressed format to DDR;

[0231] (2) The data to be written is non-compressed data cached in L3 → it is determined whether the data to be written is compressible → if it is compressible, it is written to the low 64B address position in DDR after compression → if it is not compressible, it is written to the corresponding 128B address position in DDR in a non-compressed state.

[0232] Scenario two: 64B write process

[0233] After the processor issues a DDR request of 64B, and after the memory controller 105 receives the 64B write or read-write request, the following cases can be included:

[0234] (1) L1 miss → L2 miss → L3 hit → if the preset condition is met, it is determined whether the other 64B is on-chip → if it is on-chip, the data is obtained from other L3 on-chip → and the write 128B is processed.

[0235] (2) L1 miss → L2 miss → L3 hit → it is determined whether the other 64B is on-chip → if it is not on-chip and the DDR bandwidth is in a relatively idle state (i.e., the current bandwidth usage is less), the other 64B data is obtained from DDR → and the write 128B is processed.

[0236] (3) L1 miss → L2 miss → L3 hit → it is determined whether the other 64B is on-chip → if it is not on-chip and the DDR bandwidth is in a relatively tight state (i.e., the current bandwidth usage is more), the low 64B corresponding to the non-compressed position is directly written and the compression flag is updated.

[0237] It should be noted that in the description of the above embodiments, the numerical sequence (1), (2), (3), etc. do not represent the strict time execution order or sequence, that is, the sequence does not constitute a limitation on the execution order or sequence of the above scenarios, and the above different scenarios do not constitute a limitation between the embodiments. The above different embodiments can be executed independently or in combination, and will not be described in detail here.

[0238] Please refer to FIG. 6, which is a flowchart of a storage management method according to an embodiment of the present application. The storage management method can be applied to a processing device, a system on chip (SoC), an off-chip memory management system, a memory access system, an electronic device including an SoC, or a memory management module in an electronic device, etc. The electronic device includes a processor core, a last level cache (LLC) and a memory. The memory stores compressed data and / or uncompressed data compressed according to a preset compression rule. The method can include the following steps S601-S603, wherein,

[0239] S601: receiving a first memory access request for reading first data sent by a processor core, the first memory access request carrying a first memory access address;

[0240] S602: reading memory access data from a memory coupled to the processor core based on the first memory access address;

[0241] S603: if the memory access data includes the first data and second data in a compressed state, sending the first data to the processor core and caching the second data in the compressed state to the LLC in response to the first memory access request.

[0242] In a possible implementation, the memory access data further includes a compression identifier indicating whether the second data is in a compressed state. The method further includes caching the compression identifier to the LLC.

[0243] In a possible implementation, if the first data is in a compressed state, the sending of the first data to the processor core includes: sending the first data in a compressed state to the LLC in response to the first memory access request; receiving and caching the first data in the compressed state through the LLC, reading and decompressing the cached first data in the compressed state and sending the decompressed data to the processor core; or, decompressing the received first data in the compressed state through the LLC and sending the decompressed data to the processor core. The first data in the compressed state is part or all of original data corresponding to the first memory access address compressed, and the second data in the compressed state is part or all of original data corresponding to a second memory access address in the memory compressed.

[0244] In a possible implementation, if the memory access data includes the first data and the first data is in a compressed state, the method further includes: in response to the first memory access request, sending the first data in the compressed state to the LLC; receiving and caching, by the LLC, the first data in the compressed state, reading the cached first data in the compressed state and sending the first data in the compressed state to the processor core after decompression; or sending, by the LLC, the received first data in the compressed state to the processor core after decompression.

[0245] In a possible implementation, if the memory access data includes the first data and the first data is in a non-compressed state, the method further includes: in response to the first memory access request, sending the first data in the non-compressed state to the LLC; receiving and caching, by the LLC, the first data in the non-compressed state and sending the first data in the non-compressed state to the processor core; or sending, by the LLC, the received first data in the non-compressed state to the processor core.

[0246] In a possible implementation, if the memory access data includes the first data and the first data is in a non-compressed state, the method further includes: in response to the first memory access request, sending the first data in the non-compressed state to the LLC; if the first data in the non-compressed state is compressible, compressing, by the LLC, the received first data in the non-compressed state and caching the first data in the non-compressed state, and sending the first data in the non-compressed state to the processor core; if the first data in the non-compressed state is not compressible, receiving and caching, by the LLC, the first data in the non-compressed state, and sending the first data in the non-compressed state to the processor core.

[0247] In a possible implementation, the reading, based on the first memory access address, of the memory access data from a memory coupled to the processor core includes: determining data compression information corresponding to the first memory access address based on a pre-stored mapping relationship; the mapping relationship includes a mapping relationship between address information and data compression information; and reading, based on the first memory access address and the corresponding data compression information, the memory access data from the memory.

[0248] In a possible implementation, the storage granularity of the LLC is a cache line; and the reading of the memory data from the memory based on the first memory address and the corresponding data compression information comprises: if it is determined that the first memory address belongs to a first type of address, reading the memory data stored in the first memory address; the first type of address comprises an address whose length is less than or equal to the cache line and that stores data, or an address whose length is greater than the cache line and that stores original data; or if it is determined that the first memory address belongs to a second type of address, reading the memory data stored in a second memory address; the second type of address comprises an address whose length is less than or equal to the cache line and that stores compressed data of original data in the second memory address; or if it is determined that the first memory address belongs to a third type of address, reading the memory data stored in part of the first memory address; the third type of address comprises an address whose length is greater than the cache line and that stores compressed data of original data in the part of the first memory address.

[0249] In a possible implementation, the first memory request further comprises a third memory address; and the method further comprises: before reading the memory data from the memory based on the first memory address, hitting the data corresponding to the third memory address from the LLC or a cache at one or more levels above the LLC.

[0250] In a possible implementation, the method further comprises: receiving a second memory request of writing third data cached in the LLC to the cache at the one or more levels above; determining whether the third data is compressed data; if the third data is in a compressed state, decompressing, by the LLC, the third data in the compressed state, and writing the decompressed third data to the cache at the one or more levels above; and if the third data is in a non-compressed state, writing, by the LLC, the third data in the non-compressed state to the cache at the one or more levels above.

[0251] In a possible implementation, the method further comprises: receiving a write-back request of caching fourth data in the cache at the one or more levels above to the LLC; if the fourth data is compressible, compressing, by the LLC, the fourth data, and caching the compressed fourth data to the LLC; and if the fourth data is incompressible, caching, by the LLC, the fourth data to the LLC.

[0252] In a possible implementation, the method further comprises: receiving a third memory request of writing fifth data cached in the LLC to the memory; and if the fifth data is in a compressed state, writing, by the LLC, the fifth data in the compressed state to the memory.

[0253] In a possible implementation, the method further includes: if the fifth data is in a non-compressed state, compressing the fifth data by the LLC and writing the fifth data in a compressed state into the memory; or if the fifth data is in a non-compressed state, writing the fifth data in a compressed state into the memory by the LLC.

[0254] In a possible implementation, the method further includes: receiving a request for reading and rewriting sixth data in the LLC; if the sixth data meets a preset condition, determining whether seventh data is in the LLC or the other LLC, the seventh data being data physically adjacent to the sixth data in the memory; if the seventh data is in a target LLC, obtaining the seventh data from the target LLC; determining a compression state of the sixth data and the seventh data when written into the memory based on a compression state of the seventh data; and writing the sixth data and the seventh data into the memory based on the determined compression state.

[0255] It should be noted that the specific process of the storage management method described in the embodiments of the present application can refer to the related descriptions of the embodiments described in the foregoing FIGS. 2A-4D, which will not be repeated here.

[0256] The embodiments of the present application further provide a computer readable storage medium, wherein the computer readable storage medium can store a program, and the program is executed by an electronic device to include part or all steps of any one of the methods described in the embodiments.

[0257] The embodiments of the present application further provide a computer program, and the computer program includes instructions, and when the computer program is executed by an electronic device, the electronic device can execute part or all steps of any one of the storage management methods.

[0258] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0259] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the present application is not limited to the order of the actions described, because according to the present application, some steps can be performed in other order or at the same time. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application.

[0260] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments described above is merely a logical division, and there can be another division manner in actual implementation. For example, two or more units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between units can be indirect coupling or communication connection through some interface, device or unit, and can be electrical or other forms.

[0261] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place or distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0262] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0263] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc., and specifically can be a processor in the computer device) to execute all or part of the steps of the methods described above in the various embodiments of the present application. Among them, the storage medium mentioned above can include: a U disk, a mobile hard disk, a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, abbreviated as ROM) or a random access memory (Random Access Memory, abbreviated as RAM) and various program code storage media.

[0264] The above-described embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A processing device, characterized by, Comprising: a processor core, a last level cache LLC and a memory controller; the memory controller is configured to: receive a first memory access request for reading first data sent by the processor core, the first memory access request carrying a first memory access address; read memory access data from a memory coupled to the processing device based on the first memory access address; if the memory access data comprises the first data and second data in a compressed state, send the first data to the processor core through the LLC and cache the second data in the compressed state to the LLC in response to the first memory access request.

2. The apparatus of claim 1, wherein, the memory access data further comprises a compression identifier indicating whether the second data is in a compressed state; the memory controller is further configured to cache the compression identifier to the LLC.

3. The apparatus of claim 1 or 2, wherein, if the first data is in a compressed state; the memory controller is specifically configured to send the first data in a compressed state to the LLC in response to the first memory access request; the LLC is configured to receive and cache the first data in a compressed state, read the cached first data in a compressed state and send it to the processor core after decompression; or the LLC is configured to decompress the received first data in a compressed state and send it to the processor core. wherein the first data in a compressed state is obtained by compressing part or all of the original data corresponding to the first memory access address, and the second data in a compressed state is obtained by compressing part or all of the original data corresponding to a second memory access address in the memory.

4. The apparatus of any one of claims 1-3, wherein, if the memory access data comprises the first data and the first data is in a compressed state; the memory controller is further configured to send the first data in a compressed state to the LLC in response to the first memory access request; the LLC is configured to receive and cache the first data in a compressed state, read the cached first data in a compressed state and send it to the processor core after decompression; or the LLC is configured to decompress the received first data in a compressed state and send it to the processor core. if the memory access data comprises the first data and the first data is in a non-compressed state; 5. The apparatus of any one of claims 1-4, wherein, the memory controller is further configured to send the first data in a non-compressed state to the LLC in response to the first memory access request; the LLC is configured to receive and cache the first data in a non-compressed state and send it to the processor core; or the LLC is configured to send the received first data in a non-compressed state to the processor core. if the memory access data comprises the first data and the first data is in a non-compressed state; the memory controller is further configured to send the first data in a non-compressed state to the LLC in response to the first memory access request; 6. The apparatus of any one of claims 1-4, wherein, the LLC is configured to: if the first data in a non-compressed state is compressible, compress the received first data in a non-compressed state and cache it, and send the first data in a non-compressed state to the processor core; if the first data in a non-compressed state is not compressible, receive and cache the first data in a non-compressed state, and send the first data in a non-compressed state to the processor core. ​ ​ ​ 7. The apparatus of any one of claims 1-6, wherein, The memory controller stores a mapping relationship between address information and data compression information; the memory controller is specifically used for: determining data compression information corresponding to the first memory access address based on the mapping relationship; reading the memory access data from the memory based on the first memory access address and the corresponding data compression information.

8. The apparatus of claim 7, wherein, The storage granularity of the LLC is a cache line; the memory controller is specifically used for: if it is determined that the first memory access address belongs to a first type of address, reading the memory access data stored in the first memory access address; the first type of address includes an address whose address length is less than or equal to the cache line and that stores data, or an address whose address length is greater than the cache line and that stores original data; or, if it is determined that the first memory access address belongs to a second type of address, reading the memory access data stored in a second memory access address; the second type of address includes an address whose address length is less than or equal to the cache line and that stores compressed data of corresponding original data in the second memory access address; or, if it is determined that the first memory access address belongs to a third type of address, reading the memory access data stored in part of the memory access addresses in the first memory access address; the third type of address includes an address whose address length is greater than the cache line and that stores compressed data of corresponding original data in the part of the memory access addresses.

9. The apparatus of any one of claims 1-8, wherein, The device further includes an upper-level cache or a multi-level cache of the LLC; the first memory access request further includes a third memory access address; and the memory controller is further used for: before reading the memory access data from the memory based on the first memory access address, hitting data corresponding to the third memory access address from the LLC or the upper-level cache or the multi-level cache of the LLC.

10. The apparatus of any one of claims 1-9, wherein, The device further includes an upper-level cache of the LLC; and the memory controller is further used for: receiving a second memory access request of writing third data cached in the LLC to the upper-level cache, and judging whether the third data is compressed data; The LLC is further used for: if the third data is in a compressed state, decompressing the third data in the compressed state and writing the decompressed third data to the upper-level cache; if the third data is in a non-compressed state, writing the third data in the non-compressed state to the upper-level cache.

11. The apparatus of any one of claims 1-10, wherein, The device further includes an upper-level cache of the LLC; and the memory controller is further used for: receiving a write-back request of caching fourth data in the upper-level cache to the LLC; The LLC is further used for: if the fourth data is compressible, compressing the fourth data and caching the compressed fourth data to the LLC; if the fourth data is not compressible, caching the fourth data to the LLC.

12. The apparatus of any one of claims 1-11, wherein, The memory controller is further used for: receiving a third memory access request of writing fifth data cached in the LLC to the memory; The LLC is further used for: if the fifth data is in a compressed state, writing the fifth data in the compressed state to the memory.

13. The apparatus of claim 12, wherein, The LLC is further used for: If the fifth data is in a non-compressed state, the fifth data is compressed, and the compressed fifth data is written to the memory; or if the fifth data is in a non-compressed state, the compressed fifth data is written to the memory.

14. The apparatus of any one of claims 1-13, wherein, The apparatus further includes other LLCs; and the memory controller is further configured to: receive a request for reading and rewriting sixth data in the LLC; if the sixth data meets a preset condition, determine whether seventh data is in the LLC or the other LLCs, the seventh data being data adjacent to the sixth data in a physical address in the memory; if the seventh data is in a target LLC, obtain the seventh data from the target LLC; determine a compression state of the sixth data and the seventh data when written to the memory based on a compression state of the seventh data; write the sixth data and the seventh data to the memory based on the determined compression state.

15. The apparatus of any one of claims 1-14, wherein, The memory controller includes a first compression module and a first decompression module; and the LLC includes a second compression module and a second decompression module. The first compression module is configured to compress non-compressed data stored in the memory and requiring compression; and the second decompression module is configured to decompress compressed data taken from the memory and requiring decompression. The second compression module is configured to compress non-compressed data cached in the LLC and requiring compression; and the second decompression module is configured to decompress compressed data taken from the LLC and requiring decompression.

16. The apparatus of claim 15, wherein, The first compression module and the second compression module use the same preset compression rule to compress data.

17. A storage management method characterized by comprising: The method includes: receiving a first memory access request for reading first data sent by a processor core, the first memory access request carrying a first memory access address; reading memory access data from a memory coupled to the processor core based on the first memory access address; if the memory access data includes the first data and second data in a compressed state, sending the first data to the processor core and caching the second data in the compressed state to the LLC in response to the first memory access request.

18. The method of claim 17, wherein, The memory access data further includes a compression identifier indicating whether the second data is in a compressed state; and the method further includes caching the compression identifier to the LLC.

19. The method of claim 17 or 18, wherein, If the first data is in a compressed state, the sending of the first data to the processor core includes: sending first data in a compressed state to the LLC in response to the first memory access request; receiving and caching, by the LLC, the first data in the compressed state, reading and decompressing the cached first data in the compressed state, and sending the decompressed first data to the processor core; or decompressing, by the LLC, the received first data in the compressed state, and sending the decompressed first data to the processor core; wherein the first data in the compressed state is obtained by compressing part or all of original data corresponding to the first memory access address, and the second data in the compressed state is obtained by compressing part or all of original data corresponding to a second memory access address in the memory.

20. The method of any one of claims 17-19, wherein, If the access data includes the first data and the first data is in a compressed state; the method further comprises: In response to the first access request, sending the first data in a compressed state to the LLC; Receiving and caching the first data in the compressed state through the LLC, reading the cached first data in the compressed state and sending to the processor core after decompression; or, sending the received first data in the compressed state to the processor core after decompression through the LLC.

21. The method according to any one of claims 17-20, characterized by, If the access data includes the first data and the first data is in a non-compressed state; the method further comprises: In response to the first access request, sending the first data in a non-compressed state to the LLC; Receiving and caching the first data in the non-compressed state through the LLC and sending to the processor core; or, sending the received first data in the non-compressed state to the processor core through the LLC.

22. The method of any one of claims 17-20, wherein, If the access data includes the first data and the first data is in a non-compressed state; the method further comprises: In response to the first access request, sending the first data in a non-compressed state to the LLC; If the first data in the non-compressed state is compressible, compressing the received first data in the non-compressed state through the LLC and caching, and sending the first data in the non-compressed state to the processor core; If the first data in the non-compressed state is not compressible, receiving and caching the first data in the non-compressed state through the LLC, and sending the first data in the non-compressed state to the processor core.

23. The method of any of claims 17-22, wherein, The reading of the access data from the memory coupled to the processor core based on the first access address comprises: Determining the data compression information corresponding to the first access address based on the pre-stored mapping relationship; the mapping relationship comprises the mapping relationship between address information and data compression information; Reading the access data from the memory based on the first access address and the corresponding data compression information.

24. The method of claim 23, wherein, The storage granularity of the LLC is a cache line; the reading of the access data from the memory based on the first access address and the corresponding data compression information comprises: If it is determined that the first access address belongs to a first type of address, reading the access data stored in the first access address; the first type of address includes an address whose length is less than or equal to the cache line and which stores data, or an address whose length is greater than the cache line and which stores original data; or, If it is determined that the first access address belongs to a second type of address, reading the access data stored in the second access address; the second type includes an address whose length is less than or equal to the cache line and whose corresponding compressed data of the original data is stored in the second access address; or, If it is determined that the first access address belongs to a third type of address, reading the access data stored in part of the access addresses in the first access address; the third type of address includes an address whose length is greater than the cache line and whose corresponding compressed data of the original data is stored in the part of the access addresses.

25. The method of any of claims 17-24, wherein, The method further comprises: receiving a second memory access request for writing third data buffered in the LLC to the upper-level cache, determining whether the third data is compressed data; if the third data is in a compressed state, decompressing the third data in the compressed state by the LLC, and writing the decompressed third data to the upper-level cache; if the third data is in a non-compressed state, writing the third data in the non-compressed state to the upper-level cache by the LLC.

26. The method of any one of claims 17-25, wherein, The method further comprises: receiving a write-back request for buffering fourth data in the upper-level cache to the LLC; if the fourth data is compressible, compressing the fourth data by the LLC, and buffering the compressed fourth data to the LLC; if the fourth data is not compressible, buffering the fourth data to the LLC by the LLC.

27. The method of any of claims 17-26, wherein, The method further comprises: receiving a third memory access request for writing fifth data buffered in the LLC to the memory; if the fifth data is in a compressed state, writing the fifth data in the compressed state to the memory by the LLC.

28. The method of claim 27, wherein, The method further comprises: if the fifth data is in a non-compressed state, compressing the fifth data by the LLC, and writing the fifth data in the compressed state to the memory; or, if the fifth data is in a non-compressed state, writing the fifth data in the compressed state to the memory by the LLC.

29. The method of any of claims 17-28, wherein, The method further comprises: receiving a request for reading and rewriting sixth data in the LLC; if the sixth data satisfies a preset condition, determining whether seventh data is in the LLC or the other LLC, the seventh data being data physically adjacent to the sixth data in the memory; if the seventh data is in a target LLC, obtaining the seventh data from the target LLC; determining a compression state of the sixth data and the seventh data written to the memory based on a compression state of the seventh data; writing the sixth data and the seventh data to the memory based on the determined compression state.

30. An electronic device, comprising: comprises: the processing apparatus and the memory according to any one of claims 1-16.

31. A computer readable storage medium, characterized in that, The computer readable medium is configured to store program codes, which are executed by an electronic device to implement the method according to any one of claims 17-29.

32. A computer program, characterized in that, The computer program comprises instructions, which, when executed by an electronic device, cause the electronic device to perform the method according to any one of claims 17-29.

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