Pin diode, preparation method therefor, and electronic apparatus

Abstract

The present application relates to the technical field of electronic devices, and provides a PIN diode, a preparation method therefor, and an electronic device, which can solve the problems of low carrier injection efficiency and high forward resistance of existing PIN diodes. The PIN diode in the present application comprises: a base substrate; an active layer which is arranged on the base substrate, wherein the active layer comprises a P-type semiconductor, an I-type semiconductor and an N-type semiconductor which are sequentially arranged, and at least two of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor have different polysilicon grain sizes. The present application can be used for improving the carrier injection efficiency of PIN diodes and reducing the forward resistance of PIN diodes.

Description

PIN diode, preparation method thereof and electronic device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of electronic devices, and particularly relates to a PIN diode, a preparation method thereof and an electronic device. BACKGROUND

[0002] PIN diodes have been widely used in the fields of photoelectric, microwave and power semiconductor devices due to their strong electric conduction modulation effect and high power resistance. Thin film PIN diodes prepared based on glass-based semiconductor technology can further reduce the manufacturing cost of PIN diodes, and can be integrated with other passive devices, thus having great potential in large-area applications such as photoelectric sensing.

[0003] There are two main structures of existing thin film PIN diodes. One is a PIN diode with a vertical structure based on amorphous silicon, and the other is a PIN diode with a horizontal structure based on low-temperature polysilicon (LTPS). However, the amorphous silicon in the prior art has low mobility and a large forward resistance, and is limited by the stress of the glass substrate, so there is an upper limit to its thickness. The low-temperature polysilicon (LTPS) is greatly affected by the grain boundary, resulting in a large number of recombination centers in the material, which also limits the further reduction of the intrinsic semiconductor (I-type semiconductor) resistance. Secondly, the PIN diodes in the prior art mostly use homojunctions, so the carrier injection efficiency from the P-type semiconductor / N-type semiconductor to the I-type semiconductor is low. Thirdly, the carriers of the P-type semiconductor / N-type semiconductor are limited by the grain boundary scattering, which also makes the series resistance of the P-type semiconductor / N-type semiconductor large. Therefore, it is essential to develop a thin film PIN diode with a low-resistance I-type semiconductor, high carrier injection efficiency and low series resistance for reducing the overall forward resistance and device application. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a PIN diode with expanded grain size, reduced grain boundary effect and high carrier injection efficiency, as well as a preparation method thereof and an electronic device.

[0005] In a first aspect, the technical solution adopted to solve the technical problems of the present application is a PIN diode, comprising:

[0006] a substrate substrate;

[0007] an active layer disposed on the substrate substrate, the active layer comprising a P-type semiconductor, an I-type semiconductor and an N-type semiconductor disposed in sequence; wherein

[0008] The P-type semiconductor, the I-type semiconductor and the N-type semiconductor have different polycrystalline grain sizes in at least two of them.

[0009] In some embodiments, the P-type semiconductor, the I-type semiconductor and the N-type semiconductor include two polysilicon grain sizes among the three, the polysilicon grain size of the P-type semiconductor is the same as the polysilicon grain size of the N-type semiconductor.

[0010] In some embodiments, the polysilicon grain size of the P-type semiconductor and the polysilicon grain size of the N-type semiconductor are smaller than the polysilicon grain size of the I-type semiconductor.

[0011] The PIN diode further includes a first insulating pattern and a second insulating pattern arranged at intervals, arranged on a side of the active layer away from the substrate substrate;

[0012] The first insulating pattern covers the P-type semiconductor in the orthographic projection of the substrate substrate.

[0013] The second insulating pattern covers the N-type semiconductor in the orthographic projection of the substrate substrate.

[0014] In some embodiments, the polysilicon grain size of the P-type semiconductor and the polysilicon grain size of the N-type semiconductor are larger than the polysilicon grain size of the I-type semiconductor.

[0015] The PIN diode further includes a third insulating pattern arranged on a side of the active layer away from the substrate substrate,

[0016] The third insulating pattern covers the I-type semiconductor in the orthographic projection of the substrate substrate.

[0017] In some embodiments, the P-type semiconductor, the I-type semiconductor and the N-type semiconductor include two polysilicon grain sizes among the three.

[0018] The polysilicon grain size of any one of the N-type semiconductor and the P-type semiconductor is the same as the polysilicon grain size of the I-type semiconductor.

[0019] In some embodiments, the polysilicon grain size of the N-type semiconductor is the same as the polysilicon grain size of the I-type semiconductor, and is larger than the polysilicon grain size of the P-type semiconductor.

[0020] The PIN diode further includes a fourth insulating pattern arranged on a side of the active layer away from the substrate substrate, the fourth insulating pattern covers the P-type semiconductor in the orthographic projection of the substrate substrate.

[0021] In some embodiments, the polysilicon grain size of the P-type semiconductor is the same as the polysilicon grain size of the I-type semiconductor, and is larger than the polysilicon grain size of the N-type semiconductor.

[0022] The PIN diode further includes a fifth insulating pattern disposed on a side of the active layer facing away from the substrate substrate, the fifth insulating pattern covering the N-type semiconductor in the orthographic projection of the substrate substrate.

[0023] In some embodiments, the PIN diode further includes a passivation layer, a first electrode and a second electrode disposed on a side of the active layer facing away from the substrate substrate;

[0024] The first electrode is electrically connected with the P-type semiconductor through a first via hole penetrating at least the passivation layer;

[0025] The second electrode is electrically connected with the N-type semiconductor through a second via hole penetrating at least the passivation layer.

[0026] In a second aspect, the embodiments of the present disclosure further provide a preparation method of a PIN diode, wherein the method comprises:

[0027] providing a substrate substrate;

[0028] forming an active layer on the substrate substrate, the active layer including a P-type semiconductor, an I-type semiconductor and an N-type semiconductor disposed in sequence along a first direction; wherein at least one of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor includes a polysilicon pattern, and the other includes an epitaxial layer; the polysilicon grain size of the epitaxial layer is greater than the polysilicon grain size in the polysilicon pattern;

[0029] wherein forming an active layer on the substrate substrate comprises:

[0030] forming the polysilicon pattern on the substrate substrate by a patterning process;

[0031] extending the sidewall of the polysilicon pattern along the first direction by an epitaxial process to obtain the epitaxial layer.

[0032] In some embodiments, two of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor include a polysilicon pattern, and the other includes an epitaxial layer; and the P-type semiconductor and the N-type semiconductor both include a polysilicon pattern, which are a first polysilicon pattern corresponding to the P-type semiconductor and a second polysilicon pattern corresponding to the N-type semiconductor, respectively; and the I-type semiconductor includes an epitaxial layer.

[0033] forming an active layer on the substrate substrate, specifically comprising:

[0034] forming a first polysilicon pattern and a second polysilicon pattern on the substrate substrate by a patterning process;

[0035] The first polysilicon pattern is epitaxied close to the sidewall of the I-type semiconductor by an epitaxial process, and the second polysilicon pattern is epitaxied close to the sidewall of the I-type semiconductor, to obtain the epitaxial layer.

[0036] In some embodiments, one of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprises a polysilicon pattern, and the other two comprise epitaxial layers; and the P-type semiconductor comprises a polysilicon pattern, and the I-type semiconductor and the N-type semiconductor each comprise an epitaxial layer, which are a first epitaxial layer corresponding to the I-type semiconductor and a second epitaxial layer corresponding to the N-type semiconductor, respectively.

[0037] Forming an active layer on the substrate substrate, specifically comprising:

[0038] Forming the polysilicon pattern on the substrate substrate by a patterning process;

[0039] The polysilicon pattern is epitaxied close to the sidewall of the I-type semiconductor by an epitaxial process to form the first epitaxial layer, and the first epitaxial layer is continuously epitaxied along the first direction to form the second epitaxial layer.

[0040] In some embodiments, one of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprises a polysilicon pattern, and the other two comprise epitaxial layers; and the I-type semiconductor comprises a polysilicon pattern, and the P-type semiconductor and the N-type semiconductor each comprise an epitaxial layer, which are a first epitaxial layer corresponding to the P-type semiconductor and a second epitaxial layer corresponding to the N-type semiconductor, respectively.

[0041] Forming an active layer on the substrate substrate, specifically comprising:

[0042] Forming the polysilicon pattern on the substrate substrate by a patterning process;

[0043] The polysilicon pattern is epitaxied close to the sidewall of the P-type semiconductor by an epitaxial process to form the first epitaxial layer, and the polysilicon pattern is epitaxied close to the sidewall of the N-type semiconductor to form the second epitaxial layer.

[0044] In some embodiments, the epitaxial process comprises a liquid phase epitaxial process or a low-temperature gas phase epitaxial process.

[0045] In some embodiments, the polysilicon pattern is formed on the substrate substrate by a patterning process, specifically comprising:

[0046] Forming a first insulating layer on the substrate substrate;

[0047] Depositing amorphous silicon on the first insulating layer and performing crystallization;

[0048] A second insulating layer is formed, and the polysilicon pattern is formed by a patterning process.

[0049] In a third aspect, the embodiments of the present disclosure further provide an electronic device comprising the PIN diode according to any one of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0050] FIG. 1 is a schematic diagram of a PIN diode;

[0051] FIGS. 2-5 are cross-sectional views of four different structures of PIN diodes provided by embodiments of the present disclosure, respectively;

[0052] FIG. 6 is a graph of temperature versus epitaxial rate of a vapor phase epitaxy method provided by an embodiment of the present disclosure;

[0053] FIGS. 7-9 are flowcharts of three methods for manufacturing PIN diodes provided by embodiments of the present disclosure, respectively. DETAILED DESCRIPTION

[0054] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below with reference to the drawings and specific embodiments.

[0055] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person skilled in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not indicate any order, number, or importance, but are only used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not indicate a quantity limitation, but indicate the presence of at least one. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", and the like are only used to indicate relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0056] FIG. 1 is a schematic diagram of a PIN diode. As shown in FIG. 1, the PIN diode includes a substrate 101 and an active layer 102, wherein the active layer 102 is disposed on the substrate 101, and the active layer 102 includes a P-type semiconductor 112, an I-type semiconductor 132, and an N-type semiconductor 122 disposed in sequence.

[0057] The thin-film PIN diode is divided into an amorphous silicon-based PIN diode and a low-temperature polysilicon (LTPS)-based PIN diode. The amorphous silicon-based PIN diode has low electron mobility and poor conductivity. The low-temperature polysilicon (LTPS)-based PIN diode has high conductivity and is generally applicable to small-size panels, such as mobile phones and the like. The PIN diode in the embodiments of the present disclosure refers to a low-temperature polysilicon (LTPS)-based PIN diode.

[0058] The low-temperature polysilicon (LTPS)-based PIN diode refers to a PIN diode whose semiconductor devices (P-type semiconductor 112, I-type semiconductor 132, and N-type semiconductor 122) are made of polysilicon material. The polysilicon is a kind of silicon material with a crystal structure but smaller crystal grains. The polysilicon is composed of many small crystal grains, each of which is a single crystal. The orientations of the crystal grains are random relative to each other, and the crystal grains are separated by grain boundaries. The low-temperature polysilicon is greatly affected by the grain boundaries. Because the low-temperature polysilicon has small crystal grain size and many grain boundaries, many recombination centers are formed in the low-temperature polysilicon material, thereby causing the resistance of the I-type semiconductor 132 in the PIN diode to be large. Meanwhile, the carriers of the P-type semiconductor 112 / N-type semiconductor 122 are limited by the grain boundary scattering, which also causes the series resistance of the P-type semiconductor 112 / N-type semiconductor 122 to be large. In addition, because the PIN diode generally adopts a homojunction, the P-type semiconductor 112, the I-type semiconductor 132, and the N-type semiconductor 122 of the PIN diode are deposited from the same semiconductor material and have the same energy band gap. Therefore, the carrier injection efficiency from the P-type semiconductor 112 / N-type semiconductor 122 to the I-type semiconductor 132 is low.

[0059] In a first aspect, to solve the above problems, the embodiments of the present disclosure provide a PIN diode. FIGS. 2-5 are cross-sectional views of four PIN diodes with different structures provided by the embodiments of the present disclosure.

[0060] As shown in FIGS. 2-5, the PIN diode includes a substrate 101 and an active layer 102. The active layer 102 is disposed on the substrate 101, and the active layer 102 includes a P-type semiconductor 112, an I-type semiconductor 132, and an N-type semiconductor 122 disposed in sequence. At least two of the P-type semiconductor 112, the I-type semiconductor 132, and the N-type semiconductor 122 have different polysilicon grain sizes.

[0061] In some embodiments, the P-type semiconductor 112, the I-type semiconductor 132, and the N-type semiconductor 122 include three polysilicon grain sizes, that is, the polysilicon grain sizes of the three are all different.

[0062] In some embodiments, among the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122, two of the three include polycrystalline silicon grains of the same size.

[0063] Specifically, among the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122, the semiconductor with different polycrystalline silicon grain sizes can adopt semiconductor materials with different energy bandgaps. Among the three, the two adjacent ones with different polycrystalline silicon grain sizes form a lateral double heterojunction structure due to the different energy bandgaps. Carriers are injected from the wide bandgap material to the narrow bandgap material, with a high injection ratio of ~exp(ΔEg / kT), where ΔEg is the bandgap difference. By increasing the carrier injection ratio, the carrier injection efficiency can be improved. Conversely, carriers are injected from the narrow bandgap material to the wide bandgap material, in which case the narrow bandgap material has a higher carrier mobility, which can reduce the series resistance of the PIN diode and the forward resistance of the PIN diode in the prior art.

[0064] In addition, the polycrystalline silicon grain size affects the grain boundary of the polycrystalline silicon. The larger the size of the polycrystalline silicon grains, the closer the polycrystalline silicon is to the quality of single crystal silicon (the lattice arrangement of single crystal is continuous and unchanging, without grain boundaries). Therefore, among the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122, for one or both of the ones with larger polycrystalline silicon grain size, the grain boundary of the polycrystalline silicon is reduced, resulting in a reduction in the recombination center in the material, which can reduce the resistance of the corresponding semiconductor, and further reduce the impact of the grain boundary on the PIN diode.

[0065] The PIN diode provided by the embodiments of the present disclosure reduces the forward resistance of the PIN diode by setting the polycrystalline silicon grains of at least two of the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 to different grain sizes.

[0066] It can be understood that, among the PIN diode provided by the embodiments of the present disclosure, among the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122, the polycrystalline silicon grain sizes of any two of the three can be the same, which can be divided into two cases.

[0067] In some embodiments, the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 include two polysilicon grain sizes, and the polysilicon grain size of the P-type semiconductor 112 is the same as that of the N-type semiconductor 122. In other words, in the embodiments of the present disclosure, the polysilicon grain size of the P-type semiconductor 112 is different from that of the I-type semiconductor 132, and the polysilicon grain size of the N-type semiconductor 122 is also different from that of the I-type semiconductor 132. In this way, the P-type semiconductor 112 and the N-type semiconductor 122 can use semiconductor materials with different energy band gaps from the I-type semiconductor 132, thereby increasing the injection ratio of carriers or improving the mobility of carriers, and thus reducing the forward resistance of the PIN diode.

[0068] In some embodiments, the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 include two polysilicon grain sizes, and the polysilicon grain size of the N-type semiconductor 122 is different from that of the P-type semiconductor 132. In other words, the polysilicon grain size of the I-type semiconductor 132 is the same as that of one of the P-type semiconductor 112 and the N-type semiconductor 122. In this way, one of the P-type semiconductor 112 and the N-type semiconductor 122 can use semiconductor materials with different energy band gaps from the I-type semiconductor 132, thereby increasing the injection ratio of carriers or improving the mobility of carriers, and thus reducing the forward resistance of the PIN diode.

[0069] It can also be understood that, in the PIN diode provided by the embodiments of the present disclosure, the polysilicon grain size of any two of the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 is the same, which can be further divided into four cases, and the structure of the PIN diode will be described in detail below by taking four embodiments as examples.

[0070] First example: as shown in FIG. 2, the present disclosure provides a PIN diode, which includes a substrate 101 and an active layer 102, the active layer 102 is arranged on the substrate 101, and the active layer 102 includes a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence. The polysilicon grain size of the P-type semiconductor 112 and the polysilicon grain size of the N-type semiconductor 122 are smaller than the polysilicon grain size of the I-type semiconductor 132.

[0071] Specifically, the polysilicon size in the I-type semiconductor 132 is large size polysilicon grain relative to the P-type semiconductor 112 and the N-type semiconductor 122. In one aspect, the I-type semiconductor 132 forms a lateral double heterostructure with the P-type semiconductor 112 and the N-type semiconductor 122 respectively (the band gap of polysilicon is between 1.1-1.5eV, the closer the polysilicon is to the single crystal, the narrower the band gap). Therefore, when the carrier injection is performed from the P-type semiconductor 112 and the N-type semiconductor 122 to the I-type semiconductor 132 respectively, the carrier is injected from a wide band gap material to a narrow band gap material, with a high injection ratio ~exp(ΔEg / kT), where ΔEg is the band gap difference, and the injection efficiency can be improved by increasing the injection ratio. On the other hand, the I-type semiconductor 132 has a large size of polysilicon grain, which greatly reduces the impact of the grain boundary, reduces the recombination center density of the I-type semiconductor 132, and reduces the resistance of the I-type semiconductor 132, so that a PIN diode with low forward resistance can be obtained.

[0072] In some embodiments, the PIN diode not only includes the substrate substrate 102 and the active layer 102, but also includes a first insulating pattern 11 and a second insulating pattern 12 arranged in a spaced manner, the first insulating pattern 11 and the second insulating pattern 12 are arranged on the side of the active layer 102 away from the substrate substrate 101; and the first insulating pattern 11 covers the P-type semiconductor 112 in the orthographic projection of the substrate substrate 101; the second insulating pattern 12 covers the N-type semiconductor 122 in the orthographic projection of the substrate substrate 101.

[0073] Specifically, the materials of the first insulating pattern 11 and the second insulating pattern 12 are insulating materials, which can be SiOx, SiNx or other insulating materials. In addition, the I-type semiconductor 132 can be obtained by lateral epitaxy from the sidewall of the polysilicon pattern of the P-type semiconductor 112 and the N-type semiconductor 122. During the lateral epitaxy process, the epitaxial reaction material (semiconductor material) of the I-type semiconductor 132 needs to be in contact with the interface of the P-type semiconductor 112 and the N-type semiconductor 122. Therefore, no insulating pattern needs to be arranged on the I-type semiconductor 132, and only insulating patterns need to be arranged on the P-type semiconductor 112 and the N-type semiconductor 122.

[0074] In some embodiments, the PIN diode not only includes the substrate substrate 101 and the active layer 102, but also includes a passivation layer 103, a first electrode 1 and a second electrode 2 arranged on the side of the active layer 102 away from the substrate substrate 101. Among them, the first electrode 1 is electrically connected with the P-type semiconductor 112 through at least a first via hole penetrating through the passivation layer 103; the second electrode 2 is electrically connected with the N-type semiconductor 122 through at least a second via hole penetrating through the passivation layer 103.

[0075] Specifically, as shown in FIG. 2, the first electrode is electrically connected with the P-type semiconductor 112 through a first via hole penetrating through the passivation layer 103 and the first insulating pattern 11, and the second electrode 2 is electrically connected with the N-type semiconductor 122 through a second via hole penetrating through the passivation layer 103 and the second insulating pattern 12.

[0076] A second example: as shown in FIG. 3, the embodiment of the present disclosure provides a PIN diode, which includes a substrate substrate 101 and an active layer 102, the active layer 102 is arranged on the substrate substrate 101, and the active layer 102 includes a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence. Wherein, the polysilicon grain size of the P-type semiconductor 112 and the polysilicon grain size of the N-type semiconductor 122 are larger than the polysilicon grain size of the I-type semiconductor 132.

[0077] Specifically, the polysilicon size in the P-type semiconductor 112 and the N-type semiconductor 122 is large-size polysilicon grain relative to the I-type semiconductor 132. Therefore, when the carriers are injected from the P-type semiconductor 112 and the N-type semiconductor 122 to the I-type semiconductor 132, the carriers are injected from the narrow band gap material to the wide band gap material, in this case, the narrow band gap material has a higher carrier mobility, thus reducing the series resistance of the PIN diode, and further reducing the forward resistance of the PIN diode compared with the PIN diode in the prior art.

[0078] In some embodiments, the PIN diode not only includes the substrate substrate 101 and the active layer 102, but also includes a third insulating pattern 13 arranged on the side of the active layer 102 away from the substrate substrate 101. Wherein, the third insulating pattern 13 covers the I-type semiconductor 132 in the orthographic projection of the substrate substrate 101.

[0079] Specifically, the third insulating pattern 13 is made of insulating material, for example, can be SiOx, SiNx or other insulating material. In addition, the P-type semiconductor 112 and the N-type semiconductor 122 can be obtained by lateral epitaxy from the sidewall of the polysilicon pattern of the I-type semiconductor 132, and the epitaxial reaction material of the P-type semiconductor 112 and the N-type semiconductor needs to be in contact with the interface of the I-type semiconductor 132 in the process of lateral epitaxy. Therefore, the P-type semiconductor 112 and the N-type semiconductor 122 do not need to be provided with an insulating pattern.

[0080] In some embodiments, the PIN diode not only includes the substrate substrate 101 and the active layer 102, but also includes a passivation layer 103, a first electrode 1 and a second electrode 2 arranged on the side of the active layer 102 away from the substrate substrate 101. Wherein, the first electrode 1 is electrically connected with the P-type semiconductor 112 through at least a first via hole penetrating through the passivation layer 103; the second electrode 2 is electrically connected with the N-type semiconductor 122 through at least a second via hole penetrating through the passivation layer 103.

[0081] Specifically, as shown in FIG. 3, the first electrode is electrically connected with the P-type semiconductor 112 through a first via hole penetrating through the passivation layer 103, and the second electrode 2 is electrically connected with the N-type semiconductor 122 through a second via hole penetrating through the passivation layer 103.

[0082] A third example: as shown in FIG. 4, the PIN diode provided by the embodiment of the present disclosure includes a substrate substrate 101 and an active layer 102, the active layer 102 is arranged on the substrate substrate 101, and the active layer 102 includes a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence. Among them, the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 include two kinds of polycrystalline silicon grain sizes, the polycrystalline silicon grain size of the N-type semiconductor 122 is the same as that of the I-type semiconductor 132, and is greater than that of the P-type semiconductor 112.

[0083] Specifically, the polycrystalline silicon grains of the N-type semiconductor 122 and the I-type semiconductor 132 are large-size grains, so that the influence of the grain boundary on the N-type semiconductor 122 and the I-type semiconductor 132 is greatly reduced, the recombination center density of the N-type semiconductor 122 and the I-type semiconductor 132 is reduced, and thus the resistance of the N-type semiconductor 122 and the I-type semiconductor 132 is reduced, thereby further obtaining a PIN diode with low forward resistance.

[0084] In some embodiments, the PIN diode not only includes the substrate substrate 101 and the active layer 102, but also includes a fourth insulating pattern 14 arranged on the side of the active layer 102 away from the substrate substrate 101, and the fourth insulating pattern 14 covers the P-type semiconductor 112 in the orthographic projection of the substrate substrate 101.

[0085] Specifically, the fourth insulating pattern 14 is made of an insulating material, for example, SiOx, SiNx or other insulating materials. In addition, the I-type semiconductor 132 and the N-type semiconductor 122 can be obtained by lateral epitaxy from the sidewall of the polycrystalline silicon pattern of the P-type semiconductor 112, and the epitaxial reaction material of the I-type semiconductor 132 and the N-type semiconductor needs to be in contact with the interface of the P-type semiconductor 112 in the lateral epitaxy process. Therefore, the insulating pattern does not need to be arranged on the I-type semiconductor 132 and the N-type semiconductor 122.

[0086] In some embodiments, the PIN diode not only includes the substrate substrate 101 and the active layer 102, but also includes a passivation layer 103, a first electrode 1 and a second electrode 2 arranged on the side of the active layer 102 away from the substrate substrate 101. Among them, the first electrode 1 is electrically connected with the P-type semiconductor 112 through at least a first via hole penetrating through the passivation layer 103; and the second electrode 2 is electrically connected with the N-type semiconductor 122 through at least a second via hole penetrating through the passivation layer 103.

[0087] Specifically, as shown in FIG. 4, the first electrode is electrically connected with the P-type semiconductor 112 through a first via hole penetrating through the passivation layer 103 and the fourth insulating pattern 14, and the second electrode 2 is electrically connected with the N-type semiconductor 122 through a second via hole penetrating through the passivation layer 103.

[0088] The fourth example: as shown in FIG. 5, the PIN diode provided by the embodiment of the present disclosure includes a substrate substrate 101 and an active layer 102, the active layer 102 is arranged on the substrate substrate 101, and the active layer 102 includes a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence. Wherein, the polysilicon grain size of the P-type semiconductor 112 is the same as the polysilicon grain size of the I-type semiconductor 132, and is greater than the polysilicon grain size of the N-type semiconductor 122.

[0089] Specifically, the embodiment of the present disclosure is different from the above-mentioned embodiment 3 only in that the P-type semiconductor 112 is the same as the polysilicon grain size of the I-type semiconductor 132, and the others are the same. The principle and effect are the same as the corresponding principle and effect of embodiment 3, which will not be repeated here.

[0090] In some embodiments, the PIN diode not only includes the substrate substrate 101 and the active layer 102, but also includes a fifth insulating pattern 15 arranged on the side of the active layer 102 away from the substrate substrate 101, and the fifth insulating pattern 15 covers the N-type semiconductor 122 in the orthographic projection of the substrate substrate 101.

[0091] Specifically, the fifth insulating pattern 15 is made of insulating material, for example, can be SiO, SiN or other insulating material. In addition, the I-type semiconductor 132 and the P-type semiconductor 112 can be obtained by lateral epitaxy from the sidewall of the polysilicon pattern of the N-type semiconductor 122 through epitaxy technology, and the epitaxial reaction material of the I-type semiconductor 132 and the P-type semiconductor 112 needs to contact the interface of the N-type semiconductor 122 in the process of lateral epitaxy. Therefore, the insulating pattern does not need to be arranged on the I-type semiconductor 132 and the P-type semiconductor 112.

[0092] In some embodiments, the PIN diode not only includes the substrate substrate 101 and the active layer 102, but also includes a passivation layer 103, a first electrode 1 and a second electrode 2 arranged on the side of the active layer 102 away from the substrate substrate 101. Wherein, the first electrode 1 is electrically connected with the P-type semiconductor 112 through at least a first via hole penetrating through the passivation layer 103; the second electrode 2 is electrically connected with the N-type semiconductor 122 through at least a second via hole penetrating through the passivation layer 103.

[0093] Specifically, as shown in FIG. 5, the first electrode is electrically connected with the P-type semiconductor 112 through a first via hole penetrating through the passivation layer 103, and the second electrode 2 is electrically connected with the N-type semiconductor 122 through a second via hole penetrating through the passivation layer 103 and the fifth insulating pattern 15.

[0094] In a second aspect, based on the same inventive concept, the disclosure further provides a preparation method of a PIN diode. FIGS. 7-9 are flowcharts of three preparation methods of a PIN diode provided by the disclosure.

[0095] The first example: the disclosure further provides a preparation method of a PIN diode, including the following steps:

[0096] S601, providing a substrate 101.

[0097] Specifically, the substrate 101 can be a glass substrate, and the thickness thereof can be about 0.5 mm. The substrate 101 is cleaned through a standard cleaning process to remove impurities and organic matter on the surface of the substrate 101, so as to ensure the cleanliness of the substrate.

[0098] S602, forming an active layer 102 on the substrate 101.

[0099] The active layer 102 includes a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence along a first direction; at least one of the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 includes a polysilicon pattern, and the other includes an epitaxial layer; the polysilicon grain size of the epitaxial layer is larger than that of the polysilicon pattern.

[0100] The step S602 of forming the active layer 102 on the substrate 101 specifically includes:

[0101] S6021, preparing a first insulating layer 104 on the substrate 101 by chemical vapor deposition (PECVD). The material of the first insulating layer 104 is SiNx or SiO2, the thickness of the SiNx is 300-500 nm, and the thickness of the SiO2 is 10-100 nm.

[0102] S6022, depositing amorphous silicon a-Si on the first insulating layer 104 by PECVD. The thickness of the amorphous silicon a-Si is 30-70 nm.

[0103] S6023, removing H of the a-Si by high-temperature annealing, and the temperature is 400-600℃.

[0104] S6024, crystallize the a-Si using excimer laser anneal (ELA) to obtain a polysilicon layer 107, and deposit a second insulating layer 106 such as SiNx or SiOx using PECVD, with a thickness of 100-300 nm.

[0105] S6025, prepare a polysilicon pattern.

[0106] Specifically, the polysilicon pattern covering the first insulating layer 104 is formed by photolithography, dry etching, and a stripping process, and the insulating pattern covering the polysilicon pattern is formed.

[0107] S6026, prepare an epitaxial layer 108 based on an epitaxial process.

[0108] Specifically, the epitaxial process refers to depositing a thin crystalline silicon layer on the basis of a substrate crystalline silicon layer. The newly deposited crystalline silicon layer is referred to as an epitaxial layer, and the process of forming the epitaxial layer is epitaxial growth. The epitaxial growth refers to a method of generating a required epitaxial layer on the basis of the deposited crystalline silicon under certain conditions. In the embodiment of the present disclosure, the polysilicon pattern layer is the substrate crystalline silicon layer. The epitaxial layer and the substrate crystalline silicon layer (polysilicon pattern layer) can be the same semiconductor material or different semiconductor materials, which can be selected according to actual needs.

[0109] In the embodiment of the present disclosure, the epitaxial layer 108 can be selected to be a semiconductor material different from the substrate crystalline silicon layer (polysilicon pattern layer 102). In this way, a lateral heterojunction structure can be formed between the semiconductor corresponding to the epitaxial layer 108 and the substrate crystalline silicon layer (polysilicon pattern layer 108), which improves the injection efficiency or migration efficiency of carriers. Meanwhile, the polysilicon size of the epitaxial layer is large, which can reduce the resistance of the semiconductor corresponding to the epitaxial layer, so that the PIN diode obtains a lower forward voltage.

[0110] The specific process of S6026, preparing an epitaxial layer based on an epitaxial process, is as follows: using a silicon etching solution (acidic solution such as HF+HNO3 or KOH alkaline solution) to wetly etch the sidewall of the polysilicon pattern along the first direction, and using an epitaxial process to epitaxially grow from the sidewall of the polysilicon pattern to finally form the epitaxial layer 108 with large-size grains.

[0111] In some embodiments, the epitaxial process includes a liquid phase epitaxy process and a low-temperature vapor phase epitaxy process. In the liquid phase epitaxy process, a typical method is an immersion method. In the liquid phase epitaxy process, a silicon source is generally an Au-based alloy / Si, such as Au / Bi / Si or Au / Pb / Si, and the minimum epitaxial temperature can be as low as 284°C. In addition, in the liquid phase epitaxy process, the silicon source can also be an Ag-based alloy, such as Ag / Bi, Ag / Sn, Ag / Sb, and the silicon epitaxial growth can be performed at a temperature above 500°C and below 700°C. In the low-temperature vapor phase epitaxy process, a silicon source is generally SiH4, and the growth temperature is 650°C.

[0112] S6027, forming a PIN junction.

[0113] Specifically, by photolithography, an N-type semiconductor 122 shielding layer is formed to expose the P-type semiconductor 112, and boron ion implantation is performed. Photolithography is performed again to form a P-type semiconductor 112 shielding layer to expose the N-type semiconductor 122, and phosphorus ion implantation is performed. Finally, a rapid thermal annealing process is performed to activate the ion doping of the P-type semiconductor 112 and the N-type semiconductor 122, and a PIN junction is formed.

[0114] S603, forming a passivation layer 103, a first electrode 1, and a second electrode 2.

[0115] Specifically, the passivation layer 103 is formed on the active layer 102, and the first via and the second via are formed by a via process, and the first electrode 1 and the second electrode 2 are formed, so that the first electrode 1 is electrically connected to the P-type semiconductor 112 through the first via, and the second electrode 2 is electrically connected to the N-type semiconductor 122 through the second via.

[0116] It should be noted that in the above step S602, the polysilicon pattern formed can correspond to any one or two of the P-type semiconductor 112, the I-type semiconductor 132, and the N-type semiconductor 122, and the formation process of the epitaxial layer 108 in S6026 is also different for different cases. The preparation process of the PIN diode will be described in detail below through specific embodiments. Among them, FIG. 6 is a curve diagram of the temperature and epitaxial rate of a vapor phase epitaxy method provided by an embodiment of the present disclosure, L1 indicates that the silicon source is SiH4, L2 indicates that the silicon source is SiH2Cl2, L3 indicates that the silicon source is SiHCl3, and L4 indicates that the silicon source is SiCl4.

[0117] The second example: the present disclosure provides a preparation method of a PIN diode, wherein the method can be used to prepare the PIN diode as shown in FIG. 2, as shown in FIG. 7, the preparation method includes the following steps:

[0118] S601, providing a substrate 101.

[0119] S602. Forming an active layer 102 on the substrate 101.

[0120] The active layer 102 comprises a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence along the first direction, wherein two of the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 comprise a polysilicon pattern, and the other one comprises an epitaxial layer 108. The P-type semiconductor 112 and the N-type semiconductor 122 each comprise a polysilicon pattern, which are a first polysilicon pattern 1021 corresponding to the P-type semiconductor 112 and a second polysilicon pattern 1022 corresponding to the N-type semiconductor 122, respectively, and the I-type semiconductor 132 comprises the epitaxial layer 108.

[0121] The step S602 of forming the active layer 102 on the substrate 101 comprises the following steps.

[0122] S6021. Depositing a first insulating layer 104 on the substrate 101 by PECVD. The material of the first insulating layer 104 is SiNx or SiO2, the thickness of the SiNx is 300-500 nm, and the thickness of the SiO2 is 10-100 nm.

[0123] S6022. Depositing amorphous silicon a-Si on the first insulating layer 104 by PECVD. The thickness of the amorphous silicon a-Si is 30-70 nm.

[0124] S6023. Removing H of the a-Si by high-temperature annealing at a temperature of 400-600 ℃.

[0125] S6024. Crystallizing the a-Si by ELA to obtain a polysilicon layer 107, and depositing a second insulating layer 106 such as SiNx or SiOx by PECVD, the thickness of the second insulating layer 106 is 100-300 nm.

[0126] S6025. Preparing a polysilicon pattern. Specifically, the polysilicon pattern and an insulating pattern covering the first insulating layer 104 are formed by photolithography, dry etching and stripping process. The polysilicon pattern comprises a first polysilicon pattern 1021 corresponding to the P-type semiconductor 112 and a second polysilicon pattern 1022 corresponding to the N-type semiconductor 122. The insulating pattern comprises a first insulating pattern 11 covering the first polysilicon pattern 1021 and a second insulating pattern 12 covering the second polysilicon pattern 1022.

[0127] S6026. Preparing an epitaxial layer 108 based on an epitaxial process.

[0128] Specifically, the first polysilicon pattern 1021 is wetly etched laterally using a silicon etching liquid (an acidic solution such as HF+HNO3 or a KOH alkaline solution) to approach the sidewall of the I-type semiconductor 132, and the second polysilicon pattern 1022 is wetly etched laterally using a silicon etching liquid to approach the sidewall of the I-type semiconductor 132, and the sidewall of the first polysilicon pattern 1021 and the sidewall of the second polysilicon pattern 1022 are respectively epitaxied by an epitaxial process to obtain an epitaxial layer 108, and finally a polysilicon of the I-type semiconductor 132 of a large-size crystal grain is formed.

[0129] As shown in FIG. 6, as using a vapor phase epitaxial process, a silicon source uses SiH4, a growth temperature is 650 degrees Celsius, and a rate is about 0.025 um / min. The length of the I-type semiconductor 132 along the first direction is about 2 um, and then a growth time is about 80 min.

[0130] S6027, forming a PIN junction.

[0131] Specifically, by photolithography, an N-type semiconductor 122 shielding layer is formed to expose the P-type semiconductor 112, and boron ion implantation is performed. Again by photolithography, a P-type semiconductor 112 shielding layer is formed to expose the N-type semiconductor 122, and phosphorus ion implantation is performed. Finally, a rapid thermal annealing process is performed to complete ion doping activation of the P-type semiconductor 112 and the N-type semiconductor 122, and a PIN junction is formed.

[0132] S603, forming a passivation layer 103, a first electrode 1 and a second electrode 2.

[0133] Specifically, the passivation layer 103 is formed on the active layer 102, and the first via and the second via are formed by a via process, and the first electrode 1 and the second electrode 2 are formed, so that the first electrode 1 is electrically connected to the P-type semiconductor 112 through the first via, and the second electrode 2 is electrically connected to the N-type semiconductor 122 through the second via.

[0134] Other details in the embodiments of the present disclosure are the same as those of the above-mentioned embodiment 5, which will not be repeated here.

[0135] The preparation method provided by the embodiments of the present disclosure forms the epitaxial layer 108 corresponding to the I-type semiconductor 132 through the re-etching and low-temperature lateral epitaxy of the first polysilicon pattern 1021 corresponding to the P-type semiconductor 112 and the second polysilicon pattern 1022 corresponding to the N-type semiconductor 122, and finally the polysilicon of the I-type semiconductor 132 close to single-crystal quality is obtained, and a lateral double heterojunction structure is formed. The lateral double heterojunction structure enhances the carrier injection efficiency of the P-type semiconductor 112 and the N-type semiconductor 122 to the I-type semiconductor 132, and the injection ratio is exp(ΔEg / kT). Wherein, ΔEg is the band gap difference. At the same time, the lateral growth of the epitaxial layer in the I-type semiconductor 132 is obtained by the epitaxial process, the polysilicon grain size in the I-type semiconductor 132 is expanded, the influence of the grain boundary is reduced, and thus a low forward resistance is obtained.

[0136] The third example: the embodiments of the present disclosure also provide a preparation method of a PIN diode, wherein the preparation method can be applied to prepare the PIN diode as shown in FIG. 4, as shown in FIG. 8, the preparation method comprises the following steps:

[0137] S601, providing a substrate 101.

[0138] S602, forming an active layer 102 on the substrate 101.

[0139] The active layer 102 comprises a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence along a first direction; wherein one of the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 comprises a polysilicon pattern, and the other two comprise an epitaxial layer 108. Wherein the P-type semiconductor 112 comprises a polysilicon pattern, and the N-type semiconductor 122 and the I-type semiconductor 132 comprise an epitaxial layer 108, which are a first epitaxial layer 1081 corresponding to the N-type semiconductor 112 and a second epitaxial layer 1082 corresponding to the I-type semiconductor 132, respectively.

[0140] Wherein, the step S602, forming an active layer 102 on the substrate 101, specifically comprises:

[0141] S6021, preparing a first insulating layer 104 on the substrate 101 by chemical vapor deposition (PECVD). Wherein the material of the first insulating layer 104 is SiNx, SiO2, the thickness of SiNx is 300nm-500nm, and the thickness of SiO2 is 10nm-100nm.

[0142] S6022, depositing amorphous silicon a-Si on the first insulating layer 104 by PECVD. Wherein the thickness of amorphous silicon a-Si is 30nm-70nm.

[0143] S6023, remove H of a-Si by high temperature annealing, temperature is 400-600℃.

[0144] S6024, use excimer laser annealing (ELA) to crystallize a-Si to obtain a polysilicon layer 107, and use PECVD to deposit SiNx or SiOx to obtain a second insulating layer 106, thickness is 100-300nm.

[0145] S6025, prepare a polysilicon pattern.

[0146] Specifically, by photolithography, dry etching, stripping process, a polysilicon pattern covering the first insulating layer 104 and corresponding to the P-type semiconductor 112 is formed, which is a third polysilicon pattern 1023, and a third insulating pattern 13 covering the third polysilicon pattern 1023 is formed.

[0147] S6026, prepare an epitaxial layer 108 based on epitaxial process.

[0148] Specifically, using a silicon etching solution (acidic solution such as HF+HNO3 or KOH alkaline solution) for wet lateral etching of the third polysilicon pattern 1023 close to the sidewall of the I-type semiconductor 132, and epitaxial growth of the third polysilicon pattern 1023 close to the sidewall of the I-type semiconductor 132 by epitaxial process to obtain a first epitaxial layer 1081, and continue epitaxial growth in the first direction to form a second epitaxial layer 1082, and finally form a large-size grain I-type semiconductor 132 and a polysilicon of N-type semiconductor.

[0149] As shown in FIG. 6, as using a vapor phase epitaxial process, the silicon source uses SiH4, the growth temperature is 650 degrees Celsius, and the rate is about 0.025um / min. The length of the I-type semiconductor 132 in the first direction is about 2um, so the growth time is about 160min. The I-type semiconductor 132 in the embodiment of the present disclosure is formed only by the P-type semiconductor 112 through the epitaxial process, compared with the I-type semiconductor 132 in the embodiment 6 which is formed by both the P-type semiconductor 112 and the N-type semiconductor 122 through the epitaxial process, the growth time required to form the I-type semiconductor 132 is doubled.

[0150] S6027, form a PIN junction.

[0151] Specifically, by photolithography, an N-type semiconductor 122 shielding layer is formed to expose the P-type semiconductor 112, and boron ion implantation is performed. Again, photolithography is performed to form a P-type semiconductor 112 shielding layer to expose the N-type semiconductor 122, and phosphorus ion implantation is performed. Finally, a rapid thermal annealing process is performed to complete the activation of ion doping of the P-type semiconductor 112 and the N-type semiconductor 122, and a PIN junction is formed.

[0152] S603, forming the passivation layer 103, the first electrode 1 and the second electrode 2.

[0153] Specifically, the passivation layer 105 is formed on the active layer 102, and the first via and the second via are formed by a via process, and the first electrode 1 and the second electrode 2 are formed, so that the first electrode 1 is electrically connected to the P-type semiconductor 112 through the first via, and the second electrode 2 is electrically connected to the N-type semiconductor 122 through the second via.

[0154] Other details in the embodiments of the present disclosure are the same as those in the above-mentioned embodiment 5, which will not be repeated here.

[0155] The preparation method of the PIN diode provided in the embodiments of the present disclosure is different from the second example in that the polysilicon in the N-type semiconductor 122 is also prepared by an epitaxy process, and the remaining process procedures are similar.

[0156] In the preparation method provided in the embodiments of the present disclosure, the polysilicon of the I-type semiconductor 132 and the N-type semiconductor 122 close to single crystal quality can be obtained by re-etching the third polysilicon pattern 1023 corresponding to the P-type semiconductor 112 and low-temperature lateral epitaxy, and a lateral heterojunction structure is formed at the junction of the P-type semiconductor 112 and the I-type semiconductor 132. Since the size of the polysilicon of the I-type semiconductor 132 is larger than that of the single crystal silicon of the P-type semiconductor 112, the carrier is injected from the wide-bandgap material to the narrow-bandgap material, which enhances the carrier injection efficiency from the P-type semiconductor 112 to the I-type semiconductor 132. At the same time, the lateral growth of the epitaxial layer in the I-type semiconductor 132 and the N-type semiconductor 122 is obtained by the epitaxy process, which expands the size of the polysilicon grains in the I-type semiconductor 132 and the N-type semiconductor 122, and reduces the influence of the grain boundary. On the one hand, the resistance of the I-type semiconductor 132 is reduced, and on the other hand, the series resistance of the P-type semiconductor and the N-type semiconductor 122 is also reduced, thereby obtaining a low forward resistance.

[0157] In addition, it should be noted that the process and principle of preparing the PIN diode as shown in FIG. 5 are similar to those in the embodiments of the present disclosure, and the only difference is that the polysilicon pattern exists in the N-type semiconductor 122. The process of preparing the PIN diode as shown in FIG. 5 will not be repeated here.

[0158] The fourth example: the embodiments of the present disclosure also provide a preparation method of a PIN diode, wherein the preparation method can be used to prepare the PIN diode as shown in FIG. 3, as shown in FIG. 9, the preparation method comprises the following steps:

[0159] S601, providing a substrate 101.

[0160] S602, forming an active layer 102 on the substrate 101.

[0161] The active layer 102 comprises a P-type semiconductor 112, an I-type semiconductor 132 and an N-type semiconductor 122 arranged in sequence along the first direction; wherein one of the P-type semiconductor 112, the I-type semiconductor 132 and the N-type semiconductor 122 comprises a polysilicon pattern, and the other two comprise an epitaxial layer 108. Among them, the I-type semiconductor 132 comprises a polysilicon pattern, and the P-type semiconductor 112 and the N-type semiconductor 122 each comprise an epitaxial layer 108, which are a first epitaxial layer 1081 corresponding to the P-type semiconductor 112 and a second epitaxial layer 1082 corresponding to the N-type semiconductor 122, respectively.

[0162] The step S602 of forming the active layer 102 on the substrate 101 comprises:

[0163] S6021, a first insulating layer 104 is prepared on the substrate 101 by chemical vapor deposition (PECVD). The material of the first insulating layer 104 is SiNx or SiO2, the thickness of SiNx is 300-500 nm, and the thickness of SiO2 is 10-100 nm.

[0164] S6022, amorphous silicon (a-Si) is deposited on the first insulating layer 104 by PECVD. The thickness of the amorphous silicon (a-Si) is 30-70 nm.

[0165] S6023, remove H of a-Si by high temperature annealing, the temperature is 400-600℃.

[0166] S6024, crystallize a-Si using excimer laser annealing (ELA) to obtain a polysilicon layer 107, and deposit SiNx or SiOx using PECVD to obtain a second insulating layer 106 with a thickness of 100-300 nm.

[0167] S6025, prepare a polysilicon pattern.

[0168] Specifically, by photolithography, dry etching, and stripping process, a polysilicon pattern 1024 corresponding to the I-type semiconductor 132 is formed covering the first insulating layer 104, and a fourth insulating layer 14 covering the fourth polysilicon pattern 1024 is formed.

[0169] S6026, prepare an epitaxial layer 108 based on an epitaxial process.

[0170] Specifically, the two sidewalls of the fourth polysilicon pattern 1023 along the first direction are wetly etched using a silicon etching liquid (an acidic solution such as HF+HNO3 or a KOH alkaline solution), and the sidewalls of the fourth polysilicon pattern 1024 close to the P-type semiconductor 112 and the N-type semiconductor 122 are respectively epitaxied by an epitaxial process to obtain a first epitaxial layer 1081 and a second epitaxial layer 1082, and finally the polysilicon of the P-type semiconductor 112 and the polysilicon of the N-type semiconductor 122 of the large-size crystal grain are formed.

[0171] As shown in FIG. 6, as using a vapor phase epitaxial process, a silicon source uses SiH4, a growth temperature is 650 degrees Celsius, and a rate is about 0.025 um / min. The length of the P-type semiconductor 112 and the N-type semiconductor 122 along the first direction is about 2 um, and the growth time is about 80 min.

[0172] S6027, forming a PIN junction.

[0173] Specifically, by photolithography, the N-type semiconductor 122 shielding layer is formed to expose the P-type semiconductor 112, and boron ion implantation is performed. Again by photolithography, the P-type semiconductor 112 shielding layer is formed to expose the N-type semiconductor 122, and phosphorus ion implantation is performed. Finally, a rapid thermal annealing process is performed to complete the ion doping activation of the P-type semiconductor 112 and the N-type semiconductor 122, and a PIN junction is formed.

[0174] S603, forming a passivation layer 103, a first electrode 1 and a second electrode 2.

[0175] Specifically, the passivation layer 103 is formed on the active layer 102, and the first via and the second via are formed by a via process, and the first electrode 1 and the second electrode 2 are formed, so that the first electrode 1 is electrically connected to the P-type semiconductor 112 through the first via, and the second electrode 2 is electrically connected to the N-type semiconductor 122 through the second via.

[0176] Other details in the embodiments of the present disclosure are the same as those of the above-mentioned embodiment 5, which will not be repeated here.

[0177] The preparation method of the PIN diode provided by the embodiments of the present disclosure is different from the second example in that the polysilicon of the P-type semiconductor 112 and the N-type semiconductor 122 in the embodiments of the present disclosure is prepared by epitaxial process from the polysilicon pattern of the I-type semiconductor 132 to both sides, and the rest of the process is similar.

[0178] In the preparation method provided by the embodiments of the present disclosure, the polycrystalline silicon of the P-type semiconductor 112 and the N-type semiconductor 122 close to single crystal quality can be obtained by re-etching the fourth polycrystalline silicon pattern 1024 corresponding to the I-type semiconductor 132 and low-temperature lateral epitaxy, and a lateral double heterojunction structure is formed. At the same time, the lateral growth of the epitaxial layer in the P-type semiconductor 112 and the N-type semiconductor 122 is obtained by the epitaxial process, the polycrystalline silicon grain size in the P-type semiconductor 112 and the N-type semiconductor 122 is expanded, the influence of the grain boundary is reduced, the series resistance of the P-type semiconductor and the N-type semiconductor 122 is reduced, and thus a low forward resistance is obtained.

[0179] The other details in the PIN diode preparation method embodiments provided by the second aspect of the present disclosure are the same as the embodiments corresponding to the PIN diode provided in the first aspect described above, and thus will not be repeated here.

[0180] In a third aspect, based on the same inventive concept, the embodiments of the present disclosure further provide an electronic device, which includes any of the PIN diodes in the embodiments of the first aspect.

[0181] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A PIN diode, comprising: a substrate substrate; an active layer disposed on the substrate substrate, the active layer comprising a P-type semiconductor, an I-type semiconductor and an N-type semiconductor disposed in sequence; wherein the P-type semiconductor, the I-type semiconductor and the N-type semiconductor have different polysilicon grain sizes in at least two of the three.

2. The PIN diode of claim 1, wherein, the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprise two polysilicon grain sizes in the three, and the P-type semiconductor has the same polysilicon grain size as the N-type semiconductor.

3. The PIN diode of claim 2, wherein, the P-type semiconductor and the N-type semiconductor have smaller polysilicon grain sizes than the I-type semiconductor. the PIN diode further comprises a first insulating pattern and a second insulating pattern disposed on a side of the active layer away from the substrate substrate; the first insulating pattern covers the P-type semiconductor in a projection of the substrate substrate; the second insulating pattern covers the N-type semiconductor in a projection of the substrate substrate.

4. The PIN diode of claim 2, wherein, the P-type semiconductor and the N-type semiconductor have larger polysilicon grain sizes than the I-type semiconductor. the PIN diode further comprises a third insulating pattern disposed on a side of the active layer away from the substrate substrate, the third insulating pattern covers the I-type semiconductor in a projection of the substrate substrate.

5. The PIN diode of claim 1, wherein, the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprise two polysilicon grain sizes in the three. the N-type semiconductor and the P-type semiconductor have the same polysilicon grain size as the I-type semiconductor.

6. The PIN diode of claim 5, wherein, the N-type semiconductor has the same polysilicon grain size as the I-type semiconductor, and larger polysilicon grain size than the P-type semiconductor. the PIN diode further comprises a fourth insulating pattern disposed on a side of the active layer away from the substrate substrate, and the fourth insulating pattern covers the P-type semiconductor in a projection of the substrate substrate.

7. The PIN diode of claim 5, wherein, the P-type semiconductor has the same polysilicon grain size as the I-type semiconductor, and larger polysilicon grain size than the N-type semiconductor. the PIN diode further comprises a fifth insulating pattern disposed on a side of the active layer away from the substrate substrate, and the fifth insulating pattern covers the N-type semiconductor in a projection of the substrate substrate.

8. The PIN diode of claim 1, wherein, the PIN diode further comprises a passivation layer, a first electrode and a second electrode disposed on a side of the active layer away from the substrate substrate; the first electrode is electrically connected to the P-type semiconductor through a first via hole penetrating at least the passivation layer; the second electrode is electrically connected to the N-type semiconductor through a second via hole penetrating at least the passivation layer.

9. A method of fabricating a PIN diode, wherein, the method comprises: providing a substrate substrate; Forming an active layer on the substrate substrate, the active layer comprising a P-type semiconductor, an I-type semiconductor and an N-type semiconductor arranged in sequence along a first direction; wherein at least one of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprises a polysilicon pattern, and the other comprises an epitaxial layer; the polysilicon grain size of the epitaxial layer is larger than the polysilicon grain size of the polysilicon pattern; wherein forming an active layer on the substrate substrate comprises: forming the polysilicon pattern on the substrate substrate by a patterning process; extending the polysilicon pattern along the sidewall of the I-type semiconductor by an epitaxial process to obtain the epitaxial layer.

10. The production method according to claim 9, wherein two of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprise a polysilicon pattern, and the other comprises an epitaxial layer; and the P-type semiconductor and the N-type semiconductor each comprise a polysilicon pattern, which is a first polysilicon pattern corresponding to the P-type semiconductor and a second polysilicon pattern corresponding to the N-type semiconductor respectively, and the I-type semiconductor comprises an epitaxial layer; forming an active layer on the substrate substrate, specifically comprising: forming a first polysilicon pattern and a second polysilicon pattern on the substrate substrate by a patterning process; extending the first polysilicon pattern along the sidewall of the I-type semiconductor by an epitaxial process, and extending the second polysilicon pattern along the sidewall of the I-type semiconductor to obtain the epitaxial layer.

11. The production method according to claim 9, wherein one of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprises a polysilicon pattern, and the other two comprise an epitaxial layer; and the P-type semiconductor comprises a polysilicon pattern, and the N-type semiconductor and the I-type semiconductor each comprise an epitaxial layer, which is a first epitaxial layer corresponding to the I-type semiconductor and a second epitaxial layer corresponding to the N-type semiconductor respectively; forming an active layer on the substrate substrate, specifically comprising: forming the polysilicon pattern on the substrate substrate by a patterning process; extending the polysilicon pattern along the sidewall of the I-type semiconductor by an epitaxial process to form the first epitaxial layer, and continuing to extend the first epitaxial layer along the first direction to form the second epitaxial layer.

12. The production method according to claim 9, wherein one of the P-type semiconductor, the I-type semiconductor and the N-type semiconductor comprises a polysilicon pattern, and the other two comprise an epitaxial layer; and the I-type semiconductor comprises a polysilicon pattern, and the P-type semiconductor and the N-type semiconductor each comprise an epitaxial layer, which is a first epitaxial layer corresponding to the P-type semiconductor and a second epitaxial layer corresponding to the N-type semiconductor respectively; forming an active layer on the substrate substrate, specifically comprising: forming the polysilicon pattern on the substrate substrate by a patterning process; extending the polysilicon pattern along the sidewall of the P-type semiconductor by an epitaxial process to form the first epitaxial layer, and extending the polysilicon pattern along the sidewall of the N-type semiconductor to form the second epitaxial layer.

13. The method of making according to any one of claims 9-12, wherein, The epitaxial process comprises a liquid phase epitaxial process or a low temperature gas phase epitaxial process.

14. The method of making according to any one of claims 9-12, wherein, forming the polysilicon pattern on the substrate substrate by a patterning process, specifically comprising: forming a first insulating layer on the substrate substrate; Depositing amorphous silicon on the first insulating layer and crystallizing; Forming a second insulating layer and forming the polysilicon pattern by a patterning process.

15. An electronic device comprising the PIN diode according to any one of claims 1-8.

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