Garbage-collection system

Abstract

A garbage-collection system is disclosed. The system comprises a pipelined processor configured for processing instructions and a garbage collector unit. The processor is configured to process a snapshot instruction that triggers a storing, by the processor, of values of at least a portion of a register file of the processor to a storage location. The garbage collector unit is configured to use the values stored at the storage location as a root set for a marking operation. Also disclosed is a method of garbage-collection. The method comprises processing, by a pipelined processor configured for processing instructions, a snapshot instruction that triggers a storing, by the processor, of values of at least a portion of a register file of the processor to a storage location. The method comprises performing, by a garbage collector unit, a marking operation using the values stored at the storage location as a root set.

Description

[0001] GARBAGE-COLLECTION SYSTEM

[0002] FIELD OF INVENTION

[0003] The present disclosure is in the field of garbage collection, and relates in particular to a garbage-collection system, e.g. a hardware garbage-collection system, and a corresponding method of garbage collection.

[0004] BACKGROUND TO INVENTION

[0005] Memory management is a necessary feature of most software-based processing systems. Memory, e.g. program and / or data storage, is a finite resource, and in deeply embedded systems may even be a scarce resource, and therefore careful management of memory usage may be required to avoid known application issues, such as heap overrun.

[0006] It is known in the art to recover memory that has been assigned to and / or used by an application that is no longer required. Such memory recovery may be known in the art as “garbage collection”.

[0007] An example of a typical, simplified garbage collection process is as follows.

[0008] In a typical application processing system, an operating system may support execution of one or more applications. A main memory of the processing system is typically used to store a heap. The heap may be used for dynamic allocation of memory to application processes.

[0009] The application may execute processes, wherein objects, e.g. data structures, may be used by said processes. A memory allocation routine of the operating system may assign heap in the main memory to store the objects.

[0010] As more objects are stored in the heap, an available remaining space in the heap is reduced. As such, reclaiming unused memory, e.g. heap that is no longer required by an application, becomes necessary.

[0011] Various garbage collection schemes are known. One known scheme is “tracing” garbage collection, which comprises determining which objects should be freed by tracing which objects are reachable by a chain of references from "root" objects. That is, garbage collection may be based on a principle that that a pointer to an object cannot be found by tracing pointers starting from the root objects, then the object cannot be reached by the application and therefore the memory assigned to the object can be freed. The tracing process may involve marking all objects identified as being reachable, and subsequently freeing objects that are not marked in a process termed “sweeping”.

[0012] Garbage collection may be a resource-intensive process, requiring significant processing capabilities and software overhead, and may severely impact the execution of applications. In examples, memory management code may account for up to -40% of runtime, in typical applications.

[0013] Furthermore, an optimum timing and extent of execution of garbage collection routines may be difficult to determine, and may vary significantly for different applications. Furthermore, execution of memory management software to handle garbage collection may also introduce a lack of determinism in embedded real-time systems, which may make an application prone to cyberattacks. Indeed, software reliant on memory management routines may generally be prone to common cyberattack vectors, such as buffer overflows and memory leaks.

[0014] In some examples, the above described “root" objects may be defined by pointers stored within registers in the processing system. In order to effectively perform a marking process as part of a garbage collection cycle, it may be necessary to rely upon the content of such registers. However, given the dynamic nature of the content of such registers, it may be critical to any marking process that the content of the registers are coherent with each other and with the contents of memory, yet accessible without significantly degrading a performance of the marking process or, more importantly, of the processing system.

[0015] It is therefore desirable to provide a method and / or system for efficiently implementing a garbage collection scheme, wherein said system / method has minimal impact upon application performance. Furthermore, it is preferable that such a system and / or method is does not significantly impact a deterministic behaviour of an underlying application.

[0016] It is therefore an aim of at least one embodiment of at least one aspect of the present disclosure to obviate or at least mitigate at least one of the above identified shortcomings of the prior art.

[0017] SUMMARY OF INVENTION

[0018] The present disclosure is in the field of garbage collection, and relates in particular to a garbage-collection system, e.g. a hardware garbage-collection system, and a corresponding method of garbage collection. According to a first aspect of the disclosure, there is provided a garbagecollection system comprising a processor configured for processing instructions. The processors may be a pipelined processor. The garbage-collection system also comprises a garbage collector unit. The processor is configured to process a snapshot instruction which triggers a storing, by the processor, of values of at least a portion of a register file of the processor to a storage location, and wherein the garbage collector unit is configured to use the values stored at the storage location as a root set for a marking operation.

[0019] The process of storing, by the processor, of values of at least a portion of a register file of the processor to a storage location, may hereafter be alternatively referred to as a snapshot, e.g. a taking of a snapshot or a snapshot process.

[0020] The values of the at least a portion of a register file may be referred to collectively as a snapshot. Said snapshot may effectively be a copy of the contents of the register file.

[0021] Advantageously, the disclosed garbage-collection system enables a snapshot of registers within the pipelined processor to be captured such that the values in those registers are coherent with each other and with the contents of memory, including any accesses to a memory up to the point that the snapshot is completed. Said memory may be a memory integrated into the garbage-collection system, coupled to the garbagecollection system, or otherwise accessible by the garbage-collection system.

[0022] Advantageously, the disclosed garbage-collection system enables the snapshot to be used as the root set in a marking operation by the garbage collector unit. Furthermore, the snapshot may advantageously be coherent with respect to all accesses to the memory up to the point at which the snapshot is completed, ensuring that the garbage collector unit sees a coherent view of the state of memory.

[0023] Advantageously, the disclosed garbage-collection system may be configured to include various kinds of state information in a snapshot. For example, in some embodiments the garbage-collection system may be configured to include at least one of: architectural general purposes registers (GPRs); special purposes registers (SPRs), a program counter (PC); control and status registers (CSRs).

[0024] The disclosed garbage-collection system may be configured to enable a logical state of the pipelined processor’s architectural register file to be captured, even in the absence of a corresponding physical architectural register file. References herein to the register file will be understood to include the GPRs, and, in some instances, also at least one of: one or more SPRs; the PC; and / or one or more CSRs.

[0025] Advantageously, the disclosed garbage-collection system enables a snapshot to be taken without pausing execution of the pipelined-processor and with minimal interruption to its execution.

[0026] In some examples, the snapshot instruction may be implemented as an instruction defined by the Instruction Set Architecture (ISA) of the processor.

[0027] In such examples, the snapshot instruction may be available to software. That is, in some instances the snapshot instruction may be included in software by implementation of an intrinsic function and / or compilation. Such a snapshot instruction may be hereafter referred to as a software-controlled snapshot variation.

[0028] In some examples, the snapshot instruction may comprises an ISA instruction having an associated tag which, when set, indicates that the ISA instruction may have an additional purpose of triggering the storing of values of the at least a portion of the register file to the storage location.

[0029] In such examples, the snapshot instruction may not be a single explicit instruction per se. Instead, the snapshot instruction may comprise a flag or indicator that may be associated with another instruction in the pipeline (e.g. ISA-defined instruction) of the pipelined processor, i.e. in the instruction stream, thus indicating that said another instruction has an additional behaviour of triggering a snapshot.

[0030] The snapshot instruction may be a hardware-defined instruction that is not defined by the Instruction Set Architecture of the processor.

[0031] That is, in some examples the snapshot instruction is not available to software, and is not part of the pipelined processor’s ISA. Such an implementation of a snapshot instruction may be known only to a given micro-architectural implementation of a given instruction set architecture. Such a snapshot instruction may be hereafter referred to as a hardware-controlled snapshot variation.

[0032] The garbage-collection system may comprise a Snapshot Instruction Active flag. In an example, the Snapshot Instruction Active flag may be stored as a 1 -bit register. In some examples, the Snapshot Instruction Active flag may comprise a plurality of bits.

[0033] The processor may be configured to set the Snapshot Instruction Active flag when the snapshot instruction enters a pipeline of the processor. The processor may be configured to clear the Snapshot Instruction Active flag when the snapshot instruction commits or is flushed from the pipeline of the processor. The processor may be further configured to store additional data when setting the Snapshot Instruction Active flag. In examples, the additional data may comprise a position at which the snapshot instruction is inserted into the instruction stream.

[0034] The garbage collector unit may be configured to issue the snapshot instruction to the pipelined processor.

[0035] Upon issuance of the snapshot instruction to the pipelined processor from the garbage collector unit, the snapshot instruction may be inserted into a frontend stage or an issue-stage of a pipeline of the processor as part of a current or a next cycle.

[0036] In some examples, upon issuance of the snapshot instruction to the pipelined processor by the garbage collector unit, the snapshot instruction may enter the instruction stream by a process of instruction fetching by the pipelined processor, e.g. when the snapshot instruction is a software-controlled snapshot variation.

[0037] The storage location may comprise a shadow register file comprising registers mapping to the register file of the processor, or mapping to a reorder buffer or register renamer configured to hold a state of the register file of the processor.

[0038] In other examples, the storage location may comprise a memory, such as a volatile memory, e.g. a RAM.

[0039] The garbage-collection system may be configured such that during the storing, by the processor, of values of at least a portion of the register file of the processor to the storage location, any committed changes to the register file are also stored in the storage location.

[0040] The storing, by the processor, of values of at least a portion of the register file of the processor to the storage location may complete when the snapshot instruction commits or when the pipeline of the pipelined processor is flushed.

[0041] In some examples, the storing of values of at least a portion of the register file of the processor to the storage location may comprise storing, at the storage location, a value of one register of the register file on each cycle.

[0042] In some examples, the storing of values of at least a portion of the register file of the processor to the storage location may comprise storing, at the storage location, a value of a plurality of registers of the register file on each cycle.

[0043] In some examples, the storing of values of at least a portion of the register file of the processor to the storage location may comprise storing, at the storage location, a value of all registers of the register file in a single cycle.

[0044] In some examples, the storage location may be updated with values from the register file as instructions are committed by the processor pipeline. In an example, while a snapshot is being taken, up to and including a cycle in which the snapshot completes, any committed changes to the register file may also be stored at (e.g. copied to) the storage location. In some example embodiments, only changes to the register file that have already been copied are stored at the storage location. In some example embodiments, all changes to the register file are written to the storage location.

[0045] The processor may be configured to process a further snapshot instruction when the snapshot instruction commits or when the pipeline of the pipelined processor is flushed before the storing of values of at least a portion of the register file of the processor to the storage location completes.

[0046] Advantageously, this may effectively extend a “snapshot time window”, e.g. number of clock cycles, during which the snapshot may be taken.

[0047] The processor may be configured to store the address of the snapshot instruction at the storage location when the snapshot instruction commits.

[0048] According to a second aspect of the disclosure, there is provided an integrated circuit comprising the garbage-collection system of the first aspect.

[0049] That is, some or all of the garbage-collection system may be implemented in hardware (e.g. CMOS circuitry or the like). The integrated circuit may be an integrated circuit die.

[0050] The garbage collector unit may be an integrated generational garbage collector. The garbage collector unit, or at least key components of said collector, may be physical components, e.g. implemented as a hard-macro or as a synthesized design, e.g. a sea- of-gates, and generally formed form as an embedded circuit, e.g. a CMOS circuit.

[0051] The garbage collector unit comprise a state machine, e.g. a finite state machine. The garbage collector unit may comprise logic, such as a combinatorial logic circuit.

[0052] The pipelined processor may comprise a processing core, e.g. a central processing unit (CPU), such as a CPU having a RISC architecture, CISC architecture, or the like. The pipelined processor may comprise one or more memory and / or data storage structures. The pipelined processor may be configured to execute instructions. Said instructions may be stored in the one or more memory and / or data storage structures. The pipelined processor may be provided as a hard-macro or as a synthesized design, e.g. a sea-of-gates. The processing circuit may comprise an embedded circuit, e.g. a CMOS circuit.

[0053] According to a third aspect of the disclosure, there is provided a method of garbage-collection. The method comprises processing, by a pipelined processor configured for processing instructions, a snapshot instruction which triggers a storing, by the processor, of values of at least a portion of a register file of the processor to a storage location.

[0054] The method comprises performing, by a garbage collector unit, a marking operation using the values stored at the storage location as a root set.

[0055] The above summary is intended to be merely exemplary and non-limiting. The disclosure includes one or more corresponding aspects, embodiments or features in isolation or in various combinations whether or not specifically stated (including claimed) in that combination or in isolation. It should be understood that features defined above in accordance with any aspect of the present disclosure or below relating to any specific embodiment of the disclosure may be utilized, either alone or in combination with any other defined feature, in any other aspect or embodiment or to form a further aspect or embodiment of the disclosure.

[0056] BRIEF DESCRIPTION OF DRAWINGS

[0057] These and other aspects of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, wherein:

[0058] Figure 1 depicts a block diagram of an example implementation of an integrated garbage collection system, according to an embodiment of the disclosure;

[0059] Figure 2 depicts a method of garbage-collection, including capturing of a coherent snapshot, according to an embodiment of the disclosure;

[0060] Figure 3 depicts a pipeline diagram showing an example of a hardware-controlled snapshot variation, according to an embodiment of the disclosure;

[0061] Figure 4 depicts a pipeline diagram showing a further example of a hardware- controlled snapshot variation, with reinsertion of a snapshot instruction, according to an embodiment of the disclosure; and

[0062] Figure 5 depicts a pipeline diagram showing an example of a software-controlled snapshot variation, according to an embodiment of the disclosure.

[0063] DETAILED DESCRIPTION OF DRAWINGS

[0064] Figure 1 depicts a block diagram of an example implementation of an integrated garbage collection system 100, according to an embodiment of the disclosure. The integrated garbage collection system 100 comprises a pipelined processor 195 configured for processing instructions, wherein an instruction pipeline 105 of the pipelined processor 195 is depicted.

[0065] The example instruction pipeline 105 comprises five stages: an instruction fetch stage 110a; an instruction decode stage 110b; an issue stage 110c; an execute stage 110d; and a com mit / write- back stage 110e.

[0066] It will be appreciated that the depicted instruction pipeline 105 is an example, and other processors having other instruction pipeline configurations may also fall within the scope of the disclosure. For example, in some embodiments the instruction pipeline may have greater than or less than five stages. In some embodiments the processor may be a multi-issue superscalar processor. The pipelined processor 195 may comprise a RISC architecture, CISC architecture, or the like.

[0067] Also depicted is a garbage collector unit 115. In the example, the garbage collector unit 115 is depicted as integrated into the pipelined processor 195. In other examples the garbage collector unit 115 may be coupled to the pipelined processor 195, such as via one or more interfaces.

[0068] The garbage collector unit 115 may be configured to implement a tracing garbage collection, which comprises determining which objects should be freed by tracing which objects are reachable by a chain of references from "root" objects. That is, garbage collection may be based on a principle that that if a pointer to an object cannot be found by tracing pointers starting from the root objects, then the object cannot be reached by the application and therefore the memory assigned to the object can be freed. The tracing process may involve marking all objects identified as being reachable, and subsequently freeing objects that are not marked in a process termed “sweeping”.

[0069] Although references made herein are to a tracing garbage collector that may implement the above-described “sweeping” process, it will be appreciated that the disclosed invention may also be applicable to so-called "copying" collectors (which may perform marking followed by a 'copying' operation, rather than 'sweeping'), and / or reference counting collectors wherein a root snapshot may be used as part of determining a count of copies of a reference in the roots.

[0070] The garbage collector unit 115 may comprise a “single-generation collector”. That is, said garbage collector unit 115 may be configured to mark and compact an entire memory space, e.g. heap, in each collection cycle.

[0071] In a preferred embodiment, the garbage collector unit 115 may be a generational garbage collector. That is, the garbage collector unit 115 may be configured to scan a “young generation” (e.g. objects which are more likely to be used) on every collection cycle and less frequently (for example one in every 10 cycles) the garbage collector unit 115 may also be configured to scan an “old generation” (e.g. objects which are less likely to be used) to identify older objects which are no longer in use.

[0072] Whether a single-generation or (multi) generational garbage collector is implemented, in some examples a snapshot of the registers of the pipelined processor 195 may be required at a start of a collection cycle. In some examples, a snapshot of the registers of the pipelined processor 195 may be required at any point (including multiple points i.e. repeated new snapshots) during a collection cycle. Such a snapshot or snapshots may involve capturing content of the register file of the (at least one) pipelined processor 195 that the garbage collector unit 115 is coupled to. This snapshot of the pipelined processor’s 195 registers provides the roots of the garbage collection.

[0073] In the example implementation of Figure 1 , a snapshot request interface 160 is depicted. The snapshot request interface 160 may be configured to receive a snapshot request from the garbage collector unit 115 and, in some embodiments, insert the snapshot request into the instruction pipeline 105 of the pipelined processor 195, as described in more detail below with reference to Figure 2.

[0074] Also depicted in Figure 1 is a register file 120, e.g. a physical register file, of the pipelined processor 195. The register file 120 may comprise General Purpose Registers (GPRs). The register file 120 may, in some instances, also comprise at least one of: one or more Special Purpose Registers (SPRs); the Program Counter (PC); and / or one or more Control and / or Status Registers (CSRs).

[0075] Also depicted is a storage location 130, which in this example is a shadow register file comprising registers mapping to the register file 120. In other non-depicted examples, a storage location 130 may map to a reorder buffer or register renamer configured to hold a state of the registers 120 of the pipelined processor 195. In yet further examples, the storage location 130 may comprise a memory, such as a volatile memory, e.g. a RAM.

[0076] For completeness, a cache system of the pipelined processor 195 is also depicted. In the example, the pipelined processor 195 comprises a Harvard-architecture having a level-one data cache 135 and a level-one instruction cache 140. In other examples, the level-one cache may be unified. Also depicted is a unified level-two cache 145, and a last-level cache 155. It will be understood that other memory and / or cache configurations may be implemented.

[0077] The pipelined processor 195 is coupled to a system memory 190, which may comprise one or more of various types of memories, e.g. SRAM, DRAM, NVM or the like. It will be appreciated that various interconnects or the like may be implemented between the pipelined processor 195 and the system memory 190.

[0078] Operation of the integrated garbage collection system 100 will now be described by reference to Figure 2, which depicts a method 200 of garbage-collection, including capturing of a coherent snapshot, according to an embodiment of the disclosure.

[0079] At a first step 205, a snapshot is requested by the garbage collector unit 115. The snapshot may be requested because the garbage collector unit 115 is scheduled or triggered to commence a collection cycle, and thus requires the snapshot to provide the roots.

[0080] The request is provided to the snapshot request interface 160. The snapshot request interface 160 may be a feature of the processor 195, or otherwise coupled to the processor 195. In some examples, the snapshot request interface 160 set a Snapshot Instruction Active flag, which may be implemented as a register comprising at least one bit for indicating that a snapshot is underway.

[0081] At a second step 210, the snapshot request interface 160 inserts a snapshot instruction into the instruction pipeline 105 of the pipelined processor 195.

[0082] In some examples, the snapshot instruction inserted by the snapshot request interface 160 may be a hardware-defined instruction that is not defined by the Instruction Set Architecture of the processor 195. That is, in some examples the snapshot instruction is not available to software, and is not part of the pipelined processor’s ISA, e.g. the hardware-controlled snapshot variation.

[0083] In some examples, the snapshot instruction inserted by the snapshot request interface 160 may comprise an ISA instruction having an associated tag which, when set, indicates that the ISA instruction has an additional purpose of triggering the snapshot, i.e. the storing of values of the at least a portion of the register file 130 to the storage location 120. That is, the snapshot instruction may comprise a flag that may be associated with another instruction in the instruction pipeline 105 (e.g. ISA-defined instruction) of the pipelined processor 195, i.e. in the instruction stream, thus indicating that said another instruction has an additional behaviour of triggering a snapshot.

[0084] A next step 215 comprises a process of storing, by the processor 195, of values of at least a portion of the register file 120 of the processor 195 to the storage location 130, e.g. the shadow register file (also termed the Shadow Architectural Register File, ARF). This may comprise storing (e.g. copying) at least one register of the register file 120 in each cycle. This process may require multiple cycles, and thus may iteratively continue until the copying of the register file 120 into the storage location 130 is complete, as indicated at depicted steps 220 and 230.

[0085] The snapshot instruction completes when either the snapshot instruction commits (as indicated at step 235) or when the pipeline of the pipelined processor is flushed (as indicated at step 240). In both of these scenarios, if the copying of the register file 120 into the storage location 130 is incomplete when the commit or flush occurs, then the processor 195 may be configured to process a further snapshot instruction, as indicated at step 250. This is described in more detail below with reference to Figure 4. Advantageously, this may effectively extend a “snapshot time window”, e.g. number of clock cycles, during which the snapshot may be taken.

[0086] Advantageously, if the instruction pipeline 105 is flushed (for example, due to aborted speculative execution of a previously mispredicted branch), then the Snapshot Instruction Active flag indicates that a snapshot instruction exists in the instruction pipeline 105. In this case, the instruction pipeline 105 is flushed as normal and the snapshot completes in the same cycle. This ensures coherency of the snapshot with the state of the memory (e.g. the memory 190, or any intervening cache 135, 140, 145, 150), as a flush of the instruction pipeline 105 indicates that no changes to memory are uncommitted. Advantageously, the Snapshot Instruction Active flag means the instruction pipeline 105 that is being flushed does not need to be scanned to try to identify the presence of the snapshot instruction. This is of particular benefit in, for example, out- of-order processor pipelines using a reorder buffer in which the absence of scanning the instruction queue means that a pipeline flush can rapidly truncate the tail of the reorder buffer.

[0087] In some examples, the storage location 130 is updated with values from the register file 120 as instructions are committed by the processor pipeline 105. In an example, while a snapshot is being taken, up to and including a cycle in which the snapshot completes, any committed changes to the register file 120 may also be stored in (e.g. copied to) the storage location 130, as indicated at step 245. In some example embodiments, only changes to the register file 120 that have already been copied are stored at the storage location 130. In some example embodiments, all changes to the register file 120 are written to the storage location 130.

[0088] Upon completion of the snapshot instruction (or one or more further snapshot instructions) such that a coherent copying of the register file 120 into the storage location 130 is complete, a signal 175 indicating completion of the snapshot is provided to the snapshot request interface 160 at step 255, such as by logic associated with the instruction pipeline 105.

[0089] Following receipt by the processor 195 of the signal 175 indicating completion of the snapshot at step 255, at a subsequent step 260 the Snapshot Instruction Active flag is cleared, thus indicating that a snapshot is no longer underway.

[0090] In some example embodiments, the registers referred to at step 210 may be GPRs. In some optional example embodiments, at a step 265 following clearing of the Snapshot Instruction Active flag, a copy may be taken of additional processor registers (also termed non-architectural registers), such as SPRs, the PC and / or one or more CSRs. In other embodiments, one or more of the SPRs, PC and / or CSRs are excluded from the snapshot. In some examples, the non-architectural registers may be copied in a same cycle that the snapshot completes (including any changes that are committed during that cycle), and are included as part of the overall snapshot.

[0091] Advantageously, the commit of the snapshot instruction will happen in the order of the instruction stream and only if all speculative instructions ahead of the snapshot instruction have committed their changes at step 270, including any changes to memory (e.g. the memory 190, and / or any intervening caches 135, 140, 145, 150). This ensures coherency of the snapshot with the state of the memory.

[0092] Advantageously, in an example embodiment, when the snapshot instruction commits, an address of the snapshot instruction may be used to supply the snapshot of the program counter.

[0093] Finally, at step 275, a signal is provided from the snapshot request interface 160 to the garbage collector unit 115 indicating that a coherent snapshot has been taken. The garbage collector unit 115 may then rely upon the values stored at the storage location 130 as a root set for a marking operation.

[0094] Figure 3 depicts a pipeline diagram 300 showing an example of a hardware- controlled snapshot variation, according to an embodiment of the disclosure. For purposes of simplicity of illustration, Figure 3 represents a processor comprising only four GPRs (rO, r1 , r2 and r3).

[0095] In the example of Figure 3, at “clock cycle 0”, a first instruction 305 that has general purpose registers r2, r1 and r2 as operands, enters the instruction fetch stage 110a of the instruction pipeline 105.

[0096] At “clock cycle 1”, a second instruction 310 that has general purpose registers r3, r1 and r2 as operands, is at the instruction fetch stage 110a of the instruction pipeline 105 and the first instruction 305 has propagated to the instruction decode stage 110b of the instruction pipeline 105.

[0097] At “clock cycle 2”, a third instruction 315 that has general purpose registers rO, r1 and r2 as operands, is at the instruction fetch stage 110a of the instruction pipeline 105, the second instruction 310 has propagated to the instruction decode stage 110b of the instruction pipeline 105, and the first instruction 305 has propagated to the issue stage 110c of the instruction pipeline 105.

[0098] At “clock cycle 3”, the third instruction 310 has propagated to the instruction decode stage 110b of the instruction pipeline 105, the second instruction 305 has propagated to the issue stage 110c of the instruction pipeline 105, and the first instruction 305 has propagated to the execute stage 110d of the instruction pipeline 105.

[0099] Following the “clock cycle 3”, a snapshot is requested by the garbage collector unit 115. In examples, this causes the snapshot request interface 160 to set the Snapshot Instruction Active flag at “clock cycle 4”, indicating that a snapshot is now underway.

[0100] At “clock cycle 4”, a snapshot instruction 320 (denoted phantom snapshot) is inserted into the instruction stream. In examples, the snapshot instruction 320 may be inserted by hardware directly to the issue stage 110c or the execute stage 110d of the instruction pipeline 105. At “clock cycle 4”, the first instruction 305 has propagated to the commit / write-back stage 110e. Since the first instruction 305 operates on r2 which is to be written back to memory, r2 is to be copied to the storage location 130 from the register file 120. Also, in this first cycle of the snapshot, register rO is copied to the storage location 130 from the register file 120.

[0101] At “clock cycle 5”, which is the second cycle of the snapshot, register r1 is copied to the storage location 130 from the register file 120. It will be appreciated that this is for purposes of example only and, as described above, in other embodiments more than one register may be copied to the storage location 130 in a single cycle.

[0102] At “clock cycle 6”, which is the third cycle of the snapshot, register r2 is copied to the storage location 130 from the register file 120.

[0103] At “clock cycle 7”, which is the fourth cycle of the snapshot, both the second instruction 310 and the third instruction 315 have propagated to the commit / write-back stage 110e. The second instruction 310 was acting upon r3 and third instruction 315 was acting upon rO. As such, both r3 and rO are copied to the storage location 130. The snapshot has completed, and the snapshot instruction 320 propagates to the commit / write-back stage. At “clock cycle 7” the snapshot request interface 160 negates the Snapshot Instruction Active flag, indicating that the snapshot is complete.

[0104] In ensuing clock cycles (e.g. “clock cycle 8” to “clock cycle N”) stores from the second instruction 310 and / or third instruction 315 are completed, and finally a “snapshot response” signal is provided from the snapshot request interface 160 to the garbage collector unit 115 indicating that a coherent snapshot has been taken. The garbage collector unit 115 may then rely upon the values stored at the storage location 130 as a root set for a marking operation.

[0105] Figure 4 depicts a pipeline diagram 400 showing a further example of a hardware- controlled snapshot variation, with reinsertion of a snapshot instruction, according to an embodiment of the disclosure. Again, for purposes of simplicity of illustration, Figure 4 represents a processor comprising only four GPRs (rO, r1 , r2 and r3).

[0106] In the example of Figure 4, at “clock cycle 0”, a first instruction 405 that has general purpose registers r2, r1 and r2 as operands, is at the instruction fetch stage 110a of the instruction pipeline 105.

[0107] At “clock cycle 1”, a second instruction 410 that has general purpose registers r3, r1 and r2 as operands, is at the instruction fetch stage 110a of the instruction pipeline 105 and the first instruction 305 has propagated to the instruction decode stage 110b of the instruction pipeline 105.

[0108] At “clock cycle 2”, a third instruction 415 that has general purpose registers rO, r1 and r2 as operands, is at the instruction fetch stage 110a of the instruction pipeline 105, the second instruction 310 has propagated to the instruction decode stage 110b of the instruction pipeline 105, and the first instruction 405 has propagated to the issue stage 110c of the instruction pipeline 105.

[0109] Following the “clock cycle 2”, a snapshot is requested by the garbage collector unit 115. In examples, this causes the snapshot request interface 160 to set the Snapshot Instruction Active flag at “clock cycle 3”, indicating that a snapshot is now underway.

[0110] At “clock cycle 3”, the third instruction 410 has propagated to the instruction decode stage 110b of the instruction pipeline 105 and the first instruction 405 has propagated to the execute stage 110d of the instruction pipeline 105.

[0111] At “clock cycle 3”, a snapshot instruction 420 (denoted phantom snapshot) is inserted into the instruction stream. In examples, the snapshot instruction 420 may be inserted by hardware directly to the issue stage 110c or the execute stage 110d of the instruction pipeline 105. In this first cycle of the snapshot, register rO is copied to the storage location 130 from the register file 120.

[0112] At “clock cycle 4”, the first instruction 405 remains at the execute stage 110d of the instruction pipeline 105 and the second instruction 410 has propagated to the issue stage 110c. In this second cycle of the snapshot, register r1 is copied to the storage location 130 from the register file 120.

[0113] At “clock cycle 5”, which is the third cycle of the snapshot, the first instruction 405 has propagated to the com mit / write- back stage 110e. Since the first instruction 405 operates on r2 which is to be written back to memory, r2 is to be copied to the storage location 130 from the register file 120.

[0114] At “clock cycle 5”, the snapshot instruction 420 also propagates to the write-back stage 110e. However, since the snapshot remains incomplete (r3 not yet copied), a further snapshot instruction 425 is inserted into the instruction pipeline 105.

[0115] At “clock cycle 6”, which is effectively the fourth cycle of the snapshot (or second cycle of the further snapshot), the second instruction 410 has propagated to the commit / write-back stage 110e. The second instruction 410 was acting upon r3 and, as such, r3 is copied to the storage location 130. The snapshot has completed, and the further snapshot instruction 425 propagates to the commit / write-back stage and the snapshot request interface 160 negates the Snapshot Instruction Active flag, indicating that the snapshot is complete.

[0116] In ensuing clock cycles (e.g. “clock cycle 7” to “clock cycle N”) stores from “clock cycle 6” onwards (e.g. write back to memory, are completed and finally a “snapshot response” signal is provided from the snapshot request interface 160 to the garbage collector unit 115 indicating that a coherent snapshot has been taken. The garbage collector unit 115 may then rely upon the values stored at the storage location 130 as a root set for a marking operation.

[0117] Figure 5 depicts a pipeline diagram 500 showing an example of a software- controlled snapshot variation, according to an embodiment of the disclosure. In this example, a snapshot instruction 515 is implemented as an instruction defined by the Instruction Set Architecture (ISA) of the processor. In this example, the snapshot instruction 515 may be available to software. That is, in some instances snapshot instruction 515 may be included in software by implementation of an intrinsic function and / or compilation.

[0118] Again, for purposes of simplicity of illustration, Figure 5 represents a processor comprising only four GPRs (rO, r1 , r2 and r3). In the example of Figure 5, at “clock cycle 0”, a first instruction 505 that has general purpose registers r2, r1 and r2 as operands, is at the instruction fetch stage 110a of the instruction pipeline 105.

[0119] At “clock cycle 1”, a second instruction 510 that has general purpose registers rO, r1 and r2 as operands, is at the instruction fetch stage 110a of the instruction pipeline 105 and the first instruction 505 has propagated to the instruction decode stage 110b of the instruction pipeline 105.

[0120] At “clock cycle 2”, a third instruction 515 which is a snapshot instruction, is at the instruction fetch stage 110a of the instruction pipeline 105, the second instruction 510 has propagated to the instruction decode stage 110b of the instruction pipeline 105, and the first instruction has propagated to the issue stage 110c of the instruction pipeline 105. That is, the snapshot instruction may be fetched in the same manner as any other instruction, such as from a memory.

[0121] At “clock cycle 3”, the first instruction 505 is at the execute stage 110d of the instruction pipeline 105, the second instruction 510 has propagated to the issue stage 110c and the snapshot instruction 515 has propagated to the instruction decode stage 110b. Following decoding of the snapshot instruction 515, the processor recognises that a snapshot has been requested. As such, the Snapshot Instruction Active flag is set by the processor 195 at “clock cycle 4”, indicating that a snapshot is now underway.

[0122] At “clock cycle 4”, which is effectively the first cycle of the snapshot, register rO is copied to the storage location 130 from the register file 120. Also, the first instruction 505 has propagated to the com mit / write- back stage 110e. Since the first instruction 505 operates on r2 which is to be written back to memory, r2 is to be copied to the storage location 130 from the register file 120.

[0123] At “clock cycle 5”, which is effectively the second cycle of the snapshot, register r1 is copied to the storage location 130 from the register file 120.

[0124] At “clock cycle 6”, which is effectively the third cycle of the snapshot, register r2 is copied to the storage location 130 from the register file 120.

[0125] At “clock cycle 7”, which is effectively the fourth and final cycle of the snapshot, register r3 is copied to the storage location 130 from the register file 120. Also, the second instruction 510 has propagated to the com mit / write- back stage 110e. Since the second instruction 510 operates on rO which is to be written back to memory, rO is to be copied to the storage location 130 from the register file 120. At “clock cycle 7”, the snapshot instruction 515 has also propagated to the commit / write-back stage 110e. The snapshot has completed, and the processor 195 negates the Snapshot Instruction Active flag, indicating that the snapshot is complete.

[0126] In ensuing clock cycles (e.g. “clock cycle 8” to “clock cycle N”) any stores from “clock cycle 7” onwards are completed, and finally a “snapshot response” signal is provided by the processor 195 to the garbage collector unit 115 indicating that a coherent snapshot has been taken. The garbage collector unit 115 may then rely upon the values stored at the storage location 130 as a root set for a marking operation.

[0127] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in any embodiments, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:

1. A garbage-collection system comprising: a pipelined processor configured for processing instructions; and a garbage collector unit; wherein the processor is configured to process a snapshot instruction which triggers a storing, by the processor, of values of at least a portion of a register file of the processor to a storage location, and wherein the garbage collector unit is configured to use the values stored at the storage location as a root set for a marking operation.

2. The garbage-collection system of claim 1 , wherein the snapshot instruction is implemented as an instruction defined by the Instruction Set Architecture (ISA) of the processor.

3. The garbage-collection system of claim 1 , wherein the snapshot instruction comprises an ISA instruction having an associated tag which, when set, indicates that the ISA instruction has an additional purpose of triggering the storing of values of the at least a portion of the register file to the storage location.

4. The garbage-collection system of claim 1 , wherein the snapshot instruction is a hardware-defined instruction that is not defined by the Instruction Set Architecture of the processor.

5. The garbage-collection system of claim 1 , comprising a Snapshot Instruction Active flag, wherein the processor is configured to: set the Snapshot Instruction Active flag when the snapshot instruction enters a pipeline of the processor; and clear the Snapshot Instruction Active flag when the snapshot instruction commits or is flushed from the pipeline of the processor.

6. The garbage-collection system of claim 5, wherein the processor is further configured to store additional data when setting the Snapshot Instruction Active flag, and optionally wherein said additional data comprises a position at which the snapshot instruction is inserted into the instruction stream.

7. The garbage-collection system of any preceding claim, wherein the garbage collector unit is configured to issue the snapshot instruction to the pipelined processor.

8. The garbage-collection system of claim 7, when dependent upon claim 3 or 4, wherein upon issuance of the snapshot instruction to the pipelined processor from the garbage collector unit, the snapshot instruction is inserted into a frontend stage or an issue-stage of the pipeline of the processor as part of a current or a next cycle.

9. The garbage-collection system of claim 7, when dependent upon claim 2, wherein upon issuance of the snapshot instruction to the pipelined processor by the garbage collector unit, the snapshot instruction enters the instruction stream by a process of instruction fetching by the pipelined processor.

10. The garbage-collection system of any preceding claim, wherein the storage location comprises a shadow register file comprising registers mapping to the register file of the processor, or mapping to a reorder buffer or register renamer configured to hold a state of the register file of the processor.

11. The garbage-collection system of claim 10, configured such that during the storing, by the processor, of values of at least a portion of the register file of the processor to the storage location, any committed changes to the register file are also stored in the storage location.

12. The garbage-collection system of any preceding claim wherein the storing, by the processor, of values of at least a portion of the register file of the processor to the storage location completes when the snapshot instruction commits or when the pipeline of the pipelined processor is flushed.

13. The garbage-collection system of any preceding claim wherein, the processor is configured to process a further snapshot instruction when the snapshot instruction commits or when the pipeline of the pipelined processor is flushedbefore the storing of values of at least a portion of the register file of the processor to the storage location completes.

14. The garbage-collection system of any preceding claim wherein, the processor is configured to store the address of the snapshot instruction at the storage location when the snapshot instruction commits.

15. An integrated circuit comprising the garbage-collection system of any preceding claim.

16. A method of garbage-collection, the method comprising: processing, by a pipelined processor configured for processing instructions, a snapshot instruction which triggers a storing, by the processor, of values of at least a portion of a register file of the processor to a storage location, and performing, by a garbage collector unit, a marking operation using the values stored at the storage location as a root set.

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