Three-dimensional flash memory including vertical channel structures having asymmetric configuration

Abstract

Disclosed is a three-dimensional flash memory including vertical channel structures having an asymmetric configuration. According to one embodiment, the vertical channel structures of the three-dimensional flash memory may be arranged in a memory cell block in a horizontal planar asymmetric configuration.

Description

3D flash memory including vertical channel structures with an asymmetric structure

[0001] The embodiments below describe a technology for a three-dimensional flash memory including vertical channel structures of an asymmetrical structure.

[0002] Flash memory devices are electrically erasable programmable read-only memories (EEPROM) that control the input and output of data electrically by Fowler-Nordheimtunneling or hot electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In order to meet the high performance and low price demands of consumers, it is required to increase the integration density in these flash memory devices, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a memory cell string has been proposed.

[0004] Furthermore, in 3D flash memory, a technology has been proposed in which vertical channel structures are arranged symmetrically within a memory cell block through horizontal scaling, which densely implements the spacing between vertical channel structures on a horizontal plane.

[0005] Meanwhile, with regard to the manufacturing method of 3D flash memory, a gate replacement process is emerging in which spaces where gate electrodes are to be formed are secured with sacrificial layers, the sacrificial layers are removed, and gate electrodes are formed in the removed spaces.

[0006] However, the technology of arranging vertical channel structures in a symmetrical structure within a memory cell block through the aforementioned horizontal scaling has the disadvantage and problem that it is difficult for an etching liquid or gas to be introduced to remove the sacrificial layers because the vertical channel structures are arranged excessively densely.

[0007] Accordingly, the embodiments below describe a three-dimensional flash memory structure for applying a gate replacement process.

[0008]

[0009] One embodiment proposes a three-dimensional flash memory and a method for manufacturing the same, which is arranged in an asymmetrical structure while securing an arbitrary space on a plane within a memory cell block so that an etchant or gas can smoothly flow into vertical channel structures in a gate replacement process.

[0010] In particular, one embodiment proposes a three-dimensional flash memory and a method for manufacturing the same, in which at least some of the vertical channel structures arranged in an asymmetrical structure within a memory cell block are arranged to contact or overlap each other, in order to secure an arbitrary space that allows an etching liquid or gas to smoothly flow into the vertical channel structures while improving the memory cell density.

[0011] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0012] According to one embodiment, a three-dimensional flash memory may include gate electrodes that are formed to extend in a horizontal direction and are stacked while being spaced apart from each other in a vertical direction; and vertical channel structures that are formed to extend in the vertical direction through the gate electrodes, wherein the vertical channel structures may be characterized in that they are arranged in an asymmetrical structure on a plane in the horizontal direction within a memory cell block.

[0013] According to one aspect, the vertical channel structures included in the memory cell block may be arranged in the asymmetrical structure while securing an arbitrary space on the plane within the memory cell block so that an etching liquid or gas can be introduced during the manufacturing process of the gate electrodes.

[0014] According to another aspect, the vertical channel structures included in the memory cell block may be arranged in an asymmetrical structure in which an asymmetrical direction is determined according to the direction of extension on the plane of the arbitrary space.

[0015] According to another aspect, at least some of the vertical channel structures arranged in the asymmetrical structure within the memory cell block may be arranged to be in contact with each other.

[0016] According to another aspect, the at least some vertical channel structures may be arranged such that at least a portion of each of the at least some vertical channel structures overlaps with each other.

[0017] According to another aspect, the at least some vertical channel structures may be arranged such that at least a portion of the blocking insulating film included in each of the at least some vertical channel structures overlaps with each other.

[0018] According to one embodiment, a method for manufacturing a three-dimensional flash memory includes the steps of: preparing a semiconductor structure including sacrificial layers that extend horizontally and are stacked while being spaced apart from each other in the vertical direction; forming vertical channel structures in the semiconductor structure in the vertical direction; removing the sacrificial layers by introducing an etchant or gas; and forming gate electrodes in spaces where the sacrificial layers are removed, wherein the step of forming the vertical channel structures may be characterized by forming the vertical channel structures by arranging them in an asymmetrical structure on a plane in the horizontal direction within a memory cell block.

[0019] According to one aspect, the step of forming the vertical channel structures in an asymmetrical structure on a plane in the horizontal direction may include the step of securing an arbitrary space on the plane within the memory cell block so that an etchant or gas can flow in the step of removing the sacrificial layers; and the step of forming the vertical channel structures included in the memory cell block in an asymmetrical structure as the arbitrary space on the plane is secured.

[0020] According to another aspect, the step of forming and arranging the vertical channel structures in the asymmetrical structure may be characterized by forming and arranging the vertical channel structures included in the memory cell block in the asymmetrical structure in which the asymmetrical direction is determined according to the plane-wise extension direction of the arbitrary space.

[0021] According to another aspect, the step of forming and arranging the vertical channel structures in a planar asymmetrical structure in the horizontal direction may be characterized by forming and arranging at least some of the vertical channel structures arranged in the asymmetrical structure within the memory cell block so that the at least some of the vertical channel structures are in contact with each other.

[0022] According to another aspect, the step of forming and arranging the vertical channel structures in a planar asymmetrical structure in the horizontal direction may be characterized by forming and arranging the at least some vertical channel structures such that at least a portion of each of the at least some vertical channel structures overlaps with each other.

[0023] According to another aspect, the step of forming and arranging the vertical channel structures in a planar asymmetrical structure in the horizontal direction may be characterized by forming and arranging the at least some vertical channel structures such that at least a portion of the blocking insulating film included in each of the at least some vertical channel structures overlaps with each other.

[0024] One embodiment proposes a three-dimensional flash memory and a manufacturing method thereof in which memory cell blocks are arranged in an asymmetrical structure while securing an arbitrary space on a plane within the memory cell block, thereby achieving a technical effect of enabling etching liquid or gas to smoothly flow into vertical channel structures in a gate replacement process.

[0025] In particular, one embodiment proposes a three-dimensional flash memory and a method for manufacturing the same in which at least some of the vertical channel structures among the vertical channel structures arranged in an asymmetrical structure within a memory cell block are arranged to contact or overlap each other, thereby achieving a technical effect of improving the memory cell integration while securing an arbitrary space that allows an etching liquid or gas to smoothly flow into the vertical channel structures.

[0026] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0027] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0028] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0029] FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

[0030] Figures 4 and 5 are plan views illustrating the structure of a three-dimensional flash memory according to another embodiment.

[0031] Figures 6 and 7 are plan views illustrating the structure of a three-dimensional flash memory according to another embodiment.

[0032] FIG. 8 is a plan view showing an enlarged view of the area where vertical channel structures overlap each other in the structure of the three-dimensional flash memory illustrated in FIG. 7.

[0033] FIG. 9 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to embodiments.

[0034] FIG. 10 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0036] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0037] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0038] Hereinafter, with reference to the drawings, a three-dimensional flash memory and a manufacturing method thereof that secure an arbitrary space that allows an etching liquid or gas to smoothly flow into vertical channel structures while improving memory cell integration are described in detail.

[0039]

[0040] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to one embodiment.

[0041] Referring to FIG. 1, an array of a three-dimensional flash memory according to one embodiment may include a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source line (CSL) and the bit lines (BL0, BL1, BL2).

[0042] The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0043] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be commonly connected to the common source line (CSL) provided between the bit lines (BL0, BL1, BL2) and one common source line (CSL). At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may be two-dimensionally arranged while extending in the first direction (D1) and being spaced apart from each other along the second direction (D2). The plurality of common source lines (CSL) may be electrically identically voltage-applied, but the present invention is not limited thereto, and each of the plurality of common source lines (CSL) may be electrically independently controlled so that different voltages may be applied.

[0044] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may be composed of a ground select transistor (GST) connected to a common source line (CSL), first and second string select transistors (SST1, SST2) connected to bit lines (BL0, BL1, BL2) and connected in series, memory cell transistors (MCT) and an erase control transistor (ECT) disposed between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2) and connected in series. In addition, each of the memory cell transistors (MCT) may include a data storage element.

[0045] For example, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, the present invention is not limited thereto, and each of the cell strings (CSTR) may include one string select transistor. As another example, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0046] A cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from common source lines (CSL). That is, the memory cell transistors (MCT) may be connected in series between a first string select transistor (SST1) and a ground select transistor (GST) along a third direction (D3). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) may further include dummy cell transistors (DMC) connected between the first string select transistor (SST1) and an uppermost one of the memory cell transistors (MCT) and between the ground select transistor (GST) and a lowermost one of the memory cell transistors (MCT).

[0047] According to an embodiment, a first string select transistor (SST1) may be controlled by first string select lines (SSL1-1, SSL1-2, SSL1-3), and a second string select transistor (SST2) may be controlled by second string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may be controlled by a dummy word line (DWL), respectively. The ground select transistor (GST) may be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) may be controlled by the erase control line (ECL). A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) can be commonly connected to the sources of erase control transistors (ECT).

[0048] The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and thus may be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be independently controlled.

[0049] Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) extend along a first direction (D1), are spaced apart from each other in a second direction (D2) and can be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) provided at substantially the same level from common source lines (CSL) can be electrically isolated from each other. In addition, erase control transistors (ECT) of different cell strings (CSTR) can be controlled by a common erase control line (ECL). Erase control transistors (ECT) may generate gate-induced drain leakage (GIDL) during an erase operation of a memory cell array. In some embodiments, an erase voltage may be applied to bit lines (BL0, BL1, BL2) and / or common source lines (CSL) during an erase operation of a memory cell array, and gate-induced leakage current may be generated in the string select transistor (SST) and / or the erase control transistors (ECT).

[0050] The string selection line (SSL) described above may be represented as an upper selection line (USL), and the ground selection line (GSL) may be represented as a lower selection line.

[0051]

[0052] FIG. 2 is a plan view illustrating a structure of a three-dimensional flash memory according to one embodiment, FIG. 3 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, FIGS. 4 and 5 are plan views illustrating a structure of a three-dimensional flash memory according to another embodiment, FIGS. 6 and 7 are plan views illustrating a structure of a three-dimensional flash memory according to still another embodiment, and FIG. 8 is a plan view illustrating an enlarged area where vertical channel structures overlap each other in the structure of the three-dimensional flash memory illustrated in FIG. 7.

[0053] Referring to FIGS. 2 and 3, the substrate (SUB) may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0054] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0055] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0056] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked on the substrate (SUB).

[0057] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0058] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0059] Although not shown, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the longest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3). By means of the step structure, each of the stacked structures (ST) can have a thickness that decreases as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0060] Each of the interlayer insulating films (ILDs) may have a different thickness. For example, the lowermost and uppermost interlayer insulating films (ILDs) may have a smaller thickness than the other interlayer insulating films (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating films (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating films (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating films (ILDs) may be formed of silicon oxide.

[0061] Although each of the above-described stacked structures (ST) is described as including interlayer insulating films (ILDs), each of the stacked structures (ST) may include air gaps instead of interlayer insulating films (ILDs). In this case, the air gaps may be arranged alternately with the gate electrodes (EL1, EL2, EL3) like the interlayer insulating films (ILDs) to enable insulation between the gate electrodes (EL1, EL2, EL3).

[0062] A plurality of channel holes (CH) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a portion of each of the vertical channel structures (VS) being embedded within the substrate (SUB), but is not limited thereto, and may also be achieved by a lower surface of the vertical channel structures (VS) being in contact with an upper surface of the substrate (SUB). When a portion of each of the vertical channel structures (VS) is embedded within the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0063] Rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. For example, as illustrated in FIG. 2, rows of six vertical channel structures (VS) may penetrating one of the stacked structures (ST). However, the present invention is not limited thereto, and rows of less than six or more than seven vertical channel structures (VS) may penetrating one of the stacked structures (ST). In a pair of adjacent rows, the vertical channel structures (VS) corresponding to one row may be shifted in a first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent row. In a plan view, the vertical channel structures (VS) may be arranged in a zigzag shape along the first direction (D1). However, without being limited or restricted thereto, the vertical channel structures (VS) may also form an array arranged side by side in rows and columns.

[0064] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a pillar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). This is due to the limitation that the width in the first direction (D1) and the second direction (D2) decreases as it goes in the opposite direction of the third direction (D3) when the channel holes (CH) are etched. The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0065] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical filled pattern (VFP), and a conductive pad (PAD). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open bottom, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. The vertical filled pattern (VFP) may fill a space surrounded by the vertical channel pattern (VCP) and the conductive pad (PAD).

[0066] The data storage pattern (DSP) may cover the inner sidewall of each of the channel holes (CH), be in contact with the vertical channel pattern (VCP) on the inside, and be in contact with the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outside. Accordingly, regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) may, together with regions corresponding to the second gate electrodes (EL2) of the vertical channel pattern (VCP), form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1.

[0067] Although the drawing shows a structure in which the data storage pattern (DSP) is formed as a continuous and extended structure along the vertical direction (e.g., the third direction (D3)) like a vertical channel pattern (VCP), it is not limited thereto and may be implemented as a segmented structure in which multiple are formed and spaced apart only in areas corresponding to the gate electrodes (EL1, EL2, EL3).

[0068] The data storage pattern (DSP) can be configured to represent a binary data value or a multi-valued data value by trapping charges by a voltage applied through the second gate electrodes (EL2), or to represent a binary data value or a multi-valued data value by changing and maintaining the state of charges by a voltage applied through the second gate electrodes (EL2). For example, an ONO (tunnel insulating film-charge storage film-blocking insulating film) can be used as the data storage pattern (DSP) to implement a structure in which at least a portion of the vertical channel structures (VS) described below overlaps. However, the present invention is not limited thereto, and a ferroelectric film can also be used as the data storage pattern (DSP).

[0069] A vertical channel pattern (VCP) may cover an inner wall of a data storage pattern (DSP). The vertical channel pattern (VCP) may include a first portion (VCP1) and a second portion (VCP2) on the first portion (VCP1).

[0070] A first portion (VCP1) of the vertical channel pattern (VCP) may be provided at a lower portion of each of the channel holes (CH) and may be in contact with the substrate (SUB). The first portion (VCP1) of the vertical channel pattern (VCP) may be used to block, suppress, or minimize leakage current in each of the vertical channel structures (VS) and / or as an epitaxial pattern. The thickness of the first portion (VCP1) of the vertical channel pattern (VCP) may be, for example, greater than the thickness of the first gate electrode (EL1). A side wall of the first portion (VCP1) of the vertical channel pattern (VCP) may be surrounded by a data storage pattern (DSP). An upper surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located at a higher level than an upper surface of the first gate electrode (EL1). More specifically, the upper surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located between the upper surface of the first gate electrode (EL1) and the lower surface of the lowest one of the second gate electrodes (EL2). The lower surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located at a level lower than the upper surface of the substrate (SUB) (i.e., the lower surface of the lowest one of the interlayer insulating films (ILD). A part of the first part (VCP1) of the vertical channel pattern (VCP) may overlap with the first gate electrode (EL1) in the horizontal direction. Hereinafter, the horizontal direction means any direction extending on a plane parallel to the first direction (D1) and the second direction (D2).

[0071] A second portion (VCP2) of the vertical channel pattern (VCP) may extend in a third direction (D3) from an upper surface of the first portion (VCP1). The second portion (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical buried pattern (VFP), and may correspond to the second gate electrodes (EL2). Accordingly, the second portion (VCP2) of the vertical channel pattern (VCP) may form memory cells together with regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP), as described above.

[0072] The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be substantially coplanar with the upper surface of the vertical buried pattern (VFP). The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be located at a level higher than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be located between the upper surface and the lower surface of the third gate electrode (EL3).

[0073] The vertical channel pattern (VCP) may be formed of single-crystalline silicon or polysilicon so as to form or boost a channel by an applied voltage. However, without limitation or restriction thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material including at least one of In, Zn, or Ga having excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx series material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Therefore, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and can improve transistor characteristics (e.g., threshold voltage distribution and speed of program / read operation) of at least one of the gate electrodes (EL1, EL2, EL3), thereby improving electrical characteristics of the three-dimensional flash memory.

[0074] A vertical buried pattern (VFP) may be surrounded by a second portion (VCP2) of a vertical channel pattern (VCP). An upper surface of the vertical buried pattern (VFP) may be in contact with a conductive pad (PAD), and a lower surface of the vertical buried pattern (VFP) may be in contact with a first portion (VCP1) of the vertical channel pattern (VCP). The vertical buried pattern (VFP) may be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertical buried pattern (VFP) may be electrically floated from the substrate (SUB).

[0075] The vertical buried pattern (VFP) can be formed of a material that helps the diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical buried pattern (VFP) can be formed of a material with excellent charge or hole mobility. For example, the vertical buried pattern (VFP) can be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical buried pattern (VFP) can be formed of polysilicon doped with the same first conductivity type impurities as the substrate (SUB), for example, a P-type impurity. That is, the vertical buried pattern (VFP) can improve the electrical characteristics of the 3D flash memory, thereby increasing the speed of the memory operation.

[0076] Although the vertical channel structures (VS) are described as including a vertically embedded pattern (VFP), the present invention is not limited thereto and the vertically embedded pattern (VFP) may be omitted.

[0077] Additionally, each of the vertical channel structures (VS) may have a structure including a back gate (BG; not shown) instead of a vertical buried pattern (VFP).

[0078] In this case, the back gate (BG) may have a form that fills the inner space of the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP), and may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) for the purpose of applying voltage to memory cells. In addition, a back gate dielectric pattern (BGDP; not shown) may be interposed between the back gate (BG) and the vertical channel pattern (VCP).

[0079] Referring back to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0080] A conductive pad (PAD) may be provided on a top surface of a second part (VCP2) of a vertical channel pattern (VCP) and a top surface of a vertical buried pattern (VFP). The conductive pad (PAD) may be connected to an upper portion of the vertical channel pattern (VCP) and an upper portion of the vertical buried pattern (VFP). A side wall of the conductive pad (PAD) may be surrounded by a data storage pattern (DSP). An upper surface of the conductive pad (PAD) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating films (ILDs). A lower surface of the conductive pad (PAD) may be located at a level lower than an upper surface of the third gate electrode (EL3). More specifically, the lower surface of the conductive pad (PAD) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the conductive pad (PAD) may overlap the third gate electrode (EL3) in a horizontal direction.

[0081] The conductive pad (PAD) may be formed of a semiconductor or conductive material doped with impurities. For example, the conductive pad (PAD) may be formed of a semiconductor material doped with impurities different from those of the vertically buried pattern (VFP) (more precisely, impurities of a second conductive type (e.g., N-type) different from those of the first conductive type (e.g., P-type).

[0082] The challenge pad (PAD) can reduce the contact resistance between the bit line (BL) and the vertical channel pattern (VCP) (or vertical buried pattern (VFP)) described below.

[0083] Above, the vertical channel structures (VS) have been described as having a structure including a conductive pad (PAD), but they are not limited thereto and may have a structure in which the conductive pad (PAD) is omitted. In this case, since the conductive pad (PAD) is omitted from the vertical channel structures (VS), the vertical channel pattern (VCP) and the vertical buried pattern (VFP) may be formed to extend in the third direction (D3) so that the upper surfaces of each of the vertical channel patterns (VCP) and the vertical buried pattern (VFP) are substantially coplanar with the upper surfaces of each of the stacked structures (ST) (i.e., the upper surfaces of the uppermost of the interlayer insulating films (ILDs)). In addition, in this case, the bit line contact plug (BLPG) described later may be directly in contact with and electrically connected to the vertical channel pattern (VCP) instead of being indirectly electrically connected to the vertical channel pattern (VCP) through the conductive pad (PAD).

[0084] In addition, although the vertical channel pattern (VCP) has been described as having a structure including a first portion (VCP1) and a second portion (VCP2), it is not limited thereto and may have a structure in which the first portion (VCP1) is excluded. For example, the vertical channel pattern (VCP) may be provided between a vertical buried pattern (VFP) formed to extend to the substrate (SUB) and a data storage pattern (DSP) and may be formed to extend to the substrate (SUB) so as to contact the substrate (SUB). In this case, a lower surface of the vertical channel pattern (VCP) may be positioned at a level lower than an uppermost surface of the substrate (SUB) (a lower surface of the lowest of the interlayer insulating films (ILDs)), and an upper surface of the vertical channel pattern (VCP) may be substantially coplanar with an upper surface of the vertical buried pattern (VFP).

[0085] A separation trench (S-TR) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR) may be provided within a substrate (SUB) exposed by the separation trench (S-TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with a second conductivity type impurity (e.g., an N-type impurity). The common source region (CSR) may correspond to a common source line (CSL) of FIG. 1.

[0086] A common source plug (CSP) may be provided within a separation trench (S-TR). The common source plug (CSP) may be connected to a common source region (CSR). An upper surface of the common source plug (CSP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer dielectrics (ILDs). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which a width in a second direction (D2) increases as it goes in the third direction (D3).

[0087] Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided so as to face each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0088] However, without being limited or restricted thereto, the common source plug (CSP) may also be implemented in a form embedded within the substrate (SUB), such as a common source region (CSR). In this case, the isolation trench (S-TR) may be filled only with insulating spacers (SP), and in some cases, the isolation trench (S-TR) itself may be omitted.

[0089] A capping insulating film (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating films (ILD), an upper surface of the conductive pad (PAD), and an upper surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating films (ILD). A bit line contact plug (BLPG) electrically connected to the conductive pad (PAD) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0090] A bit line (BL) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0091] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a vertical channel pattern (VCP) included in the vertical channel structures (VS).

[0092] In the three-dimensional flash memory described above, each of the stacked structures (ST) can be referred to as a bar memory cell block including vertical channel structures (VS) that constitute a memory cell.

[0093] In each of the stacked structures (ST) constituting the memory cell block, an arbitrary space (ASS) having a large pitch can be secured so that an etching liquid or gas can smoothly flow in during the manufacturing process of the gate electrodes (EL1, EL2, EL3). The arbitrary space (ASS) means a virtual space including the same components (stacked components of each of the stacked structures (ST) (gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD)) as the remaining area excluding the vertical channel structures (VS) in the stacked structures (ST).

[0094] Accordingly, in each of the stacked structures (ST), which are memory cell blocks, vertical channel structures (VS) can be arranged in a planar asymmetrical structure in the horizontal direction (e.g., the first direction (D1) and the second direction (D2)) to secure an arbitrary space (ASS).

[0095] That is, the vertical channel structures (VS) can be arranged in a planar asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, as an arbitrary space (ASS) is secured within each of the stacked structures (ST), which are memory cell blocks.

[0096] Hereinafter, the arrangement of vertical channel structures (VS) in an asymmetrical structure on a plane within each of the stacked structures (ST), which are memory cell blocks, means that the rows or columns of the vertical channel structures (VS) on the plane of each of the stacked structures (ST), which are memory cell blocks, are arranged in an irregular pattern by an arbitrary space (ASS), and more simply, it means that the array of vertical channel structures (VS) within each of the stacked structures (ST), which are memory cell blocks, is separated into two or more by an arbitrary space (ASS).

[0097] The vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, may have an asymmetrical direction determined according to a direction of extension in a plane of an arbitrary space (ASS). For example, as illustrated in FIG. 2, when the arbitrary space (ASS) is formed to extend along a second direction (D2), the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, may have an asymmetrical structure by determining the asymmetrical direction in a first direction (D1) that is orthogonal to the second direction (D2) in which the arbitrary space (ASS) is formed to extend in a plane. For another example, as illustrated in FIG. 4, when an arbitrary space (ASS) is formed to extend along the first direction (D1), the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, may have an asymmetrical structure by determining an asymmetrical direction in a second direction (D2) orthogonal to the first direction (D1) in which the arbitrary space (ASS) extends on a plane. For another example, as illustrated in FIG. 5, when the arbitrary space (ASS) is implemented in a cross shape to extend in the first direction (D1) and the second direction (D2), the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, may have an asymmetrical structure by determining an asymmetrical direction in the first direction (D1) and the second direction (D2) orthogonal to the first direction (D1) and the second direction (D2) in which the arbitrary space (ASS) extends on a plane.

[0098] In addition, among the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, at least some of the vertical channel structures (VS) may be arranged in contact with each other in order to secure an arbitrary space (ASS) while improving the memory cell integration. For example, among the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, at least some of the vertical channel structures (VS) may be arranged in a state in which the data storage patterns (DSPs) corresponding to their respective outer walls are in contact with each other, as illustrated in FIG. 6. In this case, ONO may be used as the data storage pattern (DSP), and the blocking insulating films of the ONOs of at least some of the vertical channel structures (VS) may be in contact with each other.

[0099] Furthermore, among the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, at least some of the vertical channel structures (VS) may be arranged to overlap each other in order to secure an arbitrary space (ASS) while improving the memory cell integration. That is, among the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, at least some of the vertical channel structures (VS) may be arranged such that at least a portion of each of the vertical channel structures (VS) overlaps each other. For example, among the vertical channel structures (VS) arranged in an asymmetrical structure within each of the stacked structures (ST), which are memory cell blocks, at least some of the vertical channel structures (VS) may be arranged such that at least a portion of a data storage pattern (DSP) corresponding to each outer wall overlaps each other, as illustrated in FIGS. 7 and 8 . In this case, ONO is used as the data storage pattern (DSP), so that the blocking insulating films of each ONO of at least some of the vertical channel structures (VS) can overlap each other.

[0100] The contact and overlap structure between the described vertical channel structures (VS) can be prevented from affecting memory operation by implementing it so that only the blocking insulating film in the ONO contacts and overlaps.

[0101] A three-dimensional flash memory having such a structure can perform memory operations (program operations, read operations, and erase operations) based on a voltage applied to each of the cell strings (CSTR), a voltage applied to a string select line (SSL), a voltage applied to each of the word lines (WL0-WLn), a voltage applied to a ground select line (GSL), and a voltage applied to a common source line (CSL) (if a back gate (BG) is included, a voltage included in the back gate (BG)).

[0102] Below, a method for manufacturing a three-dimensional flash memory having the described structure is described.

[0103]

[0104] FIG. 9 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to embodiments.

[0105] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 8, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0106] In step (S910), the manufacturing system can prepare a semiconductor structure (SEMI-STR).

[0107] Here, the semiconductor structure (SEMI-STR) may include sacrificial layers (SAC) that are formed to extend in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) and are stacked while being spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and interlayer insulating layers (ILD) interposed between the sacrificial layers (SAC).

[0108] The semiconductor structure (SEMI-STR) is prepared through the existing manufacturing process of each of the sacrificial layers (SAC) and interlayer dielectric layers (ILD), and a detailed description thereof will be omitted.

[0109] In step (S920), the manufacturing system can form vertical channel structures (VS) in a vertical direction (e.g., in the third direction (D3)) in the semiconductor structure (SEMI-STR).

[0110] In particular, in step (S920), the manufacturing system can secure an arbitrary space (ASS) on a plane within the memory cell block so that an etching liquid or gas can flow in step (S930), thereby forming vertical channel structures included within the memory cell block by arranging them in a horizontally asymmetrical structure on a plane as the arbitrary space (ASS) on the plane is secured.

[0111] At this time, the asymmetry direction in the asymmetric structure of the vertical channel structures (VS) included in the memory cell block can be determined according to the direction of extension on the plane of an arbitrary space (ASS).

[0112] Additionally, in step (S920), the manufacturing system can arrange and form at least some of the vertical channel structures (VS) arranged in an asymmetrical structure within the memory cell block so that at least some of the vertical channel structures (VS) are in contact with each other.

[0113] Furthermore, in step (S920), the manufacturing system can arrange and form at least some of the vertical channel structures (VS) such that at least a portion of each of the at least some of the vertical channel structures (VS) overlaps with each other.

[0114] For example, as the ONO is used as a data storage pattern (DSP) for each of at least some of the vertical channel structures (VS), at least some of the vertical channel structures (VS) can be arranged and formed such that at least a portion of the blocking insulating film included in the ONO overlaps with each other.

[0115] In step (S920), each of the vertical channel structures (VS) is formed, and the formation process of each of the vertical channel structures (VS) is the same as the existing one, except that it has the characteristics of the arrangement of the vertical channel structures (VS).

[0116] In step (S930), the manufacturing system can remove the sacrificial layers (SAC) by introducing an etchant or gas.

[0117] As described above, since an arbitrary space (ASS) that increases the pitch of the vertical channel structures (VS) is secured within the memory cell block, the etching liquid or gas can smoothly flow into the memory cell block to remove the sacrificial layers (SAC).

[0118] In step (S940), the manufacturing system can form gate electrodes (EL1, EL2, EL3) in spaces from which sacrificial layers (SAC) have been removed. A deposition process such as ALD or CVD can be used in the process of forming the gate electrodes (EL1, EL2, EL3).

[0119]

[0120] FIG. 10 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0121] Referring to FIG. 12, an electronic system (1000) including a three-dimensional flash memory according to embodiments may include a main substrate (1001), a controller (1002) mounted on the main substrate (1001), one or more semiconductor packages (1003), and a DRAM (1004).

[0122] The semiconductor package (1003) and DRAM (1004) can be interconnected with the controller (1002) by wiring patterns (1005) provided on the main substrate (1001).

[0123] The main board (1001) may include a connector (1006) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1006) may vary depending on the communication interface between the electronic system (1000) and the external host.

[0124] The electronic system (1000) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (1000) may operate by power supplied from an external host, for example, through a connector (1006). The electronic system (1000) may further include a PMIC (Power Management Integrated Circuit) that distributes power supplied from the external host to a controller (1002) and a semiconductor package (1003).

[0125] The controller (1002) can write data to the semiconductor package (1003) or read data from the semiconductor package (1003), and can improve the operating speed of the electronic system (1000).

[0126] The DRAM (1004) may be a buffer memory to mitigate the speed difference between the semiconductor package (1003), which is a data storage space, and an external host. The DRAM (1004) included in the electronic system (1000) may also function as a type of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package (1003). When the electronic system (1000) includes the DRAM (1004), the controller (1002) may further include a DRAM controller for controlling the DRAM (1004) in addition to the NAND controller for controlling the semiconductor package (1003).

[0127] A semiconductor package (1003) may include first and second semiconductor packages (1003a, 1003b) that are spaced apart from each other. The first and second semiconductor packages (1003a, 1003b) may each be a semiconductor package including a plurality of semiconductor chips (1020). Each of the first and second semiconductor packages (1003a, 1003b) may include a package substrate (1010), semiconductor chips (1020) on the package substrate (1010), adhesive layers (1030) disposed on a lower surface of each of the semiconductor chips (1020), connection structures (1040) that electrically connect the semiconductor chips (1020) and the package substrate (1010), and a molding layer (1050) that covers the semiconductor chips (1020) and the connection structures (1040) on the package substrate (1010).

[0128] The package substrate (1010) may be a printed circuit board including package upper pads (1011). Each of the semiconductor chips (1020) may include input / output pads (1021). Each of the semiconductor chips (1020) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 4. More specifically, each of the semiconductor chips (1020) may include a gate stack structure (1022) and memory channel structures (1023). The memory channel structures (1023) may correspond to the vertical channel structures (VS) described above.

[0129] The connection structures (1040) may be, for example, bonding wires that electrically connect the input / output pads (1021) and the package upper pads (1011). Accordingly, in each of the first and second semiconductor packages (1003a, 1003b), the semiconductor chips (1020) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (1011) of the package substrate (1010). According to embodiments, in each of the first and second semiconductor packages (1003a, 1003b), the semiconductor chips (1020) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (1040).

[0130] Unlike the illustration, the controller (1002) and the semiconductor chips (1020) may be included in one package. The controller (1002) and the semiconductor chips (1020) may be mounted on a separate interposer substrate different from the main substrate (1001), and the controller (1002) and the semiconductor chips (1020) may be connected to each other by wiring provided on the interposer substrate.

[0131]

[0132] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0133] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Gate electrodes that are formed to extend horizontally and are stacked while being spaced apart from each other in the vertical direction; and Vertical channel structures formed extending in the vertical direction through the gate electrodes Including, The above vertical channel structures are, A three-dimensional flash memory characterized in that the memory cell blocks are arranged in a plane-wise asymmetrical structure in the horizontal direction.

2. In paragraph 1, The vertical channel structures included within the memory cell block are: A three-dimensional flash memory characterized in that the gate electrodes are arranged in an asymmetrical structure, and an arbitrary space on the plane is secured within the memory cell block so that an etching liquid or gas can be introduced during the manufacturing process.

3. In paragraph 2, The vertical channel structures included within the memory cell block are: A three-dimensional flash memory characterized in that it is arranged in an asymmetric structure in which an asymmetric direction is determined according to the direction of extension on the plane of the arbitrary space.

4. In paragraph 1, At least some of the vertical channel structures among the vertical channel structures arranged in the asymmetrical structure within the memory cell block, A three-dimensional flash memory characterized in that the elements are arranged to contact each other.

5. In paragraph 4, At least some of the above vertical channel structures, A three-dimensional flash memory characterized in that at least a portion of each of the at least some vertical channel structures is arranged to overlap each other.

6. In paragraph 5, At least some of the above vertical channel structures, A three-dimensional flash memory characterized in that at least a portion of the blocking insulating film included in each of the at least some vertical channel structures is arranged to overlap each other.

7. A step of preparing a semiconductor structure including sacrificial layers that are formed to extend horizontally and are stacked while being spaced apart from each other in the vertical direction; A step of forming vertical channel structures in the vertical direction in the semiconductor structure; A step of removing the sacrificial layers by introducing an etching liquid or gas; and A step of forming gate electrodes in spaces where the above sacrificial layers have been removed. Including, The step of forming the above vertical channel structures is: A method for manufacturing a three-dimensional flash memory, characterized in that the step of forming the vertical channel structures by arranging them in a horizontally asymmetrical plane within a memory cell block.

8. In paragraph 7, The step of forming the vertical channel structures by arranging them in a planar asymmetrical structure in the horizontal direction is as follows: A step of securing an arbitrary space on the plane within the memory cell block so that an etching liquid or gas can be introduced in the step of removing the sacrificial layers; and A step of forming and arranging the vertical channel structures included in the memory cell block in the asymmetrical structure as the arbitrary space on the plane is secured. A method for manufacturing a three-dimensional flash memory, characterized by including:

9. In paragraph 8, The step of forming the vertical channel structures by arranging them in the asymmetrical structure is as follows: A method for manufacturing a three-dimensional flash memory, characterized in that the vertical channel structures included in the memory cell block are arranged and formed in an asymmetric structure in which an asymmetric direction is determined according to the direction of extension on the plane of the arbitrary space.

10. In paragraph 7, The step of forming the vertical channel structures by arranging them in a planar asymmetrical structure in the horizontal direction is as follows: A method for manufacturing a three-dimensional flash memory, characterized in that at least some of the vertical channel structures arranged in the asymmetrical structure within the memory cell block are arranged and formed so that at least some of the vertical channel structures are in contact with each other.

11. In paragraph 10, The step of forming the vertical channel structures by arranging them in a planar asymmetrical structure in the horizontal direction is as follows: A method for manufacturing a three-dimensional flash memory, characterized in that at least some of the vertical channel structures are arranged and formed so that at least a portion of each of the at least some of the vertical channel structures overlaps with each other.

12. In paragraph 11, The step of forming the vertical channel structures by arranging them in a planar asymmetrical structure in the horizontal direction is as follows: A method for manufacturing a three-dimensional flash memory, characterized in that at least some of the vertical channel structures are arranged and formed so that at least a portion of the blocking insulating film included in each of the at least some of the vertical channel structures overlaps with each other.

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