Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a base, and M rows and 2N columns of sub-pixels (P), 2M scan signal lines (Gate), and N+1 data signal lines (Data) arranged on the base. The i-th row of sub-pixels are located between the (2i-1)-th scan signal line and the 2i-th scan signal line and are electrically connected to the (2i-1)-th scan signal line and the 2i-th scan signal line, respectively. The (2j-1)-th column of sub-pixels and the 2j-th column of sub-pixels are located between the j-th data signal line and the (j+1)-th data signal line, the (2j-1)-th column of sub-pixels are electrically connected to the j-th data signal line and the (j+1)-th data signal line, respectively, and the 2j-th column of sub-pixels are electrically connected to the j-th data signal line and the (j+1)-th data signal line, respectively. The k-th column of sub-pixels and the (k+1)-th column of sub-pixels in at least one row of sub-pixels are connected to different scan signal lines.

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Liquid Crystal Display (LCD) has been rapidly developed due to its small size, low power consumption and no radiation. The liquid crystal display panel includes a thin film transistor array (TFT) substrate and a color filter (CF) substrate in a cell. Liquid crystal (LC) molecules are arranged between the array substrate and the color filter substrate. By controlling the common electrode and the pixel electrode, an electric field for driving the liquid crystal to deflect is formed to realize gray scale display.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate and M rows of 2N columns of sub-pixels, 2M scanning signal lines and N+1 data signal lines disposed on the substrate;

[0006] The ith row of sub-pixels is located between the 2i-1th scanning signal line and the 2i scanning signal line, and is electrically connected to the 2i-1th scanning signal line and the 2i scanning signal line, respectively;

[0007] The 2j-1th column of sub-pixels and the 2jth column of sub-pixels are located between the jth data signal line and the j+1th data signal line, the 2j-1th column of sub-pixels is electrically connected to the jth data signal line and the j+1th data signal line, respectively, and the 2jth column of sub-pixels is electrically connected to the jth data signal line and the j+1th data signal line, respectively;

[0008] In at least one row of sub-pixels, the kth column of sub-pixels and the k+1th column of sub-pixels are connected to different scanning signal lines, 1≤i≤M, 1≤j≤N, and 1≤k≤2N-1.

[0009] In an exemplary embodiment, in at least one row of sub-pixels, at least two adjacent columns of sub-pixels are connected to the same scanning signal line, and at least two adjacent columns of sub-pixels are connected to different scanning signal lines.

[0010] In an example embodiment, the sub-pixels in the 2j-1th column and the odd-numbered row are electrically connected to the jth data signal line, and the sub-pixels in the 2j-1th column and the even-numbered row are electrically connected to the (j+1)th data signal line.

[0011] The sub-pixels in the 2jth column and the odd-numbered row are electrically connected to the jth data signal line, and the sub-pixels in the 2jth column and the even-numbered row are electrically connected to the (j+1)th data signal line.

[0012] In an example embodiment, the sub-pixels in at least one of the 8m-7th row, the 8m-5th row, the 8m-3rd row and the 8m-1st row are connected to different scanning signal lines, 1≤m≤M / 8.

[0013] In an example embodiment, the sub-pixels in the 8m-7th row and the 12n-11th column are respectively electrically connected to the 16m-14th scanning signal line and the 6n-5th data signal line, the sub-pixels in the 8m-7th row and the 12n-10th column are respectively electrically connected to the 16m-15th scanning signal line and the 6n-5th data signal line, the sub-pixels in the 8m-7th row and the 12n-9th column are respectively electrically connected to the 16m-14th scanning signal line and the 6n-4th data signal line, the sub-pixels in the 8m-7th row and the 12n-8th column are respectively electrically connected to the 16m-15th scanning signal line and the 6n-4th data signal line, the sub-pixels in the 8m-7th row and the 12n-7th column are respectively electrically connected to the 16m-14th scanning signal line and the 6n-3rd data signal line, the sub-pixels in the 8m-7th row and the 12n-6th column are respectively electrically connected to the 16m-15th scanning signal line and the 6n-3rd data signal line, the sub-pixels in the 8m-7th row and the 12n-5th column are respectively electrically connected to the 16m-14th scanning signal line and the 6n-2nd data signal line, the sub-pixels in the 8m-7th row and the 12n-4th column are respectively electrically connected to the 16m-15th scanning signal line and the 6n-2nd data signal line, the sub-pixels in the 8m-7th row and the 12n-3rd column are respectively electrically connected to the 16m-14th scanning signal line and the 6n-1st data signal line, the sub-pixels in the 8m-7th row and the 12n-2nd column are respectively electrically connected to the 16m-15th scanning signal line and the 6n-1st data signal line, the sub-pixels in the 8m-7th row and the 12n-1st column are respectively electrically connected to the 16m-14th scanning signal line and the 6nth data signal line, and the sub-pixels in the 8m-7th row and the 12nth column are respectively electrically connected to the 16m-15th scanning signal line and the 6nth data signal line.

[0014] The sub-pixels in rows 8m-5 and columns 12n-11 are electrically connected to the 16m-10 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in rows 8m-5 and columns 12n-10 are also electrically connected to the 16m-11 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in rows 8m-5 and columns 12n-9 are also electrically connected to the 16m-10 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-5 and columns 12n-8 are also electrically connected to the 16m-11 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-5 and columns 12n-7 are also electrically connected to the 16m-10 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-5 and columns 12n-6 are also electrically connected to the 16m-11 scan signal lines and the 6n-3 data signal lines, respectively. Electrical connections are made as follows: the sub-pixel in row 8m-5, column 12n-5 is electrically connected to the 16m-10 scan signal line and the 6n-2 data signal line, the sub-pixel in row 8m-5, column 12n-4 is electrically connected to the 16m-11 scan signal line and the 6n-2 data signal line, the sub-pixel in row 8m-5, column 12n-3 is electrically connected to the 16m-10 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-5, column 12n-2 is electrically connected to the 16m-11 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-5, column 12n-1 is electrically connected to the 16m-10 scan signal line and the 6n data signal line, and the sub-pixel in row 8m-5, column 12n is electrically connected to the 16m-11 scan signal line and the 6n data signal line.

[0015] The 8th row of 12n-11th column sub-pixels are respectively connected with the 16th row of m-6th scanning signal line and the 6th row of n-5th data signal line, the 8th row of 12n-10th column sub-pixels are respectively connected with the 16th row of m-7th scanning signal line and the 6th row of n-5th data signal line, the 8th row of 12n-9th column sub-pixels are respectively connected with the 16th row of m-6th scanning signal line and the 6th row of n-4th data signal line, the 8th row of 12n-8th column sub-pixels are respectively connected with the 16th row of m-7th scanning signal line and the 6th row of n-4th data signal line, the 8th row of 12n-7th column sub-pixels are respectively connected with the 16th row of m-6th scanning signal line and the 6th row of n-3rd data signal line, the 8th row of 12n-6th column sub-pixels are respectively connected with the 16th row of m-7th scanning signal line and the 6th row of n-3rd data signal line, the 8th row of 12n-5th column sub-pixels are respectively connected with the 16th row of m-6th scanning signal line and the 6th row of n-2nd data signal line, the 8th row of 12n-4th column sub-pixels are respectively connected with the 16th row of m-7th scanning signal line and the 6th row of n-2nd data signal line, the 8th row of 12n-3rd column sub-pixels are respectively connected with the 16th row of m-6th scanning signal line and the 6th row of n-1st data signal line, the 8th row of 12n-2nd column sub-pixels are respectively connected with the 16th row of m-7th scanning signal line and the 6th row of n-1st data signal line, the 8th row of 12n-1st column sub-pixels are respectively connected with the 16th row of m-6th scanning signal line and the 6th row of n data signal line, the 8th row of 12nth column sub-pixels are respectively connected with the 16th row of m-7th scanning signal line and the 6th row of n data signal line;

[0016] The 8m-1th row and 12n-11th column sub-pixels are electrically connected with the 16m-2th scanning signal line and the 6n-5th data signal line respectively, the 8m-1th row and 12n-10th column sub-pixels are electrically connected with the 16m-3th scanning signal line and the 6n-5th data signal line respectively, the 8m-1th row and 12n-9th column sub-pixels are electrically connected with the 16m-2th scanning signal line and the 6n-4th data signal line respectively, the 8m-1th row and 12n-8th column sub-pixels are electrically connected with the 16m-3th scanning signal line and the 6n-4th data signal line respectively, the 8m-1th row and 12n-7th column sub-pixels are electrically connected with the 16m-2th scanning signal line and the 6n-3th data signal line respectively, the 8m-1th row and 12n-6th column sub-pixels are electrically connected with the 16m-3th scanning signal line and the 6n-3th data signal line respectively, the 8m-1th row and 12n-5th column sub-pixels are electrically connected with the 16m-2th scanning signal line and the 6n-2th data signal line respectively, the 8m-1th row and 12n-4th column sub-pixels are electrically connected with the 16m-3th scanning signal line and the 6n-2th data signal line respectively, the 8m-1th row and 12n-3th column sub-pixels are electrically connected with the 16m-2th scanning signal line and the 6n-1th data signal line respectively, the 8m-1th row and 12n-2th column sub-pixels are electrically connected with the 16m-3th scanning signal line and the 6n-1th data signal line respectively, the 8m-1th row and 12n-1th column sub-pixels are electrically connected with the 16m-2th scanning signal line and the 6nth data signal line respectively, and the 8m-1th row and 12nth column sub-pixels are electrically connected with the 16m-3th scanning signal line and the 6nth data signal line respectively, 1≤n≤N / 6.

[0017] In the exemplary embodiment, at least two adjacent sub-pixels in at least one row of sub-pixels in the 8m-6th row, the 8m-4th row, the 8m-2nd row and the 8mth row of sub-pixels are connected with the same scanning signal line, and at least two adjacent sub-pixels are connected with different scanning signal lines, 1≤m≤M / 8.

[0018] In the example embodiment, the 8m-6 row 12n-11 column sub-pixels are respectively electrically connected with the 16m-13 scanning signal line and the 6n-4 data signal line, the 8m-6 row 12n-10 column sub-pixels are respectively electrically connected with the 16m-12 scanning signal line and the 6n-4 data signal line, the 8m-6 row 12n-9 column sub-pixels are respectively electrically connected with the 16m-13 scanning signal line and the 6n-3 data signal line, the 8m-6 row 12n-8 column sub-pixels are respectively electrically connected with the 16m-12 scanning signal line and the 6n-3 data signal line, the 8m-6 row 12n-7 column sub-pixels are respectively electrically connected with the 16m-13 scanning signal line and the 6n-2 data signal line, the 8m-6 row 12n-6 column sub-pixels are respectively electrically connected with the 16m-12 scanning signal line and the 6n-2 data signal line, the 8m-6 row 12n-5 column sub-pixels are respectively electrically connected with the 16m-13 scanning signal line and the 6n-1 data signal line, the 8m-6 row 12n-4 column sub-pixels are respectively electrically connected with the 16m-12 scanning signal line and the 6n-1 data signal line, the 8m-6 row 12n-3 column sub-pixels are respectively electrically connected with the 16m-12 scanning signal line and the 6n data signal line, the 8m-6 row 12n-2 column sub-pixels are respectively electrically connected with the 16m-13 scanning signal line and the 6n data signal line, the 8m-6 row 12n-1 column sub-pixels are respectively electrically connected with the 16m-13 scanning signal line and the 6n+1 data signal line, and the 8m-6 row 12n column sub-pixels are respectively electrically connected with the 16m-12 scanning signal line and the 6n+1 data signal line.

[0019] The 8th row of 12n-11th column sub-pixels are electrically connected with the 16th row of m-9th scanning signal line and the 6th row of n-4th data signal line respectively, the 8th row of 12n-10th column sub-pixels are electrically connected with the 16th row of m-8th scanning signal line and the 6th row of n-4th data signal line respectively, the 8th row of 12n-9th column sub-pixels are electrically connected with the 16th row of m-9th scanning signal line and the 6th row of n-3rd data signal line respectively, the 8th row of 12n-8th column sub-pixels are electrically connected with the 16th row of m-8th scanning signal line and the 6th row of n-3rd data signal line respectively, the 8th row of 12n-7th column sub-pixels are electrically connected with the 16th row of m-9th scanning signal line and the 6th row of n-2nd data signal line respectively, the 8th row of 12n-6th column sub-pixels are electrically connected with the 16th row of m-8th scanning signal line and the 6th row of n-2nd data signal line respectively, the 8th row of 12n-5th column sub-pixels are electrically connected with the 16th row of m-9th scanning signal line and the 6th row of n-1st data signal line respectively, the 8th row of 12n-4th column sub-pixels are electrically connected with the 16th row of m-8th scanning signal line and the 6th row of n-1st data signal line respectively, the 8th row of 12n-3rd column sub-pixels are electrically connected with the 16th row of m-8th scanning signal line and the 6th row of n data signal line respectively, the 8th row of 12n-2nd column sub-pixels are electrically connected with the 16th row of m-9th scanning signal line and the 6th row of n data signal line respectively, the 8th row of 12n-1st column sub-pixels are electrically connected with the 16th row of m-9th scanning signal line and the 6th row of n+1st data signal line respectively, the 8th row of 12n column sub-pixels are electrically connected with the 16th row of m-8th scanning signal line and the 6th row of n+1st data signal line respectively;

[0020] The 8th row of 12n-11th column sub-pixels are respectively connected with the 16th row of m-5th scanning signal line and the 6th row of n-4th data signal line, the 8th row of 12n-10th column sub-pixels are respectively connected with the 16th row of m-4th scanning signal line and the 6th row of n-4th data signal line, the 8th row of 12n-9th column sub-pixels are respectively connected with the 16th row of m-4th scanning signal line and the 6th row of n-3rd data signal line, the 8th row of 12n-8th column sub-pixels are respectively connected with the 16th row of m-5th scanning signal line and the 6th row of n-3rd data signal line, the 8th row of 12n-7th column sub-pixels are respectively connected with the 16th row of m-5th scanning signal line and the 6th row of n-2nd data signal line, the 8th row of 12n-6th column sub-pixels are respectively connected with the 16th row of m-4th scanning signal line and the 6th row of n-2nd data signal line, the 8th row of 12n-5th column sub-pixels are respectively connected with the 16th row of m-5th scanning signal line and the 6th row of n-1st data signal line, the 8th row of 12n-4th column sub-pixels are respectively connected with the 16th row of m-4th scanning signal line and the 6th row of n-1st data signal line, the 8th row of 12n-3rd column sub-pixels are respectively connected with the 16th row of m-5th scanning signal line and the 6th row of n data signal line, the 8th row of 12n-2nd column sub-pixels are respectively connected with the 16th row of m-4th scanning signal line and the 6th row of n data signal line, the 8th row of 12n-1st column sub-pixels are respectively connected with the 16th row of m-5th scanning signal line and the 6th row of n+1st data signal line, the 8th row of 12n column sub-pixels are respectively connected with the 16th row of m-4th scanning signal line and the 6th row of n+1st data signal line;

[0021] The 8th row 12n-11th column sub-pixels are electrically connected with the 16th row-1st scanning signal line and the 6th row-4th data signal line respectively, the 8th row 12n-10th column sub-pixels are electrically connected with the 16th row scanning signal line and the 6th row-4th data signal line respectively, the 8th row 12n-9th column sub-pixels are electrically connected with the 16th row scanning signal line and the 6th row-3rd data signal line respectively, the 8th row 12n-8th column sub-pixels are electrically connected with the 16th row-1st scanning signal line and the 6th row-3rd data signal line respectively, the 8th row 12n-7th column sub-pixels are electrically connected with the 16th row-1st scanning signal line and the 6th row-2nd data signal line respectively, the 8th row 12n-6th column sub-pixels are electrically connected with the 16th row scanning signal line and the 6th row-2nd data signal line respectively, the 8th row 12n-5th column sub-pixels are electrically connected with the 16th row-1st scanning signal line and the 6th row-1st data signal line respectively, the 8th row 12n-4th column sub-pixels are electrically connected with the 16th row scanning signal line and the 6th row-1st data signal line respectively, the 8th row 12n-3rd column sub-pixels are electrically connected with the 16th row-1st scanning signal line and the 6th row data signal line respectively, the 8th row 12n-2nd column sub-pixels are electrically connected with the 16th row scanning signal line and the 6th row data signal line respectively, the 8th row 12n-1st column sub-pixels are electrically connected with the 16th row-1st scanning signal line and the 6th row+1st data signal line respectively, the 8th row 12n column sub-pixels are electrically connected with the 16th row scanning signal line and the 6th row+1st data signal line respectively, 1≤n≤N / 6.

[0022] In an example embodiment, the sub-pixels include: first sub-pixels to third sub-pixels;

[0023] The 3r-2nd column sub-pixel is the first sub-pixel, the 3r-1st column sub-pixel is the second sub-pixel, and the 3r column sub-pixel is the third sub-pixel, 1≤r≤2N / 3.

[0024] In an example embodiment, at least one of the first scanning signal line to the 2Mth scanning signal line extends at least partially along a first direction, and the first scanning signal line to the 2Mth scanning signal line are arranged in turn along a second direction, the first direction and the second direction intersect;

[0025] The display substrate further includes: a driving circuit, the driving circuit includes: 2M cascaded shift registers;

[0026] The 4t-3rd stage shift register is electrically connected with the 4t-3rd scanning signal line, the 4t-2nd stage shift register is electrically connected with the 4t-2nd scanning signal line, the 4t-1st stage shift register is electrically connected with the 4tth scanning signal line, the 4th stage shift register is electrically connected with the 4t-1st scanning signal line, 1≤t≤M / 2.

[0027] In an example embodiment, the at least one stage of shift register comprises a signal output end, the signal output end of the at least one stage of shift register is electrically connected with the scan signal line to which the shift register is connected;

[0028] The time period of the signal output by the signal output end of the a-th stage of shift register at least partially overlaps with the time period of the signal output by the signal output end of at least one of the a+1-th stage of shift register and the a+2-th stage of shift register, and does not overlap with the time period of the signal output by the signal output end of the a+3-th stage of shift register, 1≤a≤2M-3.

[0029] In an example embodiment, the at least one stage of shift register further comprises a signal input end and a reset signal end, and the display substrate further comprises an initial signal line;

[0030] The signal input end in the first stage of shift register and the second stage of shift register is electrically connected with the initial signal line, the signal output end of the b-th stage of shift register is electrically connected with the signal input end of the b+2-th stage of shift register, and the reset signal end of the c-th stage of shift register is electrically connected with the signal output end of the c+3-th stage of shift register, 1≤b≤2M-4, 1≤c≤2M-3.

[0031] In an example embodiment, the at least one stage of shift register further comprises a clock signal end, and the display substrate further comprises H clock signal lines;

[0032] At least part of at least one of the H clock signal lines extends along the second direction, the clock signal end of the w*H-H+h-th stage of shift register is electrically connected with the h-th clock signal line, 1≤w≤2M / H, 1≤h≤H.

[0033] In an example embodiment, the first stage of shift register to the 2M-th stage of shift register are arranged in sequence along the second direction;

[0034] The display substrate further comprises 2M output connection lines, the 2M output connection lines correspond to the 2M stages of shift register one by one, and at least one of the output connection lines is electrically connected with the corresponding stage of shift register and the scan signal line to which the corresponding stage of shift register is connected;

[0035] At least part of at least one of the fourth t-3th output connection line and the fourth t-2th output connection line extends along the first direction, at least part of the fourth t-1th output connection line extends along a third direction, at least part of the fourth tth output connection line extends along a fourth direction, and a projection of the fourth t-1th output connection line on the substrate at least partially overlaps with a projection of the fourth tth output connection line on the substrate, the third direction intersects at least one of the first direction and the second direction, the fourth direction intersects at least one of the first direction and the second direction, and the third direction intersects the fourth direction.

[0036] In an example embodiment, the first clock signal line to the Hth clock signal line are arranged in sequence along a direction away from the display area.

[0037] In an example embodiment, the first stage shift register to the 2Mth stage shift register are arranged along the first direction, the fourth t-2th stage shift register is located between the fourth t-3th stage shift register and the fourth tth stage shift register, and the fourth t-1th stage shift register is located between the fourth tth stage shift register and the fourth t+1th stage shift register.

[0038] In an example embodiment, the display substrate further comprises: 2M output connection lines, the 2M output connection lines corresponding to the 2M stage shift registers one by one, and at least one output connection line is electrically connected to the corresponding shift register and the scan signal line connected to the corresponding shift register.

[0039] At least one of the 2M output connection lines extends at least partially along the first direction.

[0040] In an example embodiment, the fourth t-3th clock signal line is located on a side of the fourth t-2th clock signal line close to the display area, the fourth t-2th clock signal line is located between the fourth t-3th clock signal line and the fourth tth clock signal line, and the fourth t-1th clock signal line is located on a side of the fourth tth clock signal line away from the display area.

[0041] In an example embodiment, further comprising: a plurality of switch transistors disposed on the substrate, the plurality of switch transistors corresponding to the plurality of sub-pixels one by one, and at least one sub-pixel comprises: oppositely disposed first and second electrodes, and a projection of the first electrode on the substrate at least partially overlaps with a projection of the second electrode on the substrate.

[0042] The control electrode of the switch transistor is electrically connected to the scan signal line connected to the corresponding sub-pixel, the first electrode of the switch transistor is electrically connected to the first electrode of the sub-pixel, and the second electrode of the switch transistor is electrically connected to the data signal line connected to the sub-pixel.

[0043] In an example embodiment, further comprising: a circuit structure layer disposed on the substrate, the switch transistor, the scan signal line, the data signal line, the first electrode and the second electrode are disposed on the circuit structure layer, the switch transistor comprises: an active layer, a gate electrode, a first electrode and a second electrode;

[0044] The circuit structure layer comprises: a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a third conductive layer, a second insulating layer and a fourth conductive layer;

[0045] The first conductive layer at least comprises: a second electrode of at least one sub-pixel;

[0046] The second conductive layer at least comprises: a gate electrode of at least one switch transistor and the scan signal line;

[0047] The semiconductor layer at least comprises: an active layer of at least one switch transistor;

[0048] The third conductive layer at least comprises: a first electrode and a second electrode of at least one switch transistor and the data signal line;

[0049] The fourth conductive layer at least comprises: a first electrode of at least one sub-pixel.

[0050] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate and a counter substrate, the display substrate is disposed opposite to the counter substrate.

[0051] In an example embodiment, the display substrate comprises an out-light side and an in-light side;

[0052] The counter substrate is located on one of the in-light side or the out-light side of the display substrate.

[0053] In an example embodiment, the counter substrate comprises: a second substrate and a color filter layer disposed on the second substrate, the color filter layer is located on a side of the second substrate close to the display substrate;

[0054] The color filter layer comprises: a plurality of filters, the plurality of filters correspond one-to-one to a plurality of sub-pixels on the display substrate, and the orthographic projection of at least one filter on the substrate at least partially overlaps the orthographic projection of at least one sub-pixel on the substrate.

[0055] In a third aspect, the present disclosure further provides a preparation method of a display substrate, the display substrate comprises: a plurality of sub-pixels, a plurality of switch transistors, a plurality of scan signal lines and a plurality of data signal lines, the switch transistor comprises: an active layer, a gate electrode, a first electrode and a second electrode, the method comprises:

[0056] Providing a substrate;

[0057] forming a first conductive layer on the substrate by a patterning process, the first conductive layer comprising: a second electrode of at least one sub-pixel;

[0058] forming a second conductive layer on the first conductive layer by a patterning process, the second conductive layer comprising: a gate electrode of at least one switching transistor and the scan signal line;

[0059] forming a semiconductor layer and a third conductive layer on the second conductive layer by a patterning process, the semiconductor layer comprising at least: an active layer of at least one switching transistor, the third conductive layer comprising at least: a first electrode and a second electrode of at least one switching transistor and the data signal line;

[0060] forming a fourth conductive layer on the third conductive layer by a patterning process, the fourth conductive layer comprising: a first electrode of at least one sub-pixel;

[0061] The ith row of sub-pixels is located between the 2i-1th scan signal line and the 2ith scan signal line, and is electrically connected to the 2i-1th scan signal line and the 2ith scan signal line respectively, the 2j-1th column of sub-pixels and the 2jth column of sub-pixels are located between the jth data signal line and the j+1th data signal line, the 2j-1th column of sub-pixels is electrically connected to the jth data signal line and the j+1th data signal line respectively, and the 2jth column of sub-pixels is electrically connected to the jth data signal line and the j+1th data signal line respectively;

[0062] The kth column of sub-pixels and the k+1th column of sub-pixels in at least one row of sub-pixels are connected to different scan signal lines, 1≤i≤M, 1≤j≤N, 1≤k≤2N-1, M is the total number of rows of sub-pixels, and 2N is the total number of columns of sub-pixels.

[0063] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0064] SUMMARY

[0065] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and do not limit the present disclosure.

[0066] FIG. 1 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0067] FIG. 2 is a timing sequence of a data signal line connected to one pixel structure;

[0068] FIG. 3 is a schematic diagram of the connection of a plurality of scan signal lines and a driving circuit;

[0069] FIG. 4 is an equivalent circuit diagram of a shift register;

[0070] FIG. 5 is a timing diagram of the operation of the shift register provided in FIG. 4;

[0071] FIG. 6 is a timing diagram of the scan signal lines connected to a pixel structure;

[0072] FIG. 7 is a schematic diagram of a cascade of shift registers, part 1;

[0073] FIG. 8 is a schematic diagram of a cascade of shift registers, part 2;

[0074] FIG. 9 is a timing diagram of the signal lines connected to a driving circuit over two display frames;

[0075] FIG. 10 is a cross-sectional view of a display substrate;

[0076] FIG. 11 is a schematic diagram of FIG. 10 after forming a first conductive layer pattern;

[0077] FIG. 12 is a schematic diagram of FIG. 10 after forming a second conductive layer pattern;

[0078] FIG. 13 is a schematic diagram of FIG. 10 after forming a third conductive layer pattern;

[0079] FIG. 14 is a schematic diagram of FIG. 10 after forming a second insulating layer pattern;

[0080] FIG. 15 is a schematic diagram of FIG. 10 after forming a fourth conductive layer pattern;

[0081] FIG. 16 is a schematic diagram of a display device provided by an embodiment of the present disclosure, part 1;

[0082] FIG. 17 is a schematic diagram of a display device provided by an embodiment of the present disclosure, part 2.

[0083] DETAILED DESCRIPTION

[0084] The present disclosure describes a plurality of embodiments, but the description is exemplary rather than limiting, and more embodiments and implementations can be possible within the scope of the embodiments described in the present disclosure for those of ordinary skill in the art. Although a number of possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment can be utilized with any other feature or element of any other embodiment, or can replace any other feature or element in any other embodiment.

[0085] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed herein can also be combined with any conventional feature or element to form a technical solution defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other technical solutions to form another technical solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be implemented alone or in any appropriate combination. Therefore, the embodiments are not limited other than as set forth in the claims and their equivalents. In addition, various modifications and changes can be made within the scope of protection of the appended claims.

[0086] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "comprise", "comprise", and similar terms mean that the elements or objects before the term encompass the elements or objects listed after the term and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute positions of the objects described change, the relative positional relationships may

[0087] The liquid crystal display device includes a plurality of sub-pixels and a plurality of transistors, each sub-pixel being driven to emit light by a transistor. The sub-pixel includes a pixel electrode, a common electrode, and a liquid crystal layer disposed between the pixel electrode and the common electrode. When displaying a sky blue picture, the liquid crystal display device will have a column of bright sub-pixels and a column of dark sub-pixels, which will appear as a vertical stripe defect from the human eye, wherein the sky blue picture refers to a gray scale picture in which green and blue are mixed together, which can be a picture with a gray scale value of 127, or can be a picture with a gray scale value of 255, thereby affecting the display effect of the display device.

[0088] FIG. 1 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 1, the display substrate provided by the embodiment of the present disclosure can include a substrate, and M rows and 2N columns of sub-pixels P, 2M scanning signal lines Gate, and N+1 data signal lines Data disposed on the substrate.

[0089] As shown in FIG. 1, the i-th row of sub-pixels is located between the (2i-1)-th scan signal line and the 2i-th scan signal line, and is electrically connected to the (2i-1)-th scan signal line and the 2i-th scan signal line, respectively. Exemplarily, the first row of sub-pixels is located between the first scan signal line Gate1 and the second scan signal line Gate2, and is electrically connected to the first scan signal line Gate1 and the second scan signal line Gate2, respectively, the second row of sub-pixels is located between the third scan signal line Gate3 and the fourth scan signal line Gate4, and is electrically connected to the third scan signal line Gate3 and the fourth scan signal line Gate4, respectively, the third row of sub-pixels is located between the fifth scan signal line Gate5 and the sixth scan signal line Gate6, and is electrically connected to the fifth scan signal line Gate5 and the sixth scan signal line Gate6, respectively, the fourth row of sub-pixels is located between the seventh scan signal line Gate7 and the eighth scan signal line Gate8, and is electrically connected to the seventh scan signal line Gate7 and the eighth scan signal line Gate8, respectively, the fifth row of sub-pixels is located between the ninth scan signal line Gate9 and the tenth scan signal line Gate10, and is electrically connected to the ninth scan signal line Gate9 and the tenth scan signal line Gate10, respectively, the sixth row of sub-pixels is located between the eleventh scan signal line Gate10 and the twelfth scan signal line Gate12, and is electrically connected to the eleventh scan signal line Gate10 and the twelfth scan signal line Gate12, respectively, the seventh row of sub-pixels is located between the thirteenth scan signal line Gate13 and the fourteenth scan signal line Gate14, and is electrically connected to the thirteenth scan signal line Gate13 and the fourteenth scan signal line Gate14, respectively, the eighth row of sub-pixels is located between the fifteenth scan signal line Gate15 and the sixteenth scan signal line Gate16, and is electrically connected to the fifteenth scan signal line Gate15 and the sixteenth scan signal line Gate16, respectively, and so on.

[0090] As shown in FIG. 1, the 2j-1th column sub-pixels and the 2jth column sub-pixels are located between the jth data signal line and the (j+1)th data signal line, the 2j-1th column sub-pixels are electrically connected to the jth data signal line and the (j+1)th data signal line respectively, and the 2jth column sub-pixels are electrically connected to the jth data signal line and the (j+1)th data signal line respectively. Exemplarily, the first column sub-pixels and the second column sub-pixels are located between the first data signal line Data1 and the second data signal line Data2, the first column sub-pixels are electrically connected to the first data signal line Data1 and the second data signal line Data2 respectively, and the second column sub-pixels are electrically connected to the first data signal line Data1 and the second data signal line Data2 respectively, the third column sub-pixels and the fourth column sub-pixels are located between the second data signal line Data2 and the third data signal line Data3, the third column sub-pixels are electrically connected to the second data signal line Data2 and the third data signal line Data3 respectively, and the fourth column sub-pixels are electrically connected to the second data signal line Data2 and the third data signal line Data3 respectively, the fifth column sub-pixels and the sixth column sub-pixels are located between the third data signal line Data3 and the fourth data signal line Data4, the fifth column sub-pixels are electrically connected to the third data signal line Data3 and the fourth data signal line Data4 respectively, and the sixth column sub-pixels are electrically connected to the third data signal line Data3 and the fourth data signal line Data4 respectively, the seventh column sub-pixels and the eighth column sub-pixels are located between the fourth data signal line Data4 and the fifth data signal line Data5, the seventh column sub-pixels are electrically connected to the fourth data signal line Data4 and the fifth data signal line Data5 respectively, and the eighth column sub-pixels are electrically connected to the fourth data signal line Data4 and the fifth data signal line Data5 respectively, the ninth column sub-pixels and the tenth column sub-pixels are located between the fifth data signal line Data5 and the sixth data signal line Data6, the ninth column sub-pixels are electrically connected to the fifth data signal line Data5 and the sixth data signal line Data6 respectively, and the tenth column sub-pixels are electrically connected to the fifth data signal line Data5 and the sixth data signal line Data6 respectively, the eleventh column sub-pixels and the twelfth column sub-pixels are located between the sixth data signal line Data6 and the seventh data signal line Data7, the eleventh column sub-pixels are electrically connected to the sixth data signal line Data6 and the seventh data signal line Data7 respectively, and the twelfth column sub-pixels are electrically connected to the sixth data signal line Data6 and the seventh data signal line Data7 respectively, and so on.

[0091] As shown in Figure 1, in at least one row of sub-pixels, the sub-pixels in the k-th column and the (k+1)-th column are connected by different scan signal lines, where 1≤i≤M, 1≤j≤N, and 1≤k≤2N-1. Figure 1 illustrates this using examples of connecting the sub-pixels in the k-th column and the (k+1)-th column in the first, third, fifth, and seventh rows of sub-pixels.

[0092] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and conductive foil. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0093] In an exemplary embodiment, the display substrate includes a display area and a non-display area located at least on one side of the display area. Subpixels P, scan signal lines Gate and Data signal lines Data are at least partially located within the display area.

[0094] In an exemplary embodiment, the display substrate further includes a source driver chip located in the non-display area. The source driver chip is disposed on a flexible circuit board and is electrically connected to multiple data signal lines, and is configured to provide data signals to the multiple data signal lines.

[0095] In an exemplary embodiment, this disclosure reduces the number of data signal lines by electrically connecting each row of subpixels to two scan signal lines, thereby reducing the area occupied by the source driver chip and lowering the cost of the display substrate.

[0096] This disclosure avoids the vertical stripe defect that occurs when the display device on which the display substrate is located displays a sky blue image by connecting different scan signal lines to the k-th column sub-pixel and the (k+1)-th column sub-pixel in at least one row of sub-pixels, thereby improving the display effect of the display device on which the display substrate is located.

[0097] In an exemplary embodiment, as shown in FIG1, at least two columns of adjacent sub-pixels in at least one row of sub-pixels are connected to the same scan signal line, and at least two columns of adjacent sub-pixels are connected to different scan signal lines. FIG1 illustrates this using the example of at least two columns of adjacent sub-pixels in the second row, fourth row, sixth row, and eighth row of sub-pixels being connected to the same scan signal line, and at least two columns of adjacent sub-pixels being connected to different scan signal lines.

[0098] In an exemplary embodiment, as shown in FIG1, the sub-pixel of the odd-numbered row in column 2j-1 is electrically connected to the j-th data signal line, and the sub-pixel of the even-numbered row in column 2j-1 is electrically connected to the (j+1)-th data signal line. For example, the sub-pixel of the odd-numbered row in the first column is electrically connected to the first data signal line Data1; the sub-pixel of the even-numbered row in the first column is electrically connected to the second data signal line Data2; the sub-pixel of the odd-numbered row in the third column is electrically connected to the second data signal line Data2; the sub-pixel of the even-numbered row in the third column is electrically connected to the third data signal line Data3; the sub-pixel of the odd-numbered row in the fifth column is electrically connected to the third data signal line Data3; the sub-pixel of the even-numbered row in the fifth column is electrically connected to the fourth data signal line Data4; the sub-pixel of the odd-numbered row in the seventh column is electrically connected to the fourth data signal line Data4; the sub-pixel of the even-numbered row in the seventh column is electrically connected to the fifth data signal line Data5; the sub-pixel of the odd-numbered row in the ninth column is electrically connected to the fifth data signal line Data5; the sub-pixel of the even-numbered row in the ninth column is electrically connected to the sixth data signal line Data6; the sub-pixel of the odd-numbered row in the eleventh column is electrically connected to the sixth data signal line Data6; and the sub-pixel of the even-numbered row in the eleventh column is electrically connected to the seventh data signal line Data7.

[0099] In an exemplary embodiment, as shown in FIG1, the sub-pixel of the odd-numbered row in the 2j column is electrically connected to the j-th data signal line, and the sub-pixel of the even-numbered row in the 2j column is electrically connected to the (j+1)-th data signal line. For example, the sub-pixel of the odd-numbered row in the second column is electrically connected to the first data signal line Data1; the sub-pixel of the even-numbered row in the second column is electrically connected to the second data signal line Data2; the sub-pixel of the odd-numbered row in the fourth column is electrically connected to the second data signal line Data2; the sub-pixel of the even-numbered row in the fourth column is electrically connected to the third data signal line Data3; the sub-pixel of the odd-numbered row in the sixth column is electrically connected to the third data signal line Data3; the sub-pixel of the even-numbered row in the sixth column is electrically connected to the fourth data signal line Data4; the sub-pixel of the odd-numbered row in the eighth column is electrically connected to the fourth data signal line Data4; the sub-pixel of the even-numbered row in the eighth column is electrically connected to the fifth data signal line Data5; the sub-pixel of the odd-numbered row in the tenth column is electrically connected to the fifth data signal line Data5; the sub-pixel of the even-numbered row in the tenth column is electrically connected to the sixth data signal line Data6; the sub-pixel of the odd-numbered row in the twelfth column is electrically connected to the sixth data signal line Data6; and the sub-pixel of the even-numbered row in the twelfth column is electrically connected to the seventh data signal line Data7.

[0100] In an exemplary embodiment, the k-th column sub-pixel and the k+1-th column sub-pixel in at least one of the sub-pixels in the 8m-7, 8m-5, 8m-3, and 8m-1 rows are connected to different scan signal lines, where 1≤m≤M / 8.

[0101] In an exemplary embodiment, as shown in FIG1, the sub-pixels in rows 8m-7 and columns 12n-11 are electrically connected to the 16m-14 scan signal lines and the 6n-5 data signal lines, respectively; the sub-pixels in rows 8m-7 and columns 12n-10 are electrically connected to the 16m-15 scan signal lines and the 6n-5 data signal lines, respectively; and the sub-pixels in rows 8m-7 and columns 12n-9 are electrically connected to the 16m-14 scan signal lines and the 6n-5 data signal lines, respectively. The 6n-4th data signal line is electrically connected. The sub-pixel in the 8m-7th row and the 12n-8th column is electrically connected to the 16m-15th scan signal line and the 6n-4th data signal line, respectively. The sub-pixel in the 8m-7th row and the 12n-7th column is electrically connected to the 16m-14th scan signal line and the 6n-3th data signal line, respectively. The sub-pixel in the 8m-7th row and the 12n-6th column is electrically connected to the 16m-15th scan signal line and the 6n-4th data signal line, respectively. -3 data signal lines are electrically connected. The sub-pixel in row 8m-7, column 12n-5 is electrically connected to the 16m-14 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-7, column 12n-4 is electrically connected to the 16m-15 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-7, column 12n-3 is electrically connected to the 16m-14 scan signal line and the 6n-1 data signal line respectively. The data signal lines are electrically connected. The sub-pixel in row 8m-7, column 12n-2 is electrically connected to the 16m-15 scan signal line and the 6n-1 data signal line, respectively. The sub-pixel in row 8m-7, column 12n-1 is electrically connected to the 16m-14 scan signal line and the 6n data signal line, respectively. The sub-pixel in row 8m-7, column 12n is electrically connected to the 16m-15 scan signal line and the 6n data signal line, respectively. Where 1 ≤ n ≤ N / 6.For example, when m=1 and n=1, the sub-pixels in the first row and first column are electrically connected to the second scan signal line Gate2 and the first data signal line Data1, respectively; the sub-pixels in the first row and second column are electrically connected to the first scan signal line Gate1 and the first data signal line Data1, respectively; the sub-pixels in the first row and third column are electrically connected to the second scan signal line Gate2 and the second data signal line Data2, respectively; the sub-pixels in the first row and fourth column are electrically connected to the first scan signal line Gate1 and the second data signal line Data2, respectively; the sub-pixels in the first row and fifth column are electrically connected to the second scan signal line Gate2 and the third data signal line Data3, respectively; and the sub-pixels in the first row and sixth column are electrically connected to the first scan signal line Gate1 and the third data signal line Data3, respectively. 3. Electrical connections: The sub-pixel in the seventh column of the first row is electrically connected to the second scan signal line Gate2 and the fourth data signal line Data4, respectively; the sub-pixel in the eighth column of the first row is electrically connected to the first scan signal line and the (6n-2)th data signal line Data4, respectively; the sub-pixel in the ninth column of the first row is electrically connected to the second scan signal line Gate2 and the fifth data signal line Data5, respectively; the sub-pixel in the tenth column of the first row is electrically connected to the first scan signal line Gate1 and the fifth data signal line Data5, respectively; the sub-pixel in the eleventh column of the first row is electrically connected to the second scan signal line Gate2 and the sixth data signal line Data6, respectively; the sub-pixel in the twelfth column of the first row is electrically connected to the first scan signal line Gate1 and the sixth data signal line Data6, respectively, and so on.

[0102] In an exemplary embodiment, as shown in FIG1, the sub-pixels in the 8m-5th row and the 12n-11th column are electrically connected to the 16m-10th scan signal line and the 6n-5th data signal line, respectively; the sub-pixels in the 8m-5th row and the 12n-10th column are electrically connected to the 16m-11th scan signal line and the 6n-5th data signal line, respectively; and the sub-pixels in the 8m-5th row and the 12n-9th column are electrically connected to the 16m-10th scan signal line and the 6n-5th data signal line, respectively. The 6n-4th data signal line is electrically connected. The sub-pixel in the 8m-5th row and the 12n-8th column is electrically connected to the 16m-11th scan signal line and the 6n-4th data signal line, respectively. The sub-pixel in the 8m-5th row and the 12n-7th column is electrically connected to the 16m-10th scan signal line and the 6n-3th data signal line, respectively. The sub-pixel in the 8m-5th row and the 12n-6th column is electrically connected to the 16m-11th scan signal line and the 6n-4th data signal line, respectively. -3 data signal lines are electrically connected. The sub-pixel in row 8m-5, column 12n-5 is electrically connected to the 16m-10 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-5, column 12n-4 is electrically connected to the 16m-11 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-5, column 12n-3 is electrically connected to the 16m-10 scan signal line and the 6n-1 data signal line respectively. The data signal lines are electrically connected. The sub-pixel in row 8m-5 and column 12n-2 is electrically connected to the scan signal line 16m-11 and the data signal line 6n-1, respectively. The sub-pixel in row 8m-5 and column 12n-1 is electrically connected to the scan signal line 16m-10 and the data signal line 6n, respectively. The sub-pixel in row 8m-5 and column 12n is electrically connected to the scan signal line 16m-11 and the data signal line 6n, respectively.For example, when m=1 and n=1, the sub-pixels in the first column of the third row are electrically connected to the sixth scan signal line Gate6 and the first data signal line Data1, respectively; the sub-pixels in the second column of the third row are electrically connected to the fifth scan signal line Gate5 and the first data signal line Data1, respectively; the sub-pixels in the third column of the third row are electrically connected to the sixth scan signal line Gate6 and the second data signal line Data2, respectively; the sub-pixels in the fourth column of the third row are electrically connected to the fifth scan signal line Gate5 and the second data signal line Data2, respectively; the sub-pixels in the fifth column of the third row are electrically connected to the sixth scan signal line Gate6 and the third data signal line Data3, respectively; and the sub-pixels in the sixth column of the third row are electrically connected to the fifth scan signal line Gate5 and the third data signal line Data3, respectively. Electrical connections are made as follows: the sub-pixel in the third row and seventh column is electrically connected to the sixth scan signal line (Gate6) and the fourth data signal line (Data4); the sub-pixel in the third row and eighth column is electrically connected to the fifth scan signal line (Gate5) and the fourth data signal line (Data4); the sub-pixel in the third row and ninth column is electrically connected to the sixth scan signal line (Gate6) and the fifth data signal line (Data5); the sub-pixel in the third row and tenth column is electrically connected to the fifth scan signal line (Gate5) and the fifth data signal line (Data5); the sub-pixel in the third row and eleventh column is electrically connected to the sixth scan signal line (Gate6) and the sixth data signal line (Data6); the sub-pixel in the third row and twelfth column is electrically connected to the fifth scan signal line (Gate5) and the sixth data signal line (Data6), and so on.

[0103] In an exemplary embodiment, as shown in FIG1, the sub-pixels in the 12n-11th column of the 8m-3rd row are electrically connected to the 16m-6th scan signal line and the 6n-5th data signal line, respectively; the sub-pixels in the 12n-10th column of the 8m-3rd row are electrically connected to the 16m-7th scan signal line and the 6n-5th data signal line, respectively; the sub-pixels in the 12n-9th column of the 8m-3rd row are electrically connected to the 16m-6th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-8th column of the 8m-3rd row are electrically connected to the 16m-7th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-7th column of the 8m-3rd row are electrically connected to the 16m-6th scan signal line and the 6n-3th data signal line, respectively; and the sub-pixels in the 12n-6th column of the 8m-3rd row are electrically connected to the 16m-7th scan signal line and the 6n-5th data signal line, respectively. -3 data signal lines are electrically connected. The sub-pixel in row 8m-3, column 12n-5 is electrically connected to the 16m-6 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-3, column 12n-4 is electrically connected to the 16m-7 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-3, column 12n-3 is electrically connected to the 16m-6 scan signal line and the 6n-1 data signal line respectively. The sub-pixel in row 8m-3, column 12n-2 is electrically connected to the 16m-7 scan signal line and the 6n-1 data signal line respectively. The sub-pixel in row 8m-3, column 12n-1 is electrically connected to the 16m-6 scan signal line and the 6n data signal line respectively. The sub-pixel in row 8m-3, column 12n is electrically connected to the 16m-7 scan signal line and the 6n data signal line respectively.For example, when m=1 and n=1, the sub-pixels in the first column of the fifth row are electrically connected to the tenth scan signal line Gate10 and the first data signal line Data1, respectively; the sub-pixels in the second column of the fifth row are electrically connected to the ninth scan signal line Gate9 and the first data signal line Data1, respectively; the sub-pixels in the third column of the fifth row are electrically connected to the tenth scan signal line Gate10 and the second data signal line Data2, respectively; the sub-pixels in the fourth column of the fifth row are electrically connected to the ninth scan signal line Gate9 and the second data signal line Data2, respectively; the sub-pixels in the fifth column of the fifth row are electrically connected to the tenth scan signal line Gate10 and the third data signal line Data3, respectively; and the sub-pixels in the sixth column of the fifth row are electrically connected to the ninth scan signal line Gate9 and the third data signal line Data3, respectively. Electrically connected, the sub-pixel in the fifth row and seventh column is electrically connected to the tenth scan signal line Gate10 and the fourth data signal line Data4, respectively; the sub-pixel in the fifth row and eighth column is electrically connected to the ninth scan signal line Gate9 and the fourth data signal line Data4, respectively; the sub-pixel in the fifth row and ninth column is electrically connected to the tenth scan signal line Gate10 and the fifth data signal line Data5, respectively; the sub-pixel in the fifth row and tenth column is electrically connected to the ninth scan signal line Gate9 and the fifth data signal line Data5, respectively; the sub-pixel in the fifth row and eleventh column is electrically connected to the tenth scan signal line Gate10 and the sixth data signal line Data6, respectively; the sub-pixel in the fifth row and twelfth column is electrically connected to the ninth scan signal line Gate9 and the sixth data signal line Data6, respectively, and so on.

[0104] In an exemplary embodiment, as shown in FIG1, the sub-pixels in the 12n-11th column of the 8m-1st row are electrically connected to the 16m-2th scan signal line and the 6n-5th data signal line, respectively; the sub-pixels in the 12n-10th column of the 8m-1st row are electrically connected to the 16m-3th scan signal line and the 6n-5th data signal line, respectively; the sub-pixels in the 12n-9th column of the 8m-1st row are electrically connected to the 16m-2th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-8th column of the 8m-1st row are electrically connected to the 16m-3th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-7th column of the 8m-1st row are electrically connected to the 16m-2th scan signal line and the 6n-3th data signal line, respectively; and the sub-pixels in the 12n-6th column of the 8m-1st row are electrically connected to the 16m-3th scan signal line and the 6n-5th data signal line, respectively. -3 data signal lines are electrically connected. The sub-pixel in row 8m-1, column 12n-5 is electrically connected to the 16m-2 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-1, column 12n-4 is electrically connected to the 16m-3 scan signal line and the 6n-2 data signal line respectively. The sub-pixel in row 8m-1, column 12n-3 is electrically connected to the 16m-2 scan signal line and the 6n-1 data signal line respectively. The sub-pixel in row 8m-1, column 12n-1 is electrically connected to the 16m-2 scan signal line and the 6n-1 data signal line respectively. The sub-pixel in row 8m-1, column 12n-1 is electrically connected to the 16m-2 scan signal line and the 6n data signal line respectively. The sub-pixel in row 8m-1, column 12n is electrically connected to the 16m-3 scan signal line and the 6n data signal line respectively.For example, when m=1 and n=1, the sub-pixels in the first column of the seventh row are electrically connected to the fourteenth scan signal line Gate14 and the first data signal line Data1, respectively; the sub-pixels in the second column of the seventh row are electrically connected to the thirteenth scan signal line Gate13 and the first data signal line Data1, respectively; the sub-pixels in the third column of the seventh row are electrically connected to the fourteenth scan signal line Gate14 and the second data signal line Data2, respectively; the sub-pixels in the fourth column of the seventh row are electrically connected to the thirteenth scan signal line Gate13 and the second data signal line Data2, respectively; the sub-pixels in the fifth column of the seventh row are electrically connected to the fourteenth scan signal line Gate14 and the third data signal line Data3, respectively; and the sub-pixels in the sixth column of the seventh row are electrically connected to the thirteenth scan signal line Gate13 and the third data signal line Data3, respectively. Electrically connected, the sub-pixel in the seventh row and seventh column is electrically connected to the fourteenth scan signal line Gate14 and the fourth data signal line Data4, respectively; the sub-pixel in the seventh row and eighth column is electrically connected to the thirteenth scan signal line Gate13 and the fourth data signal line Data4, respectively; the sub-pixel in the seventh row and ninth column is electrically connected to the fourteenth scan signal line Gate14 and the fifth data signal line Data5, respectively; the sub-pixel in the seventh row and tenth column is electrically connected to the thirteenth scan signal line Gate13 and the fifth data signal line Data5, respectively; the sub-pixel in the seventh row and eleventh column is electrically connected to the fourteenth scan signal line Gate14 and the sixth data signal line Data6, respectively; the sub-pixel in the seventh row and twelfth column is electrically connected to the thirteenth scan signal line Gate13 and the sixth data signal line Data6, respectively, and so on.

[0105] In an exemplary embodiment, at least two columns of adjacent sub-pixels in at least one row of sub-pixels in the 8m-6th row, the 8m-4th row, the 8m-2nd row, and the 8mth row are connected to the same scan signal line, and at least two columns of adjacent sub-pixels are connected to different scan signal lines, where 1≤m≤M / 8.

[0106] In an exemplary embodiment, as shown in FIG1, the sub-pixels in the 12n-11th column of the 8m-6th row are electrically connected to the 16m-13th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-10th column of the 8m-6th row are electrically connected to the 16m-12th scan signal line and the 6n-4th data signal line, respectively; and the sub-pixels in the 12n-9th column of the 8m-6th row are electrically connected to the 16m-13th scan signal line and the 6n-4th data signal line, respectively. The 6n-3 data signal line is electrically connected. The sub-pixel in the 8m-6 row and 12n-8 column is electrically connected to the 16m-12 scan signal line and the 6n-3 data signal line, respectively. The sub-pixel in the 8m-6 row and 12n-7 column is electrically connected to the 16m-13 scan signal line and the 6n-2 data signal line, respectively. The sub-pixel in the 8m-6 row and 12n-6 column is electrically connected to the 16m-12 scan signal line and the 6n-3 data signal line, respectively. -2 data signal lines are electrically connected. The sub-pixel in row 8m-6, column 12n-5 is electrically connected to the 16m-13 scan signal line and the 6n-1 data signal line, respectively. The sub-pixel in row 8m-6, column 12n-4 is electrically connected to the 16m-12 scan signal line and the 6n-1 data signal line, respectively. The sub-pixel in row 8m-6, column 12n-3 is electrically connected to the 16m-12 scan signal line and the 6n data signal line, respectively. The signal lines are electrically connected. The sub-pixel in row 8m-6, column 12n-2 is electrically connected to the 16m-13 scan signal line and the 6n data signal line, respectively. The sub-pixel in row 8m-6, column 12n-1 is electrically connected to the 16m-13 scan signal line and the 6n+1 data signal line, respectively. The sub-pixel in row 8m-6, column 12n is electrically connected to the 16m-12 scan signal line and the 6n+1 data signal line, respectively.For example, when m=1 and n=1, the sub-pixels in the first column of the second row are electrically connected to the third scan signal line Gate3 and the second data signal line Data2, respectively; the sub-pixels in the second column of the second row are electrically connected to the fourth scan signal line Gate4 and the second data signal line Data2, respectively; the sub-pixels in the third column of the second row are electrically connected to the third scan signal line Gate3 and the third data signal line Data3, respectively; the sub-pixels in the fourth column of the second row are electrically connected to the fourth scan signal line Gate4 and the third data signal line Data3, respectively; the sub-pixels in the fifth column of the second row are electrically connected to the third scan signal line Gate3 and the fourth data signal line Data4, respectively; and the sub-pixels in the sixth column of the second row are electrically connected to the fourth scan signal line Gate4 and the fourth data signal line Data4, respectively. The sub-pixels in the second row and seventh column are electrically connected to the third scan signal line (Gate3) and the fifth data signal line (Data5), respectively. The sub-pixels in the second row and eighth column are electrically connected to the fourth scan signal line (Gate4) and the fifth data signal line (Data5), respectively. The sub-pixels in the second row and ninth column are electrically connected to the fourth scan signal line (Gate4) and the sixth data signal line (Data6), respectively. The sub-pixels in the second row and tenth column are electrically connected to the third scan signal line (Gate3) and the sixth data signal line (Data6), respectively. The sub-pixels in the second row and eleventh column are electrically connected to the third scan signal line (Gate3) and the seventh data signal line (Data7), respectively. The sub-pixels in the second row and twelfth column are electrically connected to the fourth scan signal line (Gate4) and the seventh data signal line (Data7), respectively, and so on.

[0107] In an exemplary embodiment, as shown in FIG1, the sub-pixels in the 12n-11th column of the 8m-4th row are electrically connected to the 16m-9th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-10th column of the 8m-4th row are electrically connected to the 16m-8th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-9th column of the 8m-4th row are electrically connected to the 16m-9th scan signal line and the 6n-3th data signal line, respectively; the sub-pixels in the 12n-8th column of the 8m-4th row are electrically connected to the 16m-8th scan signal line and the 6n-3th data signal line, respectively; the sub-pixels in the 12n-7th column of the 8m-4th row are electrically connected to the 16m-9th scan signal line and the 6n-2th data signal line, respectively; and the sub-pixels in the 12n-6th column of the 8m-4th row are electrically connected to the 16m-8th scan signal line and the 6n-4th data signal line, respectively. -2 data signal lines are electrically connected. The sub-pixel in row 8m-4, column 12n-5 is electrically connected to the scan signal line 16m-9 and the data signal line 6n-1 respectively. The sub-pixel in row 8m-4, column 12n-4 is electrically connected to the scan signal line 16m-8 and the data signal line 6n-1 respectively. The sub-pixel in row 8m-4, column 12n-3 is electrically connected to the scan signal line 16m-8 and the data signal line 6n respectively. The sub-pixel in row 8m-4, column 12n-2 is electrically connected to the scan signal line 16m-9 and the data signal line 6n respectively. The sub-pixel in row 8m-4, column 12n-1 is electrically connected to the scan signal line 16m-9 and the data signal line 6n+1 respectively. The sub-pixel in row 8m-4, column 12n is electrically connected to the scan signal line 16m-8 and the data signal line 6n+1 respectively.For example, when m=1 and n=1, the sub-pixels in the first column of the fourth row are electrically connected to the seventh scan signal line Gate7 and the second data signal line Data2, respectively; the sub-pixels in the second column of the fourth row are electrically connected to the eighth scan signal line Gate8 and the second data signal line Data2, respectively; the sub-pixels in the third column of the fourth row are electrically connected to the seventh scan signal line Gate7 and the third data signal line Data3, respectively; the sub-pixels in the fourth column of the fourth row are electrically connected to the eighth scan signal line Gate8 and the third data signal line Data3, respectively; the sub-pixels in the fifth column of the fourth row are electrically connected to the seventh scan signal line Gate7 and the fourth data signal line Data4, respectively; and the sub-pixels in the sixth column of the fourth row are electrically connected to the eighth scan signal line Gate8 and the fourth data signal line Data4, respectively. Electrical connections are made as follows: the sub-pixel in the fourth row and seventh column is electrically connected to the seventh scan signal line (Gate7) and the fifth data signal line (Data5); the sub-pixel in the fourth row and eighth column is electrically connected to the eighth scan signal line (Gate8) and the fifth data signal line (Data5); the sub-pixel in the fourth row and ninth column is electrically connected to the eighth scan signal line (Gate8) and the sixth data signal line (Data6); the sub-pixel in the fourth row and tenth column is electrically connected to the seventh scan signal line (Gate7) and the sixth data signal line (Data6); the sub-pixel in the fourth row and eleventh column is electrically connected to the seventh scan signal line (Gate7) and the seventh data signal line (Data7); the sub-pixel in the fourth row and twelfth column is electrically connected to the eighth scan signal line (Gate8) and the seventh data signal line (Data7), and so on.

[0108] In an exemplary embodiment, as shown in FIG1, the sub-pixels in the 12n-11th column of the 8m-2th row are electrically connected to the 16m-5th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-10th column of the 8m-2th row are electrically connected to the 16m-4th scan signal line and the 6n-4th data signal line, respectively; the sub-pixels in the 12n-9th column of the 8m-2th row are electrically connected to the 16m-4th scan signal line and the 6n-3th data signal line, respectively; the sub-pixels in the 12n-8th column of the 8m-2th row are electrically connected to the 16m-5th scan signal line and the 6n-3th data signal line, respectively; the sub-pixels in the 12n-7th column of the 8m-2th row are electrically connected to the 16m-5th scan signal line and the 6n-2th data signal line, respectively; and the sub-pixels in the 12n-6th column of the 8m-2th row are electrically connected to the 16m-4th scan signal line and the 6n-4th data signal line, respectively. -2 data signal lines are electrically connected. The sub-pixel in row 8m-2, column 12n-5 is electrically connected to the 16m-5 scan signal line and the 6n-1 data signal line respectively. The sub-pixel in row 8m-2, column 12n-4 is electrically connected to the 16m-4 scan signal line and the 6n-1 data signal line respectively. The sub-pixel in row 8m-2, column 12n-3 is electrically connected to the 16m-5 scan signal line and the 6n data signal line respectively. The sub-pixel in row 8m-2, column 12n-2 is electrically connected to the 16m-4 scan signal line and the 6n data signal line respectively. The sub-pixel in row 8m-2, column 12n-1 is electrically connected to the 16m-5 scan signal line and the 6n+1 data signal line respectively. The sub-pixel in row 8m-2, column 12n is electrically connected to the 16m-4 scan signal line and the 6n+1 data signal line respectively.For example, when m=1 and n=1, the sub-pixels in the first column of the sixth row are electrically connected to the eleventh scan signal line Gate11 and the second data signal line Data2, respectively; the sub-pixels in the second column of the sixth row are electrically connected to the twelfth scan signal line Gate12 and the second data signal line Data2, respectively; the sub-pixels in the third column of the sixth row are electrically connected to the twelfth scan signal line Gate12 and the third data signal line Data3, respectively; the sub-pixels in the fourth column of the sixth row are electrically connected to the eleventh scan signal line Gate11 and the third data signal line Data3, respectively; the sub-pixels in the fifth column of the sixth row are electrically connected to the eleventh scan signal line Gate11 and the fourth data signal line Data4, respectively; and the sub-pixels in the sixth column of the sixth row are electrically connected to the twelfth scan signal line Gate12 and the fourth data signal line Data4, respectively. The sub-pixels in the sixth row and seventh column are electrically connected to the eleventh scan signal line (Gate11) and the fifth data signal line (Data5), respectively. The sub-pixels in the sixth row and eighth column are electrically connected to the twelfth scan signal line (Gate12) and the fifth data signal line (Data5), respectively. The sub-pixels in the sixth row and ninth column are electrically connected to the eleventh scan signal line (Gate11) and the sixth data signal line (Data6), respectively. The sub-pixels in the sixth row and tenth column are electrically connected to the twelfth scan signal line (Gate12) and the sixth data signal line (Data6), respectively. The sub-pixels in the sixth row and eleventh column are electrically connected to the eleventh scan signal line (Gate11) and the seventh data signal line (Data7), respectively. The sub-pixels in the sixth row and twelfth column are electrically connected to the twelfth scan signal line (Gate12) and the seventh data signal line (Data7), respectively, and so on.

[0109] In an exemplary embodiment, as shown in FIG1, the sub-pixels in the 8m row and 12n-11 columns are electrically connected to the 16m-1 scan signal line and the 6n-4 data signal line, respectively; the sub-pixels in the 8m row and 12n-10 columns are electrically connected to the 16m scan signal line and the 6n-4 data signal line, respectively; the sub-pixels in the 8m row and 12n-9 columns are electrically connected to the 16m scan signal line and the 6n-3 data signal line, respectively; the sub-pixels in the 8m row and 12n-8 columns are electrically connected to the 16m-1 scan signal line and the 6n-3 data signal line, respectively; the sub-pixels in the 8m row and 12n-7 columns are electrically connected to the 16m-1 scan signal line and the 6n-2 data signal line, respectively; and the sub-pixels in the 8m row and 12n-6 columns are electrically connected to the 16m scan signal line and the 6n-4 data signal line, respectively. -2 data signal lines are electrically connected. The sub-pixel in the 8m row and 12n-5 column is electrically connected to the 16m-1 scan signal line and the 6n-1 data signal line respectively. The sub-pixel in the 8m row and 12n-4 column is electrically connected to the 16m scan signal line and the 6n-1 data signal line respectively. The sub-pixel in the 8m row and 12n-3 column is electrically connected to the 16m-1 scan signal line and the 6n data signal line respectively. The sub-pixel in the 8m row and 12n-2 column is electrically connected to the 16m scan signal line and the 6n data signal line respectively. The sub-pixel in the 8m row and 12n-1 column is electrically connected to the 16m-1 scan signal line and the 6n+1 data signal line respectively. The sub-pixel in the 8m row and 12n column is electrically connected to the 16m scan signal line and the 6n+1 data signal line respectively.For example, when m=1 and n=1, the sub-pixels in the first column of the eighth row are electrically connected to the fifteenth scan signal line Gate15 and the second data signal line Data2, respectively; the sub-pixels in the second column of the eighth row are electrically connected to the sixteenth scan signal line Gate16 and the second data signal line Data2, respectively; the sub-pixels in the third column of the eighth row are electrically connected to the sixteenth scan signal line Gate16 and the third data signal line Data3, respectively; the sub-pixels in the fourth column of the eighth row are electrically connected to the fifteenth scan signal line Gate15 and the third data signal line Data3, respectively; the sub-pixels in the fifth column of the eighth row are electrically connected to the fifteenth scan signal line Gate15 and the fourth data signal line Data4, respectively; and the sub-pixels in the sixth column of the eighth row are electrically connected to the sixteenth scan signal line Gate16 and the fourth data signal line Data4, respectively. Electrical connections are made as follows: the sub-pixel in the 7th column of the 8th row is electrically connected to the 15th scan signal line Gate15 and the 5th data signal line Data5; the sub-pixel in the 8th column of the 8th row is electrically connected to the 16th scan signal line Gate16 and the 5th data signal line Data5; the sub-pixel in the 9th column of the 8th row is electrically connected to the 15th scan signal line Gate15 and the 6th data signal line Data6; the sub-pixel in the 10th column of the 8th row is electrically connected to the 16th scan signal line Gate16 and the 6th data signal line Data6; the sub-pixel in the 11th column of the 8th row is electrically connected to the 15th scan signal line Gate15 and the 7th data signal line Data7; the sub-pixel in the 12th column of the 8th row is electrically connected to the 16th scan signal line Gate16 and the 7th data signal line Data7, and so on.

[0110] In an exemplary embodiment, as shown in FIG1, the sub-pixel includes: a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Specifically, the sub-pixel in column 3r-2 is the first sub-pixel P1, the sub-pixel in column 3r-1 is the second sub-pixel P23, and the sub-pixel in column 3r is the third sub-pixel P3, where 1 ≤ r ≤ 2N / 3. Exemplarily, the first, fourth, seventh, and tenth columns of sub-pixels are the first sub-pixel; the second, fifth, eighth, and eleventh columns of sub-pixels are the second sub-pixels; the third, sixth, ninth, and twelfth columns of sub-pixels are the third sub-pixels, and so on.

[0111] In an exemplary embodiment, at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and at least two of the first sub-pixel, the second sub-pixel, and the third sub-pixel are not provided as sub-pixels. For example, the first sub-pixel can be a red sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a blue sub-pixel.

[0112] In an exemplary embodiment, at least one data signal line in this disclosure includes two different sub-pixels on both its first and second sides, and one of the two sub-pixels on the first side is the same sub-pixel as one of the two sub-pixels on the second side, while the other sub-pixel on the first side is a different sub-pixel from the other sub-pixel on the second side.

[0113] In an exemplary embodiment, the arrangement of two sub-pixels located between two adjacent data signal lines in the same row can be referred to as a zigzag arrangement.

[0114] In an exemplary embodiment, the display substrate includes a plurality of pixel structures. At least one pixel structure provided in this disclosure includes 8 rows and 12 columns of sub-pixels. The sub-pixels in at least two pixel structures are connected in the same manner as the connected data lines.

[0115] In an exemplary embodiment, the data signal lines on both sides of at least one sub-pixel in a column of sub-pixels include a first data signal line and a second data signal line. The distance between the sub-pixel and the first data signal line along the first direction is less than the distance between the sub-pixel and the second data signal line along the first direction. When the sub-pixel is electrically connected to the first data signal line, the connection method between the sub-pixel and the connected data signal line can be called a short connection. When the sub-pixel is electrically connected to the second data signal line, the connection method between the sub-pixel and the connected data signal line can be called a long connection. Hereinafter, long connection is referred to as long and short connection as short.

[0116] In an exemplary embodiment, as shown in FIG1, in each pixel structure, for a sub-pixel connected to the first scan signal line Gate1, the connection pattern of multiple sub-pixels with the connected data signal line is, in order, long-long-long-long-long; for a sub-pixel connected to the second scan signal line Gate2, the connection pattern of multiple sub-pixels with the connected data signal line is, in order, short-short-short-short; for a sub-pixel connected to the third scan signal line Gate3, the connection pattern of multiple sub-pixels with the connected data signal line is, in order, long-long-long-long-short-long; and for a sub-pixel connected to the fourth scan signal line Gate4, the connection pattern of multiple sub-pixels with the connected data signal line is, in order, long-long-long-long-short-long. The connection patterns of the lines are short-short-short-long-short. For the sub-pixel connected to the fifth scan signal line Gate5, the connection patterns of multiple sub-pixels with the connected data signal lines are long-long-long-long-long-long. For the sub-pixel connected to the sixth scan signal line Gate6, the connection patterns of multiple sub-pixels with the connected data signal lines are short-short-short-short. For the sub-pixel connected to the seventh scan signal line Gate7, the connection patterns of multiple sub-pixels with the connected data signal lines are long-long-long-long-short-long. For the sub-pixel connected to the eighth scan signal line Gate8, the connection patterns of multiple sub-pixels with the connected data signal lines are short. For sub-pixels connected to the ninth scan signal line (Gate9), the connection order of multiple sub-pixels to their connected data signal lines is long-long-long-long-long. For sub-pixels connected to the tenth scan signal line (Gate10), the connection order is short-short-short-short. For sub-pixels connected to the eleventh scan signal line (Gate11), the connection order is long-short-long-long-long. For sub-pixels connected to the twelfth scan signal line (Gate12), the connection order is short-long-short-short-short. For the sub-pixels connected to the thirteenth scan signal line Gate13, the connection order of multiple sub-pixels to the connected data signal lines is long long long long long long long. For the sub-pixels connected to the fourteenth scan signal line Gate14, the connection order of multiple sub-pixels to the connected data signal lines is short short short short short. For the sub-pixels connected to the fifteenth scan signal line Gate15, the connection order of multiple sub-pixels to the connected data signal lines is long short long long long long. For the sub-pixels connected to the sixteenth scan signal line Gate16, the connection order of multiple sub-pixels to the connected data signal lines is short long short short short.

[0117] In an exemplary embodiment, a sub-pixel includes a first electrode and a second electrode. The electric field formed by the first electrode and the second electrode drives the corresponding liquid crystal structure to deflect, thereby achieving display.

[0118] In an exemplary embodiment, when the display substrate displays a sky-blue image, the second and third sub-pixels can drive the corresponding liquid crystal structures to deflect, while the first sub-pixel cannot drive the corresponding liquid crystal structures to deflect. Figure 2 shows the timing of the data signal lines connected to a pixel structure. In Figure 2, 1 indicates that the data signal line is a high-level signal, and 0 indicates that the data signal line is a low-level signal.

[0119] In an exemplary embodiment, the data signal of the 3r-2 data signal line is 1011 1011 1011 1011 in a loop. Exemplarily, the data signals of (the first data signal line Data1, the fourth data signal line Data4, the seventh data signal line Data7, and so on) are 1011 1011 1011 1011 in a loop.

[0120] In an exemplary embodiment, the data signal of the 3r-1 data signal line is a loop of 0110 0110 0110 0110. Exemplarily, the data signals of the second data signal line Data2, the fifth data signal line Data5, the eighth data signal line Data8, and so on, are a loop of 0110 0110 0110 0110.

[0121] In an exemplary embodiment, the data signal of the 3rth data signal line is 1101 1101 1110 1110 in a loop. For example, the data signals of the third data signal line Data3, the sixth data signal line Data6, the ninth data signal line Data9, and so on, are 1101 1101 1110 1110.

[0122] In an exemplary embodiment, as shown in FIG1, at least one of the first scan signal lines Gate1 to Gate2M extends at least partially along the first direction D1, and the first scan signal lines Gate1 to Gate2M are arranged sequentially along the second direction D2, with the first direction D1 and the second direction D2 intersecting.

[0123] In an exemplary embodiment, as shown in FIG1, at least one of the first data signal lines Data1 to the (N+1)th data signal line DataN+1 extends at least partially along the second direction D2, and the first data signal lines Data1 to the (N+1)th data signal lines DataN+1 are arranged sequentially along the first direction D1.

[0124] Figure 3 is a schematic diagram showing the connection between multiple scan signal lines and the driving circuit. As shown in Figure 3, the display substrate also includes a driving circuit GOA, which comprises 2M cascaded shift registers. Here, GOA(m) refers to the m-th stage shift register.

[0125] As shown in Figure 3, the 4t-3 level shift register is electrically connected to the 4t-3 scan signal line, the 4t-2 level shift register is electrically connected to the 4t-2 scan signal line, the 4t-1 level shift register is electrically connected to the 4t scan signal line, and the 4t level shift register is electrically connected to the 4t-1 scan signal line, where 1≤t≤M / 2. For example, at t=1, the first-stage shift register GOA(1) is electrically connected to the first scan signal line Gate1, the second-stage shift register GOA(2) is electrically connected to the second scan signal line Gate2, the third-stage shift register GOA(3) is electrically connected to the fourth scan signal line Gate4, and the fourth-stage shift register GOA(4) is electrically connected to the third scan signal line Gate3. At t=2, the fifth-stage shift register GOA(5) is electrically connected to the fifth scan signal line Gate5, the sixth-stage shift register GOA(6) is electrically connected to the sixth scan signal line Gate6, the seventh-stage shift register GOA(7) is electrically connected to the eighth scan signal line Gate8, and the eighth-stage shift register GOA(8) is electrically connected to the seventh scan signal line Gate7. At t=3, the ninth-stage shift register... The shift register GOA(9) is electrically connected to the ninth scan signal line Gate9, the tenth shift register GOA(10) is electrically connected to the tenth scan signal line Gate10, the eleventh shift register GOA(11) is electrically connected to the twelfth scan signal line Gate12, the twelfth shift register GOA(12) is electrically connected to the eleventh scan signal line Gate1, and at t=4, the thirteenth shift register GOA(13) is electrically connected to the thirteenth scan signal line Gate13, the fourteenth shift register GOA(14) is electrically connected to the fourteenth scan signal line Gate14, the fifteenth shift register GOA(15) is electrically connected to the sixteenth scan signal line Gate16, the sixteenth shift register GOA(16) is electrically connected to the fifteenth scan signal line Gate15, and so on.

[0126] Figure 4 shows an equivalent circuit diagram of a shift register. As shown in Figure 4, the shift register can be a 19T1C circuit structure.

[0127] As shown in Figure 4, the control electrode and first terminal of the first transistor T1 are electrically connected to the signal input terminal IN, and the second terminal of the first transistor T1 is electrically connected to the pull-up node PU; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first terminal of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second terminal of the second transistor T2 is electrically connected to the second signal output terminal OUT2; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first terminal of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second terminal of the third transistor T3 is electrically connected to the first signal output terminal OUT1; the first terminal of capacitor C is electrically connected to the pull-up node PU, and the second terminal of capacitor C is electrically connected to the first signal output terminal OUT1. Electrical connections: The control electrode of the fourth transistor T4 is electrically connected to the reset signal terminal RST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the third power supply terminal V3; the control electrode and the first electrode of the fifth transistor T5 are electrically connected to the first power supply terminal V1 respectively, and the second electrode of the fifth transistor T5 is electrically connected to the control electrode of the sixth transistor T64; the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the first pull-down node PD1; the control electrode of the seventh transistor T7 is electrically connected to the pull-up node PU, the first electrode of the seventh transistor T7 is electrically connected to the control electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7 is electrically connected to the third power supply terminal V3; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the third power supply terminal V3; the control electrode of the ninth transistor T9 is electrically connected to the third power supply terminal V3; the control electrode of the ninth transistor T9 is electrically connected to the third power supply terminal V3; the first ... The control electrode and the first electrode are electrically connected to the second power supply terminal V2, respectively. The second electrode of the ninth transistor T9 is electrically connected to the control electrode of the tenth transistor T10. The first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2. The control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the control electrode of the tenth transistor T10, and the second electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3. The control electrode of the twelfth transistor T12 is electrically connected to the pull-up node PU, the first electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2, and the second electrode of the twelfth transistor T12 is electrically connected to the third power supply terminal V3. The control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3.The control electrode of the fourteenth transistor T14 is electrically connected to the second pull-down node PD2; the first electrode of the fourteenth transistor T14 is electrically connected to the pull-up node PU; and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3. The control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1; the first electrode of the fifteenth transistor T15 is electrically connected to the first signal output terminal OUT1; and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth power supply terminal V4. The control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2; the first electrode of the sixteenth transistor T16 is electrically connected to the first signal output terminal OUT1; and the second electrode of the sixteenth transistor T16 is electrically connected to the fourth power supply terminal V4. The control electrode of the seventeenth transistor T17 is electrically connected to the first pull-down node PD1; the first electrode of the seventeenth transistor T17 is electrically connected to the second signal output terminal OUT2; and the second electrode of the seventeenth transistor T17 is electrically connected to the fourth power supply terminal V4. The control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2; the first electrode of the eighteenth transistor T18 is electrically connected to the second signal output terminal OUT2; and the second electrode of the eighteenth transistor T18 is electrically connected to the fourth power supply terminal V4. The control electrode of the nineteenth transistor T19 is electrically connected to the total reset signal terminal TRST; the first electrode of the nineteenth transistor T19 is electrically connected to the pull-up node PU; and the second electrode of the nineteenth transistor T19 is electrically connected to the third power supply terminal V3.

[0128] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0129] In an exemplary embodiment, all transistors in the shift register are N-type transistors. Exemplarily, all transistors in the shift register can be metal-oxide-semiconductor (MOS) transistors. Because MOS transistors have higher mobility and lower leakage current, using MOS transistors in the shift register can improve the refresh rate of the display product, enabling high-frequency displays, and also enabling low-frequency displays, thereby reducing power consumption.

[0130] In an exemplary embodiment, the signals at the third power supply terminal V3 and the fourth power supply terminal V4 are low-level signals and are negative voltage signals. The absolute value of the voltage at the third power supply terminal V3 is greater than the absolute value of the voltage at the fourth power supply terminal V4.

[0131] In an exemplary embodiment, the first power supply terminal V1 and the second power supply terminal V2 are inverted signals. For example, when the signal at the first power supply terminal V1 is a high-level signal, the signal at the second power supply terminal V2 is a low-level signal, or when the signal at the first power supply terminal V1 is a low-level signal, the signal at the second power supply terminal V2 is a high-level signal.

[0132] In an exemplary embodiment, the display frame may include a first display frame and a second display frame, which may be alternately set. In the first display frame, the signal at the first power terminal V1 is a high-level signal, and the signal at the second power terminal V2 is a low-level signal. In the second display frame, the signal at the first power terminal V1 is a low-level signal, and the signal at the second power terminal V2 is a high-level signal.

[0133] Figure 5 is the timing diagram of the shift register provided in Figure 4. Figure 5 is illustrated using the example where all transistors in the shift register provided in Figure 4 are N-type transistors.

[0134] As shown in Figures 4 and 5, the operation of the shift register provided in Figure 4 can include the following stages:

[0135] In the first stage P1, i.e., the input stage, the signal at the signal input terminal IN is a high-level signal, while the signals at the clock signal terminal CLK, reset signal terminal RST, and global reset signal terminal TRST are low-level signals. When the signal at the signal input terminal IN is high, the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written to the pull-up node PU. When the signal at the pull-up node PU is high, the second transistor T2 and the third transistor T3 are turned on, and the low-level signal at the clock signal terminal CLK is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the low-level signal at the third power supply terminal V3 is written to the first pull-down node PD1 and the second pull-down node PD2. The thirteenth transistor T13 to the eighteenth transistor T18 are turned off. In this stage, the signal at the pull-up node PU is high, while the signals at the first pull-down node PD1, the second pull-down node PD2, the first signal output terminal OUT1, and the second signal output terminal OUT2 are low.

[0136] In the first stage, when the shift register is in the first display frame, transistors T5 and T6 are turned on, while transistors T9 and T10 are turned off. Although transistors T5 and T6 are on, the high-level signal at the first power supply terminal V1 pulls the signal of the first pull-down node PD1 high. However, because transistors T7 and T8 remain on, the signal of the first pull-down node PD1 is still pulled low. Similarly, when the shift register is in the second display frame, transistors T5 and T6 are turned off, while transistors T9 and T10 are on. Although transistors T9 and T10 are on, the high-level signal at the second power supply terminal V2 pulls the signal of the second pull-down node PD2 high. However, because transistors T11 and T12 remain on, the signal of the second pull-down node PD2 is still pulled low. Regardless of whether the shift register is in the first or second display frame, the signals of the first pull-down node PD1 and the second pull-down node PD2 remain low during the first stage.

[0137] In the second stage P2, i.e., the output stage, the signals at the signal input terminal IN, the reset signal terminal RST, and the global reset signal terminal TRST are low-level signals, while the clock signal terminal CLK is high-level. When the signal input terminal IN is low-level, the first transistor T1 is off. Under the bootstrap effect of capacitor C, the signal at the pull-up node PU is pulled high, and the second transistor T2 and the third transistor T3 are turned on. The high-level signal at the clock signal terminal CLK is written to the first signal output terminal OUT1 and the second signal output terminal OUT2. The seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the low-level signal at the third power supply terminal V3 is continuously written to the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 remain low-level signals, and the thirteenth transistor T13 to the eighteenth transistor T18 are off. In this stage, the signals at the pull-up node PU, the first signal output terminal OUT1, and the second signal output terminal OUT2 are high-level signals, while the signals at the first pull-down node PD1 and the second pull-down node PD2 are low-level signals.

[0138] In the second stage, when the shift register is in the first display frame, transistors T5 and T6 are turned on, while transistors T9 and T10 are turned off. Although transistors T5 and T6 are on, the high-level signal at the first power supply terminal V1 will pull the signal of the first pull-down node PD1 high. However, because transistors T7 and T8 remain on, the signal of the first pull-down node PD1 is still pulled low. Similarly, when the shift register is in the second display frame, transistors T5 and T6 are turned off, while transistors T9 and T10 are on. Although transistors T9 and T10 are on, the high-level signal at the second power supply terminal V2 will pull the signal of the second pull-down node PD2 high. However, because transistors T11 and T12 remain on, the signal of the second pull-down node PD2 is still pulled low. Regardless of whether the shift register is in the first or second display frame, the signals of the first pull-down node PD1 and the second pull-down node PD2 remain low during the first stage.

[0139] In the third stage P3, i.e., the reset stage, the reset signal terminal RST is high, while the signal input terminal IN, the total reset signal terminal TRST, and the clock signal terminal CLK are low. When the reset signal RST is high, the fourth transistor T4 is turned on. The low-level signal from the third power supply terminal V3 is written to the signal of the pull-up node PU, pulling the signal of the pull-up node PU low. The second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 are turned off. When the shift register is in the first display frame, the fifth transistor T5 and the transistor T6 are turned on. The high-level signal from the first power supply terminal V1 is written to the first pull-down node PD1. The thirteenth transistor T13, the fifteenth transistor T15, and the seventeenth transistor T17 are turned on. The low-level signal from the third power supply terminal V3 is written to the pull-up node PU and the second signal output terminal OUT2. The low-level signal from the fourth power supply terminal V4 is written to the first signal output terminal OUT1. The ninth transistor T9 and the tenth transistor T12 are also turned on. When 0 is disconnected, the second pull-down node PD2 maintains the low-level signal of the previous stage, and the fourteenth transistor T14, the sixteenth transistor T16, and the eighteenth transistor T18 are disconnected. Alternatively, when the shift register is in the second display frame, the ninth transistor T9 and the tenth transistor T10 are turned on, the high-level signal of the second power supply terminal V2 is written to the second pull-down node PD2, and the fourteenth transistor T14, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on. The low-level signal of the third power supply terminal V3 is written to the pull-up node PU and the second signal output terminal OUT2, and the low-level signal of the fourth power supply terminal V4 is written to the first signal output terminal OUT1. The fifth transistor T5 and the transistor T6 are disconnected, the first pull-down node PD1 maintains the low-level signal of the previous stage, and the thirteenth transistor T13, the fifteenth transistor T15, and the seventeenth transistor T17 are turned on and off.

[0140] In the fourth stage P4, i.e., the first noise reduction stage, the clock signal CLK is high, while the signal input IN, reset signal RST, and total reset signal TRST are low. With the signal input IN low, the first transistor T1 is off, and the pull-up node PU maintains the low level signal from the previous stage. The second transistor T2, third transistor T3, seventh transistor T7, eighth transistor T8, eleventh transistor T11, and twelfth transistor T12 are off. The first pull-down node PD1 and the second pull-down node PD2 are not pulled low by the low level signal of the third power supply V3. When the shift register is in the first display frame, the fifth transistor T5 and transistor T6 are on, and the high level signal of the first power supply V1 is written to the first pull-down node PD1. The thirteenth transistor T13, fifteenth transistor T15, and seventeenth transistor T17 are on, and the low level signal of the third power supply V3 is written to the pull-up node PU and the second signal output OUT2. The low level signal of the fourth power supply V4 is written to the first signal output OUT1. The ninth transistor... When transistors T9 and T10 are disconnected, the second pull-down node PD2 maintains the low-level signal of the previous stage. Transistors T14, T16, and T18 are disconnected. Alternatively, when the shift register is in the second display frame, transistors T9 and T10 are turned on. The high-level signal of the second power supply terminal V2 is written to the second pull-down node PD2. Transistors T14, T16, and T18 are turned on. The low-level signal of the third power supply terminal V3 is written to the pull-up node PU and the second signal output terminal OUT2. The low-level signal of the fourth power supply terminal V4 is written to the first signal output terminal OUT1. Transistors T5 and T6 are disconnected. The first pull-down node PD1 maintains the low-level signal of the previous stage. Transistors T13, T15, and T17 are turned on and off.

[0141] In the fifth stage P5, i.e., the second noise reduction stage, the clock signal terminal CLK, the signal input terminal IN, the reset signal terminal RST1, and the total reset signal terminal TRST are all low-level signals. The signal input terminal IN is low-level, the first transistor T1 is off, the pull-up node PU maintains the low-level signal from the previous stage, and the second transistor T2, third transistor T3, seventh transistor T7, eighth transistor T8, eleventh transistor T11, and twelfth transistor T12 are off. The first pull-down node PD1 and the second pull-down node PD2 are not pulled low by the low-level signal of the third power supply terminal V3. When the shift register is in the first display frame, the fifth transistor T5 and transistor T6 are turned on, the high-level signal of the first power supply terminal V1 is written to the first pull-down node PD1, the thirteenth transistor T13, fifteenth transistor T15, and seventeenth transistor T17 are turned on, the low-level signal of the third power supply terminal V3 is written to the pull-up node PU and the second signal output terminal OUT2, and the low-level signal of the fourth power supply terminal V4 is written to the first signal output terminal OUT1. The ninth transistor... When transistors T9 and T10 are disconnected, the second pull-down node PD2 maintains the low-level signal of the previous stage. Transistors T14, T16, and T18 are disconnected. Alternatively, when the shift register is in the second display frame, transistors T9 and T10 are turned on. The high-level signal of the second power supply terminal V2 is written to the second pull-down node PD2. Transistors T14, T16, and T18 are turned on. The low-level signal of the third power supply terminal V3 is written to the pull-up node PU and the second signal output terminal OUT2. The low-level signal of the fourth power supply terminal V4 is written to the first signal output terminal OUT1. Transistors T5 and T6 are disconnected. The first pull-down node PD1 maintains the low-level signal of the previous stage. Transistors T13, T15, and T17 are turned on and off.

[0142] The operation of a shift register may also include multiple fourth-stage P4s and multiple fifth-stage P5s, with the fourth-stage P4s and fifth-stage P5s working alternately.

[0143] The fourth stage P4 and the fifth stage P5 can ensure that the signals of the pull-up node PU, the first signal output terminal OUT1 and the second signal output terminal OUT2 of the shift register are always low-level signals, which can reduce the noise of the shift register and improve its reliability.

[0144] In an exemplary embodiment, the first signal output terminal OUT1 and the second signal output terminal OUT2 can be different signal terminals. Specifically, the first signal output terminal OUT1 is configured to provide a drive signal to the scan signal line connected to the shift register, and the second signal output terminal OUT2 is configured to provide a cascaded signal to the signal input terminal IN of at least one stage shift register.

[0145] In an exemplary embodiment, at least one shift register includes a signal output terminal, which is electrically connected to a scan signal line to which the shift register is connected. Exemplarily, when the signal output terminal includes a first signal output terminal and a second signal output terminal, the first signal output terminal of the at least one shift register is electrically connected to the scan signal line to which the shift register is connected.

[0146] In an exemplary embodiment, the first signal output terminal OUT1 and the second output signal terminal OUT2 can be the same signal terminal. In this case, the second transistor T2 and the third transistor T3 can be the same transistor. The first signal output terminal OUT1 (which is also the second output signal terminal OUT2) can provide a drive signal to the connected scan signal line and can also provide a cascaded signal to the signal input terminal IN of at least one shift register.

[0147] Figure 6 is a timing diagram of the scan signal lines connected to a pixel structure. As shown in Figure 6, the content displayed on the display substrate includes multiple display frames. In at least one display frame, the start time of the signal of the 4t-3 scan signal line being an effective level signal is earlier than the start time of the signal of the 4t-2 scan signal line being an effective level signal, the start time of the signal of the 4t-2 scan signal line being an effective level signal is earlier than the start time of the signal of the 4t scan signal line being an effective level signal, and the start time of the signal of the 4t scan signal line being an effective level signal is earlier than the start time of the signal of the 4t-1 scan signal line being an effective level signal. For example, at t=1, the start time of the first scan signal line Gate1 being an effective signal is earlier than the start time of the second scan signal line Gate2 being an effective signal; the start time of the second scan signal line Gate2 being an effective signal is earlier than the start time of the fourth scan signal line Gate2 being an effective signal; the start time of the fourth scan signal line Gate4 being an effective signal is earlier than the start time of the third scan signal line Gate3 being an effective signal. At t=2, the start time of the fifth scan signal line Gate5 being an effective signal is earlier than the start time of the sixth scan signal line Gate6 being an effective signal; the start time of the sixth scan signal line Gate6 being an effective signal is earlier than the start time of the eighth scan signal line Gate8 being an effective signal; the start time of the eighth scan signal line Gate8 being an effective signal is earlier than the start time of the seventh scan signal line Gate7 being an effective signal. At t=3, the ninth scan signal line... The start time of the valid signal level of signal line Gate9 is earlier than the start time of the valid signal level of signal line 10 (10th scan signal line), the start time of the valid signal level of signal line 10 (10th scan signal line) is earlier than the start time of the valid signal level of signal line 11 (11th scan signal line), the start time of the valid signal level of signal line 11 (11th scan signal line) is earlier than the start time of the valid signal level of signal line 12 (12th scan signal line). At t=4, the start time of the valid signal level of signal line 13 (13th scan signal line) is earlier than the start time of the valid signal level of signal line 14 (14th scan signal line) is earlier than the start time of the valid signal level of signal line 15 (15th scan signal line) is earlier than the start time of the valid signal level of signal line 16 (16th scan signal line), and so on.

[0148] In an exemplary embodiment, as shown in FIG6, the time period of the signal output terminal of the a-th stage shift register at least partially overlaps with the time period of the signal output terminal of at least one of the shift registers of the (a+1)-th stage and the (a+2)-th stage, respectively. The time period of the signal output terminal of the a-th stage shift register does not overlap with the time period of the signal output terminal of the (a+3)-th stage shift register, and 1≤a≤2M-3. For example, when a=1, the time period of the signal output terminal of the first-stage shift register GOA(1) overlaps at least partially with the time period of the signal output terminal of at least one of the second-stage shift register GOA(2) and the third-stage shift register GOA(3), and the time period of the signal output terminal of the first-stage shift register GOA(1) does not overlap with the time period of the signal output terminal of the fourth-stage shift register GOA(4). When a=2, the time period of the signal output terminal of the second-stage shift register GOA(2) overlaps at least partially with the time period of the signal output terminal of at least one of the third-stage shift register GOA(3) and the fourth-stage shift register GOA(4), and the time period of the signal output terminal of the second-stage shift register GOA(2) does not overlap with the time period of the signal output terminal of the fifth-stage shift register GOA(5), and so on.

[0149] In an exemplary embodiment, the time period of the signal output terminal of the a-th level shift register at least partially overlaps with the time periods of the signal output terminals of at least one of the shift registers of the (a+1)-th and (a+2)-th levels. This enables the data signal to be pre-stored in the sub-pixel of the current row when writing data to at least one row of sub-pixels preceding the current row, i.e., pre-charging the sub-pixel of the current row. When the data signal written to the sub-pixel of the previous at least one row is a low-level signal, while the data signal to be written to the sub-pixel of the current row is a high-level signal, it indicates that the pre-charging situation is poor (hereinafter referred to as poor). When the data signal written to the sub-pixel of the previous at least one row is a high-level signal, while the data signal to be written to the sub-pixel of the current row is a high-level signal, it indicates that the pre-charging situation is good (hereinafter referred to as good).

[0150] The duration of the valid level signal on the scan signal line connected to the sub-pixel in this row includes a first time period and a second time period that occur consecutively, with the first time period occurring between the second time periods. The first time period is the pre-storage time, meaning that during the first time period, the scan signal line connected to at least one row of sub-pixels preceding the current row is turned on, causing the data signal of at least one row of sub-pixels preceding the current row to be written into the current row of sub-pixels, i.e., the current row of sub-pixels is pre-stored. The second time period is the scan time, meaning that during the second time period, the scan signal line is turned on, causing the data signal of the current row of sub-pixels to be written into the current row of sub-pixels.

[0151] In an exemplary embodiment, the duration of the first time period can be twice the duration of the second time period. For example, the duration of the first time period is 2H and the duration of the second time period is H.

[0152] Referring to Figures 1, 3, and 6, taking the first sub-pixel as a red sub-pixel, the second sub-pixel as a green sub-pixel, and the third sub-pixel as a blue sub-pixel as an example, in at least one display frame of a sky-blue image, the first sub-pixel located in the first column, the fourth column, and the seventh column cannot drive the corresponding liquid crystal molecules to deflect.

[0153] Referring to Figures 1, 3, and 6, in at least one display frame of the sky-blue image displayed on the display substrate, for the second sub-pixel in the first row and second column, when the signal of the first scan signal line Gate1 is in the second time period, the data signal written by the first data signal line Data1 is a high-level signal. Since the last data signal written by the first data signal line Data1 in the previous display frame was a high-level signal, the pre-charge condition of the second sub-pixel located in the first row and second column is good. For the second sub-pixel in the second row and second column, when the signal of the fourth scan signal line Gate4 is in the second time period, the data signal written by the second data signal line Data2 is a high-level signal. Since the signal of the second scan signal line Gate2 is in the second time period, the pre-charge condition of the second sub-pixel located in the first row and second column is good. During the second time period, the data signal written by the second data signal line Data2 is a high-level signal. Therefore, the pre-charge of the second sub-pixel located in the second row and second column is good. For the second sub-pixel in the third row and second column, when the signal of the fifth scan signal line Gate5 is in the second time period, the data signal written by the first data signal line Data1 is a high-level signal. Since the data signal written by the first data signal line Data1 is a high-level signal when the signal of the third scan signal line Gate3 is in the second time period, the pre-charge of the second sub-pixel located in the third row and second column is good. For the second sub-pixel in the fourth row and second column, when the signal of the eighth scan signal line Gate8 is in the second time period, the data signal written by the second data line... The data signal written by signal line Data2 is a high-level signal. Since the data signal written by the second data signal line Data2 is a high-level signal when the signal of the sixth scan signal line Gate6 is in the second time period, the pre-charge of the second sub-pixel located in the fourth row and second column is good. For the second sub-pixel in the fifth row and second column, when the signal of the ninth scan signal line Gate9 is in the second time period, the data signal written by the first data signal line Data1 is a high-level signal. Since the data signal written by the first data signal line Data1 is a high-level signal when the signal of the fifth scan signal line Gate5 is in the second time period, the pre-charge of the second sub-pixel located in the fifth row and second column is good. For the second sub-pixel in the sixth row and second column, when the signal of the twelfth scan signal line Gate12 is in the second time period, the data signal written by the second data signal line Data2 is a high-level signal. Since the data signal written by the second data signal line Data2 is a high-level signal when the signal of the tenth scan signal line Gate10 is in the second time period, the pre-charge of the second sub-pixel in the sixth row and second column is good. For the second sub-pixel in the seventh row and second column, when the signal of the thirteenth scan signal line Gate13 is in the second time period, the data signal written by the first data signal line Data1 is a high-level signal. Since the data signal written by the eleventh scan signal line Gate11 is in the second time period...The data signal written by the first data signal line, Data1, is a high-level signal. Therefore, the pre-charge of the second sub-pixel located in the seventh row and second column is good. For the second sub-pixel in the eighth row and second column, when the signal of the sixteenth scan signal line, Gate16, is in the second time period, the data signal written by the second data signal line, Data2, is a high-level signal. Since the data signal written by the second data signal line, Data2, is a high-level signal when the signal of the fourteenth scan signal line, Gate14, is in the second time period, the pre-charge of the second sub-pixel located in the eighth row and second column is good. In summary, the pre-charge of the second sub-pixels located in the second column is good.

[0154] Referring to Figures 1, 3, and 6, in at least one display frame of a sky-blue image displayed on the display substrate, in at least one pixel structure, for the second sub-pixel in the first row and fifth column, when the signal of the second scan signal line Gate2 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal; when the signal of the first scan signal line Gate1 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal, indicating that the pre-charge of the second sub-pixel in the first row and fifth column is good. For the second sub-pixel in the second row and fifth column, when the signal of the third scan signal line Gate3 is in the second time period, the data signal written by the fourth data signal line Data4 is high. Regarding the level signals, since the data signal written by the fourth data signal line Data4 is a high-level signal when the signal of the fourth scan signal line Gate4 is in the second time period, the pre-charge of the second sub-pixel located in the second row and fifth column is good. For the second sub-pixel in the third row and fifth column, since the signal of the sixth scan signal line Gate6 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. Since the data signal written by the third data signal line Data3 is a high-level signal when the signal of the fifth scan signal line Gate5 is in the second time period, the pre-charge of the second sub-pixel located in the third row and fifth column is good. For the second sub-pixel in the fourth row and fifth column, the seventh... When the signal of the first scan signal line Gate7 is in the second time period, the data signal written by the fourth data signal line Data4 is a high-level signal. Since the data signal written by the fourth data signal line Data4 is a high-level signal when the signal of the eighth scan signal line Gate8 is in the second time period, the pre-charge of the second sub-pixel located in the fourth row and fifth column is good. For the second sub-pixel in the fifth row and fifth column, when the signal of the tenth scan signal line Gate10 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. Since the data signal written by the third data signal line Data3 is a high-level signal when the signal of the ninth scan signal line Gate9 is in the second time period, the pre-charge of the second sub-pixel located in the fourth row and fifth column is good. Therefore, the pre-charge of the second sub-pixel located in the fifth row and fifth column is good. For the second sub-pixel in the sixth row and fifth column, when the signal of the eleventh scan signal line Gate11 is in the second time period, the data signal written by the fourth data signal line Data4 is a high-level signal. Since the data signal written by the fourth data signal line Data4 is a high-level signal when the signal of the twelfth scan signal line Gate12 is in the second time period, the pre-charge of the second sub-pixel located in the sixth row and fifth column is good. For the second sub-pixel in the seventh row and fifth column, when the signal of the fourteenth scan signal line Gate14 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal.Because the data signal written by the third data signal line Data3 is high when the signal of the thirteenth scan signal line Gate13 is in the second time period, the pre-charge of the second sub-pixel located in the seventh row and fifth column is good. For the second sub-pixel in the eighth row and fifth column, because the data signal written by the fourth data signal line Data4 is high when the signal of the fifteenth scan signal line Gate15 is in the second time period, and because the data signal written by the fourth data signal line Data4 is high when the signal of the sixteenth scan signal line Gate16 is in the second time period, the pre-charge of the second sub-pixel located in the eighth row and fifth column is good. In summary, the pre-charge of the second sub-pixel located in the fifth column is good.

[0155] Similarly, the second sub-pixels in the eighth column and the eleventh column are all well pre-charged. That is, all second sub-pixels in at least one pixel structure are well pre-charged.

[0156] In summary, the second sub-pixel in any row of at least one pixel structure is well pre-charged, and the second sub-pixel in any column of at least one pixel structure is well pre-charged.

[0157] Referring to Figures 1, 3, and 6, in at least one display frame of a sky-blue image displayed on the display substrate 4, in at least one pixel structure, for the third sub-pixel in the first row and third column, when the signal of the second scan signal line Gate2 is in the second time period, the data signal written by the second data signal line Data2 is a high-level signal; when the signal of the first scan signal line Gate1 is in the second time period, the data signal written by the second data signal line Data2 is a low-level signal. This indicates that the pre-charge condition of the third sub-pixel in the first row and third column is poor. For the third sub-pixel in the second row and third column, when the signal of the third scan signal line Gate3 is in the second time period, the data signal written by the third data signal line Data3 is... A high-level signal occurs because, during the second time period, the data signal written by the third data signal line Data3 is a low-level signal. Therefore, the pre-charge of the third sub-pixel located in the second row and third column is poor. For the third sub-pixel in the third row and third column, when the sixth scan signal line Gate6 is in the second time period, the data signal written by the second data signal line Data2 is a high-level signal. However, because, during the second time period, the data signal written by the second data signal line Data2 is a low-level signal, the pre-charge of the third sub-pixel located in the third row and third column is poor. For the third sub-pixel in the fourth row and third column, the... When the signal of the seventh scan signal line Gate7 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. Since the data signal written by the third data signal line Data3 is a low-level signal when the signal of the eighth scan signal line Gate8 is in the second time period, the pre-filling of the third sub-pixel located in the fourth row and third column is poor. For the third sub-pixel in the fifth row and third column, when the signal of the tenth scan signal line Gate10 is in the second time period, the data signal written by the second data signal line Data2 is a high-level signal. Since the data signal written by the second data signal line Data2 is a low-level signal when the signal of the ninth scan signal line Gate9 is in the second time period... Because the signal is low, the pre-charge of the third sub-pixel located in the fifth row and third column is poor. For the third sub-pixel in the sixth row and third column, when the signal of the twelfth scan signal line Gate12 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. Since the data signal written by the second data signal line Data2 is a high-level signal when the signal of the tenth scan signal line Gate10 is in the second time period, the pre-charge of the third sub-pixel in the sixth row and third column is good. For the third sub-pixel in the seventh row and third column, when the signal of the fourteenth scan signal line Gate14 is in the second time period, the data signal written by the second data signal line Data2 is a high-level signal.Because the data signal written by the second data signal line Data2 is a low-level signal when the signal of the thirteenth scan signal line Gate13 is in the second time period, the pre-charge condition of the third sub-pixel located in the seventh row and third column is poor. For the third sub-pixel located in the eighth row and third column, when the signal of the sixteenth scan signal line Gate16 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. Because the data signal written by the third data signal line Data3 is a high-level signal when the signal of the fourteenth scan signal line Gate14 is in the second time period, the pre-charge condition of the third sub-pixel located in the eighth row and third column is good. In summary, the pre-charge condition of the third sub-pixel located in the third column is: Poor Poor Poor Poor Poor Poor Good Poor Good.

[0158] Referring to Figures 1, 3, and 6, in at least one display frame displaying a sky-blue image, in at least one pixel structure, for the third sub-pixel in the first row and sixth column, when the signal of the first scan signal line Gate1 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. In the last display frame, the data signal written by the third data signal line Data3 was a low-level signal, indicating poor pre-charge of the third sub-pixel in the first row and sixth column. For the third sub-pixel in the second row and sixth column, when the signal of the fourth scan signal line Gate4 is in the second time period, the data signal written by the fourth data signal line Data4 is a high-level signal. This is because the signal of the second scan signal line Gate2... When the signal is in the second time period, the data signal written by the fourth data signal line Data4 is a low-level signal. Therefore, the pre-charge of the third sub-pixel located in the second row and sixth column is poor. For the third sub-pixel in the third row and sixth column, when the signal of the fifth scan signal line Gate5 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. Since the data signal written by the third data signal line Data3 is a high-level signal when the signal of the third scan signal line Gate3 is in the second time period, the pre-charge of the third sub-pixel located in the third row and sixth column is good. For the third sub-pixel in the fourth row and sixth column, when the signal of the eighth scan signal line Gate8 is in the second time period, the fourth... The data signal written by data signal line Data4 is a high-level signal. Since the data signal written by data signal line Data4 is a low-level signal when the signal of the sixth scan signal line Gate6 is in the second time period, the pre-charge of the third sub-pixel located in the fourth row and sixth column is poor. For the third sub-pixel in the fifth row and sixth column, the data signal written by data signal line Data3 is a high-level signal when the signal of the ninth scan signal line Gate9 is in the second time period. Since the data signal written by data signal line Data3 is a high-level signal when the signal of the seventh scan signal line Gate7 is in the second time period, the pre-charge of the third sub-pixel located in the fifth row and sixth column is good. For the third sub-pixel in the sixth row and sixth column, when the signal of the twelfth scan signal line Gate12 is in the second time period, the data signal written by the fourth data signal line Data4 is a high-level signal. Since the data signal written by the third data signal line Data3 is a low-level signal when the signal of the tenth scan signal line Gate10 is in the second time period, the pre-charge condition of the third sub-pixel in the sixth row and sixth column is poor. For the third sub-pixel in the seventh row and sixth column, when the signal of the thirteenth scan signal line Gate13 is in the second time period, the data signal written by the third data signal line Data3 is a high-level signal. Since the signal of the eleventh scan signal line Gate11 is in the second time period...The data signal written by the third data signal line, Data3, is a low-level signal. Therefore, the pre-charge condition of the third sub-pixel located in the seventh row and sixth column is poor. For the third sub-pixel in the eighth row and sixth column, when the signal of the sixteenth scan signal line, Gate16, is in the second time period, the data signal written by the fourth data signal line, Data4, is a high-level signal. Since the data signal written by the fourth data signal line, Data4, is a low-level signal when the signal of the fourteenth scan signal line, Gate14, is in the second time period, the pre-charge condition of the third sub-pixel located in the eighth row and sixth column is also poor. In summary, the pre-charge condition of the third sub-pixel located in the sixth column is: Poor Poor Good Poor Good Poor Poor Poor.

[0159] Referring to Figures 1, 3, and 6, in at least one display frame showing a sky-blue image, in at least one pixel structure, for the third sub-pixel in the first row and ninth column, when the signal of the second scan signal line Gate2 is in the second time period, the data signal written by the fifth data signal line Data5 is a high-level signal; when the signal of the first scan signal line Gate1 is in the second time period, the data signal written by the fifth data signal line Data5 is a low-level signal. This indicates that the pre-charge condition of the third sub-pixel in the first row and ninth column is poor. For the third sub-pixel in the second row and ninth column, when the signal of the fourth scan signal line Gate4 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal. Because the data signal written by the sixth data signal line Data6 is a high-level signal when the signal of the second scan signal line Gate2 is in the second time period, the pre-filling of the third sub-pixel located in the second row and ninth column is good. For the third sub-pixel located in the third row and ninth column, because the data signal written by the fifth data signal line Data5 is a high-level signal when the signal of the sixth scan signal line Gate6 is in the second time period, and the data signal written by the fifth data signal line Data5 is a low-level signal when the signal of the fifth scan signal line Gate5 is in the second time period, the pre-filling of the third sub-pixel located in the third row and ninth column is poor. For the third sub-pixel located in the fourth row and ninth column, the data pre-filling of the third sub-pixel located in the third row and ninth column is poor. When the signal on the scanning signal line Gate8 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal. Since the data signal written by the sixth data signal line Data6 is a high-level signal when the signal on the sixth scanning signal line Gate6 is in the second time period, the pre-charge of the third sub-pixel located in the fourth row and ninth column is good. For the third sub-pixel in the fifth row and ninth column, when the signal on the tenth scanning signal line Gate10 is in the second time period, the data signal written by the fifth data signal line Data5 is a high-level signal. Since the data signal written by the fifth data signal line Data5 is a low-level signal when the signal on the ninth scanning signal line Gate9 is in the second time period... Because the signal is flat, the pre-charge of the third sub-pixel located in the fifth row and ninth column is poor. For the third sub-pixel in the sixth row and ninth column, when the signal of the eleventh scan signal line Gate11 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal. Since the signal of the twelfth scan signal line Gate12 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal. Therefore, the pre-charge of the third sub-pixel located in the sixth row and ninth column is poor. For the third sub-pixel in the seventh row and ninth column, when the signal of the fourteenth scan signal line Gate14 is in the second time period, the data signal written by the fifth data signal line Data5 is a high-level signal.Because the data signal written by the fifth data signal line (Data5) is low when the signal of the thirteenth scan signal line (Gate13) is in the second time period, the pre-charge condition of the third sub-pixel located in the seventh row and ninth column is poor. For the third sub-pixel in the eighth row and ninth column, because the data signal written by the sixth data signal line (Data6) is high when the signal of the fifteenth scan signal line (Gate15) is in the second time period, and because the data signal written by the sixth data signal line (Data6) is low when the signal of the sixteenth scan signal line (Gate16) is in the second time period, the pre-charge condition of the third sub-pixel located in the eighth row and ninth column is poor. In summary, the pre-charge condition of the third sub-pixel located in the ninth column is: Poor Good Poor Good Poor Poor Poor Poor Poor.

[0160] Referring to Figures 1, 3, and 6, in at least one display frame of a sky-blue image displayed on the display substrate, in at least one pixel structure, for the third sub-pixel in the first row and twelfth column, when the signal of the first scan signal line Gate1 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal. The data signal written by the sixth data signal line Data6 at the end of the previous display frame was also a high-level signal, indicating that the pre-charge of the third sub-pixel in the first row and twelfth column is good. For the third sub-pixel in the second row and twelfth column, when the signal of the fourth scan signal line Gate4 is in the second time period, the data signal written by the seventh data signal line Data7 is a high-level signal. Since in the second scan... When the signal on signal line Gate2 is in the second time period, the data signal written by the seventh data signal line Data7 is a low-level signal. Therefore, the pre-charge condition of the third sub-pixel located in the second row and twelfth column is poor. For the third sub-pixel in the third row and twelfth column, when the signal on the fifth scan signal line Gate5 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal. Since the data signal written by the sixth data signal line Data6 is a low-level signal when the signal on the third scan signal line Gate3 is in the second time period, the pre-charge condition of the third sub-pixel located in the third row and twelfth column is poor. For the third sub-pixel in the fourth row and twelfth column, the eighth scan signal line Ga... When the signal te8 is in the second time period, the data signal written by the seventh data signal line Data7 is a high-level signal. Since the data signal written by the seventh data signal line Data7 is a low-level signal when the signal of the sixth scan signal line Gate6 is in the second time period, the pre-filling condition of the third sub-pixel located in the fourth row and twelfth column is poor. For the third sub-pixel in the fifth row and twelfth column, when the signal of the ninth scan signal line Gate9 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal. Since the data signal written by the sixth data signal line Data6 is a low-level signal when the signal of the seventh scan signal line Gate7 is in the second time period, the pre-filling condition of the third sub-pixel located in the fourth row and twelfth column is poor. Therefore, the pre-charge condition of the third sub-pixel located in the fifth row and twelfth column is poor. For the third sub-pixel in the sixth row and twelfth column, when the signal of the twelfth scan signal line Gate12 is in the second time period, the data signal written by the seventh data signal line Data7 is a high-level signal. Since the data signal written by the sixth data signal line Data6 is a low-level signal when the signal of the tenth scan signal line Gate10 is in the second time period, the pre-charge condition of the third sub-pixel located in the sixth row and twelfth column is poor. For the third sub-pixel in the seventh row and twelfth column, when the signal of the thirteenth scan signal line Gate13 is in the second time period, the data signal written by the sixth data signal line Data6 is a high-level signal.Because the data signal written by the sixth data signal line (Data6) is high when the signal of the eleventh scan signal line (Gate11) is in the second time period, the pre-charge condition of the third sub-pixel located in the seventh row and twelfth column is good. For the third sub-pixel located in the eighth row and twelfth column, because the data signal written by the seventh data signal line (Data7) is high when the signal of the sixteenth scan signal line (Gate16) is in the second time period, and the data signal written by the seventh data signal line (Data7) is low when the signal of the fourteenth scan signal line (Gate14) is in the second time period, the pre-charge condition of the third sub-pixel located in the eighth row and twelfth column is poor. In summary, the pre-charge condition of the third sub-pixel located in the twelfth column is: Good Poor Poor Poor Poor Poor Good Poor.

[0161] In an exemplary embodiment, in at least one pixel structure, the pre-charge condition in at least one row of third sub-pixels is three-difference-one-good, and the pre-charge condition in at least one column of third sub-pixels is six-difference-two-good.

[0162] Therefore, in this disclosure, the pre-charging status of the second sub-pixels in different columns is good, which can be expressed as the pre-charging effect of the second sub-pixels being the same. The pre-charging status of the third sub-pixels in different columns is partly good and partly poor, which can be passed on to each other, which can be expressed as the pre-charging effect of the third sub-pixels in different columns being the same, with no brightness difference, thereby avoiding the occurrence of vertical and horizontal stripe defects and improving the display effect of the display substrate.

[0163] In an exemplary embodiment, Figure 7 is a schematic diagram of a cascaded array of multiple shift registers, and Figure 8 is a schematic diagram of a cascaded array of multiple shift registers. As shown in Figures 7 and 8, the display substrate also includes an initial signal line (STV).

[0164] The signal input terminals IN of the first-stage shift register GOA(1) and the second-stage shift register GOA(2) are electrically connected to the initial signal line. The signal output terminal of the b-th stage shift register is electrically connected to the signal input terminal of the b+2-th stage shift register. The reset signal terminal of the c-th stage shift register is electrically connected to the signal output terminal of the c+3-th stage shift register. 1≤b≤2M-4, 1≤c≤2M-3. For example,

[0165] In an exemplary embodiment, the display substrate further includes H clock signal lines. At least a portion of at least one of the H clock signal lines extends along a second direction D2, and the clock signal terminal of the w*H-H+h stage shift register is electrically connected to the h-th clock signal line, where 1≤w≤2M / H and 1≤h≤H. Figures 7 and 8 are illustrated with H=4 as an example. The clock signal terminal of the 4t-3 stage shift register is electrically connected to the first clock signal line CLK1, the clock signal terminal of the 4t-2 stage shift register is electrically connected to the second clock signal line CLK2, the clock signal terminal of the 4t-1 stage shift register is electrically connected to the third clock signal line CLK3, and the clock signal terminal of the 4t stage shift register is electrically connected to the fourth clock signal line CLK4.

[0166] In an exemplary embodiment, as shown in FIG7, the first-stage shift register to the 2M-stage shift register are arranged sequentially along the second direction D2;

[0167] In an exemplary embodiment, as shown in FIG7, the display substrate further includes: 2M output connection lines CL, each of which corresponds to one of the 2M stage shift registers, and at least one output connection line is electrically connected to the corresponding shift register and the corresponding scan signal line connected to the shift register. For example, the first output connection line CL1 is electrically connected to the first stage shift register GOA(1) and the first scan signal line Gate1 connected to the first stage shift register GOA(1); the second output connection line CL2 is electrically connected to the second stage shift register GOA(2) and the second scan signal line Gate2 connected to the second stage shift register GOA(2); the third output connection line CL3 is electrically connected to the third stage shift register GOA(3) and the fourth scan signal line Gate4 connected to the third stage shift register GOA(3); the fourth output connection line CL4 is electrically connected to the fourth stage shift register GOA(4) and the third scan signal line Gate3 connected to the fourth stage shift register GOA(4), and so on.

[0168] In an exemplary embodiment, as shown in FIG7, at least a portion of at least one of the 4t-3 and 4t-2 output connection lines extends along a first direction D1, at least a portion of the 4t-1 output connection line extends along a third direction D3, at least a portion of the 4t output connection line extends along a fourth direction D4, and the orthographic projection of the 4t-1 output connection line on the substrate at least partially overlaps with the orthographic projection of the 4t output connection line on the substrate. The third direction D3 intersects with at least one of the first direction D1 and the second direction D2, the fourth direction D4 intersects with at least one of the first direction D1 and the second direction D2, and the third direction D3 intersects with the fourth direction D4. For example, at least a portion of at least one of the first output connection line CL1 and the second output connection line CL2 extends along a first direction D1, at least a portion of the third output connection line CL3 extends along a third direction D3, at least a portion of the fourth output connection line CL4 extends along a fourth direction D4, and the orthographic projection of the third output connection line CL3 on the substrate at least partially overlaps with the orthographic projection of the fourth output connection line CL4 on the substrate.

[0169] In an exemplary embodiment, as shown in FIG7, the first clock signal line to the Hth clock signal line are arranged sequentially in a direction away from the display area. For example, the first clock signal line CLK1 to the fourth clock signal line CLK4 are arranged sequentially in a direction away from the display area.

[0170] In an exemplary embodiment, as shown in FIG8, the first-stage shift registers to the 2M-stage shift registers are arranged along a first direction, the 4t-2-stage shift register is located between the 4t-3-stage shift register and the 4t-stage shift register, and the 4t-1-stage shift register is located between the 4t-stage shift register and the 4t+1-stage shift register. Exemplarily, the second-stage shift register GOA(2) is located between the first-stage shift register GOA(1) and the fourth-stage shift register GOA(4), and the third-stage shift register GOA(3) is located between the fourth-stage shift register GOA(4) and the fifth-stage shift register GOA(5).

[0171] In an exemplary embodiment, as shown in FIG8, the display substrate further includes: 2M output connection lines, each of which corresponds to one of the 2M stage shift registers, and at least one output connection line is electrically connected to the corresponding shift register and the corresponding scan signal line connected to the shift register. For example, the first output connection line CL1 is electrically connected to the first stage shift register GOA(1) and the first scan signal line Gate1 connected to the first stage shift register GOA(1); the second output connection line CL2 is electrically connected to the second stage shift register GOA(2) and the second scan signal line Gate2 connected to the second stage shift register GOA(2); the third output connection line CL3 is electrically connected to the third stage shift register GOA(3) and the fourth scan signal line Gate4 connected to the third stage shift register GOA(3); the fourth output connection line CL4 is electrically connected to the fourth stage shift register GOA(4) and the third scan signal line Gate3 connected to the fourth stage shift register GOA(4), and so on.

[0172] In an exemplary embodiment, as shown in FIG8, at least one of the 2M output connection lines extends at least partially along a first direction. Exemplarily, at least portions of the first output connection line CL1 to the 2Mth output connection line CL2M extend along the first direction D1.

[0173] In an exemplary embodiment, as shown in FIG8, the 4t-3 clock signal line is located on the side of the 4t-2 clock signal line closer to the display area, and the 4t-2 clock signal line is located between the 4t-3 clock signal line and the 4t clock signal line. The 4t-1 clock signal line is located on the side of the 4t clock signal line farther from the display area. Exemplarily, the first clock signal line CLK1 is located on the side of the second clock signal line CLK2 closer to the display area, and the second clock signal line CLK2 is located between the first clock signal line CLK1 and the fourth clock signal line CLK4. The third clock signal line CLK3 is located on the side of the fourth clock signal line CLK4 farther from the display area.

[0174] In an exemplary embodiment, as shown in Figures 7 and 8, at least one clock signal line extends at least partially along the second direction D2.

[0175] In an exemplary embodiment, as shown in Figures 7 and 8, the display substrate may further include: a first power line VDDL1, a second power line VDDL2, a third power line LVGL, and a fourth power line VGL disposed in the non-display area.

[0176] In an exemplary embodiment, the first power line VDDL1 is electrically connected to the first power supply terminal V1 of at least one shift register.

[0177] In an exemplary embodiment, the first power line VDDL1 extends at least partially along the second direction D2.

[0178] In an exemplary embodiment, the second power line VDDL2 is electrically connected to the second power supply terminal V2 of at least one level shift register.

[0179] In an exemplary embodiment, the second power line VDDL2 extends at least partially along the second direction D2.

[0180] In an exemplary embodiment, the third power line LVGL is electrically connected to the third power terminal V3 of at least one shift register.

[0181] In an exemplary embodiment, the third power line LVGL extends at least partially along the second direction D2.

[0182] In an exemplary embodiment, the fourth power line VGL is electrically connected to the fourth power terminal V4 of at least one level shift register.

[0183] In an exemplary embodiment, the fourth power line VGL extends at least partially along the second direction D2.

[0184] In an exemplary embodiment, as shown in Figures 7 and 8, the display substrate may further include a total reset signal line RSTL.

[0185] In an exemplary embodiment, the total reset signal line RSTL is electrically connected to the total reset signal terminal TRST of at least one shift register.

[0186] In an exemplary embodiment, the total reset signal line RSTL extends at least partially along the second direction D2.

[0187] Figure 9 shows the timing diagram of the signal lines connected to the drive circuit in two display frames. As shown in Figure 9, the total reset signal line RSTL is a high-level signal during the last period of the i-th display frame and a high-level signal during the beginning period of the (i+1)-th display frame.

[0188] In an exemplary implementation, the initial signal line STV is a high-level signal for a short period at the beginning of each display frame.

[0189] In an exemplary embodiment, the signals of the first clock signal line CLK1 and the fourth clock signal line CLK4 are inverted signals.

[0190] In an exemplary implementation, the first power line VDDL1 is a high-level signal in the i-th display frame and a low-level signal in the i+1-th display frame, while the second power line VDDL2 is a low-level signal in the i-th display frame and a high-level signal in the i+1-th display frame.

[0191] In an exemplary embodiment, as shown in FIG1, the display substrate may further include: a plurality of switching transistors T disposed on the substrate, wherein the plurality of switching transistors T correspond one-to-one with a plurality of sub-pixels P.

[0192] Figure 10 is a cross-sectional view of the display substrate. As shown in Figure 10, at least one sub-pixel includes: a first electrode 31 and a second electrode 32 disposed opposite to each other, wherein the orthographic projection of the first electrode 31 on the substrate and the orthographic projection of the second electrode 32 on the substrate at least partially overlap. The control electrode 21 of the switching transistor T is electrically connected to the scan signal line connected to the corresponding sub-pixel, the first electrode of the switching transistor T is electrically connected to the first electrode 23 of the sub-pixel, and the second electrode 42 of the switching transistor T is electrically connected to the data signal line connected to the sub-pixel.

[0193] In an exemplary embodiment, the second electrodes of adjacent sub-pixels can be a single integrated structure.

[0194] In an exemplary embodiment, as shown in FIG10, the display substrate further includes: a circuit structure layer disposed on the substrate, a switching transistor, a scan signal line, a data signal line, a first electrode and a second electrode disposed on the circuit structure layer, and the switching transistor includes: an active layer 22, a gate electrode 21, a first electrode 23 and a second electrode 24.

[0195] In an exemplary embodiment, as shown in FIG10, the circuit structure layer includes: a first conductive layer, a second conductive layer, a first insulating layer 41, a semiconductor layer, a third conductive layer, a second insulating layer 42, and a fourth conductive layer;

[0196] The first conductive layer includes at least: a second electrode 32 of at least one sub-pixel;

[0197] The second conductive layer includes at least: a gate electrode 21 of at least one switching transistor and a scan signal line Gate;

[0198] The semiconductor layer includes at least: an active layer 22 of at least one switching transistor;

[0199] The third conductive layer includes at least: a first electrode 23 and a second electrode 24 of at least one switching transistor and a data signal line Data;

[0200] The fourth conductive layer includes at least: a first electrode 31 of at least one sub-pixel.

[0201] In an exemplary embodiment, the gate electrode 21 of at least one switching transistor and the scan signal line Gate can be an integral structure.

[0202] The third conductive layer includes at least: at least one switching transistor and a second electrode 24, which can be integrated with the data signal line Data.

[0203] In an exemplary embodiment, the first conductive layer may be a transparent conductive layer, and the material used to fabricate the first conductive layer may be indium tin oxide.

[0204] In an exemplary embodiment, the thickness of the first conductive layer can be between 600 angstroms and 800 angstroms, and exemplaryly, the thickness of the first conductive layer can be 700 angstroms.

[0205] In an exemplary embodiment, the fourth conductive layer may be a transparent conductive layer. For example, the material used to fabricate the fourth conductive layer may be indium tin oxide (ITO).

[0206] In an exemplary embodiment, the thickness of the fourth conductive layer can be between 600 angstroms and 800 angstroms; for example, the thickness of the fourth conductive layer can be 700 angstroms.

[0207] In an exemplary embodiment, the second and third conductive layers can be metallic conductive layers. The second and third conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo or Mo / Al / Mo, etc.

[0208] In an exemplary embodiment, when the second conductive layer is a multilayer composite structure, the second conductive layer may include: a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer that are sequentially stacked along the substrate.

[0209] In an exemplary embodiment, the conductivity of the second sub-conductive layer is greater than the conductivity of at least one of the first and third sub-conductive layers. For example, the second sub-conductive layer may be made of aluminum, while the first and third sub-conductive layers may be made of molybdenum.

[0210] In an exemplary embodiment, the thickness of the second sub-conductive layer is greater than the thickness of at least one of the first and third sub-conductive layers, and the thickness of the third sub-conductive layer is greater than the thickness of the first sub-conductive layer.

[0211] In an exemplary embodiment, the thickness of the first sub-conductive layer can be in the range of 100 to 200 angstroms. For example, the thickness of the first sub-conductive layer can be 150 angstroms.

[0212] In an exemplary embodiment, the thickness of the second sub-conductive layer can be in the range of 2000 angstroms to 4000 angstroms. For example, the thickness of the second sub-conductive layer can be 3000 angstroms.

[0213] In an exemplary embodiment, the thickness of the third sub-conductive layer can be in the range of 700 angstroms to 900 angstroms. For example, the thickness of the third sub-conductive layer can be 800 angstroms.

[0214] In an exemplary embodiment, when the third conductive layer is a multilayer composite structure, the third conductive layer may include: a fourth sub-conductive layer, a fifth sub-conductive layer, and a sixth sub-conductive layer that are sequentially stacked along the substrate.

[0215] In an exemplary embodiment, the conductivity of the fifth sub-conductive layer is greater than the conductivity of at least one of the fourth and sixth sub-conductive layers. For example, the fifth sub-conductive layer may be made of aluminum, while the fourth and sixth sub-conductive layers may be made of molybdenum.

[0216] In an exemplary embodiment, the thickness of the fifth sub-conductive layer is greater than the thickness of at least one of the fourth and sixth sub-conductive layers, and the thickness of the sixth sub-conductive layer is greater than the thickness of the fourth sub-conductive layer.

[0217] In an exemplary embodiment, the thickness of the fourth sub-conductive layer can be in the range of 100 to 200 angstroms. For example, the thickness of the fourth sub-conductive layer can be 150 angstroms.

[0218] In an exemplary embodiment, the thickness of the fifth sub-conductive layer can be in the range of 2000 angstroms to 4000 angstroms. For example, the thickness of the fifth sub-conductive layer can be 3000 angstroms.

[0219] In an exemplary embodiment, the thickness of the sixth sub-conductive layer can be in the range of 700 angstroms to 900 angstroms. For example, the thickness of the sixth sub-conductive layer can be 800 angstroms.

[0220] In an exemplary embodiment, the first insulating layer and the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers.

[0221] In an exemplary embodiment, the first insulating layer may be referred to as a gate insulating layer, and the thickness of the first insulating layer may be in the range of 3,500 angstroms to 4,500 angstroms. For example, the thickness of the first insulating layer may be 4,000 angstroms.

[0222] In an exemplary embodiment, the second insulating layer may be referred to as a passivation layer, and the thickness of the second insulating layer may be in the range of 3,500 angstroms to 4,500 angstroms. For example, the thickness of the second insulating layer may be 4,000 angstroms.

[0223] In an exemplary embodiment, the second conductive layer may further include at least a common electrode line 51, which is configured to provide a signal to a second electrode of at least one sub-pixel.

[0224] In an exemplary embodiment, the semiconductor layer further includes a first active structure 52 and a second active structure 53, and the third conductive layer further includes a common connection electrode 54 and a touch signal line 55. The common connection electrode 54 is electrically connected to the second electrode of at least one sub-pixel.

[0225] In an exemplary embodiment, the orthographic projection of the common connection electrode 54 on the substrate at least partially overlaps with the orthographic projection of the first active structure 52 on the substrate, and the orthographic projection of the touch signal line 55 on the substrate at least partially overlaps with the orthographic projection of the second active structure 53 on the substrate.

[0226] In an exemplary embodiment, the fourth conductive layer further includes a common connection line 56, which is electrically connected to the common connection electrode 54 and the common electrode line 51, respectively.

[0227] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0228] The fabrication process of a display substrate may include the following operations.

[0229] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: providing a substrate, depositing a first transparent conductive film on the substrate, and patterning the first transparent conductive film using a patterning process to form a first conductive layer pattern disposed on the substrate. As shown in FIG11, FIG11 is a schematic diagram after the first conductive layer pattern in FIG10 is formed.

[0230] In an exemplary embodiment, the first conductive layer pattern may include: a second electrode 32 of at least one sub-pixel.

[0231] (2) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing at least one metal thin film based on the aforementioned pattern, and patterning the at least one metal thin film using a patterning process to form a second conductive layer pattern disposed on the substrate. As shown in FIG12, FIG12 is a schematic diagram after the formation of the second conductive layer pattern in FIG10.

[0232] The second conductive layer includes at least: a common electrode line 51, a gate electrode 21 of at least one switching transistor, and a scan signal line Gate.

[0233] (3) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a first insulating film, a semiconductor film, and at least one metal film on a substrate on which the aforementioned pattern is formed; patterning the semiconductor film and at least one metal film using a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern and a third conductive layer pattern disposed on the first insulating layer. Figure 13 is a schematic diagram of Figure 10 after the third conductive layer pattern has been formed.

[0234] The semiconductor layer pattern includes at least: an active layer 22 of at least one switching transistor, a first active structure 52, and a second active structure 53.

[0235] The third conductive layer pattern includes at least: a first electrode 23 and a second electrode 24 of at least one switching transistor, a data signal line Data, a touch signal line 54, and a common connection electrode 55.

[0236] In an exemplary embodiment, the patterning process in forming the third conductive layer pattern includes a dry etching process and a wet etching process, wherein the dry etching process forms a first electrode 23 and a second electrode 24 of at least one switching transistor, a data signal line Data, a touch signal line 55 and a common connection electrode 54, and the wet etching process exposes the channel region of the active layer 22 of the switching transistor.

[0237] (4) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a substrate on which the aforementioned pattern is formed, and patterning the second insulating film using a patterning process to form a second insulating layer 42 pattern. As shown in FIG14, FIG14 is a schematic diagram after the second insulating layer pattern is formed in FIG10.

[0238] The second insulating layer pattern 42 may include at least: a first via V1 located in the display area and a second via V2 and a third via V3 located in the non-display area.

[0239] The first via V1 exposes the first electrode of the switching transistor, the first insulating layer in the second via V2 is etched away and the common electrode line is exposed, and the third via V3 exposes the common connection electrode.

[0240] (5) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a first insulating film, a semiconductor film, and at least one metal film on a substrate on which the aforementioned pattern is formed; patterning the semiconductor film and at least one metal film using a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern and a third conductive layer pattern disposed on the first insulating layer. Figure 15 is a schematic diagram of the fourth conductive layer pattern formed in Figure 10.

[0241] The fourth conductive layer pattern includes at least: a first electrode 31 of at least one sub-pixel and a common connection line 56.

[0242] Figure 16 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure, and Figure 17 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. As shown in Figures 16 and 17, the display device provided in the embodiment of this disclosure may include: a display substrate 100 and a counter substrate 200, wherein the display substrate 100 and the counter substrate 200 are disposed opposite to each other.

[0243] In an exemplary embodiment, the display device may further include a liquid crystal layer 300 disposed between the display substrate 100 and the cell substrate 200.

[0244] The display substrate is the same as the display substrate provided in any of the foregoing embodiments, and the implementation principle and effect are the same, so it will not be described again here.

[0245] In an exemplary embodiment, the display substrate 100 includes a light-emitting side and a light-receiving side; the cell substrate is located on either the light-receiving side or the light-emitting side of the display substrate. FIG16 illustrates an example where the cell substrate is located on the light-receiving side of the display substrate, and FIG17 illustrates an example where the cell substrate is located on the light-emitting side of the display substrate.

[0246] In an exemplary embodiment, when the cell substrate is disposed on the light-incident side of the display substrate, that is, when the display substrate is disposed close to the human eye, this arrangement can make the bezel of the display device smaller and make the display device more aesthetically pleasing.

[0247] As shown in Figures 16 and 17, the display device further includes a backlight module 400. As shown in Figure 16, when the cell substrate 200 is disposed on the light-emitting side of the display substrate 100, the backlight module is located on the side of the display substrate 100 away from the cell substrate 200. As shown in Figure 17, when the cell substrate 200 is located on the light-incident side of the display substrate 100, the backlight module 400 is located on the side of the cell substrate 200 away from the display substrate 100.

[0248] In an exemplary embodiment, the display device may further include a protective cover. When the cell substrate 200 is disposed on the light-emitting side of the display substrate 100, the protective cover may be located on the side of the cell substrate 200 away from the display substrate 100. When the cell substrate 200 is located on the light-incident side of the display substrate 100, the protective cover may be located on the side of the display substrate away from the cell substrate.

[0249] In an exemplary embodiment, the protective cover may be a glass cover.

[0250] In an exemplary embodiment, the cell substrate includes: a second substrate and a color filter layer disposed on the second substrate, the color filter layer being located on the side of the second substrate closer to the display substrate.

[0251] The color filter layer includes: a plurality of filters, each filter corresponding to a plurality of sub-pixels on the display substrate, and at least one of the orthographic projections of the filters on the substrate and at least one of the sub-pixels on the substrate at least partially overlap.

[0252] In an exemplary embodiment, the filter includes a first color filter, a second color filter, and a third color filter.

[0253] The orthographic projection of the first color filter on the substrate at least partially overlaps with the orthographic projection of the first sub-pixel on the substrate, the orthographic projection of the second color filter on the substrate at least partially overlaps with the orthographic projection of the second sub-pixel on the substrate, and the orthographic projection of the third color filter on the substrate at least partially overlaps with the orthographic projection of the third sub-pixel on the substrate.

[0254] In an exemplary embodiment, the substrate may further include a black matrix layer disposed on a second substrate, wherein the black matrix layer and the color filter layer are disposed on the same layer.

[0255] This disclosure also provides a method for fabricating a display substrate. The display substrate includes: multiple sub-pixels, multiple switching transistors, multiple scan signal lines, and multiple data signal lines. The switching transistors include: an active layer, a gate electrode, a first electrode, and a second electrode. The method includes:

[0256] Provide a base;

[0257] A first conductive layer is formed on a substrate by a patterning process. The first conductive layer includes: a second electrode of at least one sub-pixel.

[0258] A second conductive layer is formed on the first conductive layer by a patterning process. The second conductive layer includes: a gate electrode of at least one switching transistor and a scan signal line.

[0259] A semiconductor layer and a third conductive layer are formed on the second conductive layer by a patterning process. The semiconductor layer includes at least an active layer of at least one switching transistor, and the third conductive layer includes at least a first electrode and a second electrode of at least one switching transistor and a data signal line.

[0260] A fourth conductive layer is formed on the third conductive layer by a patterning process. The fourth conductive layer includes: a first electrode of at least one sub-pixel.

[0261] The sub-pixels in the i-th row are located between the (2i-1)-th and the 2i-th scan signal lines, and are electrically connected to the (2i-1)-th and 2i-th scan signal lines, respectively. The sub-pixels in the (2j-1)-th and 2j-th columns are located between the j-th and (j+1)-th data signal lines, respectively. The sub-pixels in the (2j-1)-th column are electrically connected to the j-th and (j+1)-th data signal lines, respectively. The sub-pixels in the 2j-th column are electrically connected to the j-th and (j+1)-th data signal lines, respectively.

[0262] In at least one row of subpixels, the subpixel in column k and the subpixel in column k+1 are connected by different scan signal lines, 1≤i≤M, 1≤j≤N, 1≤k≤2N-1, where M is the total number of rows of subpixels and 2N is the total number of columns of subpixels.

[0263] In an exemplary embodiment, the display device can be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. In an exemplary embodiment, a protective cover is included.

[0264] In an exemplary embodiment, the present disclosure can perform AG treatment on the surface of the glass cover, so that the haze of the glass cover is about 10% to 15%. The treatment of the glass cover by the present disclosure can prevent specular reflection from occurring on the surface of the glass cover, improve the display effect of the display device, and enhance the visual experience of the human eye.

[0265] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0266] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0267] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: A substrate and M rows of 2N columns of sub-pixels, 2M scan signal lines, and N+1 data signal lines disposed on the substrate; The i-th row of sub-pixels is located between the (2i-1)-th scan signal line and the 2i-th scan signal line, and is electrically connected to the (2i-1)-th scan signal line and the 2i-th scan signal line, respectively; The sub-pixels in column 2j-1 and column 2j are located between the j-th data signal line and the (j+1)-th data signal line. The sub-pixels in column 2j-1 are electrically connected to the j-th data signal line and the (j+1)-th data signal line, respectively. The sub-pixels in column 2j are electrically connected to the j-th data signal line and the (j+1)-th data signal line, respectively. In at least one row of subpixels, the subpixel in column k and the subpixel in column k+1 are connected by different scan signal lines, where 1≤i≤M, 1≤j≤N, and 1≤k≤2N-1.

2. The display substrate according to claim 1, wherein, In at least one row of subpixels, at least two columns of adjacent subpixels are connected to the same scan signal line, and at least two columns of adjacent subpixels are connected to different scan signal lines.

3. The display substrate according to claim 1 or 2, wherein, The sub-pixel in the odd-numbered row of column 2j-1 is electrically connected to the j-th data signal line, and the sub-pixel in the even-numbered row of column 2j-1 is electrically connected to the (j+1)-th data signal line. The sub-pixel in the odd-numbered row of column 2j is electrically connected to the j-th data signal line, and the sub-pixel in the even-numbered row of column 2j is electrically connected to the (j+1)-th data signal line.

4. The display substrate according to claim 3, wherein, The sub-pixel in the kth column of at least one row of sub-pixels in the 8m-7th row, the 8m-5th row, the 8m-3th row, and the 8m-1st row is connected to a different scan signal line with the sub-pixel in the k+1th column, where 1≤m≤M / 8.

5. The display substrate according to claim 4, wherein, The sub-pixels in rows 8m-7 and columns 12n-11 are electrically connected to the 16m-14 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in rows 8m-7 and columns 12n-10 are electrically connected to the 16m-15 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in rows 8m-7 and columns 12n-9 are electrically connected to the 16m-14 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-7 and columns 12n-8 are electrically connected to the 16m-15 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-7 and columns 12n-7 are electrically connected to the 16m-14 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-7 and columns 12n-6 are electrically connected to the 16m-15 scan signal lines and the 6n-3 data signal lines, respectively. Electrical connections are made as follows: the sub-pixel in row 8m-7, column 12n-5 is electrically connected to the 16m-14 scan signal line and the 6n-2 data signal line, the sub-pixel in row 8m-7, column 12n-4 is electrically connected to the 16m-15 scan signal line and the 6n-2 data signal line, the sub-pixel in row 8m-7, column 12n-3 is electrically connected to the 16m-14 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-7, column 12n-2 is electrically connected to the 16m-15 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-7, column 12n-1 is electrically connected to the 16m-14 scan signal line and the 6n data signal line, and the sub-pixel in row 8m-7, column 12n is electrically connected to the 16m-15 scan signal line and the 6n data signal line. The sub-pixels in row 8m-5 and column 12n-11 are electrically connected to the 16m-10 scan signal line and the 6n-5 data signal line, respectively. The sub-pixels in row 8m-5 and column 12n-10 are electrically connected to the 16m-11 scan signal line and the 6n-5 data signal line, respectively. The sub-pixels in row 8m-5 and column 12n-9 are electrically connected to the 16m-10 scan signal line and the 6n-4 data signal line, respectively. The sub-pixels in row 8m-5 and column 12n-8 are electrically connected to the 16m-10 scan signal line and the 6n-4 data signal line, respectively. Each pixel is electrically connected to the 16m-11th scan signal line and the 6n-4th data signal line, respectively. The sub-pixel in row 8m-5, column 12n-7 is electrically connected to the 16m-10th scan signal line and the 6n-3rd data signal line, respectively. The sub-pixel in row 8m-5, column 12n-6 is electrically connected to the 16m-11th scan signal line and the 6n-3rd data signal line, respectively. The sub-pixel in row 8m-5, column 12n-5 is electrically connected to the 16m-10th scan signal line, respectively. The first line and the 6n-2 data signal line are electrically connected. The sub-pixel in the 12n-4th column of the 8m-5th row is electrically connected to the 16m-11th scan signal line and the 6n-2nd data signal line, respectively. The sub-pixel in the 12n-3rd column of the 8m-5th row is electrically connected to the 16m-10th scan signal line and the 6n-1st data signal line, respectively. The sub-pixel in the 12n-2nd column of the 8m-5th row is electrically connected to the 16m-11th scan signal line and the 6n-1st data signal line, respectively. The sub-pixel in the 12nth column of the 8m-5th row is electrically connected to the 16m-10th scan signal line and the 6nth data signal line, respectively. The sub-pixel in the 12nth column of the 8m-5th row is electrically connected to the 16m-11th scan signal line and the 6nth data signal line, respectively. The sub-pixels in rows 8m-3 and columns 12n-11 are electrically connected to the 16m-6 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in rows 8m-3 and columns 12n-10 are electrically connected to the 16m-7 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in rows 8m-3 and columns 12n-9 are electrically connected to the 16m-6 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-3 and columns 12n-8 are electrically connected to the 16m-7 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-3 and columns 12n-7 are electrically connected to the 16m-6 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-3 and columns 12n-6 are electrically connected to the 16m-7 scan signal lines and the 6n-3 data signal lines, respectively. Electrical connections are made as follows: the sub-pixel in row 8m-3, column 12n-5 is electrically connected to the 16m-6 scan signal line and the 6n-2 data signal line, the sub-pixel in row 8m-3, column 12n-4 is electrically connected to the 16m-7 scan signal line and the 6n-2 data signal line, the sub-pixel in row 8m-3, column 12n-3 is electrically connected to the 16m-6 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-3, column 12n-2 is electrically connected to the 16m-7 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-3, column 12n-1 is electrically connected to the 16m-6 scan signal line and the 6n data signal line, and the sub-pixel in row 8m-3, column 12n is electrically connected to the 16m-7 scan signal line and the 6n data signal line. The sub-pixels in row 8m-1 and column 12n-11 are electrically connected to the 16m-2 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in row 8m-1 and column 12n-10 are electrically connected to the 16m-3 scan signal lines and the 6n-5 data signal lines, respectively. The sub-pixels in row 8m-1 and column 12n-9 are electrically connected to the 16m-2 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in row 8m-1 and column 12n-8 are electrically connected to the 16m-3 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in row 8m-1 and column 12n-7 are electrically connected to the 16m-2 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in row 8m-1 and column 12n-6 are electrically connected to the 16m-3 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixel in row 8m-1, column 12n-5 is electrically connected to the 16m-2 scan signal lines and the 6n-2 data signal lines, respectively. The sub-pixel in row 8m-1, column 12n-4 is electrically connected to the 16m-3 scan signal lines and the 6n-2 data signal lines, respectively. The sub-pixel in row 8m-1, column 12n-3 is electrically connected to the 16m-2 scan signal lines and the 6n-1 data signal lines, respectively. The sub-pixel in row 8m-1, column 12n-2 is electrically connected to the 16m-3 scan signal lines and the 6n-1 data signal lines, respectively. The sub-pixel in row 8m-1, column 12n-1 is electrically connected to the 16m-2 scan signal lines and the 6n data signal lines, respectively. The sub-pixel in row 8m-1, column 12n is electrically connected to the 16m-3 scan signal lines and the 6n data signal lines, respectively. 1≤n≤N / 6.

6. The display substrate according to claim 5, wherein, At least two columns of adjacent subpixels in at least one row of subpixels in the 8m-6, 8m-4, 8m-2 and 8m rows are connected to the same scan signal line, and at least two columns of adjacent subpixels are connected to different scan signal lines, 1≤m≤M / 8.

7. The display substrate according to claim 6, wherein, The sub-pixels in rows 8m-6 and columns 12n-11 are electrically connected to the 16m-13 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-6 and columns 12n-10 are electrically connected to the 16m-12 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-6 and columns 12n-9 are electrically connected to the 16m-13 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-6 and columns 12n-8 are electrically connected to the 16m-12 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-6 and columns 12n-7 are electrically connected to the 16m-13 scan signal lines and the 6n-2 data signal lines, respectively. The sub-pixels in rows 8m-6 and columns 12n-6 are electrically connected to the 16m-12 scan signal lines and the 6n-2 data signal lines, respectively. Electrical connections are made as follows: the sub-pixel in row 8m-6, column 12n-5 is electrically connected to the 16m-13 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-6, column 12n-4 is electrically connected to the 16m-12 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-6, column 12n-3 is electrically connected to the 16m-12 scan signal line and the 6n data signal line, the sub-pixel in row 8m-6, column 12n-2 is electrically connected to the 16m-13 scan signal line and the 6n data signal line, the sub-pixel in row 8m-6, column 12n-1 is electrically connected to the 16m-13 scan signal line and the 6n+1 data signal line, and the sub-pixel in row 8m-6, column 12n is electrically connected to the 16m-12 scan signal line and the 6n+1 data signal line. The sub-pixels in rows 8m-4 and columns 12n-11 are electrically connected to the 16m-9 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-4 and columns 12n-10 are electrically connected to the 16m-8 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-4 and columns 12n-9 are electrically connected to the 16m-9 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-4 and columns 12n-8 are electrically connected to the 16m-8 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-4 and columns 12n-7 are electrically connected to the 16m-9 scan signal lines and the 6n-2 data signal lines, respectively. The sub-pixels in rows 8m-4 and columns 12n-6 are electrically connected to the 16m-8 scan signal lines and the 6n-2 data signal lines, respectively. Electrical connections are made as follows: the sub-pixel in row 8m-4, column 12n-5 is electrically connected to the 16m-9 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-4, column 12n-4 is electrically connected to the 16m-8 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-4, column 12n-3 is electrically connected to the 16m-8 scan signal line and the 6n data signal line, the sub-pixel in row 8m-4, column 12n-2 is electrically connected to the 16m-9 scan signal line and the 6n data signal line, the sub-pixel in row 8m-4, column 12n-1 is electrically connected to the 16m-9 scan signal line and the 6n+1 data signal line, and the sub-pixel in row 8m-4, column 12n is electrically connected to the 16m-8 scan signal line and the 6n+1 data signal line. The sub-pixels in rows 8m-2 and columns 12n-11 are electrically connected to the 16m-5 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-2 and columns 12n-10 are also electrically connected to the 16m-4 scan signal lines and the 6n-4 data signal lines, respectively. The sub-pixels in rows 8m-2 and columns 12n-9 are also electrically connected to the 16m-4 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-2 and columns 12n-8 are also electrically connected to the 16m-5 scan signal lines and the 6n-3 data signal lines, respectively. The sub-pixels in rows 8m-2 and columns 12n-7 are also electrically connected to the 16m-5 scan signal lines and the 6n-2 data signal lines, respectively. The sub-pixels in rows 8m-2 and columns 12n-6 are also electrically connected to the 16m-4 scan signal lines and the 6n-2 data signal lines, respectively. Electrical connections are made as follows: the sub-pixel in row 8m-2, column 12n-5 is electrically connected to the 16m-5 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-2, column 12n-4 is electrically connected to the 16m-4 scan signal line and the 6n-1 data signal line, the sub-pixel in row 8m-2, column 12n-3 is electrically connected to the 16m-5 scan signal line and the 6n data signal line, the sub-pixel in row 8m-2, column 12n-2 is electrically connected to the 16m-4 scan signal line and the 6n data signal line, the sub-pixel in row 8m-2, column 12n-1 is electrically connected to the 16m-5 scan signal line and the 6n+1 data signal line, and the sub-pixel in row 8m-2, column 12n is electrically connected to the 16m-4 scan signal line and the 6n+1 data signal line. The sub-pixels in the 12n-11th column of the 8m row are electrically connected to the 16m-1 scan signal line and the 6n-4 data signal line, respectively. The sub-pixels in the 12n-10th column of the 8m row are electrically connected to the 16m scan signal line and the 6n-4 data signal line, respectively. The sub-pixels in the 12n-9th column of the 8m row are electrically connected to the 16m scan signal line and the 6n-3 data signal line, respectively. The sub-pixels in the 12n-8th column of the 8m row are electrically connected to the 16m-1 scan signal line and the 6n-3 data signal line, respectively. The sub-pixels in the 12n-7th column of the 8m row are electrically connected to the 16m-1 scan signal line and the 6n-2 data signal line, respectively. The sub-pixels in the 12n-6th column of the 8m row are electrically connected to the 16m scan signal line and the 6n-2 data signal line, respectively. The signal lines are electrically connected as follows: the sub-pixel in column 12n-5 of row 8m is electrically connected to the 16m-1 scan signal line and the 6n-1 data signal line, respectively; the sub-pixel in column 12n-4 of row 8m is electrically connected to the 16m scan signal line and the 6n-1 data signal line, respectively; the sub-pixel in column 12n-3 of row 8m is electrically connected to the 16m-1 scan signal line and the 6n data signal line, respectively; the sub-pixel in column 12n-2 of row 8m is electrically connected to the 16m scan signal line and the 6n data signal line, respectively; the sub-pixel in column 12n-1 of row 8m is electrically connected to the 16m-1 scan signal line and the 6n+1 data signal line, respectively; and the sub-pixel in column 12n of row 8m is electrically connected to the 16m scan signal line and the 6n+1 data signal line, respectively. For wired connections, 1 ≤ n ≤ N / 6.

8. The display substrate according to claim 1, wherein, The sub-pixel includes: the first sub-pixel to the third sub-pixel; The sub-pixel in column 3r-2 is the first sub-pixel, the sub-pixel in column 3r-1 is the second sub-pixel, and the sub-pixel in column 3r is the third sub-pixel, where 1≤r≤2N / 3.

9. The display substrate according to claim 7 or 8, wherein, At least one of the first to the second M scan signal lines extends at least partially along a first direction, and the first to the second M scan signal lines are arranged sequentially along a second direction, wherein the first direction and the second direction intersect. The display substrate further includes a driving circuit, which includes 2M cascaded shift registers. The 4t-3 level shift register is electrically connected to the 4t-3 scan signal line, the 4t-2 level shift register is electrically connected to the 4t-2 scan signal line, the 4t-1 level shift register is electrically connected to the 4t scan signal line, and the 4t level shift register is electrically connected to the 4t-1 scan signal line, where 1≤t≤M / 2.

10. The display substrate according to claim 9, wherein, At least one shift register includes: a signal output terminal, wherein the signal output terminal of the at least one shift register is electrically connected to the scan signal line connected to the shift register; The time period of the signal output terminal of the a-th stage shift register at least partially overlaps with the time period of the signal output terminal of at least one of the (a+1)-th and (a+2)-th stage shift registers. The time period of the signal output terminal of the a-th stage shift register does not overlap with the time period of the signal output terminal of the (a+3)-th stage shift register, and 1≤a≤2M-3.

11. The display substrate according to claim 10, wherein, The at least one shift register further includes a signal input terminal and a reset signal terminal, and the display substrate further includes an initial signal line; The signal input terminals of the first-stage shift register and the second-stage shift register are electrically connected to the initial signal line. The signal output terminal of the b-th stage shift register is electrically connected to the signal input terminal of the b+2-th stage shift register. The reset signal terminal of the c-th stage shift register is electrically connected to the signal output terminal of the c+3-th stage shift register. 1≤b≤2M-4, 1≤c≤2M-3.

12. The display substrate according to claim 10, wherein, The at least one level shift register further includes a clock signal terminal, and the display substrate further includes H clock signal lines; At least a portion of at least one of the H clock signal lines extends along the second direction, and the clock signal terminal of the w*H-H+h stage shift register is electrically connected to the h-th clock signal line, 1≤w≤2M / H, 1≤h≤H.

13. The display substrate according to claim 12, wherein, The first-stage shift register to the 2Mth-stage shift register are arranged sequentially along the second direction; The display substrate further includes: 2M output connection lines, each of which corresponds to a 2M-level shift register, and at least one output connection line is electrically connected to the corresponding shift register and the scan signal line connected to the corresponding shift register. At least a portion of at least one of the 4t-3 and 4t-2 output connection lines extends along a first direction, at least a portion of the 4t-1 output connection line extends along a third direction, at least a portion of the 4t output connection line extends along a fourth direction, and the orthographic projection of the 4t-1 output connection line on the substrate at least partially overlaps with the orthographic projection of the 4t output connection line on the substrate, the third direction intersects with at least one of the first and second directions, the fourth direction intersects with at least one of the first and second directions, and the third direction intersects with the fourth direction.

14. The display substrate according to claim 13, wherein, The first clock signal line to the Hth clock signal line are arranged sequentially in the direction away from the display area.

15. The display substrate according to claim 12, wherein, The first-level shift register to the second-level shift register is arranged along the first direction. The fourth-level shift register (4t-2) is located between the fourth-level shift register (4t-3) and the fourth-level shift register (4t). The fourth-level shift register (4t-1) is located between the fourth-level shift register (4t) and the fourth-level shift register (4t+1).

16. The display substrate according to claim 15, wherein, The display substrate further includes: 2M output connection lines, each of which corresponds to a 2M-level shift register, and at least one output connection line is electrically connected to the corresponding shift register and the scan signal line connected to the corresponding shift register. At least one of the 2M output connection lines extends at least partially along a first direction.

17. The display substrate according to claim 16, wherein, The 4t-3 clock signal line is located on the side of the 4t-2 clock signal line closest to the display area, and the 4t-2 clock signal line is located between the 4t-3 clock signal line and the 4t clock signal line. The 4t-1 clock signal line is located on the side of the 4t clock signal line furthest from the display area.

18. The display substrate according to claim 1, further comprising: Multiple switching transistors are disposed on the substrate, and the multiple switching transistors correspond one-to-one with multiple sub-pixels. At least one sub-pixel includes: a first electrode and a second electrode disposed opposite to each other, wherein the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlap. The control electrode of the switching transistor is electrically connected to the scan signal line connected to the corresponding sub-pixel, the first electrode of the switching transistor is electrically connected to the first electrode of the sub-pixel, and the second electrode of the switching transistor is electrically connected to the data signal line connected to the sub-pixel.

19. The display substrate according to claim 18, further comprising: A circuit structure layer is disposed on the substrate, and the switching transistor, the scan signal line, the data signal line, the first electrode, and the second electrode are disposed on the circuit structure layer. The switching transistor includes: an active layer, a gate electrode, a first electrode, and a second electrode. The circuit structure layer includes: a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a third conductive layer, a second insulating layer, and a fourth conductive layer; The first conductive layer includes at least: a second electrode of at least one sub-pixel; The second conductive layer includes at least: the gate electrode of at least one switching transistor and the scan signal line; The semiconductor layer includes at least: an active layer with at least one switching transistor; The third conductive layer includes at least: a first electrode and a second electrode of at least one switching transistor and the data signal line; The fourth conductive layer includes at least one first electrode of at least one sub-pixel.

20. A display device, comprising: The display substrate and the cell substrate as described in any one of claims 1 to 19, wherein the display substrate and the cell substrate are disposed opposite to each other.

21. The display device according to claim 20, wherein, The display substrate includes a light-emitting side and a light-receiving side; The cell substrate is located on either the light-incident side or the light-outceasing side of the display substrate.

22. The display device according to claim 20 or 21, wherein, The cell substrate includes: a second substrate and a color filter layer disposed on the second substrate, wherein the color filter layer is located on the side of the second substrate closer to the display substrate; The color filter layer includes: a plurality of filters, each filter corresponding to a plurality of sub-pixels on the display substrate, and at least one orthogonal projection of a filter onto the substrate at least partially overlaps with the orthogonal projection of at least one sub-pixel onto the substrate.

23. A method for preparing a display substrate, the display substrate comprising: The method comprises: multiple sub-pixels, multiple switching transistors, multiple scan signal lines, and multiple data signal lines; wherein each switching transistor includes an active layer, a gate electrode, a first electrode, and a second electrode; and the method includes: Provide a base; A first conductive layer is formed on a substrate using a patterning process. The first conductive layer includes at least one sub-pixel. Second electrode; A second conductive layer is formed on the first conductive layer by a patterning process. The second conductive layer includes: the gate electrode of at least one switching transistor and the scan signal line. A semiconductor layer and a third conductive layer are formed on the second conductive layer by a patterning process. The semiconductor layer includes at least an active layer of at least one switching transistor, and the third conductive layer includes at least a first electrode and a second electrode of at least one switching transistor and the data signal line. A fourth conductive layer is formed on the third conductive layer by a patterning process, the fourth conductive layer comprising: a first electrode of at least one sub-pixel; The sub-pixels in the i-th row are located between the (2i-1)-th and the 2i-th scan signal lines, and are electrically connected to the (2i-1)-th and 2i-th scan signal lines, respectively. The sub-pixels in the (2j-1)-th and 2j-th columns are located between the j-th and (j+1)-th data signal lines, respectively. The sub-pixels in the (2j-1)-th column are electrically connected to the j-th and (j+1)-th data signal lines, respectively. The sub-pixels in the 2j-th column are electrically connected to the j-th and (j+1)-th data signal lines, respectively. In at least one row of subpixels, the subpixel in column k and the subpixel in column k+1 are connected by different scan signal lines, 1≤i≤M, 1≤j≤N, 1≤k≤2N-1, where M is the total number of rows of subpixels and 2N is the total number of columns of subpixels.

Images