Shift register unit and driving method therefor, and gate driver on array circuit and display apparatus

Abstract

A shift register unit and a driving method therefor, and a gate driver on array circuit and a display apparatus. In the shift register unit, in response to the potentials of a first node (Q) and a second node (QB), a second output circuit (03) can control a first power supply terminal (VGH) or a reference clock terminal (CKC) to output a signal to a redundant output terminal (GD); and the second output circuit (03) comprises a capacitor (C1) coupled between the second node (QB) and the redundant output terminal (GD), and under the coupling effect of the capacitor (C1), the second output circuit (03) can adjust the potential of the first node (Q) on the basis of the potential of the redundant output terminal (GD). Therefore, it can be ensured that the potential of the first node (Q) remains stable, such that a third output circuit (04) reliably outputs a signal to a scan output terminal (G‹N›) in response to the potential of the first node (Q) and the potential of the second node (QB), thereby reliably driving pixels to emit light and accordingly ensuring a better display effect of a display panel.

Description

Shift register unit and driving method thereof, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a shift register unit and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0002] At present, the gate driving circuit can be integrated on the display panel by using the array substrate row driving (GOA) technology, so as to facilitate the narrow frame design of the display device. Correspondingly, the gate driving circuit is also called GOA circuit.

[0003] In the related art, the GOA circuit generally includes a plurality of GOA units connected in cascade, and each GOA unit includes an input circuit and an output circuit. The input circuit is coupled with an input clock terminal, an input signal terminal and a driving node respectively, and is configured to control the on-off of the input signal terminal and the driving node in response to a clock signal provided by the input clock terminal, so as to control the potential of the driving node. The output circuit is coupled with the driving node, an output power supply terminal, an output clock terminal and an output signal terminal respectively, and is configured to control the on-off of any one of the output power supply terminal and the output clock terminal and the output signal terminal based on the potential of the driving node, so as to output a gate driving signal to a pixel in the display panel through the output signal terminal, so as to drive the pixel to emit light, thereby driving the display panel to display a picture.

[0004] However, due to some factors (such as leakage), the potential of the driving node cannot be kept stable, and thus the output circuit cannot reliably output a signal, so as to fail to reliably drive the pixel to emit light, resulting in poor display effect of the display panel.

[0005] SUMMARY

[0006] The present disclosure provides a shift register unit and driving method thereof, a light emitting driving circuit and a display device. The technical solutions are as follows:

[0007] In one aspect, a shift register unit is provided, which includes:

[0008] an input circuit coupled with a first clock terminal, a second clock terminal, a first input terminal, a first node and a second node respectively, and configured to control the potential of the first node and the potential of the second node based on a first clock signal provided by the first clock terminal, a second clock signal provided by the second clock terminal, and a first input signal provided by the first input terminal;

[0009] a first output circuit coupled to the first node, the second node, the second clock terminal, a first power terminal and a shift output terminal, and configured to control the second clock terminal and the shift output terminal in response to a potential of the first node, and to control the first power terminal and the shift output terminal in response to a potential of the second node; wherein the shift output terminal is configured to be coupled to a first input terminal of another stage of the shift register unit in cascade;

[0010] a second output circuit coupled to a first control node, the second node, the first power terminal, a reference clock terminal and a redundant output terminal, and configured to control the first power terminal and the redundant output terminal in response to a potential of the first control node, to control the reference clock terminal and the redundant output terminal in response to a potential of the second node, and to include a first capacitor coupled between the second node and the redundant output terminal; wherein the first control node is the first node or is coupled to the shift output terminal;

[0011] a third output circuit coupled to a second control node, the second node, a third clock terminal, a second power terminal and a scan output terminal, and configured to control the third clock terminal and the scan output terminal in response to a potential of the second control node, and to control the second power terminal and the scan output terminal in response to a potential of the second node; wherein the scan output terminal is configured to be coupled to a pixel in a display panel, and the second control node is the first node or is coupled to the shift output terminal.

[0012] Optionally, the reference clock terminal and the first clock terminal are shared.

[0013] Alternatively, the reference clock terminal and the second clock terminal are shared.

[0014] Alternatively, the reference clock terminal is independent of the first clock terminal and the second clock terminal, and a rising edge of a reference clock signal provided by the reference clock terminal is after a rising edge of a second clock signal provided by the second clock terminal.

[0015] Optionally, the first node includes a first sub-node and a second sub-node; the input circuit is coupled to the first sub-node, the first output circuit is coupled to the second sub-node, the first control node is the first sub-node or the second sub-node, and the second control node is the first sub-node or the second sub-node; the shift register unit further includes:

[0016] The first control circuit is coupled with the third power supply end, the first sub-node and the second sub-node respectively, and is configured to control the first sub-node and the second sub-node in response to a third power supply signal provided by the third power supply end.

[0017] Optionally, the first control circuit comprises a first transistor.

[0018] The gate of the first transistor is coupled with the third power supply end, the first pole of the first transistor is coupled with the first sub-node, and the second pole of the first transistor is coupled with the second sub-node.

[0019] Optionally, the second node comprises a third sub-node and a fourth sub-node; the input circuit and the first output circuit are coupled with the third sub-node, and the second output circuit and the third output circuit are coupled with the fourth sub-node; and the shift register unit further comprises:

[0020] The second control circuit is coupled with the third power supply end, the third sub-node and the fourth sub-node respectively, and is configured to control the third sub-node and the fourth sub-node in response to a third power supply signal provided by the third power supply end.

[0021] Optionally, the second control circuit comprises a second transistor.

[0022] The gate of the second transistor is coupled with the third power supply end, the first pole of the second transistor is coupled with the third sub-node, and the second pole of the second transistor is coupled with the fourth sub-node.

[0023] Optionally, the second control circuit comprises two second transistors connected in series.

[0024] The gates of the two second transistors are coupled with the third power supply end, the first poles of the two second transistors are coupled with the third sub-node and the fourth sub-node respectively, and the second poles of the two second transistors are coupled with a series node; and the shift register unit further comprises:

[0025] The leakage prevention circuit is coupled with the fourth sub-node, a fourth power supply end and the series node respectively, and is configured to control the fourth power supply end and the series node in response to the potential of the fourth sub-node.

[0026] Optionally, the leakage prevention circuit comprises a third transistor.

[0027] The gate of the third transistor is coupled with the fourth sub-node, the first pole of the third transistor is coupled with the fourth power supply end, and the second pole of the third transistor is coupled with the series node.

[0028] Optionally, the second control circuit is further coupled with the first node, and is further configured to control the third sub-node and the fourth sub-node in response to the third power supply signal and a potential of the first node.

[0029] Optionally, the second control circuit comprises two second transistors connected in series.

[0030] Gates of the two second transistors are coupled with the third power supply terminal and the first node respectively, first poles of the two second transistors are coupled with the third sub-node and the fourth sub-node respectively, and second poles of the two second transistors are coupled.

[0031] Optionally, any one of the first control node and the second control node comprises a first control sub-node and a second control sub-node, the first control sub-node is the first node or is coupled with the shift output terminal, in a case that the any one of the control node is the second control node, the third output circuit is coupled with the second control sub-node, and in a case that the any one of the control node is the first control node and the second control node, the second output circuit and the third output circuit are both coupled with the second control sub-node; the shift register unit further comprises:

[0032] a third control circuit, coupled with the third power supply terminal, the first control sub-node and the second control sub-node respectively, and configured to control the first control sub-node and the second control sub-node in response to a third power supply signal provided by the third power supply terminal.

[0033] Optionally, the third control circuit comprises a fourth transistor.

[0034] A gate of the fourth transistor is coupled with the third power supply terminal, a first pole of the fourth transistor is coupled with the first control sub-node, and a second pole of the fourth transistor is coupled with the second control sub-node.

[0035] Optionally, the second node comprises a third sub-node and a fifth sub-node, the input circuit, the first output circuit and the third output circuit are all coupled with the third sub-node, and the second output circuit is coupled with the fifth sub-node; the shift register unit further comprises:

[0036] a fourth control circuit, coupled with the third power supply terminal, the third sub-node and the fifth sub-node respectively, and configured to control the third sub-node and the fifth sub-node in response to a third power supply signal provided by the third power supply terminal, and to control the third sub-node and the fifth sub-node in response to a potential of the fifth sub-node.

[0037] Optionally, the fourth control circuit comprises a fifth transistor and a sixth transistor.

[0038] The gate of the fifth transistor is coupled with the third power supply end, the first pole of the fifth transistor is coupled with the third sub-node, and the second pole of the fifth transistor is coupled with the fifth sub-node.

[0039] The gate and the second pole of the sixth transistor are both coupled with the fifth sub-node, and the first pole of the sixth transistor is coupled with the third sub-node.

[0040] Optionally, the input circuit comprises:

[0041] The first input sub-circuit is coupled with the first clock end, the first input end, the first node, the second node, the second clock end and the first power supply end respectively, and is configured to control the on-off of the first input end and the first node in response to the first clock signal, and control the on-off of the first power supply end and the first node in response to the potential of the second node and the second clock signal, so as to control the potential of the first node.

[0042] The second input sub-circuit is coupled with an input control end, a second input end, the first node and the second node respectively, and is configured to control the on-off of the second input end and the second node in response to an input control signal provided by the input control end, and control the on-off of the input control end and the second node in response to the potential of the first node, so as to control the potential of the second node; wherein the input control end and the second input end are the first power supply end and the second clock end respectively; or the input control end and the second input end are the first clock end and the third power supply end respectively.

[0043] Optionally, the first input sub-circuit comprises a seventh transistor, an eighth transistor and a ninth transistor; and the second input sub-circuit comprises a tenth transistor and an eleventh transistor.

[0044] The gate of the seventh transistor is coupled with the first clock end, the first pole of the seventh transistor is coupled with the first input end, and the second pole of the seventh transistor is coupled with the first node.

[0045] The gate of the eighth transistor is coupled with the second node, the first pole of the eighth transistor is coupled with the first power supply end, and the second pole of the eighth transistor is coupled with the first pole of the ninth transistor.

[0046] The gate of the ninth transistor is coupled with the second clock end, and the second pole of the ninth transistor is coupled with the first node.

[0047] A gate of the tenth transistor is coupled with the input control end, a first electrode of the tenth transistor is coupled with the second input end, and a second electrode of the tenth transistor is coupled with the second node.

[0048] A gate of the eleventh transistor is coupled with the first node, a first electrode of the eleventh transistor is coupled with the input control end, and a second electrode of the eleventh transistor is coupled with the second node.

[0049] Optionally, in the case where the input control end and the second input end are the first power supply end and the second clock end respectively, the second input sub-circuit further includes a second capacitor coupled between the second input end and the input control end, and the shift register unit further includes:

[0050] A fifth control circuit is coupled with the first node, the input control end and the second input sub-circuit respectively, and is configured to control the on-off of the input control end and the second input sub-circuit in response to the potential of the first node.

[0051] Optionally, the fifth control circuit includes a twelfth transistor.

[0052] A gate of the twelfth transistor is coupled with the first node, a first electrode of the twelfth transistor is coupled with the input control end, and a second electrode of the twelfth transistor is coupled with the second input sub-circuit.

[0053] Optionally, the second node includes a third sub-node and a sixth sub-node; the first input sub-circuit, the second input sub-circuit, the first output circuit and the third output circuit are coupled with the third sub-node, and the fourth control circuit included in the shift register unit is coupled with the sixth sub-node; the input circuit further includes:

[0054] A third input sub-circuit is coupled with the input control end, the second input end, the first node and the sixth sub-node respectively, and is configured to control the on-off of the second input end and the sixth sub-node in response to the input control signal, and control the on-off of the input control end and the sixth sub-node in response to the potential of the first node.

[0055] Optionally, the third input sub-circuit includes a thirteenth transistor and a fourteenth transistor.

[0056] A gate of the thirteenth transistor is coupled with the input control end, a first electrode of the thirteenth transistor is coupled with the second input end, and a second electrode of the thirteenth transistor is coupled with the second node.

[0057] A gate of the fourteenth transistor is coupled with the first node, a first pole of the fourteenth transistor is coupled with the input control end, and a second pole of the fourteenth transistor is coupled with the second node.

[0058] Optionally, the first output circuit comprises a fifteenth transistor, a sixteenth transistor and a third capacitor; the second output circuit comprises a seventeenth transistor, an eighteenth transistor and a third capacitor; and the third output circuit comprises a nineteenth transistor and a twentieth transistor.

[0059] A gate of the fifteenth transistor is coupled with the first node, a first pole of the fifteenth transistor is coupled with the second clock end, and a second pole of the fifteenth transistor is coupled with the shift output end.

[0060] A gate of the sixteenth transistor is coupled with the second node, a first pole of the sixteenth transistor is coupled with the first power supply end, and a second pole of the sixteenth transistor is coupled with the shift output end.

[0061] The third capacitor is coupled between the first node and the shift output end.

[0062] A gate of the seventeenth transistor is coupled with the first control node, a first pole of the seventeenth transistor is coupled with the first power supply end, and a second pole of the seventeenth transistor is coupled with the redundancy output end.

[0063] A gate of the eighteenth transistor is coupled with the second node, a first pole of the eighteenth transistor is coupled with the reference clock end, and a second pole of the eighteenth transistor is coupled with the redundancy output end.

[0064] A gate of the nineteenth transistor is coupled with the second control node, a first pole of the nineteenth transistor is coupled with the third clock end, and a second pole of the nineteenth transistor is coupled with the scan output end.

[0065] A gate of the twentieth transistor is coupled with the second node, a first pole of the twentieth transistor is coupled with the second power supply end, and a second pole of the twentieth transistor is coupled with the scan output end.

[0066] Optionally, all the transistors in the shift register unit are P-type transistors, and the scan output end is coupled with N-type transistors in the pixels through a gate line.

[0067] In another aspect, a driving method of a shift register unit is provided, which is used for driving the shift register unit as described in the above aspect, and the method comprises:

[0068] In a first stage, the input circuit controls the potential of the first node to be a first potential and controls the potential of the second node to be a second potential based on a first clock signal provided by a first clock terminal, a second clock signal provided by a second clock terminal and a first input signal provided by a first input terminal, the first output circuit controls the second clock terminal and the shift output terminal to be conductive in response to the potential of the first node, the second output circuit controls the first power terminal and the redundant output terminal to be conductive in response to the potential of the first control node, and the third output circuit controls the third clock terminal and the scan output terminal to be conductive in response to the potential of the second control node.

[0069] In a second stage, the input circuit controls the potential of the first node to be a second potential and controls the potential of the second node to be a first potential based on the first clock signal, the second clock signal and the first input signal, the first output circuit controls the first power terminal and the shift output terminal to be conductive in response to the potential of the second node, the second output circuit controls the reference clock terminal and the redundant output terminal to be conductive in response to the potential of the second node and adjusts the potential of the second node based on the potential of the redundant output terminal through coupling, and the third output circuit controls the second power terminal and the scan output terminal to be conductive in response to the potential of the second node.

[0070] In yet another aspect, a gate driving circuit is provided, which includes at least two cascaded shift register units as described in the above aspect.

[0071] In still another aspect, a display device is provided, which includes a display panel including a plurality of pixels and a gate driving circuit as described in the above aspect.

[0072] The gate driving circuit is coupled to the plurality of pixels and configured to transmit a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0074] FIG. 1 is a structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0075] FIG. 2 is a structural schematic diagram of another shift register unit provided by an embodiment of the present disclosure;

[0076] FIG. 3 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0077] FIG. 4 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0078] FIG. 5 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0079] FIG. 6 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0080] FIG. 7 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0081] FIG. 8 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0082] FIG. 9 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0083] FIG. 10 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0084] FIG. 11 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0085] FIG. 12 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0086] FIG. 13 is a circuit structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0087] FIG. 14 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0088] FIG. 15 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0089] FIG. 16 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0090] FIG. 17 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0091] FIG. 18 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0092] FIG. 19 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0093] FIG. 20 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0094] Fig. 21 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0095] Fig. 22 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0096] Fig. 23 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0097] Fig. 24 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0098] Fig. 25 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0099] Fig. 26 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0100] Fig. 27 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0101] Fig. 28 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0102] Fig. 29 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0103] Fig. 30 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0104] Fig. 31 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0105] Fig. 32 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0106] Fig. 33 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0107] Fig. 34 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present disclosure;

[0108] Fig. 35 is a schematic diagram of a driving method of a shift register unit according to an embodiment of the present disclosure;

[0109] Fig. 36 is a schematic diagram of a signal timing of a shift register unit according to an embodiment of the present disclosure;

[0110] Fig. 37 is a schematic diagram of a signal timing simulation of a shift register unit according to an embodiment of the present disclosure;

[0111] Figure 38 is a signal timing diagram of another shift register cell shown on the basis of the structure of Figure 13;

[0112] Figure 39 is a signal timing diagram of yet another shift register cell shown on the basis of the structure of Figure 14;

[0113] Figure 40 is a signal timing diagram of still another shift register cell shown on the basis of the structure of Figure 15;

[0114] Figure 41 is a signal timing diagram of another shift register cell shown on the basis of the structure of Figure 13;

[0115] Figure 42 is a signal timing diagram of yet another shift register cell shown on the basis of the structure of Figure 15;

[0116] Figure 43 is a signal timing diagram of still another shift register cell shown on the basis of the structure of Figure 19;

[0117] Figure 44 is a signal timing diagram of still another shift register cell shown on the basis of the structure of Figure 21;

[0118] Figure 45 is a signal timing diagram of still another shift register cell shown on the basis of the structure of Figure 23;

[0119] Figure 46 is a signal timing diagram of still another shift register cell shown on the basis of the structure of Figure 23;

[0120] Figure 47 is a structure diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0121] Figure 48 is a structure diagram of another gate drive circuit according to an embodiment of the present disclosure;

[0122] Figure 49 is a structure diagram of yet another gate drive circuit according to an embodiment of the present disclosure;

[0123] Figure 50 is a structure diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0124] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in further detail below with reference to the drawings.

[0125] It can be understood that the transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. The transistors used in the embodiments of the present disclosure are mainly switching transistors according to their role in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchangeable. In the embodiments of the present disclosure, the source is referred to as the first pole and the drain is referred to as the second pole. According to the mode in the drawings, the middle end of the transistor is defined as the control pole, which can also be referred to as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present disclosure can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is low and is turned off when the gate is high, and the N-type switching transistor is turned on when the gate is high and is turned off when the gate is low. In addition, the plurality of signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential represent only two states of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text.

[0126] In the display field, especially in the display field of the light-emitting device being an organic light-emitting diode (OLED), the development of low-temperature poly crystalline oxide (LTPO+) is more and more urgent. That is, considering the narrow frame design, the low temperature poly-silicon (LTPS) material is usually used to prepare the GOA circuit, and the oxide material is usually used to prepare the pixel circuit in the pixel. It can be understood that here refers to the transistor in the circuit. Among them, the transistor prepared by the LTPS material is usually a P-type transistor, and the transistor prepared by the oxide material is usually an N-type transistor. Therefore, it is very important to output a high potential positive shift voltage from the P-type transistor in the GOA circuit to the N-type transistor in the pixel, and it is also very important to maintain the stability of the low potential in the signal waveform output from the P-type transistor in the GOA circuit to the pixel to realize reliable noise release.

[0127] Alternatively, the light-emitting device can be selected and set according to actual needs, and is not limited to the OLED described above. For example, in some embodiments, the light-emitting device can also be a quantum dot light emitting diode (QLED) or a micro light emitting diode (Micro LED) or the like. The embodiments of the present disclosure do not limit the structure of the light-emitting device.

[0128] Based on this, the embodiment of the disclosure provides a shift register unit which can stably output a signal to a pixel. As shown in FIG. 1, the shift register unit includes an input circuit 01, a first output circuit 02, a second output circuit 03 and a third output circuit 04.

[0129] The input circuit 01 is coupled with a first clock terminal CKA, a second clock terminal CKB, a first input terminal IN1, a first node Q and a second node QB respectively. The input circuit 01 is configured to control the potential of the first node Q and the potential of the second node QB based on a first clock signal provided by the first clock terminal CKA, a second clock signal provided by the second clock terminal CKB and a first input signal provided by the first input terminal IN1.

[0130] For example, the input circuit 01 can control the potential of the first node Q to be the first potential and the potential of the second node QB to be the second potential when the potential of the first clock signal provided by the first clock terminal CKA is the first potential, the potential of the second clock signal provided by the second clock terminal CKB is the second potential and the potential of the first input signal provided by the first input terminal IN1 is the first potential. In addition, the input circuit 01 can control the potential of the first node Q to be the second potential and the potential of the second node QB to be the first potential when the potential of the first clock signal provided by the first clock terminal CKA is the first potential, the potential of the second clock signal provided by the second clock terminal CKB is the second potential and the potential of the first input signal provided by the first input terminal IN1 is the second potential. That is, the input circuit 01 can control the potential of the first node Q and the potential of the second node QB to be different in the same period.

[0131] Optionally, in the embodiment of the disclosure, the first potential can be an effective potential, the second potential can be an ineffective potential, and the first potential can be a low potential relative to the second potential, that is, the first potential of the effective potential can be a low potential, and the second potential of the ineffective potential can be a high potential. Of course, in some other embodiments, the first potential can also be a high potential relative to the second potential.

[0132] The first output circuit 02 is coupled with the first node Q, the second node QB, the second clock terminal CKB, a first power terminal VGH and a shift output terminal CR <n>Coupling. The first output circuit 02 is configured to control the second clock terminal CKB to be coupled to the shift output terminal CR in response to the potential of the first node Q <n>turn-on and turn-off of the transistor, and controls the first power source terminal VGH in response to the potential of the second node QB <n>the on-off of the light.

[0133] wherein the shift output terminal CR <n>The first input terminal IN1 is coupled with another stage shift register unit in cascade to drive the another stage shift register unit in cascade to work. Of course, in combination with Fig. 1, for the first stage shift register unit, since there is no shift register unit in cascade, the first input terminal IN1 can be coupled with the separate start signal terminal STV to receive the start signal provided from the start signal terminal STV and work under the driving of the start signal. Correspondingly, the first output circuit 02 can also be called a cascade output circuit.

[0134] It can be understood that, <n>Nth stage shift register unit, N can be an integer greater than or equal to 1 and less than or equal to the total number of stages of shift register units. The following embodiments and, without going into too much detail.

[0135] Optionally, in some embodiments, another stage shift register unit cascaded can refer to the next stage shift register unit cascaded with the current stage shift register unit; that is, the adjacent Nth stage shift register unit and the N+1th stage shift register unit can be cascaded through the shift output end CR <n>Cascade with each other. In other embodiments, another stage shift register unit cascaded can refer to the next two stage shift register units cascaded with the current stage shift register unit; that is, the Nth stage shift register unit and the N+2th stage shift register unit are cascaded through the shift output end CR <n>Cascade with each other. In yet some embodiments, another stage shift register unit cascaded with the current stage shift register unit can refer to the next three stage shift register units cascaded with the current stage shift register unit; that is, the Nth stage shift register unit and the N+3th stage shift register unit are cascaded through the shift output end CR <n>Cascade with each other. In still other embodiments, another stage shift register unit of the cascade can refer to the next four stages or other stage shift register units cascaded with the current stage shift register unit. Embodiments of the present disclosure cascade the current stage shift register unit through the shift output end CR <n>The number of stages of the other stage shift register unit in the cascade is not limited.

[0136] For example, the first output circuit 02 can control the second clock terminal CKB to be connected to the shift output terminal CR when the potential of the first node Q is the first potential. <n>is turned on, so that the second clock signal provided by the second clock end CKB is transmitted to the shift output end CR <n>; and the first output circuit 02 is capable of controlling the second clock terminal CKB and the shift output terminal CR to be in the second state when the potential of the first node Q is the second potential <n>The coupling is disconnected. Moreover, the first output circuit 02 is capable of controlling the first power terminal VGH to be connected to the shift output terminal CR when the potential of the second node QB is the first potential <n>is turned on, so that the first power signal provided by the first power end VGH is transmitted to the shift output end CR <n>; and the first output circuit 02 is capable of controlling the first power terminal VGH to be connected to the shift output terminal CR when the potential of the second node QB is the second potential <n>decoupling. That is, the first output circuit 02 is able to respond to the potential of the first node Q and the potential of the second node QB via the shift output terminal CR <n>The first input end IN1 of the shift register unit of the next stage in the cascade outputs the second clock signal or the first power signal, to realize cascade driving.

[0137] The second output circuit 03 is coupled with the first control node N1, the second node QB, the first power terminal VGH, the reference clock terminal CKC and the dummy output terminal GD respectively. The second output circuit 03 is used to control the on-off of the first power terminal VGH and the dummy output terminal GD in response to the potential of the first control node N1, and to control the on-off of the reference clock terminal CKC and the dummy output terminal GD in response to the potential of the second node QB, and comprises a first capacitor C1 coupled between the second node QB and the dummy output terminal GD. Accordingly, the second output circuit 03 can adjust the potential of the second node QB based on the potential of the dummy output terminal GD under the coupling effect of the first capacitor C1. That is, the second output circuit 03 can adjust the potential of the second node QB based on the potential of the dummy output terminal GD through the coupling effect.

[0138] The first control node N1 is the first node Q or is coupled to the shift output terminal CR <n>.

[0139] That is, in one embodiment, as shown in FIG. 1, the second output circuit 03 can be coupled with the first node Q, and correspondingly, the second output circuit 03 can be configured to control the on-off of the first power terminal VGH and the redundant output terminal GD in response to the potential of the first node Q.

[0140] Alternatively, in another embodiment, as shown in FIG. 2, the second output circuit 03 can be coupled with the shift output terminal CR <n>coupled, in response, the second output circuit 03 can be used to respond to the shift output end CR <n>The first control node N1 is coupled to the first power terminal VGH and the dummy output terminal GD. The second control node N2 is coupled to the second power terminal VGL1 and the dummy output terminal GD. The second node QB is coupled to the dummy output terminal GD and the reference clock terminal CKC. The dummy output terminal GD is not coupled to any other terminal. The dummy output terminal GD is also referred to as a redundant output terminal.

[0141] For example, the second output circuit 03 is capable of controlling the first power terminal VGH and the dummy output terminal GD to be coupled when the first control node N1 has the first potential, so that the first power signal provided by the first power terminal VGH is transmitted to the dummy output terminal GD. The second output circuit 03 is also capable of controlling the first power terminal VGH and the dummy output terminal GD to be decoupled when the first control node N1 has the second potential. The second output circuit 03 is capable of controlling the reference clock terminal CKC and the dummy output terminal GD to be coupled when the second node QB has the first potential, so that the reference clock signal provided by the reference clock terminal CKC is transmitted to the dummy output terminal GD. The second output circuit 03 is also capable of controlling the reference clock terminal CKC and the dummy output terminal GD to be decoupled when the second node QB has the second potential. The second output circuit 03 is further capable of adjusting the potential of the second node QB based on the potential of the dummy output terminal GD, so that the potential of the second node QB is further reliably pulled down based on the low potential reference clock signal when the reference clock signal is transmitted to the dummy output terminal GD in response to the first potential of the second node QB.

[0142] The third output circuit 04 is coupled to the second control node N2, the second node QB, the third clock terminal GCK, the second power terminal VGL1 and the scan output terminal G <n>Coupling. The third output circuit 04 is configured to control the third clock terminal GCK to be coupled to the scan output terminal GSO in response to the potential of the second control node N2. <n>turn-on and turn-off of the transistor Q1, and controls the second power supply terminal VGL1 to be connected to the scan output terminal G <n>turn on or off.

[0143] wherein the scan output end G <n>for coupling with a pixel in a display panel to drive the pixel to emit light. For example, a scan output G <n>The gate line can be coupled with the pixel circuit in the pixel, and be used for outputting a gate driving signal to the pixel circuit, so that the pixel circuit drives the light emitting element in the pixel to emit light. Correspondingly, the third output circuit 04 can also be called a scan output circuit. Optionally, a plurality of rows and columns of pixels arranged in an array can be generally included in the display panel, and a plurality of cascaded shift register units can be coupled with the plurality of rows of pixels one by one through the gate lines, so as to scan the pixels row by row.

[0144] And the second control node N2 is the first node Q or is coupled to the shift output end CR <n>.

[0145] That is, the third output circuit 04 can be coupled with the first node Q in one embodiment, as shown in Fig. 1, and the third output circuit 04 can be configured to control the third clock terminal GCK and the scan output terminal GSO in response to the potential of the first node Q. <n>the on-off of the light.

[0146] Alternatively, in another embodiment, as shown in Figure 2, the third output circuit 04 can be connected to the shift output terminal CR <n>Coupled, in response, the third output circuit 04 can be used to respond to the shift output end CR <n>the potential of the scan output terminal GSO, the third clock terminal GCK is controlled to be in a high impedance state. <n>the on-off of the first output circuit 03.

[0147] For example, the third output circuit 04 is capable of controlling the third clock terminal GCK to be in a high impedance state when the potential of the second control node N2 is the first potential, and controlling the scan output terminal GSO to be in a low impedance state when the potential of the second control node N2 is the second potential. <n>GCK is enabled, so that the third clock signal provided by the third clock terminal GCK is transmitted to the scan output terminal G <n>; and the third output circuit 04 is capable of controlling the third clock terminal GCK to be in a high impedance state when the potential of the second control node N2 is the second potential, and controlling the third clock terminal GCK to be in a low impedance state when the potential of the second control node N2 is the first potential. <n>The coupling is disconnected. Furthermore, the third output circuit 04 is capable of controlling the second power supply terminal VGL1 to be connected to the scan output terminal G <n>is turned on, so that the second power signal provided by the second power supply end VGL1 is transmitted to the scan output end G <n>; and the third output circuit 04 is capable of controlling the second power supply terminal VGL1 and the scan output terminal G <n>decoupling.

[0148] Optionally, the first power signal provided by the first power supply end VGH can have a high potential; the second power signal provided by the second power supply end VGL1 can have a low potential. And for the shift register unit including the P-type transistor, the first output circuit 02 responds to the first potential of the second node QB to output the shift signal through the shift output end CR <n>The first power signal outputting high potential to the first input terminal IN1 of the next stage shift register unit can be considered as performing noise elimination; and the first output circuit 02 responds to the first potential of the first node Q, and outputs the first output signal through the shift output terminal CR <n>Outputting the second clock signal to the first input terminal IN1 of the next stage shift register unit can be considered as cascade driving. The third output circuit 04 is responsive to the first potential of the second node QB to output a signal to the scanning output terminal G <n>The second power supply signal outputting a low potential to the pixel can be considered as performing noise reduction; and the third output circuit 04, in response to the first potential of the second control node N2 (e.g., the first node Q), outputs a high potential to the scanning output terminal G <n>The third clock signal output to the pixel can be considered as scan driving. Thus, in the embodiments of the present disclosure, the first node Q can also be referred to as a pull-up node, and the second node QB can also be referred to as a pull-down node.

[0149] It can be understood that in some embodiments without the second output circuit 03, the potential of the second node QB cannot be stably maintained at the first potential due to the influence of some factors, i.e., low voltage is insufficient, so that the third output circuit 04 cannot reliably control the second power end VGL1 and the scan output end G <n>The second power signal is not transmitted to the scan output terminal G <n>to the scan output end G <n>The coupled signal line (e.g., gate line) is noise-released.

[0150] In the embodiment of the present disclosure, the second output circuit 03 is further arranged, and the second output circuit 03 can reliably pull down the potential of the second node QB when the potential of the second node QB is low. Therefore, the third output circuit 04 can reliably control the second power supply end VGL1 and the scan output end G <n>Conducting, so that the low potential second power signal can be reliably transmitted to the scan output end G <n>to the scan output end G <n>The coupled gate lines are fully denoised. The first output circuit 02, on the basis of reliably pulling down the potential of the second node QB in the second output circuit 03, can also ensure that the first output circuit 02 reliably controls the first power end VGH and the shift output end CR in response to a lower potential of the second node QB <n>Conduct, so that the first power signal can be reliably transmitted to the shift output end CR <n>.

[0151] It is appreciated that, taking the second control node N2 as an example, in the case that the second control node N2 is set to be coupled to the shift output end CR <n>on the basis of the first node Q being at the first potential, the second node QB is generally at the second potential, so when the first output circuit 02 responds to the first potential of the first node Q, the second clock terminal CKB and the shift output terminal CR are controlled to be at the second potential and the first potential, respectively <n>Conducting, so that the second clock signal is transmitted to the shift output end CR <n>When the second node QB is at the second potential, the second output circuit 04 can control the second power supply terminal VGL1 to be at the second potential and the scan output terminal G <n>The coupling is disconnected. At this time, if the potential of the second clock signal is also the second potential, the second output circuit 04 can also respond to the shift output end CR <n>a second potential, the third clock terminal GCK is controlled to be in a high potential state, and the scan output terminal GSO is controlled to be in a low potential state. <n>decoupling so that the scan output G <n>In a floating state. That is, the shift output end CR <n>The potential of the second node QB and the potential of the first node QA can be the same as the first potential for a relatively long time, so the first control node Nl is coupled to the shift input terminal CI <n>With respect to setting the second control node N2 as the first node N1, the scan output end G can be increased <n>time in floating. Based on this, in some embodiments, the second control node N2 is coupled to the shift output end CR <n>On the basis of the above, the second output circuit 03 can not be provided.

[0152] Optionally, in some embodiments, the first control node N1 and the second control node N2 can be the same, i.e., can be the same node. For example, with reference to FIG. 1, the first control node N1 and the second control node N2 can both be the first node Q; or with reference to FIG. 2, the first control node N1 and the second control node N2 can both be the shift output end CR <n>Alternatively, in other embodiments, the first control node N1 and the second control node N2 can also be different. For example, with reference to Figure 3, the first control node N1 can be the first node Q, while the second control node N2 can be the shifted output end CR <n>The present disclosure is not limited in this regard.

[0153] In summary, the present disclosure provides a shift register unit. In the shift register unit, an input circuit can control potentials of a first node and a second node. A first output circuit can control a second clock terminal or a first power terminal to output a signal to a shift output terminal in response to the potentials of the first node and the second node. A second output circuit can control a first power terminal or a reference clock terminal to output a signal to a redundant output terminal in response to the potentials of the first node and the second node, and the second output circuit includes a capacitor coupled between the second node and the redundant output terminal. Accordingly, the second output circuit can adjust the potential of the first node based on the potential of the redundant output terminal under the coupling effect of the capacitor. A third output circuit can control a third clock terminal or a second power terminal to output a signal to a scan output terminal in response to the potentials of the first node and the second node. In this way, the reference clock signal provided by the reference clock terminal can be flexibly set, so that the second output circuit controls the potential of the first node to remain stable, and the third output circuit reliably outputs a signal, such as a gate drive signal, to the scan output terminal, thereby reliably driving the pixels to emit light and ensuring that the display effect of the display panel is better.

[0154] Optionally, in an optional implementation, in combination with FIG. 1, the reference clock terminal CKC can be shared with the first clock terminal CKA. In this way, the second output circuit 03 can further pull down the potential of the second node QB based on the low potential of the first clock signal through the coupling effect, thereby ensuring that the third output circuit 04 reliably controls the second power terminal VGL1 and the scan output terminal G <n>turned on to realize the scan output end G <n>Reliable noise pull-down of coupled gate lines.

[0155] Alternatively, in another optional implementation, with reference to FIG. 2, the reference clock terminal CKC can be shared with the second clock terminal CKB. In this way, the second output circuit 03 can further pull down the potential of the second node QB based on the low potential of the second clock signal through the coupling effect, so as to also ensure that the third output circuit 04 reliably controls the second power terminal VGL1 and the scan output terminal GO to be low potentials. <n>turned on to realize the scan output end G <n>Reliable noise release of coupled gate lines.

[0156] Or, in yet another optional implementation, in combination with FIG. 3, the reference clock end CKC can be independent of the first clock end CKA and the second clock end CKB, and the rising edge of the reference clock signal provided by the reference clock end CKC jumping from the second potential to the first potential can be after the rising edge of the second clock signal provided by the second clock end CKB jumping from the second potential to the first potential.

[0157] Wherein, on the basis that the second potential is a high potential and the first potential is a low potential, the rising edge of the reference clock signal jumping from the second potential to the first potential can be a falling edge. That is, the falling edge of the reference clock signal can be after the falling edge of the second clock signal. In this way, the problem that the second clock signal provided by the second clock end CKB jumps from the high potential to the low potential before the second output circuit 03 reliably controls the conduction of the reference clock end CKC and the redundant output end GD and before the second node QB is reliably pulled low by the coupling effect based on the reference clock signal can be prevented. That is, the problem that the falling edge of the second clock signal is delayed and the potential of the second node QB is coupled poorly can be avoided. In other words, the potential of the second node QB can be further ensured to remain stable and be reliably pulled to a lower potential by the coupling effect of the second output circuit 03, so that the third output circuit 04 can reliably control the conduction of the second power end VGL1 and the scan output end GD <n>turned on, the scanning output terminal G <n>Sufficient noise rejection of coupled gate lines.

[0158] Optionally, FIG. 4 is a structural schematic diagram of another shift register unit provided by the embodiments of the present disclosure. As shown in FIG. 4, the first node Q can include a first sub-node Q1 and a second sub-node Q2.

[0159] The input circuit 01 can be coupled with the first sub-node Q1. That is, the input circuit 01 can control the potential of the first sub-node Q1 in the first node Q. The first output circuit 02 can be coupled with the second sub-node Q2. That is, the first output circuit 02 can control the second clock end CKB and the shift output end CR in response to the potential of the second sub-node Q2 in the first node Q. <n>The first control node N1 can be the first sub-node Q1 or the second sub-node Q2. That is, the second output circuit 03 can control the on-off of the first power supply end VGH and the redundant output end GD in response to the potential of the first sub-node Q1 or the potential of the second sub-node Q2 in the first node Q. The second control node N2 can be the first sub-node Q1 or the second sub-node Q2. That is, the third output circuit 04 can control the on-off of the third clock end GCK and the scan output end GSO in response to the potential of the first sub-node Q1 or the potential of the second sub-node Q2 in the first node Q. <n>The first control node N1 and the second control node N2 are both the second sub-node Q2 in the first node Q.

[0160] With the above, with reference to FIG. 4 continuously, the shift register unit can further include a first control circuit 05.

[0161] The first control circuit 05 can be coupled with the third power supply end VGL2, the first sub-node Q1 and the second sub-node Q2 respectively. The first control circuit 05 can be used to control the on-off of the first sub-node Q1 and the second sub-node Q2 in response to the third power supply signal provided by the third power supply end VGL2.

[0162] For example, the first control circuit 05 can control the first sub-node Q1 and the second sub-node Q2 to be on when the potential of the third power supply signal provided by the third power supply end VGL2 is the first potential.

[0163] Optionally, the potential of the third power supply signal provided by the third power supply end VGL2 can be a low potential. And in some embodiments, the third power supply end VGL2 and the second power supply end VGL1 can be shared. In this way, the wiring can be simplified and the cost can be saved.

[0164] It can be understood that by setting the first control circuit 05, the input circuit and each output circuit can be isolated to prevent interference between the input circuit and the output circuit, such as preventing the bootstrap effect of the capacitor arranged in the output circuit, so that the input circuit and the output circuit can both maintain stable output.

[0165] Optionally, FIG. 5 is a structural schematic diagram of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG. 5, the second node QB can include a third sub-node QB1 and a fourth sub-node QB2.

[0166] Among them, the input circuit 01 and the first output circuit 02 can be coupled with the third sub-node QB1. That is, the input circuit 01 can control the potential of the third sub-node QB1 in the second node QB, and the first output circuit 02 can control the on-off of the first power supply end VGH and the shift output end CR <n>; the second output circuit 03 and the third output circuit 04 can be coupled with the fourth sub-node QB2. That is, the second output circuit 03 can control the on-off of the reference clock terminal CKC and the redundant output terminal GD in response to the potential of the fourth sub-node QB2 in the second node QB; the third output circuit 04 can control the on-off of the second power supply terminal VGL1 and the scan output terminal G <n>Of course, in some other embodiments, the input circuit 01, the first output circuit 02 and the second output circuit 03 can all be coupled with the third sub-node QB1, and only the third output circuit 04 can be coupled with the fourth sub-node QB2.

[0167] On this basis, it can be seen from the continuing reference to FIG. 5 that the shift register unit can further include a second control circuit 06.

[0168] The second control circuit 06 can be coupled with the third power supply end VGL2, the third sub-node QB1 and the fourth sub-node QB2 respectively. The second control circuit 06 can be used to control the on-off of the third sub-node QB1 and the fourth sub-node QB2 in response to the third power signal provided by the third power supply end VGL2.

[0169] For example, the first control circuit 05 can control the third sub-node QB1 and the fourth sub-node QB2 to be turned on when the potential of the third power signal provided by the third power supply end VGL2 is the first potential.

[0170] It can be understood that, like the first control circuit 05, the second control circuit 06 can also have an isolation effect. For example, the second control circuit 06 can better isolate the first output circuit 02 and the third output circuit 04.

[0171] Optionally, FIG. 6 is a structural schematic diagram of another shift register unit provided by the embodiments of the present disclosure. As shown in FIG. 6, any one of the first control node N1 and the second control node N2 can include a first control sub-node N11 and a second control sub-node N12.

[0172] The first control sub-node N11 can be the first node Q or coupled with the shift output end CR <n>, and in the case that any one of the control nodes is the second control node N2, the third output circuit 04 can be coupled with the second control sub-node N12, and in the case that any one of the control nodes is the first control node N1 and the second control node N2, the second output circuit 03 and the third output circuit 04 can be coupled with the second control sub-node N12. It can be understood that, on the basis that the first node Q is divided into the first sub-node Q1 and the second sub-node Q2, the first node Q here can refer to the first sub-node Q1 or the second sub-node Q2.

[0173] For example, in the shift register unit shown in FIG. 6, the first control node N1 and the second control node N2 each include the first control sub-node N11 and the second control sub-node N12, and the first control sub-node N11 is the second sub-node Q2 in the first node Q, and the second output circuit 03 and the third output circuit 04 are coupled with the second control sub-node N12.

[0174] For example, in the shift register unit shown in FIG. 7, only the second control node N2 includes the first control sub-node N11 and the second control sub-node N12, and the first control sub-node N11 and the first control node N1 are each the second sub-node Q2 in the first node Q, and the third output circuit 04 is coupled with the second control sub-node N12.

[0175] Optionally, the second control sub-node N12 is also identified as a node Q3 in FIG. 6 and FIG. 7, and can be considered as another sub-node included in the first node Q.

[0176] On this basis, it can be seen from FIG. 6 and FIG. 7 that the shift register unit can further include a third control circuit 07.

[0177] The third control circuit 07 can be coupled with the third power supply end VGL2, the first control sub-node N11 and the second control sub-node N12 respectively, and can be used to control the on-off of the first control sub-node N11 and the second control sub-node N12 in response to a third power signal provided by the third power supply end VGL2.

[0178] For example, the third control circuit 07 can control the first control sub-node N11 and the second control sub-node N12 to be turned on when the potential of the third power signal provided by the third power supply end VGL2 is the first potential.

[0179] It can be understood that, like the second control circuit 06, the third control circuit 07 can also have an isolation effect. For example, the third control circuit 07 can better isolate the first output circuit 02 and the third output circuit 04.

[0180] That is, in one implementation, as shown in FIG. 6, the third control circuit 07 can be coupled between the second sub-node Q2 and the second output circuit 03 and the third output circuit 04. Alternatively, in another implementation, as shown in FIG. 7, the third control circuit 07 can be coupled between the second sub-node Q2 and the third output circuit 04. It can be understood that, compared with the structure of FIG. 6, by coupling the third control circuit 07 between the second sub-node Q2 and the third output circuit 04, the potential of the second sub-node Q2 can be prevented from being too low, and the negative bias temperature stress (NBTS) of the transistor coupled with the second sub-node Q2 in the second output circuit 03 can be reduced.

[0181] Of course, as the third control circuit 07, in one implementation, the second control circuit 06 can be coupled between the third sub-node QB1 and the second output circuit 03 and the third output circuit 04, as shown in FIGS. 5 to 7. Alternatively, in another implementation, the second control circuit 06 can be coupled between the third sub-node QB1 and the third output circuit 04.

[0182] Optionally, FIG. 8 is a structural schematic diagram of still another shift register unit provided by the embodiment of the present disclosure. As shown in FIG. 9, the second node QB can include a third sub-node QB1 and a fifth sub-node QB3.

[0183] Wherein, the input circuit 01, the first output circuit 02 and the third output circuit 04 can all be coupled with the third sub-node QB1. That is, as described above, the input circuit 01 can control the potential of the third sub-node QB1 in the second node QB; the first output circuit 02 can control the first power supply end VGH and the shift output end CR <n>the on / off of the second node QB; and the third output circuit 04 can control the second power terminal VGL1 and the scan output terminal G <n>The second output circuit 03 can be coupled with the fifth sub-node QB3. That is, the second output circuit 03 can control the on-off of the reference clock terminal CKC and the redundant output terminal GD in response to the potential of the fifth sub-node QB3 in the second node QB.

[0184] On this basis, with reference to FIG. 8, it can be seen that the shift register unit can further include a fourth control circuit 08.

[0185] The fourth control circuit 08 can be coupled with the third power terminal VGL2, the third sub-node QB1 and the fifth sub-node QB3 respectively. The fourth control circuit 08 can be configured to control the on-off of the third sub-node QB1 and the fifth sub-node QB3 in response to the third power signal provided by the third power terminal VGL2, and control the on-off of the third sub-node QB1 and the fifth sub-node QB3 in response to the potential of the fifth sub-node QB3.

[0186] For example, the fourth control circuit 08 can control the third sub-node QB1 and the fifth sub-node QB3 to be turned on when the potential of the third power signal provided by the third power terminal VGL2 is the first potential. In addition, the fourth control circuit 08 can control the third sub-node QB1 and the fifth sub-node QB3 to be turned on when the potential of the fifth sub-node QB3 is the first potential, and can control the third sub-node QB1 and the fifth sub-node QB3 to be decoupled when the potential of the fifth sub-node QB3 is the second potential.

[0187] It can be understood that, like the second control circuit 06, the fourth control circuit 08 can also have an isolation effect. For example, the fourth control circuit 08 can better isolate the input circuit 01 and the third output circuit 04.

[0188] Optionally, on the basis that the second node QB further includes a fourth sub-node QB2, with reference to FIG. 8, it can be seen that the third output circuit 04 can be coupled with the fourth sub-node QB2 in the second node QB, and the fourth control circuit 08 can be further coupled with the fourth sub-node QB2, and can control the on-off of the fourth sub-node QB2 and the fifth sub-node QB3 in response to the potential of the fifth sub-node QB3, instead of controlling the on-off of the third sub-node QB1 and the fifth sub-node QB3.

[0189] Optionally, FIG. 9 is a structural schematic diagram of another shift register unit provided by the embodiment of the present disclosure. As shown in FIG. 9, the input circuit 01 can include a first input sub-circuit 011 and a second input sub-circuit 012.

[0190] The first input sub-circuit 011 can be coupled to the first clock terminal CKA, the first input terminal IN1, the first node Q, the second node QB, the second clock terminal CKB and the first power supply terminal VGH respectively. The first input sub-circuit 011 can be configured to control the first input terminal IN1 and the first node Q in response to the first clock signal, and control the first power supply terminal VGH and the first node Q in response to the potential of the second node QB and the second clock signal, so as to control the potential of the first node Q.

[0191] For example, the first input sub-circuit 011 can control the first input terminal IN1 and the first node Q to be conductive when the potential of the first clock signal is the first potential, so that the first input signal provided by the first input terminal IN1 is transmitted to the first node Q; and the first input sub-circuit 011 can control the first input terminal IN1 and the first node Q to be decoupled when the potential of the first clock signal is the second potential. In addition, the first input sub-circuit 011 can control the first power supply terminal VGH and the first node Q to be conductive when the potential of the second node QB and the potential of the second clock signal are both the first potential, so that the first power signal provided by the first power supply terminal VGH is transmitted to the first node Q; and the first input sub-circuit 011 can control the first power supply terminal VGH and the first node Q to be decoupled when the potential of the second node QB and / or the potential of the second clock signal is the second potential.

[0192] The second input sub-circuit 012 can be coupled to the input control terminal Con, the second input terminal IN2, the first node Q and the second node QB respectively. The second input sub-circuit 012 can be configured to control the second input terminal IN2 and the second node QB in response to the input control signal provided by the input control terminal Con, and control the input control terminal Con and the second node QB in response to the potential of the first node Q, so as to control the potential of the second node QB.

[0193] For example, the second input sub-circuit 012 can control the second input terminal IN2 and the second node QB to be conductive when the potential of the input control signal provided by the input control terminal Con is the first potential, so that the second input signal provided by the second input terminal IN2 is transmitted to the second node QB; and the second input sub-circuit 012 can control the second input terminal IN2 and the second node QB to be decoupled when the potential of the input control signal provided by the input control terminal Con is the second potential. In addition, the second input sub-circuit 012 can control the input control terminal Con and the second node QB to be conductive when the potential of the first node Q is the first potential, so that the input control signal provided by the input control terminal Con is transmitted to the second node QB; and the second input sub-circuit 012 can control the input control terminal Con and the second node QB to be decoupled when the potential of the first node Q is the second potential.

[0194] It can be understood that, on the basis that the first node Q is divided into the first sub-node Q1 and the second sub-node Q2, and the second node QB is divided into the third sub-node QB1, the fourth sub-node QB2 and the fifth sub-node QB3, the first input sub-circuit 011 and the second input sub-circuit 012 can be coupled with the first sub-node Q1 and the third sub-node QB1. That is, the first input sub-circuit 011 can control the on-off of the first input end IN1 and the first sub-node Q1 in the first node Q in response to the first clock signal, and control the on-off of the first power supply end VGH and the first sub-node Q1 in the first node Q in response to the potential of the third sub-node QB1 in the second node QB and the second clock signal. In addition, the second input sub-circuit 012 can control the on-off of the second input end IN2 and the third sub-node QB1 in the second node QB in response to the input control signal provided by the input control end Con, and control the on-off of the input control end Con and the third sub-node QB1 in the second node QB in response to the potential of the first sub-node Q1 in the first node Q.

[0195] Alternatively, as an optional implementation manner, as shown in FIG. 9, the input control end Con and the second input end IN2 can be the first clock end CKA and the third power supply end VGL2 respectively. That is, the second input sub-circuit 012 can be used to control the on-off of the third power supply end VGL2 and the third sub-node QB1 in the second node QB in response to the first clock signal provided by the first clock end CKA, and control the on-off of the first clock end CKA and the third sub-node QB1 in the second node QB in response to the potential of the first sub-node Q1 in the first node Q.

[0196] Alternatively, as another optional implementation manner, as shown in FIG. 10, the input control end Con and the second input end IN2 can be the first power supply end VGH and the second clock end CKB respectively. That is, the second input sub-circuit 012 can be used to control the on-off of the second clock end CKB and the third sub-node QB1 in the second node QB in response to the first power supply signal provided by the first power supply end VGH, and control the on-off of the first power supply end VGH and the third sub-node QB1 in the second node QB in response to the potential of the first sub-node Q1 in the first node Q.

[0197] Optionally, in the case that the input control terminal Con and the second input terminal IN2 are the first power terminal VGH and the second clock terminal CKB respectively, the second input sub-circuit 012 can further comprise a second capacitor C2 coupled between the second input terminal IN2 and the input control terminal Con. Accordingly, it can be understood that the second input sub-circuit 012 can adjust the input control signal based on the second input signal provided by the second input terminal IN2 under the coupling effect of the second capacitor C2. That is, the second input sub-circuit 012 can adjust the input control signal based on the second input signal provided by the second input terminal IN2 under the coupling effect. It can be further understood with reference to FIG. 10 that the shift register unit can further comprise a fifth control circuit 09.

[0198] The fifth control circuit 09 can be coupled with the first node Q, the input control terminal Con and the second input sub-circuit 012 respectively. The fifth control circuit 09 can be configured to control the on-off of the input control terminal Con and the second input sub-circuit 012 in response to the potential of the first node Q.

[0199] For example, the fifth control circuit 09 can control the input control terminal Con (i.e., the first power terminal VGH) and the second input sub-circuit 012 to be conductive when the potential of the first node Q is the first potential, so that the input control signal provided by the input control terminal Con (i.e., the first power signal provided by the first power terminal VGH) is transmitted to the second input sub-circuit 012; and the fifth control circuit 09 can control the input control terminal Con and the second input sub-circuit 012 to be decoupled when the potential of the first node Q is the second potential.

[0200] It can be understood that, as described above, the fifth control circuit 09 can be coupled with the first sub-node Q1 based on the division of the first node Q into the first sub-node Q1 and the second sub-node Q2. That is, the fifth control circuit 05 can control the on-off of the input control terminal Con and the second input sub-circuit 012 in response to the potential of the first sub-node Q1 in the first node Q.

[0201] It can be further understood that the second input sub-circuit 012 is also directly coupled with the first power terminal VGH and is configured to control the on-off of the first power terminal VGH and the second node QB in response to the potential of the first node Q. That is, the fifth control circuit 05 can control the on-off of the first power terminal VGH and the second input sub-circuit 012, so that the second input sub-circuit 012 further controls the on-off of the second input terminal IN2 and the second node QB in response to the first power signal provided by the first power terminal VGH.

[0202] Optionally, based on FIG. 9, FIG. 11 shows a structural schematic diagram of still another shift register unit provided by an embodiment of the present disclosure. Based on FIG. 10, FIG. 12 shows a structural schematic diagram of still another shift register unit provided by an embodiment of the present disclosure. As shown in FIG. 11 and FIG. 12, the second node QB can include a third sub-node QB1 and a sixth sub-node QB4.

[0203] The first input sub-circuit 011, the second input sub-circuit 012, the first output circuit 02 and the third output circuit 04 can all be coupled with the third sub-node QB1. That is, as described above, the first input sub-circuit 011 can control the potential of the first sub-node Q1 in the first node Q in response to the potential of the third sub-node QB1 in the second node QB; the second input sub-circuit 012 can control the potential of the third sub-node QB1 in the second node QB; the first output circuit 02 can control the first power supply end VGH and the shift output end CR <n>the third output circuit 04 can control the connection / disconnection between the second power supply terminal VGL1 and the scan output terminal G <n>The fourth control circuit 08 can be coupled with the sixth sub-node QB4. That is, the fourth control circuit 08 can control the on-off of the sixth sub-node QB4 and the fifth sub-node QB3 in the second node QB in response to the third power signal provided by the third power supply end VGL2.

[0204] On this basis, with continuous reference to FIG. 11 and FIG. 12, it can be seen that the input circuit 01 can further include a third input sub-circuit 013.

[0205] The third input sub-circuit 013 can be coupled with the input control end Con, the second input end IN2, the first node Q and the sixth sub-node QB4 respectively. The third input sub-circuit 013 can be used to control the on-off of the second input end IN2 and the sixth sub-node QB4 in response to the input control signal, and control the on-off of the input control end Con and the sixth sub-node QB4 in response to the potential of the first node Q. That is, the third input sub-circuit 013 and the second input sub-circuit 012 can be input sub-circuits with the same function.

[0206] For example, the third input sub-circuit 013 can control the second input end IN2 and the sixth sub-node QB4 to be conductive when the potential of the input control signal is the first potential, so that the second input signal provided by the second input end IN2 is transmitted to the sixth sub-node QB4; and the third input sub-circuit 013 can control the second input end IN2 and the sixth sub-node QB4 to be decoupled when the potential of the input control signal is the second potential. And the third input sub-circuit 013 can control the input control end Con and the sixth sub-node QB4 to be conductive when the potential of the first node Q is the first potential, so that the input control signal provided by the input control end Con is transmitted to the sixth sub-node QB4; and the third input sub-circuit 013 can control the input control end Con and the sixth sub-node QB4 to be decoupled when the potential of the first node Q is the second potential.

[0207] It can be understood that, on the basis of the first node Q being divided into the first sub-node Q1 and the second sub-node Q2, the third input sub-circuit 013 here can be coupled with the first sub-node Q1 in the first node Q. That is, the third input sub-circuit 013 can control the on-off of the input control end Con and the sixth sub-node QB4 in response to the potential of the first sub-node Q1 in the first node Q.

[0208] Optionally, in combination with the embodiments described in the foregoing, FIG. 13 to FIG. 34 schematically show the circuit structure schematic diagram of the shift register unit under different embodiments.

[0209] Optionally, with reference to FIG. 13 to FIG. 34, it can be seen that the first control circuit 05 can include a first transistor T1.

[0210] The gate of the first transistor T1 can be coupled with the third power supply end VGL2, the first pole of the first transistor T1 can be coupled with the first sub-node Q1, and the second pole of the first transistor T1 can be coupled with the second sub-node Q2.

[0211] Optionally, as an optional implementation, it can be seen from FIGS. 16 to 33 that the second control circuit 06 can include a second transistor T2.

[0212] The gate of the second transistor T2 can be coupled with the third power supply end VGL2, the first pole of the second transistor T2 can be coupled with the third sub-node QB1, and the second pole of the second transistor T2 can be coupled with the fourth sub-node QB2.

[0213] Optionally, as another optional implementation, it can be seen from FIG. 26 that the second control circuit 06 can include two second transistors T2-1 and T2-2 connected in series.

[0214] The gates of the two second transistors T2-1 and T2-2 can be coupled with the third power supply end VGL2, the first poles of the two second transistors T2-1 and T2-2 can be coupled with the third sub-node QB1 and the fourth sub-node QB2 respectively, and the second poles of the two second transistors T2-1 and T2-2 can be coupled with the series node P0. Correspondingly, it can be seen from FIG. 26 that the shift register unit can further include an anti-leakage circuit 10.

[0215] The anti-leakage circuit 10 can be coupled with the fourth sub-node QB2, the fourth power supply end VGL3 and the series node P0 respectively. The anti-leakage circuit 10 can be configured to control the fourth power supply end VGL3 and the series node P0 in response to the potential of the fourth sub-node QB2.

[0216] For example, the anti-leakage circuit 10 can control the fourth power supply end VGL3 and the series node P0 to be conductive when the potential of the fourth sub-node QB2 is a first potential, so that the fourth power supply signal provided by the fourth power supply end VGL3 is transmitted to the series node P0; and the anti-leakage circuit 10 can control the fourth power supply end VGL3 and the series node P0 to be decoupled when the potential of the fourth sub-node QB2 is a second potential.

[0217] Optionally, as shown in FIG. 27, the anti-leakage circuit 10 can include a third transistor T3.

[0218] The gate of the third transistor T3 can be coupled with the fourth sub-node QB2, the first pole of the third transistor T3 can be coupled with the fourth power supply end VGL3, and the second pole of the third transistor T3 can be coupled with the series node P0.

[0219] It can be understood that the potential of the fourth power signal provided by the fourth power terminal VGL3 can be a low potential, and the potential of the fourth power signal provided by the fourth power terminal VGL3 can be less than or equal to the third power terminal VGL2. In this way, the leakage path of the fourth sub-node QB2 to the third sub-node QB1 can be prevented, thereby facilitating low-frequency driving.

[0220] Alternatively, as another optional implementation, referring to FIG. 28, the second control circuit 06 can also be coupled with the first node Q, and can also be used to control the on-off of the third sub-node QB1 and the fourth sub-node QB2 in response to the third power signal and the potential of the first node Q. Here, the first node Q can refer to any of the sub-nodes Q1, Q2 and Q3 included in the first node Q. In this way, the purpose of preventing leakage can still be achieved, and the anti-leakage circuit 10 can be omitted.

[0221] That is, on this basis, referring to FIG. 28, the second control circuit 06 can include two second transistors T2-1 and T2-2 connected in series.

[0222] And the gates of the two second transistors T2-1 and T2-2 can be coupled with the third power terminal VGL2 and the first node Q respectively, the first poles of the two second transistors T2 can be coupled with the third sub-node QB1 and the fourth sub-node QB2 respectively, and the second poles of the two second transistors T2-1 and T2-2 are coupled.

[0223] Of course, in some other embodiments, other transistors (such as the first transistor T1) whose gates are coupled with the third power terminal VGL2 can also be designed as the structure of the second control circuit 06, such as providing that the first transistor T1 includes two transistors connected in series to achieve the purpose of preventing leakage.

[0224] Alternatively, referring to FIGS. 17-33, the third control circuit 07 can include a fourth transistor T4.

[0225] The gate of the fourth transistor T4 can be coupled with the third power terminal VGL2, the first pole of the fourth transistor T4 can be coupled with the first control sub-node N11, and the second pole of the fourth transistor T4 can be coupled with the second control sub-node N12.

[0226] Alternatively, referring to FIGS. 20-28 and 33, the fourth control circuit 08 can include a fifth transistor T5 and a sixth transistor T6.

[0227] The gate of the fifth transistor T5 can be coupled with a third power supply end VGL2, the first electrode of the fifth transistor T5 can be coupled with a third sub-node QB1, and the second electrode of the fifth transistor T5 can be coupled with a fifth sub-node QB3.

[0228] The gate and the second electrode of the sixth transistor T6 can be coupled with the fifth sub-node QB3, and the first electrode of the sixth transistor T6 can be coupled with the third sub-node QB1.

[0229] Optionally, it can be seen with reference to FIGS. 13 to 34 that the first input sub-circuit 011 can include a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The second input sub-circuit 012 can include a tenth transistor T10 and an eleventh transistor T11.

[0230] The gate of the seventh transistor T7 can be coupled with a first clock end CKA, the first electrode of the seventh transistor T7 can be coupled with a first input end IN1, and the second electrode of the seventh transistor T7 can be coupled with a first node Q.

[0231] The gate of the eighth transistor T8 can be coupled with a second node QB, the first electrode of the eighth transistor T8 can be coupled with a first power supply end VGH, and the second electrode of the eighth transistor T8 can be coupled with the first electrode of the ninth transistor T9.

[0232] The gate of the ninth transistor T9 can be coupled with a second clock end CKB, and the second electrode of the ninth transistor T9 can be coupled with the first node Q.

[0233] The gate of the tenth transistor T10 can be coupled with an input control end Con, the first electrode of the tenth transistor T10 can be coupled with a second input end IN2, and the second electrode of the tenth transistor T10 can be coupled with the second node QB.

[0234] The gate of the eleventh transistor T11 can be coupled with the first node Q, the first electrode of the eleventh transistor T11 can be coupled with the input control end Con, and the second electrode of the eleventh transistor T11 can be coupled with the second node QB.

[0235] Optionally, it can be seen with reference to FIGS. 13 to 21, FIGS. 29 to 32, and FIG. 34 that the fifth control circuit 09 can include a twelfth transistor T12.

[0236] The gate of the twelfth transistor T12 can be coupled with the first node Q, the first electrode of the twelfth transistor T12 can be coupled with the input control end Con, and the second electrode of the twelfth transistor T12 can be coupled with the second input sub-circuit 012.

[0237] Optionally, with continued reference to FIG. 21, FIG. 23-28, and FIG. 33, the third input sub-circuit 013 can include a thirteenth transistor T13 and a fourteenth transistor T14.

[0238] The gate of the thirteenth transistor T13 can be coupled with the input control end Con, the first electrode of the thirteenth transistor T13 can be coupled with the second input end IN2, and the second electrode of the thirteenth transistor T13 can be coupled with the second node QB.

[0239] The gate of the fourteenth transistor T14 can be coupled with the first node Q, the first electrode of the fourteenth transistor T14 can be coupled with the input control end Con, and the second electrode of the fourteenth transistor T14 can be coupled with the second node QB.

[0240] Optionally, with continued reference to FIG. 13-33, the first output circuit 02 can include a fifteenth transistor T15, a sixteenth transistor T16, and a third capacitor C3. Accordingly, the first output circuit 02 can be capable of outputting a shift output end CR <n>The potential of the first node Q is adjusted by the potential of the first output circuit 02. That is, the first output circuit 02 can also be used to couple the effect of the shift output CR <n>The potential of the first node Q is adjusted by the potential of the first output circuit 02. The second output circuit 03 can include a seventeenth transistor T17 and an eighteenth transistor T18. The third output circuit 04 can include a nineteenth transistor T19 and a twentieth transistor T20.

[0241] The gate of the fifteenth transistor T15 can be coupled with the first node Q, the first pole of the fifteenth transistor T15 can be coupled with the second clock end CKB, and the second pole of the fifteenth transistor T15 can be coupled with the shift output end CR <n>coupled.

[0242] The gate of the sixteenth transistor T16 can be coupled with the second node QB, the first pole of the sixteenth transistor T16 can be coupled with the first power supply end VGH, and the second pole of the sixteenth transistor T16 can be coupled with the shift output end CR <n>coupled.

[0243] The third capacitor C3 can be coupled between the first node Q and the shift output terminal CR <n>between.

[0244] The gate of the seventeenth transistor T17 can be coupled with the first control node N1, the first pole of the seventeenth transistor T17 can be coupled with the first power supply end VGH, and the second pole of the seventeenth transistor T17 can be coupled with the redundant output end GD.

[0245] The gate of the eighteenth transistor T18 can be coupled with the second node QB, the first pole of the eighteenth transistor T18 can be coupled with the reference clock end CKC, and the second pole of the eighteenth transistor T18 can be coupled with the redundant output end GD.

[0246] The gate of the nineteenth transistor T19 can be coupled with the second control node N2, the first pole of the nineteenth transistor T19 can be coupled with the third clock end GCK, and the second pole of the nineteenth transistor T19 can be coupled with the scan output end G <n>coupled.

[0247] The gate of the twentieth transistor T20 can be coupled with the second node QB, the first pole of the twentieth transistor T20 can be coupled with the second power supply end VGL1, and the second pole of the twentieth transistor T20 can be coupled with the scan output end G <n>Coupled.

[0248] It can be understood that the input control end Con of the shift register unit coupling shown in FIGS. 13-21, 29-32, and 34 is all the first power end VGH, and the second input end IN2 of the coupling is all the second clock end CKB. The input control end Con of the shift register unit coupling shown in FIGS. 22-28 and 33 is all the first clock end CKA, and the second input end IN2 of the coupling is all the third power end VGL2.

[0249] Optionally, in some embodiments, it can be seen in combination with FIGS. 22-28 and 33 that, on the basis that the input control end Con of the shift register unit coupling is all the first clock end CKA, and the second input end IN2 of the coupling is all the third power end VGL2, the third output circuit 04 can further include a connection between the shift output end G <n>a fourth capacitance C4 between the second node QB and a ground. Accordingly, it is known that the third output circuit 04 is also capable of outputting the shifted output signal CR based on the second node QB under the coupling action of the fourth capacitance C4. <n>The potential of the first node Q is adjusted.

[0250] That is, the shift register unit provided by the embodiments of the present disclosure can at least include the following various embodiments (it can be understood that each circuit mentioned in the following embodiments includes the device structure shown in the corresponding figure, and will not be described one by one):

[0251] Embodiment 1: In combination with FIG. 13, the shift register unit includes an input circuit 01, a first output circuit 02, a second output circuit 03, and a third output circuit 04. Moreover, the input circuit 01 can include a first input sub-circuit 011 and a second input sub-circuit 012, and the input control end Con and the second input end IN2 coupled to the second input sub-circuit 012 are respectively the first power supply end VGH and the second clock end CKB. Correspondingly, the shift register unit further includes a fifth control circuit 09. Moreover, the first node Q is divided into a first sub-node Q1 and a second sub-node Q2. Correspondingly, the shift register unit further includes a first control circuit 05. Moreover, the reference clock end CKC can be shared with the first clock end CKA. In this way, the wiring can be simplified, and the cost can be saved.

[0252] Embodiment 2: In combination with FIG. 14, compared with the structure shown in FIG. 13, the reference clock end CKC shared with the first clock end CKA is replaced by being shared with the second clock end CKB. In this way, the wiring can be simplified, and the cost can be saved.

[0253] Embodiment 3: In combination with FIG. 15, compared with the structure shown in FIG. 13, the reference clock end CKC shared with the first clock end CKA / second clock end CKB is replaced by being independent of the first clock end CKA and the second clock end CKB. Moreover, as described above, the falling edge of the reference clock signal provided by the independent reference clock end CKC is located after the falling edge of the second clock signal provided by the second clock end CKB. In this way, the potential stability of the second node QB can be further ensured to be good.

[0254] Embodiment 4: In combination with FIG. 16, compared with any one of the structures shown in FIGS. 13 to 15, the second node QB is divided into a third sub-node QB1 and a fourth sub-node QB2, and the shift register unit further includes a second control circuit 06. In this way, as described above, a good isolation effect can be achieved, and the bootstrap effect of the capacitor can be prevented from being affected.

[0255] Embodiment 5: in combination with FIG. 17, relative to the structure shown in FIG. 16, dividing the first control node N1 and the second control node N2 both includes the first control sub-node N11 and the second control sub-node N12, and a shift register unit is also provided to include the third control circuit 07 coupled between the first control sub-node N11 and the second output circuit 03 and the third output circuit 04. In this way, a better isolation effect can be achieved, and the bootstrap effect of the capacitor can be prevented from being affected.

[0256] Embodiment 6: in combination with FIG. 18, relative to the structure shown in FIG. 17, only dividing the second control node N2 includes the first control sub-node N11 and the second control sub-node N12. Correspondingly, the shift register unit is provided to include the third control circuit 07 coupled between the first control sub-node N11 and the third output circuit 04. That is, relative to FIG. 17, the position of the third control circuit 07 is changed. In this way, the NBTS of the seventeenth transistor T17 included in the second output circuit 03 can be reduced.

[0257] Embodiment 7: in combination with FIG. 19, relative to the structure shown in FIG. 18, the reference clock end CKC and the second clock end CKB2 are shared. Here, the second clock end CKB2 can refer to the second clock end CKB2 coupled to the shift register unit coupled to the even-numbered row of pixels. That is, in some embodiments, for the shift register unit coupled to the odd-numbered row of pixels, the corresponding coupled clock end can include: the first clock end CKA, the second clock end CKB, and the third clock ends GCK1 and GCK3; for the shift register unit coupled to the even-numbered row of pixels, the corresponding coupled clock end can include: the first clock end CKA2, the second clock end CKB2, and the third clock ends GCK2 and GCK4. In other words, double clocks can be used to drive the shift register unit coupled to the odd-numbered row of pixels and the shift register unit coupled to the even-numbered row of pixels to work, respectively.

[0258] Embodiment 8: in combination with FIG. 20, relative to the structure shown in FIG. 18, on the basis of dividing the second node QB to include the third sub-node QB1 and the fourth sub-node QB2, the second node QB is also divided to include the fifth sub-node QB3. Correspondingly, the shift register unit is also provided to include the fourth control circuit 08. In this way, a better isolation effect can be achieved, and the bootstrap effect of the capacitor can be prevented from being affected.

[0259] Embodiment 9: in combination with FIG. 21, relative to the structure shown in FIG. 20, on the basis of dividing the second node QB to include the third sub-node QB1, the fourth sub-node QB2 and the fifth sub-node QB3, the second node QB is also divided to include the sixth sub-node QB4. Correspondingly, the input circuit 01 in the shift register unit includes the third input sub-circuit 013. In this way, the operation of the second output circuit 03 can be ensured to be controlled individually and reliably.

[0260] Embodiment 10: In combination with Fig. 22, the input control end Con coupled with the second input sub-circuit 012 is replaced by the first clock end CKA from the first power end VGH relative to the structure shown in Fig. 20, and correspondingly, the second input end IN2 coupled with the second input sub-circuit 012 is replaced by the third power end VGL2 from the second clock end CKB, and at the same time, the fifth control circuit 09 is omitted. In this way, the structure can be simplified, and the cost can be saved.

[0261] Embodiment 11: In combination with Fig. 23, based on the division of the second node QB including the third sub-node QB1, the fourth sub-node QB2 and the fifth sub-node QB3 relative to the structure shown in Fig. 22, the second node QB is further divided to include the sixth sub-node QB4. Correspondingly, the input circuit 01 in the shift register unit further includes the third input sub-circuit 013. That is, similar to the change of Fig. 21 relative to Fig. 20.

[0262] Embodiment 12: In combination with Fig. 24, the first control sub-node N11 included in the first control node N1 and the second control node N2 is replaced by the first sub-node Q1 from the second sub-node Q2 relative to the structure shown in Fig. 23. That is, the second output circuit 03 is coupled with the first sub-node Q1, and the third output circuit 04 is coupled with the first sub-node Q1 through the third control circuit 07. In this way, the nineteenth transistor T19 can not be in series with the fifteenth transistor T15 and the seventeenth transistor T17, so that mutual interference between the nineteenth transistor T19 and the fifteenth transistor T15 can be avoided.

[0263] Embodiment 13: In combination with Fig. 25, the second output circuit 03 coupled with the first sub-node Q1 is replaced by being coupled with the second sub-node Q2 relative to the structure shown in Fig. 24. In this way, mutual interference between the nineteenth transistor T19 and the fifteenth transistor T15 can also be avoided.

[0264] Embodiment 14: In combination with Fig. 26 and Fig. 27, the second control circuit 06 is set to include two second transistors T2-1 and T2-2 in series instead of one second transistor T2 relative to the structure shown in Fig. 24, and the gates of the two second transistors T2-1 and T2-2 are both coupled with the same third power end VGL2. Correspondingly, the shift register unit further includes the anti-leakage circuit 10. In this way, as previously described, the leakage path from the fourth sub-node QB2 to the third sub-node QB1 can be blocked, a better anti-leakage effect can be achieved, and low-frequency driving can be facilitated.

[0265] In the structure shown in FIG. 27, the second control circuit 06 includes two second transistors T2-1 and T2-2 connected in series, one of the two second transistors T2-1 is coupled to the third power supply end VGL2, and the other second transistor T2-2 is coupled to the node Q1, Q2 or Q3 included in the first node Q. Accordingly, the leakage prevention circuit 10 can be omitted. In this way, not only a better leakage prevention effect can be achieved, but also the structure can be simplified and the cost can be saved.

[0266] In the structure shown in FIG. 27, the second control circuit 06 includes two second transistors T2-1 and T2-2 connected in series, one of the two second transistors T2-1 is coupled to the third power supply end VGL2, and the other second transistor T2-2 is coupled to the node Q1, Q2 or Q3 included in the first node Q. Accordingly, the leakage prevention circuit 10 can be omitted. In this way, not only a better leakage prevention effect can be achieved, but also the structure can be simplified and the cost can be saved. <n>That is, the second output circuit 03 and the third output circuit 04 are both set to be connected to the shift output terminal CR <n>coupled. In this way, the scan output G <n>Time in floating.

[0267] Example 17: In combination with Figure 30, relative to the structure shown in Figure 16, the second output circuit 03 and the third output circuit 04 are arranged to be connected to the shift output end CR <n>Coupling.

[0268] Embodiment 18: In combination with Figure 31, relative to the structure shown in Figure 17, the second output circuit 03 and the third output circuit 04 are both arranged to pass through the third control circuit 07 and the shift output terminal CR <n>Coupling.

[0269] Example 19: In combination with Figure 32, relative to the structure shown in Figure 18, the second output circuit 03 is provided with a shift output end CR <n>coupled, and the third output circuit 04 is arranged to be coupled to the shift output terminal CR via the third control circuit 07 <n>Coupling.

[0270] Example 20: In connection with Fig. 33, in relation to the structure shown in Fig. 24, the third output circuit 04 is provided with a third control circuit 07 and a shift output terminal CR <n>Coupling.

[0271] Example 21: In combination with Figure 34, relative to the structure shown in 13, the second output circuit 03 is omitted, and the third output circuit 04 is provided with the shift output end CR <n>Coupled.

[0272] It can be understood that each of the above embodiments described in combination with FIGS. 13 to 34 is only illustrative, and various modifications of the circuit should be included in combination with any of the structures shown in FIGS. 1 to 12, which will not be described one by one here. For example, for FIGS. 22 to 33, the second clock end CKB coupled to the eighteenth transistor T18 can be replaced by the first clock end CKA.

[0273] Optionally, the transistors included in the shift register unit can all be P-type transistors, and the scan output end G <n>The N-type transistor in the pixel can be coupled with the gate line. That is, as described above, the shift register unit provided by the embodiments of the present disclosure can be a circuit of LTPS structure, and the pixel circuit can be a circuit of oxide structure, and the shift register unit can be applied in the architecture of LTPO+. Moreover, the shift register unit of LTPS structure can realize the secondary bootstrap of low potential through the dummy output part, so that the scan output part can output the low potential to the scan output end G <n>The signal outputting low potential reliably, and noise reduction is realized.

[0274] In conclusion, the shift register unit is provided in the embodiments of the present disclosure. In the shift register unit, the input circuit can control the potentials of the first node and the second node. The first output circuit can control the second clock terminal or the first power terminal to output a signal to the shift output terminal in response to the potentials of the first node and the second node. The second output circuit can control the first power terminal or the reference clock terminal to output a signal to the redundant output terminal in response to the potentials of the first node and the second node, and the second output circuit includes a capacitor coupled between the second node and the redundant output terminal, and accordingly, the second output circuit can be coupled to the capacitor. The third output circuit can control the third clock terminal or the second power terminal to output a signal to the scan output terminal in response to the potentials of the first node and the second node. In this way, the reference clock signal provided by the reference clock terminal can be flexibly set, so that the second output circuit controls the potential of the first node to remain stable, and the third output circuit reliably outputs a signal, such as a gate drive signal, to the scan output terminal, thereby reliably driving the pixel to emit light, and ensuring that the display effect of the display panel is better.

[0275] The embodiments of the present disclosure further provide a driving method of the shift register unit, which can be used to drive the shift register unit as described in the above embodiments. As shown in FIG. 35, the method includes the following steps.

[0276] In step 3501, in the first stage, the input circuit controls the potential of the first node to be the first potential and controls the potential of the second node to be the second potential based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, and the first input signal provided by the first input terminal, the first output circuit controls the second clock terminal and the shift output terminal to be conductive in response to the potential of the first node, the second output circuit controls the first power terminal and the redundant output terminal to be conductive in response to the potential of the first control node, and the third output circuit controls the third clock terminal and the scan output terminal to be conductive in response to the potential of the second control node.

[0277] In step 3502, in the second stage, the input circuit controls the potential of the first node to be the second potential and controls the potential of the second node to be the first potential based on the first clock signal, the second clock signal, and the first input signal, the first output circuit controls the first power terminal and the shift output terminal to be conductive in response to the potential of the second node, the second output circuit controls the reference clock terminal and the redundant output terminal to be conductive in response to the potential of the second node, and adjusts the potential of the second node based on the potential of the redundant output terminal through the coupling effect, and the third output circuit controls the second power terminal and the scan output terminal to be conductive in response to the potential of the second node.

[0278] Optionally, in combination with FIG. 34, taking the example that the gate of the nineteenth transistor T19 is coupled with the second sub-node Q2, in combination with FIG. 36, the working process of the shift register unit is briefly described as follows:

[0279] In stage t01, the potential of the start signal provided by the start signal terminal STV, the potential of the first clock signal provided by the first clock terminal CKA and the potential of the third clock signal provided by the third clock terminal GCK are all low potentials, and the potential of the second clock signal provided by the second clock terminal CKB is a high potential. Correspondingly, the seventh transistor T7 can be turned on, and the ninth transistor T9 can be turned off. Further, the low potential start signal can be transmitted to the first sub-node Q1 through the turned-on seventh transistor T7. In addition, because the potential of the third power signal provided by the third power supply terminal VGL2 is a low potential, the first transistor T1 can be turned on, and the low potential start signal transmitted to the first sub-node Q1 can be transmitted to the second sub-node Q2 through the turned-on first transistor T1.

[0280] That is, in this stage t01, the potential of the first sub-node Q1 and the potential of the second sub-node Q2 can be set to low potentials. On this basis, the eleventh transistor T11 and the twelfth transistor T12 can be turned on, and further the high potential first power signal provided by the first power supply terminal VGH can be transmitted to the gate of the tenth transistor T10 and the second node QB through the turned-on eleventh transistor T11 and the twelfth transistor T12 respectively, so that the eighth transistor T8 and the tenth transistor T10 are turned off. That is, in this stage t01, the potential of the second node QB can be set to a low potential.

[0281] On the basis that the potential of the first sub-node Q1 and the potential of the second sub-node Q2 are low potentials and the potential of the second node QB is a high potential, the sixteenth transistor T16 and the twentieth transistor T20 can be turned off, and the fifteenth transistor T15 and the nineteenth transistor T19 can be turned on, so that the high potential second clock signal provided by the second clock terminal CKB is transmitted to the shift output terminal CR <n>and the low level third clock signal provided by the third clock terminal GCK is transmitted to the scan output terminal G through the opened nineteenth transistor T19 <n>. That is, in this stage t01, the shift register unit can be shifted out of the CR <n>and scan out G <n>The second clock signal with a high level and the third clock signal with a low level are output respectively.

[0282] In the stage t02 to the stage t03, the potential of the start signal provided by the start signal terminal STV and the potential of the first clock signal provided by the first clock terminal CKA are both high, the potential of the second clock signal provided by the second clock terminal CKB is low first and then high, and the potential of the third clock signal provided by the third clock terminal GCK is high first and then low. In addition, under the coupling of the capacitor, the potential of the second sub-node Q2 and the potential of the second node QB can be kept as the low potential and the high potential of the stage t01 respectively, that is, in the stage t02 to the stage t03, the sixteenth transistor T16 and the twentieth transistor T20 can be kept off, and the fifteenth transistor T15 and the nineteenth transistor T19 can be kept on. Correspondingly, the shift register unit can be made to output the data signal through the shift output terminal CR <n>and scan out G <n>The second clock signal of low potential and the third clock signal of high potential are output respectively, and then output through the shift output terminal CR <n>and scan out G <n>The second clock signal with a high potential and the third clock signal with a low potential are output respectively.

[0283] In stage t04, the potential of the first clock signal provided by the first clock terminal CKA becomes a low potential, at the same time, the potential of the enable signal provided by the enable signal terminal STV and the potential of the second clock signal provided by the second clock terminal CKB are both high potentials, and the potential of the third clock signal provided by the third clock terminal GCK is a low potential. Correspondingly, the seventh transistor T7 is enabled again, and the ninth transistor T9 is turned off. Further, the high potential enable signal is transmitted to the first sub-node Q1 through the enabled seventh transistor T7, and then transmitted to the second sub-node Q2 through the enabled first transistor T1. That is, in the stage t04, the potential of the first sub-node Q1 and the potential of the second sub-node Q2 can be set to high potentials. On this basis, the eleventh transistor T11 and the twelfth transistor T12 are both turned off, and the tenth transistor T10 remains off in response to the high potential second clock signal. That is, in the stage t04, the potential of the second node QB can remain a high potential. On the basis that the potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the second node QB are all high potentials, the sixteenth transistor T16 and the twentieth transistor T20 are both turned off, and the fifteenth transistor T15 and the nineteenth transistor T19 are both turned off, so that the shift output terminal CR <n>and scan out G <n>Under the coupling of the capacitor, the high potential and the low potential of the previous stage t03 are maintained respectively.

[0284] In stage t05, the potential of the second clock signal provided by the second clock terminal CKB becomes low potential, while the potential of the first clock signal provided by the first clock terminal CKA, the potential of the start signal provided by the start signal terminal STV and the potential of the third clock signal provided by the third clock terminal GCK are all high potential. Correspondingly, the ninth transistor T9 and the tenth transistor T10 are both turned on, and the seventh transistor T7 is turned off. Then the low potential second clock signal is transmitted to the second node QB through the turned-on tenth transistor T10. On this basis, the eighth transistor T8 is turned on, and on the basis that the eighth transistor T8 and the ninth transistor T9 are both turned on, the high potential first power signal provided by the first power supply terminal VGH is transmitted to the first sub-node Q1 through the turned-on eighth transistor T8 and the ninth transistor T9 in turn, and then transmitted to the second sub-node Q2 through the turned-on first transistor T1. That is, in this stage t05, the potential of the first sub-node Q1 and the potential of the second sub-node Q2 can be set to high potential, and the potential of the second node QB can be set to low potential.

[0285] On the basis that the potential of the first sub-node Q1 and the potential of the second sub-node Q2 are both high potential, and the potential of the second node QB is low potential, the sixteenth transistor T16 and the twentieth transistor T20 are turned on, and the fifteenth transistor T15 and the nineteenth transistor T19 are turned off, so that the first power signal provided by the first power supply terminal VGH is transmitted to the shift output terminal CR <n>and the low potential second power signal supplied by the second power supply terminal VGL1 is transmitted to the scan output terminal G through the turned-on second tenth transistor T20 <n>. That is, in this stage t05, the shift register unit can be shifted out of the CR <n>and scan out G <n>The first power signal of high potential and the second power signal of low potential are output, respectively.

[0286] It can be understood that the potential of the second power signal of low potential is about -5 volts (V) and the potential of the third power signal of low potential is about -8 V. Thus, as can be known from the signal simulation diagram shown in FIG. 37, after the stage t05, the potential of the second node QB remains about -5 V, and the potential of the first node QA remains about -8 V. Therefore, the potential of the first node QA is lower than that of the second node QB. <n>The potential of the output low potential second power supply signal is also kept at about -5V, which results in a gate-source voltage difference Vgs - threshold voltage Vth > 0 of the twentieth transistor T20, i.e. the twentieth transistor T20 is in a floating state and cannot pull up the scan output end G <n>The coupled gate line is sufficiently discharged. That is, during the stage t04, the low voltage of the second node QB is not sufficient to maintain the scan output end G <n>The state of the signal outputting a low potential.

[0287] In the embodiment of the present disclosure, the structure shown in FIG. 13 is taken as an example, that is, the shift register unit further includes a second output circuit 03, and the reference clock end CKC coupled to the second output circuit 03 is shared with the first clock end CKA, and a corresponding signal timing diagram is shown in FIG. 38. In combination with FIG. 38, the working process of the shift register unit in an embodiment provided by the present disclosure is briefly described as follows:

[0288] In stage t01, the potential of the start signal provided by the start signal end STV, the potential of the first clock signal provided by the first clock end CKA, and the potential of the third clock signal provided by the third clock end GCK are all low potentials, and the potential of the second clock signal provided by the second clock end CKB is a high potential. Correspondingly, the seventh transistor T7 can be turned on, and the ninth transistor T9 can be turned off. Further, the low potential start signal can be transmitted to the first sub-node Q1 through the turned-on seventh transistor T7. In addition, because the potential of the third power signal provided by the third power end VGL2 is a low potential, the first transistor T1 can be turned on, and the low potential start signal transmitted to the first sub-node Q1 can be transmitted to the second sub-node Q2 through the turned-on first transistor T1. That is, in stage t01, the potential of the first sub-node Q1 and the potential of the second sub-node Q2 can both be set to low potentials. On this basis, the eleventh transistor T11 and the twelfth transistor T12 can both be turned on, and the high potential first power signal provided by the first power end VGH can be transmitted to the gate of the tenth transistor T10 and the second node QB through the turned-on eleventh transistor T11 and the twelfth transistor T12 respectively, so that the eighth transistor T8 and the tenth transistor T10 are both turned off. That is, in stage t01, the potential of the second node QB can be set to a low potential.

[0289] On the basis that the potential of the first sub-node Q1 and the potential of the second sub-node Q2 are both low potentials and the potential of the second node QB is a high potential, the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 can all be turned off, and the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 can all be turned on, so that the high potential second clock signal provided by the second clock end CKB is transmitted to the shift output end CR <n>so that the high potential first power signal provided by the first power end VGH is transmitted to the redundancy output end GD through the turned-on seventeenth transistor T17, and the low potential third clock signal provided by the third clock end GCK is transmitted to the scan output end G through the turned-on nineteenth transistor T19 <n>. That is, in this stage t01, the shift register unit can be shifted out of the CR <n>and scan out G <n>The second clock signal of high potential and the third clock signal of low potential are output respectively, and the first power signal of high potential is output through the redundant output terminal GD.

[0290] In the stage t02 to stage t03, the potential of the start signal provided by the start signal terminal STV and the potential of the first clock signal provided by the first clock terminal CKA are both high potential, the potential of the second clock signal provided by the second clock terminal CKB is low potential first and then high potential, and the potential of the third clock signal provided by the third clock terminal GCK is high potential first and then low potential. In addition, under the coupling effect of the capacitor, the potential of the second sub-node Q2 and the potential of the second node QB can be maintained as the low potential and the high potential of stage t01 respectively, that is, in the stage t02 to stage t03, the sixteenth transistor T16, the eighteenth transistor T18 and the twentieth transistor T20 can all be maintained off, and the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 can all be maintained on. Correspondingly, the shift register unit can be made to output through the shift output terminal CR <n>and scan out G <n>The second clock signal of low potential and the third clock signal of high potential are output respectively, and then output through the shift output terminal CR <n>and scan out G <n>The second clock signal of high potential and the third clock signal of low potential are output respectively, and the first power signal of high potential is continuously output through the redundancy output terminal GD.

[0291] In stage t04, the potential of the first clock signal provided by the first clock terminal CKA becomes low potential, at the same time, the potential of the enable signal provided by the enable signal terminal STV and the potential of the second clock signal provided by the second clock terminal CKB are both high potential, and the potential of the third clock signal provided by the third clock terminal GCK is low potential. Correspondingly, the seventh transistor T7 is enabled again, and the ninth transistor T9 is turned off. Further, the high potential enable signal can be transmitted to the first sub-node Q1 through the enabled seventh transistor T7, and then transmitted to the second sub-node Q2 through the enabled first transistor T1. That is, in the stage t04, the potential of the first sub-node Q1 and the potential of the second sub-node Q2 can be set to high potential. On this basis, the eleventh transistor T11 and the twelfth transistor T12 are turned off, and the tenth transistor T10 remains off in response to the high potential second clock signal. That is, in the stage t04, the potential of the second node QB can remain high potential. On the basis that the potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the second node QB are all high potential, the sixteenth transistor T16, the eighteenth transistor T18 and the twentieth transistor T20 are turned off, and the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off, so that the shift output terminal CR <n>and scan out G <n>Under the coupling of the capacitor, the high potential and the low potential of the previous stage t03 are maintained respectively, and the redundant output terminal GD is also maintained as the high potential of the previous stage t03.

[0292] In the stage t05, firstly, the potential of the second clock signal provided by the second clock terminal CKB becomes the low potential, at the same time, the potential of the first clock signal provided by the first clock terminal CKA and the potential of the third clock signal provided by the third clock terminal GCK both become the high potential, and the potential of the start signal provided by the start signal terminal STV is maintained as the high potential. Correspondingly, the ninth transistor T9 and the tenth transistor T10 are both turned on, and the seventh transistor T7 is turned off. Then the low potential second clock signal is transmitted to the second node QB through the turned-on tenth transistor T10. On this basis, the eighth transistor T8 is turned on, and on the basis that the eighth transistor T8 and the ninth transistor T9 are both turned on, the high potential first power signal provided by the first power supply terminal VGH is transmitted to the first sub-node Q1 through the turned-on eighth transistor T8 and the ninth transistor T9 in turn, and then transmitted to the second sub-node Q2 through the turned-on first transistor T1. That is, in the stage t05, firstly, the potential of the first sub-node Q1 and the potential of the second sub-node Q2 can both be set as the high potential, and the potential of the second node QB can be set as the low potential.

[0293] On the basis that the potential of the first sub-node Q1 and the potential of the second sub-node Q2 are both the high potential, and the potential of the second node QB is the low potential, the sixteenth transistor T16, the eighteenth transistor T18 and the twentieth transistor T20 are all turned on, and the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 are all turned off, so that the first power signal provided by the first power supply terminal VGH is transmitted to the shift output terminal CR <n>so that the first clock signal of high potential provided by the first clock end CKA is transmitted to the redundant output end GD, and the second power signal of low potential provided by the second power end VGL1 is transmitted to the scan output end G through the opened second tenth transistor T20 <n>. That is, in this phase t05, the shift register unit can first output the data D0 to D3 via the shift output terminals CR0 to CR3 <n>and scan out G <n>The first power signal of high potential and the second power signal of low potential are output respectively, and the first clock signal of high potential is output through the redundant output terminal GD.

[0294] After that, when the potential of the first clock signal provided by the first clock signal terminal CKA becomes low again, the first clock signal of low potential can be output through the redundant output terminal GD, and the potential of the second node QB can be pulled to a lower potential under the coupling effect of the third capacitor C3, so that the twentieth transistor T20 is fully turned on, and then the second power signal of low potential can be reliably transmitted to the scan output terminal G <n>to achieve sufficient noise discharge.

[0295] That is, after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the first clock signal provided by the first clock terminal CKA changes from a high potential to a low potential, thereby being sufficient to maintain the potential of the scanned output terminal G <n>The state in which the low potential is output. As can be seen from the signal simulation diagram shown in FIG. 39, after the stage t04, when the potential of the first clock signal changes from the high potential to the low potential, the potential of the second node QB can be coupled to be pulled down to about -15 V or so, and the potential of the first node QA can be coupled to be pulled up to about 15 V or so because the scanned output end G <n>The potential of the output low potential second power supply signal is generally about -5V, so that the gate-source voltage difference Vgs-threshold voltage Vth of the twentieth transistor T20 is less than 0, that is, the twentieth transistor T20 is fully turned on, so that the scanning output end G <n>The second power supply signal with a low potential is reliably outputted, and noise is sufficiently discharged.

[0296] Alternatively, in combination with the above description for the structure shown in Fig. 13, Fig. 40 schematically shows another signal timing diagram of the shift register unit, taking the structure shown in Fig. 14 as an example, i.e., taking the example that the reference clock terminal CKC coupled with the second output circuit 03 is shared with the second clock terminal CKB. As can be seen from Fig. 40, after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the second clock signal provided by the second clock terminal CKB changes from a high potential to a low potential, so as to be sufficient to maintain the scanned output terminal G <n>The output low potential state is also capable of achieving sufficient noise discharge.

[0297] Alternatively, in combination with the above description for the structure shown in Fig. 13, taking the structure shown in Fig. 15 as an example, that is, the reference clock terminal CKC coupled with the second output circuit 03 is independent of the first clock terminal CKA and the second clock terminal CKB, and the falling edge of the reference clock signal provided by the reference clock terminal CKC is after the falling edge of the second clock signal provided by the second clock terminal CKB, Fig. 41 schematically shows another signal timing diagram of the shift register unit, and Fig. 42 also shows the corresponding signal simulation diagram. It can be seen from Fig. 41 that after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the reference clock signal provided by the reference clock terminal CKC changes from high potential to low potential, thereby being sufficient to maintain the output low potential state of the scanned output terminal G <n>The output low potential state also achieves sufficient noise discharge.

[0298] Alternatively, in combination with the above description for the structure shown in FIG. 13, taking the structure shown in FIG. 19 as an example, FIG. 43 schematically shows a signal timing diagram of another shift register unit. In FIG. 43, the first clock terminal CKA, the second clock terminal CKB, the third clock terminals GCK1 and GCK3 correspond to the clock terminals coupled to the shift register units of the odd rows of pixels, i.e., the clock terminals coupled to the odd-stage shift register units; the first clock terminal CKA2, the second clock terminal CKB2, the third clock terminals GCK2 and GCK4 correspond to the clock terminals coupled to the shift register units of the even rows of pixels, i.e., the clock terminals coupled to the even-stage shift register units. The fourth sub-node QB2-1 is a node in the odd-stage shift register unit; the fourth sub-node QB2-2 is a node in the even-stage shift register unit. In addition, it can be seen from FIG. 43 that, because the reference clock terminal CKC coupled to the odd-stage shift register units is shared with the second clock terminal CKB, after stage t04, the potential of the fourth sub-node QB2-1 can be coupled to a lower potential each time the potential of the second clock signal provided by the second clock terminal CKB changes from a high potential to a low potential, thereby being sufficient to maintain the fourth sub-node QB2-1 at a low potential. <n>The state of outputting low potential also achieves sufficient noise discharge. Since the reference clock end CKC coupled with the even-stage shift register unit shares the second clock end CKB2, after stage t04, the potential of the fourth sub-node QB2-2 can be coupled to a lower potential each time the potential of the second clock signal provided by the second clock end CKB2 changes from high potential to low potential, thereby being sufficient to maintain the scanned output end G <n>The output low potential state is also capable of fully discharging the noise.

[0299] Alternatively, in combination with the above description for the structure shown in Fig. 13, taking the structure shown in Fig. 21 as an example, Fig. 44 also shows a signal timing diagram of another shift register unit. As can be seen from Fig. 44, because the reference clock terminal CKC is shared with the first clock terminal CKA, after stage t04, the potential of the second node QB can be coupled to a lower potential each time the potential of the first clock signal provided by the first clock terminal CKA changes from a high potential to a low potential, thereby being sufficient to maintain the scanned output terminal G <n>The output low potential state is also capable of achieving sufficient noise discharge.

[0300] Optionally, taking the structure shown in FIG. 23 as an example, FIG. 45 shows a corresponding signal timing diagram. In combination with FIG. 45, the working process of the shift register unit in another embodiment provided by the present disclosure is briefly described as follows (the working process of the structure shown in FIG. 44 can be referred to the description below, and the above is not described again):

[0301] In stage t01, the potential of the start signal provided by the start signal terminal STV, the potential of the first clock signal provided by the first clock terminal CKA, and the potential of the third clock signal provided by the third clock terminal GCK are all low potentials, and the potential of the second clock signal provided by the second clock terminal CKB is a high potential. Correspondingly, the seventh transistor T7, the tenth transistor T10, and the thirteenth transistor T13 are all turned on, and the ninth transistor T9 is turned off. Further, the low potential start signal can be transmitted to the first sub-node Q1 through the turned-on seventh transistor T7, and the low potential third power signal provided by the third power supply terminal VGL2 can be transmitted to the third sub-node QB1 through the turned-on tenth transistor T10 and to the sixth sub-node QB4 through the turned-on thirteenth transistor T13. In addition, because the potential of the third power signal is a low potential, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all turned on, and the low potential start signal transmitted to the first sub-node Q1 can be transmitted to the second sub-node Q2 through the turned-on first transistor T1 and to the sub-node Q3 through the turned-on fourth transistor T4, and the low potential third power signal transmitted to the third sub-node QB1 can be transmitted to the fourth sub-node QB2 through the turned-on second transistor T2 and to the fifth sub-node QB3 through the turned-on fifth transistor T5. That is, in this stage t01, the potential of the first sub-node Q1, the potential of the second sub-node Q2, the potential of the sub-node Q3, the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3, and the potential of the sixth sub-node QB4 can all be set to low potentials.

[0302] On the basis that the potential of the first sub-node Q1, the potential of the second sub-node Q2, the potential of the sub-node Q3, the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 are all low potentials, the eighth transistor T8, the eleventh transistor T11 and the fourteenth transistor T14 can be first turned on, and then the low potential first clock signal provided by the first clock end CKA can be transmitted to the third sub-node QB1 and the sixth sub-node QB4 through the turned-on eleventh transistor T11 and the turned-on fourteenth transistor T14, further ensuring that the potential of the third sub-node QB1 and the potential of the sixth sub-node QB4 remain low potentials. On the basis that the potentials of all nodes are low potentials, the sixth transistor T6, and the fifteenth transistor T15 to the twentieth transistor T20 can be turned on. Because in this stage t01, the potential of the second clock signal is high, and the potential of the third clock signal is low, the shift register unit can be made to output the low potential second clock signal through the shift output end CR <n>and scan out G <n>Output a high potential signal and a low potential signal respectively, and output the high potential signal through the redundant output terminal GD.

[0303] In stage t02, the potential of the start signal provided by the start signal terminal STV, the potential of the first clock signal provided by the first clock terminal CKA and the potential of the second clock signal provided by the second clock terminal CKB are all high potentials, and the potential of the third clock signal provided by the third clock terminal GCK is a low potential. Correspondingly, the first transistor T1, the tenth transistor T10, the thirteenth transistor T13 and the ninth transistor T9 can all be turned off. In addition, under the coupling effect of the capacitor, the potential of the first sub-node Q1 can be maintained as the low potential in stage t01, and correspondingly, the potential of the second sub-node Q2 and the potential of the sub-node Q3 can also be maintained as low potentials, so that the eleventh transistor T11 and the fourteenth transistor T14 can be maintained as on, and then the high potential first clock signal can be transmitted to the third sub-node QB1 and the sixth sub-node QB4 through the on eleventh transistor T11 and the on fourteenth transistor T14, and then transmitted to the fourth sub-node QB2 and the fifth sub-node QB3 through the on second transistor T2 and the on fifth transistor T5. That is, in this stage t02, the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 can all be set to high potentials. The potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the sub-node Q3 can all be maintained as low potentials.

[0304] On the basis that the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 are all high potentials, and the potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the sub-node Q3 are all low potentials, the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 can all be turned on, and the eighth transistor T8, the sixteenth transistor T16, the eighteenth transistor T18 and the twentieth transistor T20 can all be turned off. Further, the high potential second clock signal provided by the second clock terminal CKB can be transmitted to the shift output terminal CR <n>so that the high potential first power signal provided by the first power end VGH is transmitted to the redundancy output end GD through the turned-on seventeenth transistor T17, and the low potential third clock signal provided by the third clock end GCK is transmitted to the scan output end G through the turned-on nineteenth transistor T19 <n>. That is, in this stage t02, the shift register unit can be shifted output end CR <n>and scan out G <n>The second clock signal of high potential and the third clock signal of low potential are output respectively, and the first power signal of high potential is output through the redundant output terminal GD.

[0305] In stage t03, the potential of the third clock signal provided by the third clock terminal GCK becomes high potential, the potential of the second clock signal provided by the second clock terminal CKB becomes low potential, and the potential of the enable signal provided by the enable signal terminal STV and the potential of the first clock signal provided by the first clock terminal CKA remain high potential. In addition, under the coupling of the capacitor, the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 can remain high potential of stage t02 respectively. The potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the sub-node Q3 can remain low potential of stage t02. That is, in stage t03, the sixteenth transistor T16, the eighteenth transistor T18 and the twentieth transistor T20 can remain off, and the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 can remain on. Correspondingly, the shift register unit can be enabled to output through the shift output terminal CR <n>and scan out G <n>The second clock signal of low potential and the third clock signal of high potential are output respectively, and the first power signal of high potential is continuously output through the redundant output terminal GD.

[0306] In stage t04, the potential of the first clock signal provided by the first clock terminal CKA becomes low potential, at the same time, the potential of the enable signal provided by the enable signal terminal STV and the potential of the second clock signal provided by the second clock terminal CKB are both high potential, and the potential of the third clock signal provided by the third clock terminal GCK is low potential. Correspondingly, the seventh transistor T7, the tenth transistor T10 and the thirteenth transistor T13 are enabled again, and the ninth transistor T9 is turned off. Further, the enable signal of high potential is transmitted to the first sub-node Q1 through the enabled seventh transistor T7, and then transmitted to the second sub-node Q2 through the enabled first transistor T1, and transmitted to the sub-node Q3 through the enabled fourth transistor T4. And the third power signal of low potential provided by the third power terminal VGL2 is transmitted to the third sub-node QB1 and the sixth sub-node QB4 through the enabled tenth transistor T10 and the thirteenth transistor T13 respectively, and then transmitted to the fourth sub-node QB2 through the enabled second transistor T2, and transmitted to the fifth sub-node QB3 through the enabled fifth transistor T5. That is, in this stage t04, the potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the sub-node Q3 can all be set to high potential, while the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 can all be set to low potential.

[0307] On the basis that the potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the sub-node Q3 are all high potential, and the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 are all low potential, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 are all turned off, and the eighth transistor T8, the sixteenth transistor T16, the sixth transistor T6, the eighteenth transistor T18 and the twentieth transistor T20 are all enabled. Further, the first power signal of high potential provided by the first power terminal VGH is transmitted to the shift output terminal CR <n>so that the high-level second clock signal provided by the second clock terminal CKB is transmitted to the redundancy output terminal GD through the turned-on eighteenth transistor T18, and the low-level second power supply signal provided by the second power supply terminal VGL1 is transmitted to the scan output terminal G through the turned-on twentieth transistor T20 <n>. That is, in this stage t04, the shift register unit can be shifted out of the CR <n>and scan out G <n>The first power signal of high potential and the second power signal of low potential are output respectively, and the second clock signal of high potential is output through the redundant output terminal GD.

[0308] In stage t05, the potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the sub-node Q3 all remain high potential, the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 all remain low potential. Correspondingly, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 all remain off, and make the eighth transistor T8, the sixteenth transistor T16, the sixth transistor T6, the eighteenth transistor T18 and the twentieth transistor T20 all remain on. Correspondingly, the first power terminal VGH can continue to transmit the first power signal of high potential to the shift output terminal CR through the on sixteenth transistor T16 <n>so that the second clock signal provided by the second clock terminal CKB is transmitted to the redundancy output terminal GD through the turned-on eighteenth transistor T18, and the low potential second power signal provided by the second power supply terminal VGL1 continues to be transmitted to the scan output terminal G through the turned-on twentieth transistor T20 <n>.

[0309] Further, because the potential of the second clock signal provided by the second clock terminal CKB becomes a low potential, the potential of the redundant output terminal GD can be controlled to become a low potential in this stage t05. The potential of the fifth sub-node QB3 can be first pulled to a lower potential under the coupling effect of the third capacitor C3, so that the sixth transistor T6 is fully turned on, thereby making the lower potential of the fifth sub-node QB3 transmitted to the fourth sub-node QB2 through the fully turned-on sixth transistor T6, the potential of the fourth sub-node QB2 is pulled to a lower potential, so that the twentieth transistor T20 is fully turned on, and then the low potential of the second power supply signal can be reliably transmitted to the scan output terminal G <n>to achieve sufficient noise discharge. That is, in this stage t05, the shift register unit can be shifted output end CR <n>and scan out G <n>The first power supply signal of high level and the second power supply signal of low level are continuously output, and the second clock signal of low level is output through the redundant output terminal GD.

[0310] In stage t06, the potential of the first sub-node Q1, the potential of the second sub-node Q2 and the potential of the sub-node Q3 all remain high level, and the potential of the third sub-node QB1, the potential of the fourth sub-node QB2, the potential of the fifth sub-node QB3 and the potential of the sixth sub-node QB4 all remain low level. Correspondingly, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, the seventeenth transistor T17 and the nineteenth transistor T19 all remain off, and the eighth transistor T8, the sixteenth transistor T16, the sixth transistor T6, the eighteenth transistor T18 and the twentieth transistor T20 all remain on. Correspondingly, the first power supply terminal VGH can continuously transmit the first power supply signal of high level to the shift output terminal CR through the on sixteenth transistor T16 <n>so that the second clock signal provided by the second clock terminal CKB is transmitted to the redundancy output terminal GD through the turned-on eighteenth transistor T18, and the low potential second power signal provided by the second power supply terminal VGL1 continues to be transmitted to the scan output terminal G through the turned-on twentieth transistor T20 <n>.

[0311] Further, the potential of the second clock signal provided by the second clock terminal CKB becomes high potential again, so in this stage t06, the potential of the redundant output terminal GD can be controlled to become high potential. The potential of the fifth sub-node QB3 can be first raised under the coupling effect of the third capacitor C3, so that the sixth transistor T6 is turned off. In this way, it can be ensured that the potential of the fourth sub-node QB2 remains as the low potential of stage t05 without being affected by the potential of the fifth sub-node QB3 being raised. Correspondingly, the twentieth transistor T20 can be kept on, and further the low potential second power signal can be reliably transmitted to the scan output terminal G <n>to achieve sufficient noise discharge. That is, in this stage t06, the shift register unit can be shifted output end CR <n>and scan out G <n>The first power supply signal of high potential and the second power supply signal of low potential are continuously output, and the second clock signal of high potential is output through the redundant output terminal GD. Based on the timing shown in FIG. 45, FIG. 46 also schematically shows a corresponding signal simulation diagram.

[0312] To sum up, the disclosed embodiment provides a driving method of a shift register unit. In the method, the input circuit can control the potentials of the first node and the second node. The first output circuit can control the second clock terminal or the first power supply terminal to output a signal to the shift output terminal in response to the potentials of the first node and the second node. The second output circuit can control the first power supply terminal or the reference clock terminal to output a signal to the redundant output terminal in response to the potentials of the first node and the second node, and can adjust the potential of the first node based on the potential of the redundant output terminal through coupling. The third output circuit can control the third clock terminal or the second power supply terminal to output a signal to the scan output terminal in response to the potentials of the first node and the second node. In this way, the reference clock signal provided by the reference clock terminal can be flexibly set, so that the potential of the first node controlled by the second output circuit remains stable, and the third output circuit reliably outputs a signal, such as a gate drive signal, to the scan output terminal, thereby reliably driving the pixels to emit light and ensuring that the display effect of the display panel is better.

[0313] The disclosed embodiment also provides a gate drive circuit. The gate drive circuit includes at least two cascaded shift register units GOA as described above.

[0314] For example, the first input terminal IN1 of the first shift register unit GOA-1 can be coupled with the start signal terminal STV. In each shift register unit except the first shift register unit GOA-1, the first input terminal IN1 of each shift register unit can be coupled with the shift output terminal CR of the cascaded previous shift register unit. <n>Coupling.

[0315] Alternatively, taking the structure shown in FIG. 19 as an example, FIG. 47 shows a structural schematic diagram of a gate driving circuit. As can be further seen from FIG. 47, the odd-stage shift register units (e.g., GOA-1, GOA-3 and GOA-5) and the even-stage shift register units (e.g., GOA-2 and GOA-4) can be coupled with different clock terminals respectively, and the first-stage shift register unit GOA-1 can also be coupled with the start signal terminal STV, and the shift register units at other stages can be coupled with each other, which is not shown in FIG. 47.

[0316] Alternatively, taking the structure shown in FIG. 23 as an example, FIG. 48 shows another structural schematic diagram of a gate driving circuit. FIG. 49 shows still another structural schematic diagram of a gate driving circuit.

[0317] As can be seen from FIG. 48, the odd-stage shift register units (e.g., GOA-1) can be coupled with the first clock terminal CKA, the second clock terminal CKB and the third clock terminal GCK1 respectively, the even-stage shift register units (e.g., GOA-2) can be coupled with the first clock terminal CKA2, the second clock terminal CKB2 and the third clock terminal GCK2 respectively, the first-stage shift register unit GOA-1 can also be coupled with the start signal terminal STV, and the odd-stage shift register units can be coupled with each other, and the even-stage shift register units can be coupled with each other. That is, for example, the shift output terminal CR<1> of the first-stage shift register unit GOA-1 can be coupled with the first input terminal IN1 (not shown in the figure) of the third-stage shift register unit GOA-3; the shift output terminal CR<3> of the third-stage shift register unit GOA-3 can be coupled with the fifth-stage shift register unit GOA-5; the shift output terminal CR<2> of the second-stage shift register unit GOA-2 can be coupled with the fourth-stage shift register unit GOA-4; and so on.

[0318] As can be seen from FIG. 49, the shift register units (e.g., GOA-1, GOA-2 and GOA-3) shown therein are all coupled with the same first clock terminal CKA and the same second clock terminal CKB, only the odd-stage shift register units (e.g., GOA-1) are coupled with the third clock terminal GCK1, and only the even-stage shift register units (e.g., GOA-2) are coupled with the third clock terminal GCK2, the first-stage shift register unit GOA-1 can also be coupled with the start signal terminal STV, and the shift register units at other stages can be coupled with each other. That is, the shift output terminal CR<1> of the first-stage shift register unit GOA-1 can be coupled with the second-stage shift register unit GOA-2; the shift output terminal CR<2> of the second-stage shift register unit GOA-2 can be coupled with the third-stage shift register unit GOA-3; and so on.

[0319] That is, there can be one set of first clock terminal CKA and second clock terminal CKB, or multiple sets of first clock terminal CKA and second clock terminal CKB, which are not limited in the embodiments of the present disclosure.

[0320] It can be understood that the gate drive circuit can have substantially the same technical effects as the shift register unit described in the foregoing embodiments, and therefore the technical effects of the gate drive circuit are not repeated here for the purpose of brevity.

[0321] The embodiments of the present disclosure also provide a display device. As shown in FIG. 50, the display device includes a display panel 100 and a gate drive circuit 000 as described above.

[0322] The display panel 100 includes a plurality of pixels. The gate drive circuit 000 is coupled to the plurality of pixels and configured to transmit a gate drive signal to the plurality of pixels to drive the plurality of pixels to emit light.

[0323] Of course, in some embodiments, the gate drive circuit 000 here can also be a circuit for providing other display driving signals to the pixels, such as a light emitting drive circuit for providing a light emitting control signal to the pixels.

[0324] It can be understood that the display device can have substantially the same technical effects as the gate drive circuit described in the foregoing embodiments, and therefore the technical effects of the display device are not repeated here for the purpose of brevity.

[0325] Optionally, the display device can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, or navigator.

[0326] It can be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by those skilled in the art to which the present disclosure belongs.

[0327] As used in the present patent application specification and claims, "first", "second", or "third" and similar words do not indicate any order, number, or importance, but are only used to distinguish different components.

[0328] Similarly, "one" or "a" and similar words do not indicate a quantity limitation, but indicate the existence of at least one.

[0329] The terms "comprise", "comprising", "include", "including" or "contain", "containing" and the like are used in the sense of "including" and / or "comprising" and not by way of "consisting only of".

[0330] The terms "upper", "lower", "left", "right" and the like are used for ease of description to describe the orientation of the components to each other. Other orientations are possible such that the relative position can be changed when the absolute position of the described object is changed.

[0331] The term "and / or", "and / or" means that there can be three kinds of relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, B exists alone. The character " / " generally represents that the front and rear associated objects are a kind of "or" relationship.

[0332] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described gate drive circuit, shift register unit, each circuit and each sub-circuit can refer to the corresponding processes in the method embodiments, which will not be described here.

[0333] The above description is only optional embodiments of the present disclosure, and does not limit the present disclosure. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A shift register unit, the shift register unit comprising: The input circuit is coupled to a first clock terminal, a second clock terminal, a first input terminal, a first node, and a second node, respectively, and is used to control the potential of the first node and the potential of the second node based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, and the first input signal provided by the first input terminal. A first output circuit is coupled to the first node, the second node, the second clock terminal, the first power supply terminal, and the shift output terminal, respectively, and is used to control the on / off state of the second clock terminal and the shift output terminal in response to the potential of the first node, and to control the on / off state of the first power supply terminal and the shift output terminal in response to the potential of the second node; wherein, the shift output terminal is used to be coupled to the first input terminal of another cascaded shift register unit; The second output circuit is coupled to the first control node, the second node, the first power supply terminal, the reference clock terminal, and the redundant output terminal, respectively. It is used to control the switching between the first power supply terminal and the redundant output terminal in response to the potential of the first control node, and to control the switching between the reference clock terminal and the redundant output terminal in response to the potential of the second node. It also includes a first capacitor coupled between the second node and the redundant output terminal. The first control node is either the first node itself or coupled to the shift output terminal. The third output circuit is coupled to the second control node, the second node, the third clock terminal, the second power supply terminal, and the scan output terminal, respectively, and is used to control the on / off state of the third clock terminal and the scan output terminal in response to the potential of the second control node, and to control the on / off state of the second power supply terminal and the scan output terminal in response to the potential of the second node; wherein, the scan output terminal is used to be coupled to a pixel in the display panel, and the second control node is the first node or coupled to the shift output terminal.

2. The shift register unit according to claim 1, wherein, The reference clock terminal is shared with the first clock terminal; Alternatively, the reference clock terminal may be shared with the second clock terminal; Alternatively, the reference clock terminal is independent of both the first clock terminal and the second clock terminal, and the transition edge of the reference clock signal provided by the reference clock terminal from the second potential to the first potential is located after the transition edge of the second clock signal provided by the second clock terminal from the second potential to the first potential.

3. The shift register unit according to claim 1 or 2, wherein, The first node includes: a first child node and a second child node; the input circuit is coupled to the first child node, the first output circuit is coupled to the second child node, the first control node is either the first child node or the second child node, and the second control node is either the first child node or the second child node; the shift register unit further includes: A first control circuit is coupled to a third power supply terminal, the first sub-node, and the second sub-node, respectively, and is used to control the on / off state of the first sub-node and the second sub-node in response to a third power supply signal provided by the third power supply terminal.

4. The shift register unit according to claim 3, wherein, The first control circuit includes: a first transistor; The gate of the first transistor is coupled to the third power supply terminal, the first electrode of the first transistor is coupled to the first sub-node, and the second electrode of the first transistor is coupled to the second sub-node.

5. The shift register unit according to any one of claims 1 to 4, wherein, The second node includes: a third child node and a fourth child node; the input circuit and the first output circuit are both coupled to the third child node, and the second output circuit and the third output circuit are both coupled to the fourth child node; the shift register unit further includes: The second control circuit is coupled to the third power supply terminal, the third sub-node, and the fourth sub-node respectively, and is used to control the on / off state of the third sub-node and the fourth sub-node in response to the third power supply signal provided by the third power supply terminal.

6. The shift register unit according to claim 5, wherein, The second control circuit includes: a second transistor; The gate of the second transistor is coupled to the third power supply terminal, the first terminal of the second transistor is coupled to the third sub-node, and the second terminal of the second transistor is coupled to the fourth sub-node.

7. The shift register unit according to claim 5, wherein, The second control circuit includes two second transistors connected in series; The gates of both second transistors are coupled to the third power supply terminal, the first terminals of the two second transistors are coupled to the third sub-node and the fourth sub-node respectively, and the second terminals of the two second transistors are coupled to the series node; the shift register unit further includes: The leakage protection circuit is coupled to the fourth sub-node, the fourth power supply terminal and the series node respectively, and is used to control the on / off state of the fourth power supply terminal and the series node in response to the potential of the fourth sub-node.

8. The shift register unit according to claim 7, wherein, The leakage protection circuit includes: a third transistor; The gate of the third transistor is coupled to the fourth sub-node, the first terminal of the third transistor is coupled to the fourth power supply terminal, and the second terminal of the third transistor is coupled to the series node.

9. The shift register unit according to claim 5, wherein, The second control circuit is also coupled to the first node and is also used to control the on / off state of the third sub-node and the fourth sub-node in response to the third power signal and the potential of the first node.

10. The shift register unit according to claim 9, wherein, The second control circuit includes two second transistors connected in series; The gates of the two second transistors are respectively coupled to the third power supply terminal and the first node, the first terminals of the two second transistors are respectively coupled to the third sub-node and the fourth sub-node, and the second terminals of the two second transistors are coupled together.

11. The shift register unit according to any one of claims 1 to 10, wherein, Each of the first control node and the second control node includes: a first control sub-node and a second control sub-node; the first control sub-node is the first node or coupled to the shift output terminal; when either control node is the second control node, the third output circuit is coupled to the second control sub-node; when either control node is both the first control node and the second control node, both the second output circuit and the third output circuit are coupled to the second control sub-node; the shift register unit further includes: The third control circuit is connected to the third power supply terminal, the first control sub-node, and the second control circuit, respectively. The sub-nodes are coupled and used to control the on / off state of the first control sub-node and the second control sub-node in response to the third power signal provided by the third power supply terminal.

12. The shift register unit according to claim 11, wherein, The third control circuit includes: a fourth transistor; The gate of the fourth transistor is coupled to the third power supply terminal, the first terminal of the fourth transistor is coupled to the first control sub-node, and the second terminal of the fourth transistor is coupled to the second control sub-node.

13. The shift register unit according to any one of claims 1 to 12, wherein, The second node includes a third child node and a fifth child node; the input circuit, the first output circuit, and the third output circuit are all coupled to the third child node, and the second output circuit is coupled to the fifth child node; the shift register unit further includes: The fourth control circuit is coupled to the third power supply terminal, the third sub-node, and the fifth sub-node respectively, and is used to control the on / off state of the third sub-node and the fifth sub-node in response to the third power supply signal provided by the third power supply terminal, and to control the on / off state of the third sub-node and the fifth sub-node in response to the potential of the fifth sub-node.

14. The shift register unit according to claim 13, wherein, The fourth control circuit includes: a fifth transistor and a sixth transistor; The gate of the fifth transistor is coupled to the third power supply terminal, the first terminal of the fifth transistor is coupled to the third sub-node, and the second terminal of the fifth transistor is coupled to the fifth sub-node. The gate and second terminal of the sixth transistor are both coupled to the fifth sub-node, and the first terminal of the sixth transistor is coupled to the third sub-node.

15. The shift register unit according to any one of claims 1 to 14, wherein, The input circuit includes: The first input sub-circuit is coupled to the first clock terminal, the first input terminal, the first node, the second node, the second clock terminal, and the first power supply terminal, respectively, and is used to control the on / off state of the first input terminal and the first node in response to the first clock signal, and in response to the... The potential of the second node and the second clock signal control the connection and disconnection between the first power supply terminal and the first node, thereby controlling the potential of the first node. The second input sub-circuit is coupled to the input control terminal, the second input terminal, the first node, and the second node, respectively, and is used to control the on / off state of the second input terminal and the second node in response to the input control signal provided by the input control terminal, and to control the on / off state of the input control terminal and the second node in response to the potential of the first node, so as to control the potential of the second node; wherein the input control terminal and the second input terminal are respectively the first power supply terminal and the second clock terminal; or, the input control terminal and the second input terminal are respectively the first clock terminal and the third power supply terminal.

16. The shift register unit according to claim 15, wherein, The first input sub-circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor; the second input sub-circuit includes: a tenth transistor and an eleventh transistor; The gate of the seventh transistor is coupled to the first clock terminal, the first terminal of the seventh transistor is coupled to the first input terminal, and the second terminal of the seventh transistor is coupled to the first node. The gate of the eighth transistor is coupled to the second node, the first terminal of the eighth transistor is coupled to the first power supply terminal, and the second terminal of the eighth transistor is coupled to the first terminal of the ninth transistor. The gate of the ninth transistor is coupled to the second clock terminal, and the second terminal of the ninth transistor is coupled to the first node; The gate of the tenth transistor is coupled to the input control terminal, the first terminal of the tenth transistor is coupled to the second input terminal, and the second terminal of the tenth transistor is coupled to the second node; The gate of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the input control terminal, and the second electrode of the eleventh transistor is coupled to the second node.

17. The shift register unit according to claim 15, wherein, When the input control terminal and the second input terminal are respectively the first power supply terminal and the second clock terminal, the second input sub-circuit further includes a second capacitor coupled between the second input terminal and the input control terminal, and the shift register unit further includes: The fifth control circuit is coupled to the first node, the input control terminal, and the second input sub-circuit, respectively, and is used to control the input control terminal in response to the potential of the first node. On / off state of the two-input sub-circuit.

18. The shift register unit according to claim 17, wherein, The fifth control circuit includes: a twelfth transistor; The gate of the twelfth transistor is coupled to the first node, the first terminal of the twelfth transistor is coupled to the input control terminal, and the second terminal of the twelfth transistor is coupled to the second input sub-circuit.

19. The shift register unit according to any one of claims 15 to 18, wherein, The second node includes a third sub-node and a sixth sub-node; the first input sub-circuit, the second input sub-circuit, the first output circuit, and the third output circuit are all coupled to the third sub-node, and the fourth control circuit included in the shift register unit is coupled to the sixth sub-node; the input circuit further includes: The third input sub-circuit is coupled to the input control terminal, the second input terminal, the first node, and the sixth sub-node, respectively, and is used to control the on / off state of the second input terminal and the sixth sub-node in response to the input control signal, and to control the on / off state of the input control terminal and the sixth sub-node in response to the potential of the first node.

20. The shift register unit according to claim 19, wherein, The third input sub-circuit includes: a thirteenth transistor and a fourteenth transistor; The gate of the thirteenth transistor is coupled to the input control terminal, the first terminal of the thirteenth transistor is coupled to the second input terminal, and the second terminal of the thirteenth transistor is coupled to the second node; The gate of the fourteenth transistor is coupled to the first node, the first terminal of the fourteenth transistor is coupled to the input control terminal, and the second terminal of the fourteenth transistor is coupled to the second node.

21. The shift register unit according to any one of claims 1 to 20, wherein, The first output circuit includes a fifteenth transistor, a sixteenth transistor, and a third capacitor; the second output circuit further includes a seventeenth transistor and an eighteenth transistor; the third output circuit includes a nineteenth transistor and a twentieth transistor. The gate of the fifteenth transistor is coupled to the first node, and the first... The second terminal of the fifteenth transistor is coupled to the second clock terminal, and the second terminal of the fifteenth transistor is coupled to the shift output terminal; The gate of the sixteenth transistor is coupled to the second node, the first terminal of the sixteenth transistor is coupled to the first power supply terminal, and the second terminal of the sixteenth transistor is coupled to the shift output terminal. The third capacitor is coupled between the first node and the shift output terminal; The gate of the seventeenth transistor is coupled to the first control node, the first terminal of the seventeenth transistor is coupled to the first power supply terminal, and the second terminal of the seventeenth transistor is coupled to the redundant output terminal. The gate of the eighteenth transistor is coupled to the second node, the first terminal of the eighteenth transistor is coupled to the reference clock terminal, and the second terminal of the eighteenth transistor is coupled to the redundant output terminal. The gate of the nineteenth transistor is coupled to the second control node, the first terminal of the nineteenth transistor is coupled to the third clock terminal, and the second terminal of the nineteenth transistor is coupled to the scan output terminal. The gate of the twentieth transistor is coupled to the second node, the first terminal of the twentieth transistor is coupled to the second power supply terminal, and the second terminal of the twentieth transistor is coupled to the scan output terminal.

22. The shift register unit according to any one of claims 1 to 21, wherein, The shift register unit includes P-type transistors, and the scan output terminal is used to couple to the N-type transistor in the pixel via a gate line.

23. A method for driving a shift register unit, used to drive the shift register unit as described in any one of claims 1 to 22, the method comprising: In the first stage, the input circuit controls the potential of the first node to the first potential and the potential of the second node to the second potential based on the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, and the first input signal provided by the first input terminal. The first output circuit responds to the potential of the first node by controlling the second clock terminal to conduct with the shift output terminal. The second output circuit responds to the potential of the first control node by controlling the first power supply terminal to conduct with the redundant output terminal. The third output circuit responds to the potential of the second control node by controlling the third clock terminal to conduct with the scan output terminal. In the second stage, the input circuit, based on the first clock signal, the second clock signal, and the first input signal, controls the potential of the first node to the second potential and controls the potential of the second node to the first potential. The first output circuit responds to the potential of the second node and controls the... The first power supply terminal is connected to the shift output terminal. The second output circuit responds to the potential of the second node, controls the reference clock terminal to be connected to the redundant output terminal, and adjusts the potential of the second node based on the potential of the redundant output terminal through coupling. The third output circuit responds to the potential of the second node, controls the second power supply terminal to be connected to the scan output terminal.

24. A gate driving circuit, the gate driving circuit comprising: At least two cascaded shift register units as described in any one of claims 1 to 22.

25. A display device, the display device comprising: The display panel, and the gate driving circuit as described in claim 24, wherein the display panel includes a plurality of pixels; The gate driving circuit is coupled to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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