Display panel and manufacturing method therefor, and display device comprising display panel

Abstract

The present disclosure provides a display panel. The display panel comprises a substrate, a time-varying signal wire arranged above the substrate, and a direct-current constant signal wire, adjacent to the time-varying signal wire, in a film layer, wherein the orthographic projection of the direct-current constant signal wire on the substrate does not overlap with the orthographic projection of the time-varying signal wire on the substrate. In addition, the present disclosure further relates to a manufacturing method for the display panel, and a display device comprising the display panel.

Description

Display panel, manufacturing method thereof, and display device including the display panel TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel and a manufacturing method thereof, and further relates to a display device including the display panel. BACKGROUND

[0002] With the continuous improvement of resolution and refresh frequency of organic light emitting diode (OLED) display panels, the power consumption thereof is also increasing. In particular, in the current stacked structure of OLED display panels, the metal layer for the common ground network trace is generally arranged adjacent to the film layer where the array substrate gate driven circuit (GOA) for driving the OLED display panel is located. Therefore, there is mutual capacitance between the metal layer where the common ground network trace is located and the GOA circuit. The existence of mutual capacitance, on the one hand, will significantly increase the power consumption of the GOA circuit, and on the other hand, will greatly increase the load of the common ground network.

[0003] SUMMARY

[0004] According to a first aspect of the present disclosure, a display panel is provided, comprising: a substrate, a time-varying signal trace arranged above the substrate, and a direct-current constant signal trace in a film layer adjacent to the time-varying signal trace, wherein a projection of the direct-current constant signal trace on the substrate does not overlap with a projection of the time-varying signal trace on the substrate.

[0005] According to some example embodiments, the projection of the direct-current constant signal trace on the substrate surrounds the projection of the time-varying signal trace on the substrate.

[0006] According to some example embodiments, the projection of the direct-current constant signal trace on the substrate and the projection of the time-varying signal trace on the substrate are staggered with each other.

[0007] According to some example embodiments, the display panel further comprises a GOA circuit arranged on the substrate, wherein the time-varying signal trace comprises a clock signal line for providing a clock signal for the GOA circuit, and the direct-current constant signal trace comprises a common ground network trace.

[0008] According to some example embodiments, the time-varying signal trace further comprises a start signal line for providing a start signal for the GOA circuit.

[0009] According to some example embodiments, the common ground network trace further has a footprint on the substrate that does not overlap with a footprint of the GOA circuit on the substrate.

[0010] According to some example embodiments, the common ground network trace further has a footprint on the substrate that surrounds a footprint of the GOA circuit on the substrate.

[0011] According to some example embodiments, the common ground network trace further has a footprint on the substrate that is staggered with a footprint of the GOA circuit on the substrate.

[0012] According to some example embodiments, the common ground network trace further has a footprint on the substrate that covers a footprint of the GOA circuit on the substrate, wherein a portion of the footprint of the common ground network trace on the substrate that overlaps with the footprint of the GOA circuit on the substrate comprises a plurality of openings.

[0013] According to some example embodiments, the common ground network trace further has a footprint on the substrate that covers a footprint of the GOA circuit on the substrate, wherein a portion of the footprint of the common ground network trace on the substrate that overlaps with the footprint of the GOA circuit on the substrate has a mesh shape.

[0014] According to some example embodiments, the common ground network trace further has a footprint on the substrate that is covered by a footprint of a display area of the display panel on the substrate, and the clock signal line and the GOA circuit have footprints on the substrate that do not overlap with the footprint of the display area on the substrate.

[0015] According to some example embodiments, the display panel further comprises a common ground network trace, wherein a film layer in which the common ground network trace is located and a film layer in which the time-varying signal trace is located are further provided with at least one metal trace film layer, and wherein the common ground network trace has a footprint on the substrate that does not overlap with a footprint of the time-varying signal trace on the substrate.

[0016] According to a second aspect of the present disclosure, there is provided a display panel manufacturing method comprising the following steps: providing a substrate; forming a time-varying signal trace above the substrate; forming a direct-current constant signal trace in a film layer adjacent to the time-varying signal trace, wherein a footprint of the direct-current constant signal trace on the substrate does not overlap with a footprint of the time-varying signal trace on the substrate.

[0017] According to some example embodiments, the display panel manufacturing method further comprises: forming a GOA circuit on the substrate; wherein the time-varying signal trace comprises a clock signal line providing a clock signal for the GOA circuit, and the direct-current constant signal trace comprises a common ground network trace.

[0018] According to a third aspect of the present disclosure, there is provided a display device comprising the display panel according to the first aspect of the present disclosure and example embodiments thereof.

[0019] According to some example embodiments, the display device is an OLED display device. BRIEF DESCRIPTION OF DRAWINGS

[0020] In the following, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings:

[0021] FIG. 1 schematically illustrates a display panel in the related art;

[0022] FIG. 2A and FIG. 2B schematically illustrate a case of mutual capacitance existing in a display panel in the related art;

[0023] FIG. 3A and FIG. 3B schematically illustrate a structure of a display panel according to an example embodiment of the present disclosure;

[0024] FIG. 4A and FIG. 4B schematically illustrate a structure of a display panel according to another example embodiment of the present disclosure;

[0025] FIG. 5A and FIG. 5B schematically illustrate a structure of a display panel according to another example embodiment of the present disclosure;

[0026] FIG. 6A and FIG. 6B schematically illustrate a structure of a display panel according to another example embodiment of the present disclosure;

[0027] FIG. 7A and FIG. 7B schematically illustrate a structure of a display panel according to another example embodiment of the present disclosure;

[0028] FIG. 8A and FIG. 8B schematically illustrate a structure of a display panel according to another example embodiment of the present disclosure;

[0029] FIG. 9 schematically illustrates a structure of a display panel according to another example embodiment of the present disclosure;

[0030] FIG. 10 schematically illustrates a structure of a display panel according to another example embodiment of the present disclosure;

[0031] FIG. 11 schematically illustrates a structure of a display panel according to another example embodiment of the present disclosure;

[0032] FIG. 12 schematically illustrates a structure of a display panel according to another exemplary embodiment of the present disclosure;

[0033] FIG. 13 schematically illustrates a structure of various parts in a display panel according to one exemplary embodiment of the present disclosure;

[0034] FIG. 14 schematically illustrates a display panel manufacturing method according to one exemplary embodiment of the present disclosure in the form of a flowchart; and

[0035] FIG. 15 schematically illustrates a display device according to one exemplary embodiment of the present disclosure in the form of a block diagram.

[0036] It should be understood that the accompanying drawings are only schematic and are intended to provide a general illustration of the exemplary embodiments of the present disclosure delivered to the addressee(s). They are not intended to provide an explanation of structures and / or components represented, nor are they necessarily drawn to scale relative to one another. Furthermore, like or similar features are denoted by like or similar reference numerals in the various drawings. DETAILED DESCRIPTION

[0037] The exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, so as to enable those skilled in the art to fully understand and implement the technical solutions according to the present disclosure.

[0038] Referring to FIG. 1, a display panel in the related art is schematically illustrated. As shown in FIG. 1, the display panel 100 can be a liquid crystal display panel or an OLED display panel, which can include a display area AA for displaying an image and an edge area surrounding the display area AA. The timing controller 110, a clock signal line CLK, a start signal line STV, and a GOA circuit 120 can be generally disposed in the above-described edge area of the display panel 100. The timing controller 110 can generate a clock signal and a start signal required for controlling the GOA circuit 120, and can transmit the clock signal and the start signal to the GOA circuit 120 via the clock signal line CLK and the start signal line STV, respectively. The GOA circuit 120 can include a plurality of gate driving units ST-1, ST-2,..., and ST-n, each of which is connected to one gate line in order to drive the display panel 100.

[0039] Referring to FIGS. 2A and 2B, which schematically illustrate a case of mutual capacitance existing in a display panel in the related art, FIG. 2A schematically illustrates a partial layer stack structure of a display panel in the related art in the form of a cross-sectional view, and FIG. 2B schematically illustrates a top view case of the partial display panel shown in FIG. 2A in the form of a plan view. As shown in FIG. 2A, the display panel 200 can include a layer stack structure 210 including a substrate 220, GOA circuits 230a, 230b, a clock signal line CL1 providing a clock signal for the GOA circuit 230a and a start signal line ST1 providing a start signal, a clock signal line CL2 providing a clock signal for the GOA circuit 230b and a start signal line ST2 providing a start signal, and a common ground network trace VSS. The GOA circuits 230a, 230b can be disposed on the substrate 220, the clock signal lines CL1 and CL2 and the start signal lines ST1 and ST2 can be disposed in a first source / drain trace layer SD1 above the GOA circuits 230a, 230b, and the common ground network trace VSS can be disposed in a second source / drain trace layer SD2 adjacent to the first source / drain trace layer SD1, and as shown in FIG. 2B, the common ground network trace VSS in the second source / drain trace layer SD2 covers the clock signal lines CL1 and CL2, the start signal lines ST1 and ST2 in the first source / drain trace layer SD1, and also covers the GOA circuits 230a, 230b. Thus, the clock signal lines CL1 and CL2 and the start signal lines ST1 and ST2 located in the first source / drain trace layer SD1 form mutual capacitances C1, C2, C3 and C4, respectively, between the common ground network trace VSS located in the second source / drain trace layer SD2. The existence of the mutual capacitances C1, C2, C3 and C4 can cause a time-varying signal such as a clock signal and / or a start signal to need to repeatedly charge and discharge these capacitances during the transition of high and low levels, which on the one hand can cause the power consumption of the GOA circuits 230a, 230b to significantly increase, and on the other hand can greatly increase the load of a direct current stable signal trace such as the common ground network trace VSS.

[0040] Referring to FIGS. 3A and 3B, which schematically illustrate a structure of a display panel according to one example embodiment of the present disclosure, FIG. 3A schematically illustrates a partial layer stack structure of the display panel in a cutaway view, and FIG. 3B schematically illustrates a top view of the partial display panel shown in FIG. 3A. As shown in FIG. 3A, the display panel 300a can include a layer stack structure 310, which includes a substrate 320, GOA circuits 330a, 330b, clock signal lines CL1 and CL2 providing clock signals for the GOA circuits 330a and 330b, respectively, start signal lines ST1 and ST2 providing start signals for the GOA circuits 330a and 330b, respectively, and a common ground network trace VSS. The GOA circuits 330a, 330b can be disposed on the substrate 320, the clock signal lines CL1 and CL2 and the start signal lines ST1 and ST2 can be disposed in a first source / drain trace layer SD1 above the GOA circuits 330a, 330b, and the common ground network trace VSS can be disposed in a second source / drain trace layer SD2 adjacent to the first source / drain trace layer SD1. It should be understood that, in the context of the present disclosure, the substrate 320 can be any suitable substrate known in the art, which can be a rigid substrate (e.g., a glass substrate, etc.), or a flexible substrate (e.g., a resin substrate, a plastic substrate, etc.) for implementing a flexible display panel, and further, the GOA circuits 330a, 330b can be any suitable GOA circuits known in the art, and the number of GOA circuits can be less or more. The present disclosure does not make any limitation on the specific type or number of the substrate and the GOA circuits.

[0041] In the display panel 300a shown in FIG. 3A, the common ground network trace VSS in the second source / drain trace layer SD2 can include an opening 340a. The opening 340a can be located above the clock signal line CL1. Referring to FIG. 3B in conjunction, the orthogonal projection of the opening 340a on the substrate 320 covers the orthogonal projection of the clock signal line CL1 on the substrate 320. That is, the orthogonal projection of the common ground network trace VSS on the substrate 320 surrounds the orthogonal projection of the clock signal line CL1 on the substrate 320. Thus, in the display panel 300a, the orthogonal projection of the common ground network trace VSS on the substrate 320 does not coincide with the orthogonal projection of the clock signal line CL1 on the substrate 320. In this way, the mutual capacitance C1 between the clock signal line CL1 and the common ground network trace VSS is eliminated, so that the power consumption of the GOA circuit 330a can be reduced, and the load of the common ground network trace VSS can be reduced.

[0042] It should be appreciated that the opening 340a in the common ground network trace VSS corresponding to the clock signal line CL1 shown in FIGS. 3A and 3B is merely illustrative and not restrictive. Thus, it is also possible to implement openings in the common ground network trace VSS corresponding to other time-varying signal traces. For example, based on the teachings of the embodiment shown in FIGS. 3A and 3B, one skilled in the art would recognize that a similar opening can also be provided in the common ground network trace VSS at a location corresponding to the clock signal line CL2 such that the orthogonal projection of the common ground network trace VSS on the substrate 320 also encloses the orthogonal projection of the clock signal line CL2 on the substrate 320 so as to thereby eliminate the mutual capacitance C3 between the clock signal line CL2 and the common ground network trace VSS, thereby enabling a reduction in the power consumption of the GOA circuit 330b and also enabling a further reduction in the loading of the common ground network trace VSS.

[0043] Referring to FIGS. 4A and 4B, which schematically illustrate the structure of a display panel according to another exemplary embodiment of the present disclosure, FIG. 4A schematically illustrates the layer stack structure of a portion of the display panel in the form of a cross-sectional view, and FIG. 4B schematically illustrates the top view of the portion of the display panel shown in FIG. 4A in the form of a plan view. It should be appreciated that the display panel 300b shown in FIGS. 4A and 4B is substantially identical in structure to the display panel 300a shown in FIGS. 3A and 3B, with the exception that the common ground network trace VSS in the second source / drain trace layer SD2 has a different arrangement. Thus, only the difference will be described hereinafter, and the same will not be described again.

[0044] As shown in FIGS. 4A and 4B, in the display panel 300b, the common ground network line VSS in the second source / drain wire layer SD2 can be arranged such that the orthogonal projection of the common ground network line VSS on the substrate 320 is staggered with the orthogonal projection of the clock signal line CL1 on the substrate 320, thereby also making the orthogonal projection of the common ground network line VSS on the substrate 320 not coincide with the orthogonal projection of the clock signal line CL1 on the substrate 320. It should be understood that the term "staggered" in the context of the present disclosure refers to the case that the orthogonal projection of the common ground network line VSS on the substrate 320 is not coincided with the orthogonal projection of the clock signal line CL1 on the substrate 320, but the orthogonal projection of the common ground network line VSS on the substrate 320 does not surround the orthogonal projection of the clock signal line CL1 on the substrate 320 (as shown in FIG. 4B). Hereinafter, the term "staggered" shall have the same meaning as the above-mentioned meaning unless specifically stated. In this way, in the display substrate 300b, the mutual capacitance C1 between the clock signal line CL1 and the common ground network line VSS is eliminated, thereby being able to reduce the power consumption of the GOA circuit 330a, and also being able to reduce the load of the common ground network line VSS.

[0045] It should be understood that the staggered arrangement of the common ground network line VSS relative to the clock signal line CL1 shown in FIGS. 4A and 4B is merely illustrative and is not limiting. Therefore, the staggered arrangement of the common ground network line VSS relative to other time-varying signal lines is also possible. For example, based on the teachings of the embodiment shown in FIGS. 4A and 4B, those skilled in the art can realize that the common ground network line VSS can also be arranged to be staggered relative to the corresponding position of the clock signal line CL2, such that the orthogonal projection of the common ground network line VSS on the substrate 320 is also staggered relative to the orthogonal projection of the clock signal line CL2 on the substrate 320, and thereby being able to eliminate the mutual capacitance C3 between the clock signal line CL2 and the common ground network line VSS, thereby being able to reduce the power consumption of the GOA circuit 330b, and also being able to further reduce the load of the common ground network line VSS.

[0046] Referring to FIGS. 5A and 5B, the structure of a display panel according to another exemplary embodiment of the present disclosure is schematically shown, wherein FIG. 5A schematically shows the layer stack structure of a partial region of the display panel in a cross-sectional view, and FIG. 5B schematically shows the top view of the partial region of the display panel shown in FIG. 5A in a plan view. It should be understood that the display panel 300c shown in FIGS. 5A and 5B is substantially the same as the display panel 300a shown in FIGS. 3A and 3B in structure, with the only difference being that the common ground network line VSS in the second source / drain wire layer SD2 has a different arrangement. Therefore, only the difference will be described below, and the same parts will not be described again.

[0047] As shown in FIG. 5A, in the display panel 300c, the common ground network line VSS in the second source / drain wire layer SD2 can include an opening 340b. The opening 340b can be located above both the clock signal line CL1 and the start signal line ST1. In combination, referring to FIG. 5B, the orthogonal projection of the opening 340b on the substrate 320 covers the orthogonal projections of both the clock signal line CL1 and the start signal line ST1 on the substrate 320, i.e., there is no common ground network line VSS above the wire regions of the clock signal line CL1 and the start signal line ST1 in the first source / drain wire layer SD1. That is, the orthogonal projection of the common ground network line VSS on the substrate 320 surrounds the orthogonal projections of both the clock signal line CL1 and the start signal line ST1 on the substrate 320, so that the orthogonal projection of the common ground network line VSS on the substrate 320 does not overlap with the orthogonal projections of both the clock signal line CL1 and the start signal line ST1 on the substrate 320. Thus, the mutual capacitance C1 between the clock signal line CL1 and the common ground network line VSS, and the mutual capacitance C2 between the start signal line ST1 and the common ground network line VSS are both eliminated, so that the power consumption of the GOA circuit 330a can be reduced, and the load of the common ground network line VSS can be reduced

[0048] It should be understood that the opening in the common ground network trace VSS corresponding to both the clock signal line CL1 and the start signal line ST1 shown in FIGS. 5A and 5B is merely illustrative and not limiting. Thus, it is also possible to implement an opening in the common ground network trace VSS corresponding to other time-varying signal traces. For example, based on the teachings of the embodiment shown in FIGS. 5A and 5B, one skilled in the art can recognize that similar openings can also be provided at locations where the common ground network trace VSS corresponds to both the clock signal line CL2 and the start signal line ST2, such that the orthogonal projection of the common ground network trace VSS on the substrate 320 also encloses the orthogonal projection of both the clock signal line CL2 and the start signal line ST2 on the substrate 320, thereby eliminating the mutual capacitance C3 between the clock signal line CL2 and the common ground network trace VSS, the mutual capacitance C4 between the start signal line ST2 and the common ground network trace VSS, and thus also reducing the power consumption of the GOA circuit 330b, and further reducing the load of the common ground network trace VSS.

[0049] Referring to FIGS. 6A and 6B, which schematically illustrate the structure of a display panel according to another exemplary embodiment of the present disclosure, FIG. 6A schematically illustrates the layer stack structure of a portion of the display panel in the form of a cross-sectional view, and FIG. 6B schematically illustrates the top view of the portion of the display panel shown in FIG. 6A in the form of a plan view. It should be understood that the display panel 300d shown in FIGS. 6A and 6B is substantially the same as the display panel 300c shown in FIGS. 5A and 5B in terms of structure, except that the common ground network trace VSS in the second source / drain trace layer SD2 is provided differently. Thus, only the difference will be described below, and the same will not be described again.

[0050] As shown in FIGS. 6A and 6B, in the display panel 300d, the common ground network trace VSS in the second source / drain trace layer SD2 can be provided such that the orthogonal projection of the common ground network trace VSS on the substrate 320 is staggered with the orthogonal projection of both the clock signal line CL1 and the start signal line ST1 on the substrate 320, thereby also making the orthogonal projection of the common ground network trace VSS on the substrate 320 not coincide with the orthogonal projection of the clock signal line CL1 on the substrate 320. In this way, in the display panel 300d, the mutual capacitance C1 between the clock signal line CL1 and the common ground network trace VSS and the mutual capacitance C2 between the start signal line ST1 and the common ground network trace VSS are both eliminated, thus reducing the power consumption of the GOA circuit 330a, and further reducing the load of the common ground network trace VSS.

[0051] It should be appreciated that the staggered arrangement of the common ground network trace VSS relative to the clock signal line CL1 and the start signal line ST1 shown in FIGS. 6A and 6B is merely illustrative and not restrictive. Thus, it is also possible that the common ground network trace VSS is staggered relative to other time-varying signal traces. For example, based on the teachings of the embodiment shown in FIGS. 6A and 6B, one skilled in the art would recognize that it is also possible to stagger the common ground network trace VSS relative to the corresponding positions of the clock signal line CL2 and the start signal line ST2 as well, such that the orthogonal projection of the common ground network trace VSS on the substrate 320 is staggered relative to the orthogonal projection of the clock signal line CL2 and the start signal line ST2 on the substrate 320 as well, thereby further eliminating the mutual capacitance C3 between the clock signal line CL2 and the common ground network trace VSS and the mutual capacitance C4 between the start signal line ST2 and the common ground network trace VSS, which in turn enables to reduce the power consumption of the GOA circuit 330b as well, and which in turn enables to further reduce the load of the common ground network trace VSS as well.

[0052] Referring to FIGS. 7A and 7B, which schematically illustrate the structure of a display panel according to another exemplary embodiment of the present disclosure, FIG. 7A schematically illustrates the layer stack structure of a portion of the display panel in the form of a cross-sectional view, and FIG. 7B schematically illustrates the top view of the portion of the display panel shown in FIG. 7A in the form of a plan view. It should be appreciated that the display panel 300e shown in FIGS. 7A and 7B is substantially identical in structure to the display panel 300a shown in FIGS. 3A and 3B and the display panel 300c shown in FIGS. 5A and 5B, with the only difference being that the common ground network trace VSS in the second source / drain trace layer SD2 has a different arrangement. Thus, only the difference will be described hereinafter, and the same will not be described again.

[0053] As shown in Figure 7A, in the display panel 300e, the common ground network trace VSS located in the second source / drain layer SD2 may include an opening 340c. The opening 340c may be located above the clock signal line CL1, the start signal line ST1, and the GOA circuit 330a. Referring to Figure 7B, the orthographic projection of the opening 340c onto the substrate 320 overlaps with the orthographic projections of the clock signal line CL1, the start signal line ST1, and the GOA circuit 330a onto the substrate 320. That is, the orthographic projection of the common ground network trace VSS onto the substrate 320 surrounds the orthographic projections of the clock signal line CL1, the start signal line ST1, and the GOA circuit 330a onto the substrate 320, thus ensuring that the orthographic projection of the common ground network trace VSS onto the substrate 320 does not coincide with the orthographic projections of the clock signal line CL1, the start signal line ST1, and the GOA circuit 330a onto the substrate 320. As a result, the mutual capacitance C1 between the clock signal line CL1 and the common ground network trace VSS, the mutual capacitance C2 between the start signal line ST1 and the common ground network trace VSS, and the mutual capacitance that may exist between the GOA circuit 330a and the common ground network trace VSS are all eliminated, thus reducing the power consumption of the GOA circuit 330a and also reducing the load on the common ground network trace VSS.

[0054] It should be understood that the openings in the common ground network trace VSS shown in Figures 7A and 7B corresponding to the clock signal line CL1, the start signal line ST1, and the GOA circuit 330a are merely illustrative and not restrictive. Therefore, it is also possible to implement openings in the common ground network trace VSS corresponding to other time-varying signal traces. For example, based on the teachings of the embodiments shown in Figures 7A and 7B, those skilled in the art can recognize that similar openings can also be provided at the locations corresponding to the common ground network trace VSS and the clock signal line CL2, the start signal line ST2, and the GOA circuit 330b, so that the orthographic projection of the common ground network trace VSS on the substrate 320 also surrounds the orthographic projections of the clock signal line CL2, the start signal line ST2, and the GOA circuit 330b on the substrate 320. This eliminates the mutual capacitance C3 between the clock signal line CL2 and the common ground network trace VSS, the mutual capacitance C4 between the start signal line ST2 and the common ground network trace VSS, and the mutual capacitance that may exist between the GOA circuit 330b and the common ground network trace VSS. Therefore, the power consumption of the GOA circuit 330b can be reduced, and the load of the common ground network trace VSS can be further reduced. Furthermore, it should be understood that in some other embodiments, the orthogonal projection of the common ground network trace VSS on the substrate 320 may also surround both the clock signal line CL1 and the GOA circuit 330a, and / or may surround both the clock signal line CL2 and the GOA circuit 330b.

[0055] Referring to Figures 8A and 8B, which schematically illustrate the structure of a display panel according to another exemplary embodiment of the present disclosure, Figure 8A schematically shows a partial stacked structure of the display panel in cross-sectional view, and Figure 8B schematically shows a partial top view of the display panel shown in Figure 8A in plan view. It should be understood that the display panel 300f shown in Figures 8A and 8B is structurally substantially the same as the display panel 300e shown in Figures 7A and 7B, the only difference being the different arrangement of the common ground network trace VSS in the second source / drain trace layer SD2. Therefore, only this difference will be described below, and the similarities will not be repeated.

[0056] As shown in Figures 8A and 8B, in the display panel 300f, the common ground network trace VSS in the second source / drain trace layer SD2 can be configured such that the orthographic projection of the common ground network trace VSS on the substrate 320 is offset from the orthographic projections of the clock signal line CL1, the start signal line ST1, and the GOA circuit 330a on the substrate 320. This also ensures that the orthographic projection of the common ground network trace VSS on the substrate 320 does not coincide with the orthographic projection of the clock signal line CL1 on the substrate 320. In this way, the mutual capacitance C1 between the clock signal line CL1 and the common ground network trace VSS, the mutual capacitance C2 between the start signal line ST1 and the common ground network trace VSS, and the potential mutual capacitance between the GOA circuit 330a and the common ground network trace VSS are eliminated in the display substrate 300f. This reduces the power consumption of the GOA circuit 330a and also reduces the load on the common ground network trace VSS.

[0057] It should be understood that the staggered arrangement of the common ground network trace VSS relative to the clock signal line CL1, the start signal line ST1, and the GOA circuit 330a shown in Figures 8A and 8B is merely illustrative and not restrictive. Therefore, it is also possible to stagger the common ground network trace VSS relative to other time-varying signal traces. For example, based on the teachings of the embodiments shown in Figures 8A and 8B, those skilled in the art can recognize that the common ground network trace VSS can also be staggered relative to the positions corresponding to the clock signal line CL2, the start signal line ST2, and the GOA circuit 330b, so that the orthographic projection of the common ground network trace VSS on the substrate 320 is also staggered relative to the orthographic projections of the clock signal line CL2, the start signal line ST2, and the GOA circuit 330b on the substrate 320. This eliminates the mutual capacitance C3 between the clock signal line CL2 and the common ground network trace VSS, the mutual capacitance C4 between the start signal line ST2 and the common ground network trace VSS, and the mutual capacitance that may exist between the GOA circuit 330b and the common ground network trace VSS. This also reduces the power consumption of the GOA circuit 330b and further reduces the load on the common ground network trace VSS.

[0058] Referring to Figure 9, a plan view schematically illustrates a top view of a display panel according to another exemplary embodiment of this disclosure. It should be understood that the display panel 300g shown in Figure 9 is substantially the same in structure as the display panels 300a shown in Figures 3A and 3B, the only difference being the different arrangement of the common ground network trace VSS in the second source / drain layer SD2. Therefore, only this difference will be described below, and the similarities will not be repeated.

[0059] As shown in the plan view in Figure 9, the orthographic projection of the common ground network trace VSS in the display panel 300g onto the substrate 320 overlaps with the orthographic projection of the GOA circuit 330a onto the substrate 320. However, the portion of the common ground network trace VSS corresponding to the GOA circuit 330a also includes multiple openings 350a, 350b, and 350c. Therefore, the orthographic projections of the multiple openings 350a, 350b, and 350c onto the substrate 320 also at least partially overlap with the orthographic projection of the GOA circuit 330a onto the substrate 320. In this way, the mutual capacitance C1 between the clock signal line CL1 and the common ground network trace VSS in the display substrate 300g is eliminated, and the capacitance that may exist between the GOA circuit 330a and the common ground network trace VSS is at least reduced. This reduces the power consumption of the GOA circuit 330a and also reduces the load on the common ground network trace VSS.

[0060] It should be understood that the configuration of the common ground network trace VSS shown in FIG9 is merely illustrative and not restrictive. Therefore, it is possible to implement openings in the common ground network trace VSS corresponding to other time-varying signal traces and / or circuits. For example, based on the teachings of the embodiment shown in FIG9, those skilled in the art will recognize that the orthographic projection of the common ground network trace VSS on the substrate 320 can also cover the orthographic projections of other components such as start signal lines ST1 and ST2 and / or GOA circuit 330b on the substrate 320 in the display panel 300g, and multiple openings can be present in the portion of the common ground network trace VSS that overlaps with these orthographic projections. In this way, the power consumption of the GOA circuit 330b can also be reduced, and the load on the common ground network trace VSS can be further reduced.

[0061] Referring to Figure 10, a plan view schematically illustrates a top view of a display panel according to another exemplary embodiment of the present disclosure. It should be understood that the display panel 300h shown in Figure 10 is structurally substantially the same as the display panels 300a shown in Figures 3A and 3B and the display panel 300g shown in Figure 9, the only difference being the different arrangement of the common ground network trace VSS in the second source / drain layer SD2. Therefore, only this difference will be described below, and the similarities will not be repeated.

[0062] As shown in the plan view in Figure 10, the orthographic projection of the common ground network trace VSS in the display panel 300h onto the substrate 320 overlaps with the orthographic projection of the GOA circuit 330a onto the substrate 320. However, the portion of the common ground network trace VSS corresponding to the GOA circuit 330a has a grid shape 360, such that the portion of the orthographic projection of the common ground network trace VSS onto the substrate 320 that overlaps with the orthographic projection of the GOA circuit 330a onto the substrate 320 also has a grid shape. In this way, the mutual capacitance C1 between the clock signal line CL1 and the common ground network trace VSS, as well as the mutual capacitance that may exist between the GOA circuit 330a and the common ground network trace VSS, in the display substrate 300h are eliminated or reduced, thereby reducing the power consumption of the GOA circuit 330a and also reducing the load on the common ground network trace VSS.

[0063] It should be understood that the configuration of the common ground network trace VSS shown in FIG10 is merely illustrative and not restrictive. Therefore, it is possible to implement a mesh structure in the common ground network trace VSS corresponding to other time-varying signal traces and / or circuits. For example, based on the teachings of the embodiment shown in FIG10, those skilled in the art will recognize that the orthographic projection of the common ground network trace VSS on the substrate 320 can also cover the orthographic projection of other components such as start signal lines ST1 and ST2 and / or GOA circuit 330b on the substrate 320 in the display panel 300h, and the portion of the common ground network trace VSS that overlaps with these orthographic projections can have a mesh shape. In this way, the power consumption of the GOA circuit 330b can also be reduced, and the load on the common ground network trace VSS can be further reduced.

[0064] Referring to Figure 11, which schematically illustrates the structure of a display panel according to another exemplary embodiment of the present disclosure. The display panel 300i shown in Figure 11 is structurally essentially the same as the display panel 300a shown in Figures 3A and 3B, the only difference being the different arrangement of the common ground network trace VSS. Therefore, only this difference will be described below, and the similarities will not be repeated.

[0065] In the display panel 300i shown in Figure 11, the film layer containing the common ground network trace VSS is not adjacent to the film layer containing the clock signal line CL1. That is, there is at least one additional metal trace layer between the film layer containing the common ground network trace VSS and the film layer containing the clock signal line CL1. As shown in Figure 11, the clock signal lines CL1 and CL2 can be located in the first source / drain layer SD1, while the common ground network trace VSS can be located in a non-adjacent third source / drain layer SD3 or an anode layer Anode. Of course, the common ground network trace VSS can still include an opening 340d, which is located above and corresponds to the clock signal line CL1. Therefore, the mutual capacitance C1 between the clock signal line CL1 and the common ground network trace VSS is eliminated. Furthermore, due to the increased distance between the common ground network trace VSS and the first source / drain trace layer SD1, the mutual capacitance between the clock signal line CL2, the start signal lines ST1 and ST2, and the GOA circuits 330a and 3303b and the common ground network trace VSS is significantly reduced. This reduces the power consumption of the GOA circuit 330a and the load on the common ground network trace VSS.

[0066] It should be understood that the common ground network trace VSS shown in Figure 11, located in the third source / drain layer SD3 or the anode layer, is merely illustrative and not limiting. For example, based on the teachings of the embodiment shown in Figure 11, those skilled in the art will recognize that the common ground network trace VSS can be located in any other film layer not adjacent to the first source / drain layer SD1 where the clock signal lines CL1 and CL2 are located, as long as the distance between the common ground network trace VSS and the first source / drain layer SD1 can be increased.

[0067] Referring to Figure 12, which schematically illustrates the structure of a display panel according to another exemplary embodiment of the present disclosure. The display panel 300j shown in Figure 12 is structurally substantially the same as the display panel 300f shown in Figures 8A and 8B, the only difference being the different arrangement of the common ground network trace VSS. Therefore, only this difference will be described below, and the similarities will not be repeated.

[0068] In the display panel 300j shown in Figure 12, the common ground network trace VSS is located within the display area AA of the display panel 300j, while the clock signal lines CL1 and CL2, the start signal lines ST1 and ST2, and the GOA circuits 330a and 330b are located outside the display area AA. In this way, the orthographic projection of the common ground network trace VSS on the substrate 320 is completely offset from the orthographic projections of the clock signal lines CL1 and CL2, the start signal lines ST1 and ST2, and the GOA circuits 330a and 330b on the substrate 320. Therefore, the mutual capacitance between CL1 and CL2, the start signal lines ST1 and ST2, and the GOA circuits 330a and 330b and the common ground network trace VSS is eliminated, thereby reducing the power consumption of the GOA circuits 330a and 330b and reducing the load on the common ground network trace VSS.

[0069] Referring to Figure 13, which schematically illustrates, in exploded view, a first source / drain layer SD1 and a common ground network trace VSS located in an adjacent second source / drain layer SD2 in a display panel according to an exemplary embodiment of the present disclosure, and the stack-up structure after the two are stacked together. As shown in Figure 13, views (a), (b), and (c) relate to the upper part of the display panel, views (d), (e), and (f) relate to the middle part of the display panel, and views (g), (h), and (i) relate to the lower part of the display panel. It should be understood that views (a) to (i) only show the first source / drain layer SD1, the common ground network trace VSS in the adjacent second source / drain layer SD2, and the stacking of the two in some areas of the various parts of the display panel (i.e., the upper, middle, and lower parts of the display panel), but it does not mean that the views (a), (b), and (c) involving the upper part of the display panel, and the views (g), (h), and (i) involving the lower part of the display panel can necessarily be completely matched with the views (d), (e), and (f) involving the middle part of the display panel.

[0070] Views (a), (d), and (g) respectively show the first source / drain layer SD1 at the top, middle, and bottom of the display panel. The first source / drain layer SD1 includes corresponding clock signal lines CL1 and CL2, start signal lines ST1 and ST2, and GOA circuits G1 and G2. Each GOA circuit G1 and G2 includes multiple driver modules. Clock signal line CL1 and start signal line ST1 provide corresponding signals to GOA circuit G1, and clock signal line CL2 and start signal line ST2 provide corresponding signals to GOA circuit G2.

[0071] Views (b), (e), and (h) respectively show the common ground network trace VSS in the second source / drain layer SD2 at the top, middle, and bottom of the display panel. As shown in these views, the common ground network trace VSS has an opening OP1 corresponding to the respective clock signal line CL1 and start signal line ST1, and an opening OP2 corresponding to the respective clock signal line CL2 and start signal line ST2, and also has grid-like covering portions NET1 and NET2 corresponding to GOA circuits G1 and G2, respectively. The grid-like covering portions NET1 and NET2 corresponding to GOA circuits G1 and G2 each include multiple vents AP. The size of the vents AP is much smaller than the sizes of the openings OP1 and OP2, so their orthographic projection on the substrate of the display panel does not surround the orthographic projection of the corresponding signal line and / or GOA circuit on the substrate, unlike the openings OP1 and OP2. Furthermore, the exhaust port AP is primarily used to release moisture generated in the organic layers covering the GOA circuits G1 and G2, and not primarily for removing or reducing the mutual capacitance between the common ground network trace VSS and the corresponding signal lines and / or GOA circuits. As shown in view (b), in the upper part of the display panel, openings OP1 and OP2 can have different shapes at their respective ends to accommodate the traces of the corresponding clock signal lines and start signal lines in the first source / drain trace layer SD1, so that after stacking, the orthographic projection of the corresponding openings on the substrate of the display panel can cover the orthographic projection of the corresponding clock signal lines and start signal lines on the substrate. Furthermore, as shown in view (h), in the lower part of the display panel, openings OP1 and OP2 can be arranged with different deflection angles relative to the vertical extension direction of the display panel, so that in the stacked structure, openings OP1 and OP2 can cover the clock signal lines and start signal lines deflected and extended at different angles. For example, in the upper part of the display panel, the tilt angle of opening OP1 relative to a first direction (e.g., the horizontal direction H shown by the dashed double arrow in the figure) is A, and in the lower part of the display panel, the tilt angle of opening OP1 relative to the first direction (i.e., the horizontal direction H) is B, where the tilt angle A is smaller than the tilt angle B. In other words, opening OP1 is tilted more towards the display area (or pixel area) in the upper part of the display panel than in the lower part. Opening OP2 also has a similar tilt setting to opening OP1 in both the upper and lower parts of the display panel, which will not be described in detail here. Furthermore, as shown in views (b) and (e), no exhaust port AP is provided on the side of the opening OP1 opposite to the grid-like covering portion NET1 in the upper and middle parts of the display panel, while as shown in view (h), an exhaust port AP is provided on the side of the opening OP1 opposite to the grid-like covering portion NET1 in the lower part of the display panel; and for the opening OP2, exhaust ports AP are provided on both sides in the upper, middle and lower parts of the display panel.Furthermore, in the upper part of the display panel, multiple exhaust ports AP are arranged to be approximately flush with the ends of openings OP1 and OP2, while in the lower part of the display panel, multiple exhaust ports AP are formed to surround the portion of openings OP1 and OP2 in that lower part.

[0072] Views (c), (f), and (i) respectively illustrate the stacked configuration of the common ground network traces VSS in the first source / drain layer SD1 and the second source / drain layer SD2 at the top, middle, and bottom of the display panel. In these configurations, the opening OP1 in the common ground network traces VSS at the top, middle, and bottom of the display panel corresponds to the corresponding clock signal line CL1 and start signal line ST1 in the first source / drain layer SD1. The length and width of the opening OP1 at each location are greater than the trace range of the clock signal line CL1 and the start signal line ST1, such that in the stacked structure, the opening OP1 is positioned within the display panel... The orthographic projection of the common ground network trace VSS on the substrate completely covers the orthographic projection of the clock signal line CL and the start signal line ST1 on the substrate. The opening OP2 in the common ground network trace VSS at the top, middle, and bottom of the display panel corresponds to the corresponding clock signal line CL2 and start signal line ST2 in the first source / drain layer SD1. The length and width of the opening OP2 at each location are greater than the trace range of the clock signal line CL2 and the start signal line ST2, such that in the stacked structure, the orthographic projection of the opening OP2 on the substrate of the display panel completely covers the orthographic projection of the clock signal line CL2 and the start signal line ST2 on the substrate of the display panel. Therefore, the orthographic projection of the common ground network trace VSS on the substrate of the display panel surrounds the orthographic projections of the clock signal lines CL1, CL2 and the start signal lines ST1, ST2 on the substrate of the display panel. Furthermore, the grid-shaped covering portions NET1 and NET2 in the common ground network trace VSS correspond to the GOA circuits G1 and G2 in the first source / drain layer, respectively. The orthographic projection of the grid-like covering portion NET1 onto the substrate of the display panel completely covers the orthographic projection of the GOA circuit G1 onto the substrate of the display panel, while the orthographic projection of the grid-like covering portion NET2 onto the substrate of the display panel only partially covers the orthographic projection of the GOA circuit G2 onto the substrate of the display panel. Of course, depending on actual needs, the orthographic projection of the grid-like covering portion NET2 onto the substrate of the display panel can also completely cover the orthographic projection of the GOA circuit G2 onto the substrate of the display panel, and the orthographic projection of the grid-like covering portion NET1 onto the substrate of the display panel can also only partially cover the orthographic projection of the GOA circuit G1 onto the substrate of the display panel. Therefore, the capacitance between the clock signal line and / or start signal line and the common ground network trace is eliminated, and the capacitance between the GOA circuit and the common ground network trace is reduced, thereby reducing the power consumption of the GOA circuit and the load on the common ground network trace.

[0073] Referring again to views (a) to (i), in some embodiments, at least one of openings OP1 and OP2 is a continuous elongated opening at the top, middle, and bottom of the display panel (i.e., the opening is continuous and uninterrupted, for example, not interrupted by a portion of the common ground network trace). Therefore, the position corresponding to the orthographic projection of opening OP1 onto the substrate of the display panel completely covers the positions corresponding to the orthographic projections of the corresponding clock signal line CL1 and start signal line ST1 onto the substrate of the display panel, and the position corresponding to the orthographic projection of opening OP2 onto the substrate of the display panel completely covers the positions corresponding to the orthographic projections of the clock signal line CL2 and start signal line ST2 onto the substrate of the display panel.

[0074] Referring again to views (a) to (i), in some embodiments, the spacing between openings OP1 and OP2 may not be exactly equal at the top, middle, and bottom of the display panel. As shown in views (b), (e), and (h): the spacing between openings OP1 and OP2 at the top of the display panel is a1, the spacing between openings OP1 and OP2 at the middle of the display panel is a2, and the spacing between openings OP1 and OP2 at the bottom of the display panel is a3. The relationship between the three spacings can be a1 ≥ a2 > a3, which helps to accommodate the clock signal lines CL1, CL2 and the start signal lines ST1, ST2, etc.

[0075] It should be understood that although the relative arrangement of the common ground network traces and clock signal lines and / or start signal lines has been described in detail in the exemplary embodiments described above with reference to Figures 3A to 13, in reality, in the stacked structure of the display panel, there will be mutual capacitance between any time-varying signal trace and the DC constant signal trace in the adjacent film layer, which will adversely affect the power consumption of the display panel. It should be understood that, in the context of this disclosure, the term "time-varying signal" refers to a signal whose voltage changes over time, such as a clock signal whose voltage repeatedly switches between high and low levels over time; while the term "DC constant signal" refers to a signal whose voltage remains constant over time, such as an electrical signal in a common ground network or a power supply network maintained at a specific voltage value.

[0076] Therefore, in the embodiments provided by this disclosure, the display panel may include a substrate, time-varying signal traces disposed above the substrate, and DC constant signal traces in a film layer adjacent to the time-varying signal traces, wherein the orthographic projection of the DC constant signal traces on the substrate does not coincide with the orthographic projection of the time-varying signal traces on the substrate. Specifically, in some exemplary embodiments, the orthographic projection of the DC constant signal traces on the substrate surrounds the orthographic projection of the time-varying signal traces on the substrate; in other exemplary embodiments, the orthographic projection of the DC constant signal traces on the substrate and the orthographic projection of the time-varying signal traces on the substrate are offset from each other. In this way, the mutual capacitance between the time-varying signal traces and the DC constant signal traces in adjacent film layers can be reduced or even eliminated, thereby reducing the power consumption of the display panel.

[0077] Referring to Figure 14, which schematically illustrates a display panel manufacturing method according to an exemplary embodiment of the present disclosure in the form of a flowchart, the display panel manufacturing method 500 includes the following steps:

[0078] In step 510, a substrate is provided;

[0079] In step 520, a time-varying signal trace is formed above the substrate;

[0080] In step 530, a DC constant signal trace is formed in a film layer adjacent to the time-varying signal trace, wherein the orthographic projection of the DC constant signal trace on the substrate does not coincide with the orthographic projection of the time-varying signal trace on the substrate.

[0081] Therefore, in the display panel manufactured using the display panel manufacturing method 500, the mutual capacitance between the time-varying signal traces and the DC constant signal traces in the adjacent film layers can be reduced or even eliminated, thereby reducing the power consumption of the display panel.

[0082] Furthermore, in some embodiments, the display panel manufacturing method 500 further includes the step of forming a GOA circuit on the substrate. Therefore, the time-varying signal trace formed in step 520 includes a clock signal line providing a clock signal to the GOA circuit, and the DC constant signal trace formed in step 530 includes a common ground network trace. Consequently, the mutual capacitance between the clock signal line and the common ground network trace of the GOA circuit is reduced or even eliminated, thereby reducing the power consumption of the GOA circuit and also reducing the load on the common ground network trace.

[0083] Referring to Figure 15, a block diagram schematically illustrates a display device according to an exemplary embodiment of the present disclosure. As shown in Figure 15, the display device 700 may include a display panel 710, wherein the display panel 710 may be implemented as any of the display panels 300a to 300i described in detail above. Thus, in the display device 700, the capacitance between the clock signal line and the common ground network trace is eliminated, and the capacitance between the GOA circuit and the common ground network trace is reduced, thereby reducing the power consumption of the GOA circuit and the load on the common ground network trace. In one embodiment, the display device 700 may be implemented as an OLED display device. Furthermore, in specific implementations, the display device 700 provided according to the above exemplary embodiments of the present disclosure may be implemented as any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. It should be understood that other essential components of the various display devices described above are known to those skilled in the art and will not be described further here, nor should they be construed as limiting the present disclosure.

[0084] The terminology used in this disclosure is for the purpose of describing embodiments thereof and is not intended to limit the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and “including,” as used herein, refer to the presence of the stated feature but do not exclude the presence of one or more other features or the addition of one or more other features. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this disclosure to describe various features, these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

[0085] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined in this disclosure.

[0086] In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example that is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction or violation of technical principles, those skilled in the art can combine and integrate the different embodiments or examples and features described in this specification, or omit some technical features from the different embodiments or examples described in this specification, and embodiments or examples obtained based on such combinations, arrangements, or omissions are also considered to fall within the scope of this disclosure.

[0087] The methods described in this disclosure include one or more steps or actions. These method steps and / or actions do not necessarily have to be performed in the order described in this disclosure, but can be performed in different orders, such as simultaneously or in reverse order, as long as this does not contradict the principles of the technical solutions described in this disclosure. Furthermore, depending on actual needs, the steps or actions in the methods described in this disclosure can be replaced with different steps or actions, or additional steps or actions may be included.

[0088] Although this disclosure has been described in detail with reference to some exemplary embodiments, it is not limited to the particular forms described herein. Rather, the scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate, a time-varying signal trace arranged above the substrate, and a direct-current constant signal trace in a film layer adjacent to the time-varying signal trace, wherein a projection of the direct-current constant signal trace on the substrate does not coincide with a projection of the time-varying signal trace on the substrate.

2. The display panel of claim 1, wherein, The projection of the direct-current constant signal trace on the substrate surrounds the projection of the time-varying signal trace on the substrate.

3. The display panel of claim 1, wherein, The projection of the direct-current constant signal trace on the substrate is staggered with the projection of the time-varying signal trace on the substrate.

4. The display panel of any one of claims 1 to 3, wherein, The display panel further comprises a GOA circuit arranged on the substrate, wherein the time-varying signal trace comprises a clock signal line for providing a clock signal for the GOA circuit, and the direct-current constant signal trace comprises a common ground network trace.

5. The display panel of claim 4, wherein, The time-varying signal trace further comprises a start signal line for providing a start signal for the GOA circuit.

6. The display panel of claim 4, wherein, The projection of the common ground network trace on the substrate also does not coincide with a projection of the GOA circuit on the substrate.

7. The display panel of claim 6, wherein, The projection of the common ground network trace on the substrate also surrounds the projection of the GOA circuit on the substrate.

8. The display panel of claim 6, wherein, The projection of the common ground network trace on the substrate also surrounds the projection of the GOA circuit on the substrate.

9. The display panel of claim 4, wherein, The projection of the common ground network trace on the substrate also surrounds the projection of the GOA circuit on the substrate.

10. The display panel of claim 4, wherein, The projection of the common ground network trace on the substrate covers the projection of the GOA circuit on the substrate, wherein a part of the projection of the common ground network trace on the substrate that coincides with the projection of the GOA circuit on the substrate comprises a plurality of openings.

11. The display panel of claim 4, wherein, The projection of the common ground network trace on the substrate covers the projection of the GOA circuit on the substrate, wherein a part of the projection of the common ground network trace on the substrate that coincides with the projection of the GOA circuit on the substrate has a grid shape.

12. The display panel of claim 4, wherein, The projection of the common ground network trace on the substrate is covered by a projection of a display area of the display panel on the substrate, and the projections of the clock signal line and the GOA circuit on the substrate do not coincide with the projection of the display area on the substrate.

13. A display panel manufacturing method, characterized by, The direct-current constant signal trace comprises a common ground network trace, wherein at least one metal trace film layer is further arranged between a film layer in which the common ground network trace is arranged and a film layer in which the time-varying signal trace is arranged, and wherein the projection of the common ground network trace on the substrate does not coincide with the projection of the time-varying signal trace on the substrate. Comprising: providing a substrate; forming a time-varying signal trace above the substrate; 14. The display panel manufacturing method according to claim 13, wherein forming a direct-current constant signal trace in a film layer adjacent to the time-varying signal trace, wherein a projection of the direct-current constant signal trace on the substrate does not coincide with a projection of the time-varying signal trace on the substrate. Further comprising: forming a GOA circuit on the substrate; wherein the time-varying signal trace comprises a clock signal line for providing a clock signal for the GOA circuit, and the direct-current constant signal trace comprises a common ground network trace.

15. A display device comprising: The display device includes the display panel according to any one of claims 1 to 12.

16. The display device of claim 15, wherein, The display device is an OLED display device.

Images