Semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

The present application relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a signal line (118); and storage cell layers parallel to a substrate (102). The storage cell layers comprise transistors (124). Each transistor (124) comprises: a gate dielectric layer (116) surrounding the side wall of the signal line (118); a semiconductor layer (120) surrounding the side wall of the signal line (118) and located on the side of the gate dielectric layer (116) distant from the signal line (118); and a van der Waals dielectric layer (114) surrounding the side wall of the signal line (118) and located between the semiconductor layer (120) and the gate dielectric layer (116) and adjacent to the gate dielectric layer (116).

Description

Semiconductor devices, their fabrication methods, and electronic devices

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on May 29, 2024, application number 2024106774175, entitled "Semiconductor device and method of fabrication thereof and electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for fabricating the same, and an electronic device. Background Technology

[0004] DRAM (Dynamic Random Access Memory) devices are widely used in electronic devices, the Internet of Things (IoT), and smart cars, holding the largest market share in the semiconductor market. With the miniaturization of integrated circuits, achieving higher storage density in a smaller area is key to DRAM development. On one hand, reducing the size of individual memory cells can increase storage density. However, the resulting more precise fabrication requires more advanced manufacturing processes. On the other hand, stacking multiple memory cells on a given area can also increase storage density. Devices that stack multiple memory cells in this way are called 3D DRAM. 3D DRAM devices can significantly increase storage density within a limited area without the need for advanced processes like EUV lithography.

[0005] Summary of the Invention

[0006] According to various embodiments of this application, a semiconductor device, a method for fabricating the same, and an electronic device are provided, which can optimize charge transport in the semiconductor device and improve the electron mobility and stability of the semiconductor device.

[0007] This disclosure provides a semiconductor device, including:

[0008] The signal line extends along a first direction perpendicular to the substrate;

[0009] A memory cell layer, parallel to the substrate, includes transistors, and signal lines pass through each transistor; the transistors include:

[0010] A gate dielectric layer surrounds the sidewalls of the signal line;

[0011] A semiconductor layer, surrounding the sidewall of the signal line, is located on the side of the gate dielectric layer away from the signal line;

[0012] A van der Waals dielectric layer surrounds the sidewall of the signal line, is located between the semiconductor layer and the gate dielectric layer, and is adjacent to the gate dielectric layer.

[0013] In one embodiment, the van der Waals dielectric layer surrounds the sidewalls of the signal line;

[0014] The transistors through which the signal lines pass share the van der Waals dielectric layer.

[0015] In one embodiment, the van der Waals dielectric layer is made of hexagonal boron nitride and / or antimony trioxide.

[0016] In one embodiment, the gate dielectric layer, the semiconductor layer, and the van der Waals dielectric layer all completely surround the sidewalls of the signal line.

[0017] In one embodiment, the van der Waals dielectric layers are spaced apart in the first direction, and the surfaces of the semiconductor layers near the signal lines are adjacent to the surfaces of the van der Waals dielectric layers away from the signal lines.

[0018] In one embodiment, a plurality of the memory cell layers are stacked in the first direction, the van der Waals dielectric layer extends along the first direction, and each of the transistors stacked in the first direction shares the van der Waals dielectric layer.

[0019] In one embodiment, the signal lines include word lines, the transistors include storage transistors, and the storage cell layer further includes:

[0020] Bit line;

[0021] Capacitors are disposed at intervals from the bit lines;

[0022] The semiconductor layer of the storage transistor is adjacent to the bit line and the capacitor, respectively.

[0023] In one embodiment, each of the memory transistor arrays in the memory cell layer is arranged; the bit lines extend along a second direction in a plane parallel to the substrate and are spaced apart along a third direction in a plane parallel to the substrate, the third direction intersecting the second direction.

[0024] In one embodiment, the signal line includes a bit line select signal line, the transistor includes a bit line select transistor, and the memory cell layer further includes:

[0025] Bit lines extend in a second direction in a plane parallel to the substrate;

[0026] A common bit line, spaced apart from the bit line, extends along a third direction in a plane parallel to the base, and the third direction intersects with the second direction;

[0027] The semiconductor layer of the bit line selection transistor is adjacent to the common bit line and the bit line, respectively.

[0028] In one embodiment, the bit lines and the bit line selection transistors are arranged at third-direction intervals, and the semiconductor layer of each bit line selection transistor is adjacent to each bit line and the common bit line.

[0029] This disclosure also provides a method for fabricating a semiconductor device, comprising:

[0030] A substrate having a stacked structure is provided, the stacked structure comprising conductive layers and insulating layers alternately stacked in a first direction perpendicular to the substrate;

[0031] The stacked structure is etched to form a first etched hole extending along the first direction, the first etched hole penetrating at least the conductive layer in the stacked structure near the substrate;

[0032] A semiconductor layer, a van der Waals dielectric layer, and a gate dielectric layer are sequentially formed on the sidewall of the conductive layer exposed by the first etched hole, and the semiconductor layers are spaced apart in the first direction;

[0033] A signal line is formed within the first etched hole, and the signal line is in contact with the gate dielectric layer.

[0034] In one embodiment, a semiconductor layer, a van der Waals dielectric layer, and a gate dielectric layer are sequentially formed on the sidewall of the conductive layer exposed by the first etched hole, including:

[0035] A semiconductor material layer, a van der Waals dielectric layer, and a gate dielectric layer are formed conformally on the sidewall of the first etched hole;

[0036] A first trench is formed in the first direction through the stacked structure. The first trench is located on opposite sides of the first etched hole and is spaced apart from the first etched hole. The first trench extends along a third direction in a plane parallel to the substrate.

[0037] Based on the first trench, each insulating layer is etched away in a direction parallel to the substrate to form a first transverse filling trench;

[0038] Remove the semiconductor material layer exposed by the first transverse filling groove to obtain the semiconductor layer composed of the remaining semiconductor material layer.

[0039] In one embodiment, the method for fabricating the semiconductor device further includes:

[0040] The first insulating material is filled into the first trench and the first transverse filling groove;

[0041] A second etched hole is formed through the first insulating material, the second etched hole being located on opposite sides of the first etched hole;

[0042] Based on the second etching hole, the conductive layer between the first etching hole and the second etching hole is etched in a direction parallel to the substrate until the semiconductor layer is exposed, forming a second lateral filling groove;

[0043] The second insulating material is filled into the second etched hole and the second transverse filling groove.

[0044] In one embodiment, the provision of the substrate having a laminated structure includes:

[0045] A substrate is provided having an initial stacked structure, the initial stacked structure comprising sacrificial layers and insulating layers alternately stacked in the first direction;

[0046] The initial stacked structure is etched to form a stacked main branch extending in a second direction parallel to the substrate, a plurality of stacked branches spaced apart in the second direction and connected to the stacked main branch, and a stacked connecting branch located at one end of the stacked main branch and connected to the stacked main branch in the second direction. The stacked branches and the stacked connecting branches all extend in a third direction parallel to the substrate, and the third direction intersects with the second direction.

[0047] A support structure extending in the second direction is formed on the substrate, the support structure being located on the side of the stacked branch away from the stacked main branch and adjacent to the stacked branch;

[0048] A first preset hole is formed in the first direction, penetrating the stacked branch, and a second preset hole is formed in the stacked connecting branch;

[0049] Sacrificial material is filled into the first preset hole and the second preset hole;

[0050] The sacrificial layer in the stacked main branch, the stacked branch, and the stacked connecting branch is replaced with the conductive layer to obtain a stacked structure.

[0051] An isolation structure is formed within the interval between adjacent support structures;

[0052] Specifically, the first etched hole is obtained by etching away the sacrificial material in the first preset hole and / or the second preset hole; the conductive layer in the main branch of the stack serves as a bit line; the conductive layer in the branch of the stack serves as a conductive branch; the conductive layer in the connecting branch of the stack includes a first part connected to the bit line and a second part spaced apart from the bit line; the second part is adjacent to the common bit line.

[0053] In one embodiment, the method for fabricating the semiconductor device further includes:

[0054] A capacitor is formed at the end of the conductive branch that is away from the bit line in the third direction.

[0055] The conductive branch located on the side of the semiconductor layer away from the bit line constitutes the first electrode of the capacitor, and the first electrode is adjacent to the semiconductor layer.

[0056] An electronic device includes a semiconductor device as described above; and / or a semiconductor device made by the method described above for preparing the semiconductor device.

[0057] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0059] Figure 1 is a schematic flowchart of a method for fabricating a semiconductor device in one embodiment;

[0060] Figure 2 is a three-dimensional schematic diagram of a semiconductor device after the initial stacked structure is formed in one embodiment;

[0061] Figure 3 is a three-dimensional schematic diagram of a semiconductor device after etching the initial stacked structure in one embodiment;

[0062] Figure 4 is a top view of the semiconductor device shown in Figure 3;

[0063] Figure 5 is a schematic cross-sectional view of the semiconductor device shown in Figure 3 along the AA direction in a direction perpendicular to the substrate.

[0064] Figure 6 is a schematic cross-sectional view of the semiconductor device shown in Figure 3 along the BB direction in a direction perpendicular to the substrate.

[0065] Figure 7 is a three-dimensional schematic diagram of the semiconductor device after the support structure is formed in one embodiment;

[0066] Figure 8 is a top view of the semiconductor device shown in Figure 7;

[0067] Figure 9 is a schematic cross-sectional view of the semiconductor device shown in Figure 7 along the AA direction in a direction perpendicular to the substrate.

[0068] Figure 10 is a schematic cross-sectional view of the semiconductor device shown in Figure 7 along the BB direction in a direction perpendicular to the substrate.

[0069] Figure 11 is a three-dimensional schematic diagram of a semiconductor device after the formation of the first and second preset holes in one embodiment;

[0070] Figure 12 is a top view of the semiconductor device shown in Figure 11;

[0071] Figure 13 is a schematic cross-sectional view of the semiconductor device shown in Figure 11 along the AA direction in a direction perpendicular to the substrate;

[0072] Figure 14 is a schematic cross-sectional view of the semiconductor device shown in Figure 11 along the BB direction in a direction perpendicular to the substrate;

[0073] Figure 15 is a three-dimensional schematic diagram of a semiconductor device after being filled with sacrificial material in one embodiment;

[0074] Figure 16 is a top view of the semiconductor device shown in Figure 15;

[0075] Figure 17 is a schematic cross-sectional view of the semiconductor device shown in Figure 15 along the AA direction in a direction perpendicular to the substrate.

[0076] Figure 18 is a schematic cross-sectional view of the semiconductor device shown in Figure 15 along the BB direction in a direction perpendicular to the substrate.

[0077] Figure 19 is a three-dimensional schematic diagram of the semiconductor device after the sacrificial layer has been removed in one embodiment;

[0078] Figure 20 is a top view of the semiconductor device shown in Figure 19;

[0079] Figure 21 is a schematic cross-sectional view of the semiconductor device shown in Figure 19 along the AA direction in a direction perpendicular to the substrate;

[0080] Figure 22 is a schematic cross-sectional view of the semiconductor device shown in Figure 19 along the BB direction in a direction perpendicular to the substrate;

[0081] Figure 23 is a three-dimensional schematic diagram of the semiconductor device after obtaining the stacked structure in one embodiment;

[0082] Figure 24 is a top view of the semiconductor device shown in Figure 23;

[0083] Figure 25 is a schematic cross-sectional view of the semiconductor device shown in Figure 23 along the AA direction in a direction perpendicular to the substrate;

[0084] Figure 26 is a schematic cross-sectional view of the semiconductor device shown in Figure 23 along the BB direction in a direction perpendicular to the substrate;

[0085] Figure 27 is a three-dimensional schematic diagram of a semiconductor device after the isolation structure is formed in one embodiment;

[0086] Figure 28 is a top view of the semiconductor device shown in Figure 27;

[0087] Figure 29 is a schematic cross-sectional view of the semiconductor device shown in Figure 27 along the AA direction in a direction perpendicular to the substrate;

[0088] Figure 30 is a schematic cross-sectional view of the semiconductor device shown in Figure 27 along the BB direction in a direction perpendicular to the substrate.

[0089] Figure 31 is a three-dimensional schematic diagram of a semiconductor device after signal lines have been formed in one embodiment;

[0090] Figure 32 is a top view of the semiconductor device shown in Figure 31;

[0091] Figure 33 is a schematic cross-sectional view of the semiconductor device shown in Figure 31 along the AA direction in a direction perpendicular to the substrate;

[0092] Figure 34 is a schematic cross-sectional view of the semiconductor device shown in Figure 31 along the BB direction in a direction perpendicular to the substrate.

[0093] Figure 35 is a three-dimensional schematic diagram of a semiconductor device after the semiconductor layer is formed in one embodiment;

[0094] Figure 36 is a top view of the semiconductor device shown in Figure 35;

[0095] Figure 37 is a schematic cross-sectional view of the semiconductor device shown in Figure 35 along the AA direction in a direction perpendicular to the substrate.

[0096] Figure 38 is a schematic cross-sectional view of the semiconductor device shown in Figure 35 along the BB direction in a direction perpendicular to the substrate.

[0097] Figure 39 is a three-dimensional schematic diagram of a semiconductor device after being filled with a first insulating material in one embodiment;

[0098] Figure 40 is a top view of the semiconductor device shown in Figure 39;

[0099] Figure 41 is a schematic cross-sectional view of the semiconductor device shown in Figure 39 along the AA direction in a direction perpendicular to the substrate.

[0100] Figure 42 is a schematic cross-sectional view of the semiconductor device shown in Figure 39 along the BB direction in a direction perpendicular to the substrate;

[0101] Figure 43 is a three-dimensional schematic diagram of a semiconductor device after the second lateral filling groove is formed in one embodiment;

[0102] Figure 44 is a top view of the semiconductor device shown in Figure 43;

[0103] Figure 45 is a schematic cross-sectional view of the semiconductor device shown in Figure 43 along the AA direction in a direction perpendicular to the substrate.

[0104] Figure 46 is a schematic cross-sectional view of the semiconductor device shown in Figure 43 along the BB direction in a direction perpendicular to the substrate.

[0105] Figure 47 is a three-dimensional schematic diagram of a semiconductor device after being filled with a second insulating material in one embodiment;

[0106] Figure 48 is a top view of the semiconductor device shown in Figure 47;

[0107] Figure 49 is a schematic cross-sectional view of the semiconductor device shown in Figure 47 along the AA direction in a direction perpendicular to the substrate.

[0108] Figure 50 is a schematic cross-sectional view of the semiconductor device shown in Figure 47 along the BB direction in a direction perpendicular to the substrate.

[0109] Figure 51 is a three-dimensional schematic diagram of a semiconductor device after a capacitor has been formed in one embodiment.

[0110] Explanation of reference numerals in the attached figures:

[0111] Substrate 102, initial stacked structure 104, support structure 106, stacked structure 108, isolation structure 110, semiconductor material layer 112, van der Waals dielectric layer 114, gate dielectric layer 116, signal line 118, semiconductor layer 120, capacitor 122, transistor 124, bit line 126, common bit line 128, sacrificial layer 202, insulating layer 204, conductive layer 206, stacked main branch 302, stacked branch 304, stacked connecting branch 306, first insulating material 308, second insulating material 310, first gap 402, second gap 404, first preset hole 406, second preset hole 408, sacrificial material 410, lateral groove 412, first trench 414, first lateral filling groove 416, second etched hole 418, second lateral filling groove 420. Detailed Implementation

[0112] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0113] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0114] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0115] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0116] It is understood that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a physical connection or a signal connection; they can refer to a direct connection, an indirect connection via an intermediary, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0117] It is understood that the terms "first," "second," etc., as used in this disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first etched hole may be referred to as a second etched hole, and similarly, a second etched hole may be referred to as a first etched hole. Both the first etched hole and the second etched hole are etched holes, but they are not the same etched hole.

[0118] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. In the description of this disclosure, "several" means at least one, such as one, two, etc., unless otherwise expressly specified.

[0119] As used herein, the terms “substrate” and “base” refer to and include the base material or structure of the transistor material described in this disclosure. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate comprising layers of semiconductor material.

[0120] In this disclosure, the upper surface of the substrate is the surface on which the substrate forms a stacked structure, and the lower surface of the substrate is the surface opposite to the upper surface. The upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For structures or layers located within the substrate, the surface parallel to the substrate surface is designated as the upper surface / top surface / top / top face, and the surface away from the upper surface is designated as the lower surface / bottom surface / bottom / bottom face. Conversely, for structures or layers on the substrate, the surface closer to the upper surface is designated as the lower surface / bottom surface / bottom / bottom face, and the surface away from the upper surface is designated as the upper surface / top surface / top / top face. For structures, trenches, holes, or layers formed in a semiconductor structure in a direction away from the substrate surface, the surface perpendicular to the substrate is the sidewall of the structure, trench, hole, or layer, and the point where the trench or hole stops penetrating is the bottom of the trench or hole. For trenches or holes formed in other directions in the semiconductor structure, the point where the trench or hole stops penetrating is the bottom of the trench or hole, and the surface in the penetrating direction is the sidewall of the trench or hole.

[0121] Figure 1 is a schematic flowchart of a semiconductor device fabrication method in one embodiment. As shown in Figure 1, in this embodiment, a semiconductor device fabrication method is provided, including:

[0122] S102 provides a substrate having a laminated structure.

[0123] A substrate is provided, which may be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked germanium (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the substrate is made of single-crystal silicon; a stacked structure is formed on the substrate, the stacked structure including conductive layers and insulating layers alternately stacked in a first direction perpendicular to the substrate. Alternating stacking means that in the first direction (from the side of the stacked structure closest to the substrate to the side of the stacked structure furthest from the substrate), an insulating layer is disposed on the surface of the conductive layer furthest from the substrate, and a conductive layer is disposed on the surface of the insulating layer furthest from the substrate. Both the bottom surface of the stacked structure closest to the substrate and the top surface of the stacked structure furthest from the substrate are provided with either an insulating layer or a conductive layer, and there is no necessary relationship between the two.

[0124] S104, etching the stacked structure to form a first etched hole extending along the first direction.

[0125] An etched stacked structure is formed, in which a first etched hole extending along a first direction is formed. In a direction parallel to the substrate, the periphery of the first etched hole is completely surrounded by the stacked structure. The sidewalls of the first etched hole are formed by the sidewalls of the exposed conductive layer and the sidewalls of the insulating layer in the stacked structure. The first etched hole penetrates at least the conductive layer in the stacked structure near the substrate, that is, the first etched hole penetrates at least the conductive layer at the bottom of the stacked structure. For example, the first etched hole penetrates the stacked structure along the first direction to avoid residual conductive layer material at the bottom of the first etched hole due to etching deviations.

[0126] S106, a semiconductor layer, a van der Waals dielectric layer and a gate dielectric layer are sequentially formed on the sidewall of the conductive layer exposed by the first etched hole.

[0127] A semiconductor layer, a van der Waals dielectric layer, and a gate dielectric layer are sequentially formed on the sidewall of the conductive layer exposed by the first etched hole. The van der Waals dielectric layer is in contact with the gate dielectric layer. In a first direction, the semiconductor layers are spaced apart, such that the transistors arranged in the first direction are spaced apart to avoid leakage. The semiconductor layers and conductive layers correspond one-to-one. The van der Waals dielectric layer and / or the gate dielectric layer covers the sidewall of the first etched hole. Alternatively, in the first direction, the van der Waals dielectric layers are spaced apart and correspond one-to-one with the conductive layers, and / or the gate dielectric layers are spaced apart and correspond one-to-one with the conductive layers. The transistor includes a semiconductor layer, a van der Waals dielectric layer, and a gate dielectric layer. The opposing surfaces of the van der Waals dielectric layers are in contact with the semiconductor layer and the gate dielectric layer, respectively. Compared to direct contact between the semiconductor layer and the gate dielectric layer, this reduces the defect density on the surface in contact with the gate dielectric layer.

[0128] S108, a signal line is formed in the first etched hole, and the signal line is in contact with the gate dielectric layer.

[0129] A signal line is formed in the first etched hole. The signal line extends along the first direction, and the portion corresponding to the conductive layer also serves as the gate of the transistor. The signal line contacts the gate dielectric layer to realize the control of each transistor arranged in the first direction.

[0130] In the above-mentioned semiconductor device fabrication method, a semiconductor layer, a van der Waals dielectric layer and a gate dielectric layer are sequentially formed on the sidewall of the conductive layer exposed by the first etch hole. This reduces the defect state density on the surface of the gate dielectric layer near the semiconductor layer, improves the electron mobility of the semiconductor device, increases the stability of the semiconductor device, and improves the performance of the semiconductor device.

[0131] Figure 2 is a perspective view of the semiconductor device after the initial stacked structure is formed in one embodiment. Figure 3 is a perspective view of the semiconductor device after the initial stacked structure is etched in one embodiment. Figure 4 is a top view of the semiconductor device shown in Figure 3. Figure 5 is a cross-sectional view of the semiconductor device shown in Figure 3 along the AA direction in a direction perpendicular to the substrate. Figure 6 is a cross-sectional view of the semiconductor device shown in Figure 3 along the BB direction in a direction perpendicular to the substrate. Figure 7 is a perspective view of the semiconductor device after the support structure is formed in one embodiment. Figure 8 is a top view of the semiconductor device shown in Figure 7. Figure 9 is a cross-sectional view of the semiconductor device shown in Figure 7 along the AA direction in a direction perpendicular to the substrate. Figure 10 is a view of the semiconductor device shown in Figure 7. Figure 11 is a perspective view of the semiconductor device after forming the first and second preset holes in one embodiment. Figure 12 is a top view of the semiconductor device shown in Figure 11. Figure 13 is a cross-sectional view of the semiconductor device shown in Figure 11 along the AA direction in a direction perpendicular to the substrate. Figure 14 is a cross-sectional view of the semiconductor device shown in Figure 11 along the BB direction in a direction perpendicular to the substrate. Figure 15 is a perspective view of the semiconductor device after filling with sacrificial material in one embodiment. Figure 16 is a top view of the semiconductor device shown in Figure 15. Figure 17 is a cross-sectional view of the semiconductor device shown in Figure 15 along the AA direction in a direction perpendicular to the substrate. Figure 18... Figure 15 shows a cross-sectional view of the semiconductor device along the BB direction perpendicular to the substrate. Figure 19 is a three-dimensional schematic diagram of the semiconductor device after removing the sacrificial layer in one embodiment. Figure 20 is a top view of the semiconductor device shown in Figure 19. Figure 21 is a cross-sectional view of the semiconductor device shown in Figure 19 along the AA direction perpendicular to the substrate. Figure 22 is a cross-sectional view of the semiconductor device shown in Figure 19 along the BB direction perpendicular to the substrate. Figure 23 is a three-dimensional schematic diagram of the semiconductor device after obtaining the stacked structure in one embodiment. Figure 24 is a top view of the semiconductor device shown in Figure 23. Figure 25 is a cross-sectional view of the semiconductor device shown in Figure 23 along the AA direction perpendicular to the substrate. Figure 26 is a cross-sectional view of the semiconductor device shown in Figure 23 along the BB direction in a direction perpendicular to the substrate; Figure 27 is a three-dimensional view of the semiconductor device after the isolation structure is formed in one embodiment; Figure 28 is a top view of the semiconductor device shown in Figure 27; Figure 29 is a cross-sectional view of the semiconductor device shown in Figure 27 along the AA direction in a direction perpendicular to the substrate; Figure 30 is a cross-sectional view of the semiconductor device shown in Figure 27 along the BB direction in a direction perpendicular to the substrate; exemplarily, the X direction can be the first direction perpendicular to the substrate shown in Figure 2, the Y direction can be the second direction in the plane parallel to the substrate 102 shown in Figure 2, and the Z direction can be the third direction in the plane parallel to the substrate 102 shown in Figure 2.

[0132] As shown in Figures 2-30, in one embodiment, providing the substrate 102 with the layered structure includes steps S202-S214.

[0133] S202, a substrate 102 having an initial stacked structure 104 is provided, the initial stacked structure 104 including a sacrificial layer 202 and an insulating layer 204 alternately stacked in the first direction X.

[0134] Specifically, a substrate 102 is provided, and an initial stacked structure 104 is formed on the substrate 102 using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. The initial stacked structure 104 includes a sacrificial layer 202 and an insulating layer 204 alternately stacked in a first direction X. The bottom of the initial stacked structure 104 near the substrate 102 can be either a sacrificial layer 202 or an insulating layer 204, and the top of the initial stacked structure 104 away from the substrate 102 can also be either a sacrificial layer 202 or an insulating layer 204. The following example uses the bottom of the initial stacked structure 104 as the insulating layer 204 and the top as the sacrificial layer 202 for illustration.

[0135] In some embodiments, the sacrificial layer 202 is composed of one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), carbide (silicon carbide), and silicide (germanium silicon). The insulating layer 204 is composed of one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (e.g., silicon oxynitride), and nitride (e.g., silicon nitride). For example, the sacrificial layer 202 is composed of silicon nitride, and the insulating layer 204 is composed of silicon dioxide.

[0136] S204, etch the initial stacked structure 104 to form a stacked main branch 302 extending along a second direction Y in a plane parallel to the substrate 102, a plurality of stacked branches 304 spaced apart in the second direction Y and connected to the stacked main branch 302, and a stacked connecting branch 306 located at one end of the stacked main branch 302 and connected to the stacked main branch 302 in the second direction Y. The stacked branches 304 and the stacked connecting branch 306 both extend along a third direction Z in a plane parallel to the substrate 102, and the third direction Z intersects the second direction Y.

[0137] Specifically, a dry etching process is used to pattern the initial stacked structure 104, and the initial stacked structure 104 outside the active region is etched away to form a stacked main branch 302 extending along the second direction Y, a plurality of stacked branches 304 connected to the stacked main branch 302 and spaced apart in the second direction Y, and a stacked connecting branch 306 located at one end of the stacked main branch 302 and connected to the stacked main branch 302 in the second direction Y; furthermore, in the third direction Z, the stacked branches 304 are located on opposite sides of the stacked main branch 302. The stacked connecting branch 306 and the stacked branch 304 are spaced apart. Both the stacked branch 304 and the stacked connecting branch 306 extend along the third direction Z. In the second direction Y, there is a first gap 402 between the stacked branch 304 and the adjacent stacked branch 304, and between the stacked branch 304 and the stacked connecting branch 306. In the third direction Z, the end of the stacked connecting branch 306 has a first gap 402. In the third direction Z, the side of the stacked branch 304 away from the stacked main branch 302 has a second gap 404 extending along the second direction Y. The second gap 404 and the first gap 402 are connected. Furthermore, the third direction Z intersects with the second direction Y, and furthermore, the third direction Z and the second direction Y are perpendicular.

[0138] S206, a support structure 106 extending along the second direction Y is formed on the substrate 102. The support structure 106 is located on the side of the stacked branch 304 away from the stacked main branch 302 and is adjacent to the stacked branch.

[0139] Specifically, a support structure 106 is formed in the second gap 304 on the substrate 102. The support structure 106 is adjacent to the stacked branch 304 and spaced apart from the stacked connecting branch 306. In the subsequent process of replacing the sacrificial layer 202 in the stacked main branch 302, stacked branch 304 and stacked connecting branch 306 with a conductive layer, the support structure 106 serves to support the insulating layer 204 and prevent the insulating layer 204 from collapsing.

[0140] In some embodiments, the supporting structure 106 is made of one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). Further, the supporting structure 106 is made of a material with a low dielectric constant.

[0141] S208, forming a first preset hole 406 that penetrates the stacked branch 304 in the first direction X and a second preset hole 408 that penetrates the stacked connecting branch 306.

[0142] As shown in Figures 11-14, the initial stacked structure 104 is etched to form a first preset hole 406 and a second preset hole 408 that penetrate the initial stacked structure 104 in the first direction X. The first preset hole 406 is located in the initial stacked structure 104 corresponding to the stacked branch 304, and the second preset hole 408 is located in the initial stacked structure 104 corresponding to the stacked connecting branch 306.

[0143] S210, fill the first preset hole 406 and the second preset hole 408 with sacrificial material 410.

[0144] Specifically, a chemical vapor deposition process, a physical vapor deposition process, or an atomic deposition process is used to fill the first preset hole 406 and the second preset hole 408 with a sacrificial material 410, and the sacrificial material 410 fills the first preset hole 406 and the second preset hole 408 completely.

[0145] In some embodiments, the sacrificial material 410 includes one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). Exemplarily, the sacrificial material 410 and the insulating layer 204 are made of the same material, silicon dioxide.

[0146] S212, replace the sacrificial layer 202 in the stacked main branch 302, the stacked branch 304 and the stacked connecting branch 306 with the conductive layer 206 to obtain the stacked structure 108.

[0147] As shown in Figures 19-26, specifically, firstly, the sacrificial layer 202 in the initial stacked structure 104 (stacked main branch 302, stacked branch 304, and stacked connecting branch 306) is removed by transverse etching along a direction parallel to the substrate 102 based on the first gap 402, forming a transverse groove 412 communicating with the first gap 402. Secondly, conductive material is filled into the first gap 402 and the transverse groove 412 using chemical vapor deposition, physical vapor deposition, or atomic deposition processes, filling the transverse groove 412 completely. Thirdly, the conductive material in the first gap 402 is removed by etching, forming a conductive layer 206 composed of the conductive material in the transverse groove 412. The conductive layer 206 and the insulating layer 204 constitute a stacked structure 108 located on the substrate 102. The conductive layer 206 in the main branch 302 of the stack serves as a bit line, the conductive layer 206 in the branch 304 of the stack serves as a conductive branch, and the conductive layer 206 in the connecting branch 306 of the stack includes a first part connected to the bit line and a second part spaced apart from the bit line, the second part being adjacent to the common bit line.

[0148] In some embodiments, the conductive layer 206 is composed of one or more of conductive polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal includes tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). Exemplarily, the conductive layer 206 is composed of conductive polycrystalline silicon and / or metal.

[0149] S214, forming an isolation structure 110 within the interval between adjacent support structures 106.

[0150] As shown in Figures 27-30, specifically, chemical vapor deposition, physical vapor deposition, or atomic deposition processes are used to form an isolation structure 110 between adjacent support structures 106 (in the first gap 402), and the isolation structure 110 fills the first gap 402. In the second direction Y, the isolation structure 110 is located between adjacent stacked structures 108 (stacked branches 304).

[0151] In some embodiments, the insulating structure 110 is made of one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride). For example, the insulating structure 110 is made of silicon dioxide.

[0152] In some embodiments, the sacrificial material 410 in the first preset hole 406 and / or the second preset hole 408 is etched away to obtain the first etched hole.

[0153] Figure 31 is a perspective view of the semiconductor device after the signal line is formed in one embodiment; Figure 32 is a top view of the semiconductor device shown in Figure 31; Figure 33 is a cross-sectional view of the semiconductor device shown in Figure 31 along the AA direction in a direction perpendicular to the substrate; Figure 34 is a cross-sectional view of the semiconductor device shown in Figure 31 along the BB direction in a direction perpendicular to the substrate; Figure 35 is a perspective view of the semiconductor device after the semiconductor layer is formed in one embodiment; Figure 36 is a top view of the semiconductor device shown in Figure 35; Figure 37 is a cross-sectional view of the semiconductor device shown in Figure 35 along the AA direction in a direction perpendicular to the substrate; Figure 38 is a cross-sectional view of the semiconductor device shown in Figure 35 along the BB direction in a direction perpendicular to the substrate. As shown in Figures 31-38, in one embodiment, a semiconductor layer, a van der Waals dielectric layer, and a gate dielectric layer are sequentially formed on the sidewall of the conductive layer exposed by the first etched hole, including steps S302-S308.

[0154] S302, a semiconductor material layer, a van der Waals dielectric layer and a gate dielectric layer are sequentially formed on the sidewall of the first etched hole.

[0155] As shown in Figures 31-34, the sacrificial material 410 in the first preset hole 406 and the second preset hole 408 is removed by etching to obtain the first etched hole. For example, chemical vapor deposition, physical vapor deposition or atomic deposition is used to sequentially form a semiconductor material layer 112, a van der Waals dielectric layer 114 and a gate dielectric layer 116 on the sidewall of the first etched hole. Then, a signal line 118 in contact with the gate dielectric layer 116 is formed in the first etched hole, and the signal line 118 fills the first etched hole.

[0156] S304, a first trench 414 is formed in the first direction X through the stacked structure 108. The first trench 414 is located on opposite sides of the first etched hole and is spaced apart from the first etched hole. The first trench 414 extends along a third direction Z in a plane parallel to the substrate 102.

[0157] As shown in Figures 35-38, specifically, a first trench 414 is formed on both sides of the first etched hole, and a stacked structure 108 is formed between the first trench 414 and the adjacent first etched hole; to obtain the first etched hole by removing the sacrificial material 410 in the first preset hole 406, the isolation structure 110 between the adjacent stacked branches 304 is etched away to form the first trench 414. In the second direction Y, the first trench 414 is located on both sides of the first etched hole; to obtain the first etched hole by removing the sacrificial material 410 in the second preset hole 408, the isolation structure 110 located on both sides of the stacked branch 306 in the third direction Z is etched away to form the first trench 414. In the third direction Z, the first trench 414 is located on both sides of the first etched hole. Furthermore, the isolation structure 110 filling the spaces between the support structures 106 is removed to obtain the first trench 414, the sidewalls of which expose the insulating layer 204 in the laminated structure 108 (laminated main support 302, laminated branch 304, and laminated connecting support 306). Further, the isolation structure 110 filling the first gap 402 is removed to obtain the first trench 414.

[0158] S306, based on the first trench 414, each layer of the insulating layer 204 is etched away in a direction parallel to the substrate 102 to form a first transverse filling trench 416.

[0159] As shown in Figures 35-38, specifically, based on the first trench 414, each insulating layer 204 in the stacked structure 108 is removed by transverse etching along the direction parallel to the substrate 102 (the plane where the second direction Y and the third direction Z are located), forming a first transverse filling trench 416 connected to the first trench 414. At this time, the bottom of the first transverse filling trench 416 exposes the sidewall of the semiconductor material layer 112 corresponding to each insulating layer 204, and completely surrounds the semiconductor material layer 112.

[0160] S308, the semiconductor material layer 112 exposed by the first transverse filling trench 416 is removed to obtain the semiconductor layer 120 composed of the remaining semiconductor material layer 112.

[0161] As shown in Figures 35-38, the semiconductor material layer 112 exposed at the bottom of the first lateral filling trench 416 is etched down to the van der Waals dielectric layer 114, such that the semiconductor layer 120 composed of the remaining semiconductor material layer 112 corresponds to the conductive layer 206 in a direction parallel to the substrate 102 and is spaced apart in the first direction X.

[0162] In some embodiments, after removing the semiconductor layer 120 formed by the remaining semiconductor material layer 112, the process further includes removing the van der Waals dielectric layer 114 exposed by the first lateral fill trench 416. In this case, the sidewalls of the van der Waals dielectric layer 114 away from the gate dielectric layer 116 are adjacent to the semiconductor layer 120.

[0163] In some embodiments, the constituent material of the semiconductor layer 120 includes one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, I Materials such as WO3, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0164] These materials have a wide bandgap and low leakage current. For example, when semiconductor layer 120 is IGZO, the transistor leakage current is small, which can improve the performance of dynamic memory.

[0165] The material of the aforementioned semiconductor layer 120 only emphasizes the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0166] In some embodiments, the van der Waals dielectric layer 114 is composed of hexagonal boron nitride (h-BN) and / or antimony trioxide (Sb2O3).

[0167] In some embodiments, the gate dielectric layer 116 is made of a high dielectric constant material, which can reduce parasitic capacitance. High dielectric constant materials include hafnium oxide, hafnium silicon oxide, hafnium oxysilicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide. In preferred embodiments, hafnium oxide, zirconium oxide, and aluminum oxide are used.

[0168] In some embodiments, the signal line 118 is made of one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2) and indium tin oxide (ITO); and the metal silicide includes titanium silicide (TiSi). For example, the signal line 118 is made of indium tin oxide (ITO).

[0169] Figure 39 is a perspective view of the semiconductor device after filling with the first insulating material in one embodiment; Figure 40 is a top view of the semiconductor device shown in Figure 39; Figure 41 is a cross-sectional view of the semiconductor device shown in Figure 39 along the AA direction in a direction perpendicular to the substrate; Figure 42 is a cross-sectional view of the semiconductor device shown in Figure 39 along the BB direction in a direction perpendicular to the substrate in one embodiment; Figure 43 is a perspective view of the semiconductor device after forming the second transverse filling groove in one embodiment; Figure 44 is a top view of the semiconductor device shown in Figure 43; Figure 45 is a cross-sectional view of the semiconductor device shown in Figure 43 along the AA direction in a direction perpendicular to the substrate in one embodiment; Figure 46 is a cross-sectional view of the semiconductor device shown in Figure 43 along the BB direction in a direction perpendicular to the substrate in one embodiment; Figure 47 is a perspective view of the semiconductor device after filling with the second insulating material in one embodiment; Figure 48 is a top view of the semiconductor device shown in Figure 47; Figure 49 is a cross-sectional view of the semiconductor device shown in Figure 47 along the AA direction in a direction perpendicular to the substrate in one embodiment; Figure 50 is a cross-sectional view of the semiconductor device shown in Figure 47 along the BB direction in a direction perpendicular to the substrate in one embodiment. As shown in Figures 39-50, in one embodiment, the method for fabricating a semiconductor device further includes steps S402-S408.

[0170] S402, fill the first insulating material 308 into the first trench 414 and the first transverse filling groove 416.

[0171] S404, forming a second etched hole 418 penetrating the first insulating material 308, the second etched hole 418 being located on opposite sides of the first etched hole.

[0172] As shown in Figures 43-46, etching removes the first insulating material 308 on both sides of the first etched hole, forming a second etched hole 418 penetrating the first insulating material 308 in the first direction X. For the first etched hole in the stacked branch 304, the second etched hole 418 is located on both sides of the first etched hole in the second direction Y. For the first etched hole in the stacked link 306, the second etched hole 418 is located on both sides of the first etched hole in the third direction Z. The second etched hole 418 and the first etched hole are separated by the stacked structure 108.

[0173] Furthermore, in a plane parallel to the substrate 102, the length of the second etched hole 418 is less than or equal to the length of the first etched hole, and the direction of the length is perpendicular to the line connecting the two second etched holes 418 on opposite sides of the first etched hole; that is, for the first etched hole in the stacked branch 304, the length direction is the third direction Z, and in the third direction Z, the length of the second etched hole 418 is less than or equal to the length of the first etched hole; for the first etched hole in the stacked link 306, the length direction is the second direction Y, and in the second direction Y, the length of the second etched hole 418 is less than or equal to the length of the first etched hole.

[0174] S406, based on the second etch hole 418, the conductive layer 206 between the first etch hole and the second etch hole 418 is etched in a direction parallel to the substrate 102 until the semiconductor layer 120 is exposed, forming a second lateral filling groove 420.

[0175] As shown in Figures 43-46, the conductive layer 206 between the first and second etched holes 418 is removed by lateral etching based on the second etched hole 418 until the semiconductor layer 120 is exposed, forming a second lateral filling trench 420 connected to the second etched hole 418. By etching away the conductive layer 206 between the first and second etched holes 418, the conductive layer 206 surrounding the first etched hole is broken in the region where it intersects with the line connecting the first and second etched holes 418. For the first etched hole in the stacked branch 304, the conductive layer 206 (conductive branch) in the stacked branch 304 is divided into a bit line connection portion and a capacitor connection portion spaced along the third direction Z. The bit line connection portion is connected to the conductive layer 206 (bit line) in the stacked main branch 302 (integrated molding) and can be used as part of the bit line. The capacitor connection portion is subsequently connected to the electrode of the capacitor. By controlling the conduction and turn-off of the storage transistor in the first etched hole, the connection and disconnection of the bit line connection portion and the capacitor connection portion can be controlled. For the first etched hole in the stacked connecting branch 306, the conductive layer 206 in the stacked connecting branch 306 is divided into a first part and a second part spaced along the second direction Y. The first part is connected to the conductive layer 206 (bit line) in the stacked main branch 302 (integrated molding) and can be used as part of the bit line. The second part is connected to the common bit line and can be used as part of the common bit line. By controlling the conduction and turn-off of the bit line selection transistor in the first etched hole, the connection and disconnection of the first part and the second part can be controlled.

[0176] S408, fill the second etched hole 418 and the second transverse filling groove 420 with the second insulating material 310.

[0177] As shown in Figures 47-50, a second insulating material 310 is filled into the second etched hole 418 and the second lateral filling groove 420 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes. The second insulating material 310 completely fills the second etched hole 418 and the second lateral filling groove 420.

[0178] In some embodiments, the constituent materials of the first insulating material 308 and the second insulating material 310 include one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (e.g., silicon oxynitride), and nitride (e.g., silicon nitride). For example, both the constituent materials of the first insulating material 308 and the second insulating material 310 are silicon dioxide.

[0179] Figure 51 is a three-dimensional schematic diagram of a semiconductor device after a capacitor is formed in one embodiment. As shown in Figure 51, in one embodiment, the method for fabricating the semiconductor device further includes: forming a capacitor at the end of the conductive branch that is away from the bit line in the third direction Z; wherein, the portion of the conductive branch located on the side of the semiconductor layer 120 away from the bit line (capacitor connection portion) constitutes the first electrode of the capacitor, and the first electrode is adjacent to the semiconductor layer 120.

[0180] It should be understood that although the steps in the flowchart of Figure 1 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0181] This disclosure provides a semiconductor device. The parts that are the same as or corresponding to those in the embodiments described above regarding the fabrication method of the semiconductor device will not be repeated below. As shown in Figures 47-51, in this embodiment, the semiconductor device includes: a signal line 118 and a memory cell layer; the signal line 118 extends along a first direction X perpendicular to the substrate 102; the memory cell layer is parallel to the substrate 102, and the memory cell layer includes transistors 124, with the signal line 118 penetrating each transistor 124 in the first direction X; the transistor 124 includes: a gate dielectric layer 116, a van der Waals dielectric layer 114, and a semiconductor layer 120; the gate dielectric layer 116 surrounds the sidewall of the signal line 118 in a plane parallel to the substrate 102; the semiconductor layer 120 surrounds the sidewall of the signal line 118 and is located on the side of the gate dielectric layer 116 away from the signal line 118; the van der Waals dielectric layer 114 surrounds the sidewall of the signal line 118 and is located between the semiconductor layer 120 and the gate dielectric layer 116, and is adjacent to the gate dielectric layer 116. Furthermore, the side of the gate dielectric layer 116 closest to the signal line 118 is in contact with the signal line 118.

[0182] In the aforementioned semiconductor device, a van der Waals dielectric layer 114 is disposed between the gate dielectric layer 116 and the semiconductor layer 120 of the transistor 124. This reduces the defect state density present on the surface of the gate dielectric layer 116 near the semiconductor layer 120, improves the electron mobility of the semiconductor device, increases the stability of the semiconductor device, and improves the performance of the semiconductor device.

[0183] In one embodiment, the van der Waals dielectric layer 114 completely surrounds the sidewall of the signal line 118; wherein each of the transistors 124 through which the signal line 118 passes shares the van der Waals dielectric layer 114.

[0184] In one embodiment, the gate dielectric layer 116 is made of a high dielectric constant gate dielectric material, and the van der Waals dielectric layer 114 is made of a van der Waals high dielectric constant dielectric material.

[0185] In one embodiment, the gate dielectric layer 116, the semiconductor layer 120, and the van der Waals dielectric layer 114 all surround the sidewalls of the signal line in a plane parallel to the substrate 102.

[0186] In one embodiment, the semiconductor layer 120 includes a first source / drain region and a second source / drain region spaced apart in a plane parallel to the substrate 102, and a channel region connecting the first source / drain region and the second source / drain region. A van der Waals dielectric layer 114 is located between the gate dielectric layer 116 and the channel region. The opposing surfaces of the van der Waals dielectric layer 114 are adjacent to the channel region and the gate dielectric layer 116, respectively. One of the first source / drain region and the second source / drain region serves as the source, and the other as the drain. The van der Waals dielectric layer 114 can improve the stability of charge transport in the channel region and increase electron mobility. Furthermore, each transistor 124 through which the signal line 118 passes shares the van der Waals dielectric layer 114.

[0187] In one embodiment, the van der Waals dielectric layers 114 are spaced apart in the first direction, and the surfaces of the semiconductor layers 120 near the signal lines 118 are all adjacent to the surfaces of the van der Waals dielectric layers 114 away from the signal lines 118. That is, the van der Waals dielectric layers 114 are correspondingly disposed with respect to the transistors. Furthermore, the van der Waals dielectric layers 114 completely surround the sidewalls of the signal lines 118 corresponding to the transistors.

[0188] In one embodiment, a plurality of memory cell layers are stacked in the first direction X, the van der Waals dielectric layer 114 extends along the first direction X, and each of the transistors 124 stacked in the first direction X shares the van der Waals dielectric layer 114.

[0189] As shown in Figure 51, in one embodiment, the signal line 118 includes a word line, the transistor 124 includes a storage transistor, and the storage cell layer further includes a bit line 126 and a capacitor 122; the capacitor 122 is spaced apart from the bit line 126; wherein, the semiconductor layer 120 of the storage transistor is adjacent to the bit line 126 and the capacitor 122 respectively, and the reading and storage of data are controlled by turning the storage transistor on and off, thereby improving the stability and reliability of data and storage.

[0190] In one embodiment, the memory transistor arrays in the memory cell layer are arranged; the bit line 126 extends along a second direction Y in a plane parallel to the substrate 102 and is spaced along a third direction Z in a plane parallel to the substrate 102, the third direction Z intersecting the second direction Y; the memory transistors located on opposite sides of the bit line 126 on the third direction Z share the bit line 126, which can improve the integration of the semiconductor device and reduce the size of the semiconductor device.

[0191] As shown in Figure 51, in one embodiment, the signal line 126 includes a bit line select signal line, the transistor 124 includes a bit line select transistor, and the memory cell layer further includes: bit line 126 and a common bit line 128; the bit line 126 extends along a second direction Y in a plane parallel to the substrate 102; the common bit line 128 is spaced apart from the bit line 126 and extends along a third direction Z in a plane parallel to the substrate 102, the third direction Z intersects the second direction Y; wherein, the semiconductor layer 120 of the bit line select transistor is adjacent to the common bit line 128 and the bit line 126 respectively, and the transmission of data between the bit line 126 and the common bit line 128 is controlled by turning the bit line select transistor on and off, thereby improving the stability and reliability of data transmission.

[0192] In one embodiment, the bit line 126 and the bit line selection transistor are both arranged at a Z-interval in the third direction. The semiconductor layer 120 of each bit line selection transistor is adjacent to each bit line 126, and the semiconductor layer 120 of each bit line selection transistor is adjacent to the common bit line 128. By turning the bit line selection transistor on and off, the bit line 126 connected to the common bit line 128 can be selected.

[0193] This disclosure also provides an electronic device, including any of the semiconductor devices described above. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the described electronic device.

[0194] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0195] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate formed with a stack structure, the stack structure comprising conductive layers and insulating layers alternately stacked in a first direction perpendicular to the substrate; etching the stack structure to form a first etching hole extending in the first direction, the first etching hole penetrating at least the conductive layers of the stack structure close to the substrate; sequentially forming a semiconductor layer, a van der Waals medium layer and a gate medium layer on sidewalls of the conductive layers exposed by the first etching hole, the semiconductor layer being arranged in intervals in the first direction; forming a signal line in the first etching hole, the signal line being in contact with the gate medium layer; wherein the sequentially forming a semiconductor layer, a van der Waals medium layer and a gate medium layer on sidewalls of the conductive layers exposed by the first etching hole comprises: sequentially forming a semiconductor material layer, a van der Waals medium layer and a gate medium layer on sidewalls of the first etching hole; forming a first trench penetrating the stack structure in the first direction, the first trench being located on opposite sides of the first etching hole and arranged in intervals with the first etching hole, the first trench extending in a third direction parallel to a plane of the substrate; etching and removing each of the insulating layers based on the first trench in a direction parallel to the substrate to form a first lateral filling groove; removing the semiconductor material layer exposed by the first lateral filling groove to obtain the semiconductor layer composed of the remaining semiconductor material layer; the method further comprising: filling a first insulating material in the first trench and the first lateral filling groove; forming a second etching hole penetrating the first insulating material, the second etching hole being located on opposite sides of the first etching hole; etching the conductive layer between the first etching hole and the second etching hole based on the second etching hole in a direction parallel to the substrate until the semiconductor layer is exposed to form a second lateral filling groove; and filling a second insulating material in the second etching hole and the second lateral filling groove. 2.The method according to claim 1, wherein the providing a substrate formed with a stack structure comprises: providing a substrate formed with an initial stack structure, the initial stack structure comprising sacrificial layers and insulating layers alternately stacked in the first direction; etching the initial stack structure to form a stack main branch extending in a second direction parallel to a plane of the substrate, a plurality of stack branches arranged in intervals in the second direction and connected with the stack main branch, and a stack connecting branch located at one end of the stack main branch in the second direction and connected with the stack main branch, the stack branches and the stack connecting branch extending in a third direction parallel to the plane of the substrate, the third direction intersecting with the second direction; forming a support structure extending in the second direction on the substrate, the support structure being located on a side of the stack branches away from the stack main branch and adjacent to the stack branches; forming a first preset hole penetrating the stack branches in the first direction and a second preset hole penetrating the stack connecting branch. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ filling a sacrificial material in the first and second pre-set holes; replacing the sacrificial layers in the main branch, the branch and the connecting branch of the stack structure with the conductive layers to obtain a stack structure; and forming an isolation structure in a space between adjacent support structures; wherein the first etching hole is obtained by etching and removing the sacrificial material in the first and / or second pre-set holes, the conductive layer in the main branch of the stack structure is a bit line, the conductive layer in the branch of the stack structure is a conductive branch, the conductive layer in the connecting branch of the stack structure includes a first part connected to the bit line and a second part spaced from the bit line, and the second part is adjacent to a common bit line.

3. The method of claim 2, further comprising: forming a capacitor at an end of the conductive branch away from the bit line in the third direction; wherein the part of the conductive branch on the side of the semiconductor layer away from the bit line constitutes a first electrode of the capacitor, and the first electrode is adjacent to the semiconductor layer.

4. A semiconductor device manufactured by the method of any one of claims 1-3, comprising: a signal line extending in a first direction perpendicular to a substrate; a memory cell layer parallel to the substrate, the memory cell layer comprising transistors, the signal line penetrating each transistor; the transistor comprising: a gate dielectric layer surrounding a sidewall of the signal line; a semiconductor layer surrounding the sidewall of the signal line on a side of the gate dielectric layer away from the signal line; and a van der Waals dielectric layer surrounding the sidewall of the signal line between the semiconductor layer and the gate dielectric layer and adjacent to the gate dielectric layer.

5. The semiconductor device of claim 4, wherein the van der Waals dielectric layer fully surrounds the sidewall of the signal line; wherein each transistor penetrated by the signal line shares the van der Waals dielectric layer.

6. The semiconductor device of claim 4, wherein the material of the van der Waals dielectric layer comprises hexagonal boron nitride and / or antimony trioxide.

7. The semiconductor device of claim 4, wherein the gate dielectric layer, the semiconductor layer and the van der Waals dielectric layer all fully surround the sidewall of the signal line.

8. The semiconductor device of claim 4, wherein the van der Waals dielectric layers are spaced apart in the first direction, and the surface of the semiconductor layer close to the signal line is adjacent to the surface of the van der Waals dielectric layer away from the signal line.

9. The semiconductor device of claim 4, wherein a plurality of memory cell layers are stacked in the first direction, and the van der Waals dielectric layer extends in the first direction, each transistor stacked in the first direction sharing the van der Waals dielectric layer.

10. The semiconductor device of claim 4, wherein the signal line comprises a word line, the transistor comprises a memory transistor, and the memory cell layer further comprises: a bit line; and a capacitor spaced apart from the bit line; wherein the semiconductor layer of the memory transistor is adjacent to the bit line and the capacitor, respectively.

11. The semiconductor device according to claim 10, wherein each of the memory transistor arrays is arranged in the memory cell layer; the bit lines extend in a second direction parallel to a plane of the substrate, and are arranged at intervals in a third direction parallel to the plane of the substrate, the third direction intersecting the second direction.

12. The semiconductor device according to claim 4, wherein the signal line comprises a bit line selection signal line, the transistor comprises a bit line selection transistor, the memory cell layer further comprises: a bit line extending in a second direction parallel to a plane of the substrate; and a common bit line disposed at intervals from the bit line, extending in a third direction parallel to the plane of the substrate, the third direction intersecting the second direction; wherein the semiconductor layer of the bit line selection transistor is contiguous to the common bit line and the bit line, respectively.

13. The semiconductor device according to claim 12, wherein the bit lines and the bit line selection transistors are arranged at intervals in the third direction, the semiconductor layer of each of the bit line selection transistors is contiguous to the bit line and the common bit line, respectively, in correspondence.

14. An electronic device comprising a semiconductor device selected from the group consisting of the semiconductor device according to any one of claims 4 to 13 and the semiconductor device produced by the production method according to any one of claims 1 to 3. ​ ​ ​ ​

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