Germanium-based spads sensor based on silicon-germanium multi-avalanche layer and preparation method therefor

Abstract

The present application relates to the technical field of semiconductors, and discloses a germanium-based SPADs sensor based on a silicon-germanium multi-avalanche layer and a preparation method therefor. The sensor comprises: a readout circuit, an N-type electrode, a P-type electrode, a passivation layer, and a planar sensor wafer. The planar sensor wafer comprises an N-type heavily-doped Si layer, a silicon-germanium multi-avalanche layer, a P-type charge layer, a sensing layer, and a P-type heavily-doped germanium layer which are sequentially stacked, as well as a plurality of grooves distributed at a second preset interval. The passivation layer covers the P-type heavily-doped germanium layer and the inner walls of the grooves. The P-type electrode is connected to the P-type heavily-doped germanium layer. The N-type electrode is arranged within a second groove and is connected to the N-type heavily-doped Si layer. The readout circuit is separately connected to the N-type electrode and the P-type electrode. The present application can reduce device operating voltage, dark current, and device dark count rates, and improve avalanche gain.

Description

A germanium-based SPAD sensor based on silicon-germanium multi-avalanche layers and its fabrication method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a germanium-based SPAD sensor based on silicon-germanium multi-avalanche layers and its fabrication method. Background Technology

[0002] Compared to III-V group semiconductor materials, germanium (Ge)-based materials have significant advantages such as silicon-based epitaxy (large size, 8 inches, or even 12 inches), high compatibility with CMOS process lines, and excellent photoelectric response in the short-wave infrared band. They are considered one of the important technical solutions for the large-scale mass production of short-wave infrared SPADs sensors. However, all known germanium SPADs sensors are directly formed on silicon substrates, using germanium as the short-wave infrared sensing layer and silicon as the avalanche layer (the germanium-silicon interface has significant lattice mismatch defects), as shown in "CN201980067264.X-Single-photon avalanche detector, its usage method and its manufacturing method." This results in poor performance indicators for germanium SPADs sensors, such as dark count rates (DCRs), single-photon detection efficiency, response speed, avalanche noise, and operating voltage.

[0003] Summary of the Invention

[0004] This application provides a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layers and its fabrication method, which can reduce the device's operating voltage, dark current, and dark count rate, and improve avalanche gain.

[0005] In a first aspect, this application provides a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layers, comprising:

[0006] Readout circuitry, N-type electrode, P-type electrode, passivation layer, and planar sensor wafer;

[0007] The planar sensor wafer includes an N-type heavily doped Si layer, a silicon-germanium multi-avalanche layer, a P-type charge layer, a sensing layer, and a P-type heavily doped germanium layer stacked sequentially; the P-type charge layer includes multiple P-type charge sub-layers of equal length, and each P-type charge sub-layer is uniformly embedded on the silicon-germanium multi-avalanche layer at a first preset interval.

[0008] The planar sensor wafer also includes multiple grooves distributed at a second preset interval;

[0009] The groove is located between two adjacent P-type charge sublayers and includes a first groove and a second groove;

[0010] The first groove sequentially penetrates the P-type heavily doped germanium layer, the sensing layer, and the silicon-germanium multi-avalanche layer;

[0011] The second groove extends through the silicon-germanium multi-avalanche layer and the N-type heavily doped Si layer based on the first groove; the length of the first groove is greater than the length of the second groove, but less than the first preset interval;

[0012] A passivation layer covers the p-type heavily doped germanium layer and the inner walls of each groove;

[0013] The P-type electrode is connected to the P-type heavily doped germanium layer; the N-type electrode is located in the second groove and is connected to the N-type heavily doped Si layer; the readout circuit is connected to the N-type electrode and the P-type electrode respectively.

[0014] Furthermore, the planar sensor wafer also includes a reflective layer, which is superimposed on an N-type heavily doped Si layer.

[0015] Furthermore, the sensing layer includes a germanium quantum well sensing layer and a germanium sensing layer, with the germanium sensing layer superimposed on the germanium quantum well sensing layer.

[0016] Furthermore, the planar sensor wafer also includes a substrate, which is superimposed on the reflective layer.

[0017] Furthermore, the reflective layer is made of monocrystalline silicon, amorphous silicon, or silicon oxide;

[0018] The reflective layer has a periodic structure with 1-6 periods.

[0019] Furthermore, the total thickness of the silicon-germanium multi-avalanche layer ranges from 0.1 to 3 micrometers, the number of cycles ranges from 60 to 400, the total thickness of a single cycle ranges from 8 to 40 nanometers, the thickness of the barrier layer ranges from 3 to 10 nanometers, and the thickness of the potential well layer ranges from 5 to 30 nanometers.

[0020] Furthermore, the total thickness of the germanium quantum well sensing layer ranges from 0.1 to 3 micrometers, the number of periods ranges from 10 to 300, the thickness of a single period is greater than or equal to 15 nanometers, the thickness of the barrier layer is greater than or equal to 10 nanometers, and the thickness of the potential well layer ranges from 5 to 30 nanometers.

[0021] Furthermore, the germanium content in silicon-germanium multi-avalanche layers ranges from 0% to 30%.

[0022] Furthermore, the germanium content in the germanium sensing layer or germanium quantum well sensing layer ranges from 0% to 30%.

[0023] Secondly, this application also provides a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layers, comprising:

[0024] Readout circuitry, N-type electrode, P-type electrode, passivation layer, and mesa sensor wafer;

[0025] The mesa sensor wafer includes an N-type heavily doped Si layer, a silicon-germanium multi-avalanche layer, a P-type charge layer, a sensing layer and a P-type heavily doped germanium layer stacked sequentially, as well as a plurality of grooves of equal length and distributed at a second preset interval.

[0026] The grooves sequentially penetrate the P-type heavily doped germanium layer, the sensing layer, the P-type charge layer, the silicon-germanium multi-avalanche layer, and the N-type heavily doped Si layer;

[0027] A passivation layer covers the p-type heavily doped germanium layer and the inner walls of each groove;

[0028] The P-type electrode is connected to the P-type heavily doped germanium layer; the N-type electrode is located in the groove and connected to the N-type heavily doped Si layer; the readout circuit is connected to the N-type electrode and the P-type electrode respectively.

[0029] Furthermore, the mesa sensor wafer also includes a reflective layer, which is superimposed on an N-type heavily doped Si layer.

[0030] Thirdly, this application provides a method for fabricating a germanium-based SPADs sensor based on a silicon-germanium multi-avalanche layer, comprising:

[0031] A substrate is provided, and a Si layer and an oxide layer are sequentially stacked on the substrate;

[0032] Ion implantation is performed into the Si layer to form an N-type heavily doped Si layer;

[0033] After removing the oxide layer, silicon-germanium multi-avalanche layers are sequentially stacked on the N-type heavily doped Si layer;

[0034] Each P-type charge layer of equal length is uniformly embedded on the silicon-germanium multi-avalanche layer at a first preset interval;

[0035] A sensing layer and a p-type heavily doped germanium layer are sequentially stacked on a silicon-germanium multi-avalanche layer;

[0036] Multiple first grooves of equal length are provided at a second preset interval;

[0037] The first groove passes through the P-type heavily doped germanium layer, the sensing layer, and the silicon-germanium multi-avalanche layer in sequence; the first groove is located between two adjacent P-type charge carrier layers, and the length of the first groove is less than the first preset interval;

[0038] A passivation layer is formed on the p-type heavily doped germanium layer and the first groove;

[0039] A second groove is provided at the bottom of the first groove, and a passivation layer is formed on the surface of the second groove;

[0040] The second groove penetrates the silicon-germanium multi-avalanche layer and the N-type heavily doped Si layer, and its length is shorter than that of the first groove;

[0041] A P-type electrode is installed on a heavily doped germanium P-type layer, and an N-type electrode is installed on a heavily doped Si N-type layer at the bottom of the second groove. The readout circuit is then connected to the P-type electrode and the N-type electrode respectively, and the substrate is removed.

[0042] Furthermore, the preparation method also includes forming a reflective layer on the substrate before stacking the Si layer.

[0043] Fourthly, this application provides a method for fabricating a germanium-based SPADs sensor based on a silicon-germanium multi-avalanche layer, comprising:

[0044] A substrate is provided, and a Si layer and an oxide layer are sequentially stacked on the substrate;

[0045] Ion implantation is performed on the Si layer to form an N-type heavily doped Si layer; after removing the oxide layer, a silicon-germanium multi-avalanche layer, a P-type charge layer, a sensing layer, and a P-type heavily doped germanium layer are sequentially stacked on the N-type heavily doped Si layer.

[0046] Multiple grooves of equal length are set at a second preset interval; the grooves sequentially penetrate the P-type heavily doped germanium layer, the sensing layer, the silicon-germanium multi-avalanche layer and the N-type heavily doped Si layer;

[0047] A passivation layer is formed on the P-type heavily doped germanium layer and the inner wall of the groove;

[0048] A P-type electrode is installed on a heavily doped germanium P-type layer, and an N-type electrode is installed on a heavily doped Si N-type layer at the bottom of the trench. The readout circuit is then connected to the P-type electrode and the N-type electrode respectively, and the substrate is removed.

[0049] Furthermore, the preparation method also includes forming a reflective layer on the substrate before stacking the Si layer.

[0050] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0051] This application provides a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layers, which breaks through the theoretical limit of the intrinsic avalanche effect of silicon materials. By using a silicon-germanium multilayer structure as the avalanche region, the avalanche gain of the germanium SPADs device is significantly improved, the operating voltage of the device is greatly reduced, and the introduction of a large amount of excessive noise during device operation is avoided, thereby reducing avalanche noise and reducing the dark current and dark count rate of the device. Attached Figure Description

[0052] Figure 1 is a structural diagram of a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layers provided in an embodiment of this application.

[0053] Figure 2 is a structural diagram of a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layers provided in another embodiment of this application.

[0054] Figure 3 is a schematic diagram of a partial sensor wafer fabrication process provided in one embodiment of this application.

[0055] Figure 4 is a schematic diagram of the wafer fabrication process for planar and mesa sensors provided in one embodiment of this application.

[0056] Figure 5 is a schematic diagram of a planar sensor wafer provided in one embodiment of this application.

[0057] Figure 6 is a schematic diagram of a shallow platform structure formed by a first groove according to an embodiment of this application.

[0058] Figure 7 is a schematic diagram of the formation of a passivation layer according to an embodiment of this application.

[0059] Figure 8 is a schematic diagram of forming a P-type electrode according to an embodiment of this application.

[0060] Figure 9 is a schematic diagram of a deep rectangular groove formed by a second groove according to an embodiment of this application.

[0061] Figure 10 is a schematic diagram of the surface passivation treatment of the second groove provided in an embodiment of this application.

[0062] Figure 11 is a schematic diagram of forming an N-type electrode according to an embodiment of this application.

[0063] Figure 12 is a schematic diagram of a mezzanine sensor wafer provided in one embodiment of this application.

[0064] Figure 13 is a schematic diagram of an etched rectangular groove provided in one embodiment of this application.

[0065] Figure 14 is a schematic diagram of the formation of a surface passivation layer according to an embodiment of this application.

[0066] Figure 15 is a schematic diagram of forming an N-type electrode and a P-type electrode according to an embodiment of this application.

[0067] Explanation of reference numerals in the attached figures: 100, substrate; 101, reflective layer; 102, heavily doped N-type Si layer; 103, silicon-germanium multi-avalanche layer; 104, P-type charge layer; 105, germanium quantum well sensing layer; 106, germanium sensing layer; 107, heavily doped P-type germanium layer; 108, passivation layer; 201, N-type electrode; 202, P-type electrode; 203, readout circuit. Detailed Implementation

[0068] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0069] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] Single-photon avalanche photodetectors (SPADs) are highly sensitive devices capable of detecting the energy of a single photon. Based on their operating wavelength range, SPADs are classified into three categories: near-infrared (NIR, 0.78–1.1 μm), short-wave infrared (SWIR, 1.1–3 μm), mid-wave infrared (MWIR, 3–5 μm), and long-wave infrared (LWIR, 8–14 μm). Short-wave infrared SPAD sensors play a crucial role in many emerging applications, including optical communication, quantum information, ranging, coherent sensing, medical diagnostics, analytical instruments, lidar (LIDAR), life sciences, and beyond-line-of-sight imaging.

[0071] Although commercially available indium gallium arsenide (InGaAs) short-wave infrared SPADs sensors are widely used in applications such as lidar, optical communication, and quantum communication, they typically use small-sized and expensive indium phosphide (InP) wafers as substrates. The manufacturing process is costly, incompatible with standard CMOS production lines, limits the number of SPADs that can be formed on a single wafer, results in low yields, and is expensive per chip, hindering large-scale mass production. Therefore, finding a short-wave infrared sensing material compatible with CMOS manufacturing processes is of paramount importance.

[0072] Compared to III-V semiconductor materials, germanium (Ge)-based materials have significant advantages such as silicon-based epitaxy (large size, 8 inches, or even 12 inches), high compatibility with CMOS process production lines, and excellent photoelectric response in the short-wave infrared band. They are considered one of the important technical solutions for the mass production of short-wave infrared SPADs sensors. However, all known germanium SPADs sensors are directly formed on silicon substrates, using germanium as the short-wave infrared sensing layer and silicon as the avalanche layer (the germanium-silicon interface has a large lattice mismatch defect). This introduces a large amount of capacitance into the entire SPAD device structure, slowing down its response speed. Limited by the intrinsic avalanche characteristics of silicon, its avalanche gain cannot be further increased, causing germanium SPADs sensors to typically operate at a high reverse bias voltage (10-20V). When the operating voltage is too high, a large amount of excessive noise is introduced during avalanche (carrier collision ionization), and dark current (including but not limited to surface leakage current and tunneling current) is also increased. This results in poor performance of germanium SPADs sensors in terms of dark count rates (DCRs), single photon detection efficiencies (SPDEs), response speed, avalanche noise, sensitivity, avalanche gain, resolution, operating voltage, and reliability, which cannot meet commercial standards.

[0073] To address the aforementioned issues, please refer to Figure 1. This application provides a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layers, which may specifically include the following structure:

[0074] The readout circuit 203, N-type electrode 201, P-type electrode 202, passivation layer 108, and planar sensor wafer are included.

[0075] The planar sensor wafer includes an N-type heavily doped Si layer 102, a silicon-germanium multi-avalanche layer 103, a P-type charge layer 104, a sensing layer, and a P-type heavily doped germanium layer 107 stacked sequentially. The P-type charge layer 104 includes multiple P-type charge sub-layers of equal length, and each P-type charge sub-layer is uniformly embedded on the silicon-germanium multi-avalanche layer 103 at a first preset interval.

[0076] The planar sensor wafer also includes multiple grooves distributed at a second preset interval.

[0077] The grooves are located between two adjacent P-type charge layers and include a first groove and a second groove.

[0078] The first groove passes through the P-type heavily doped germanium layer 107, the sensing layer, and the silicon-germanium multi-avalanche layer 103 in sequence.

[0079] The second groove extends through the silicon-germanium multi-avalanche layer 103 and the N-type heavily doped Si layer 102 based on the first groove; the length of the first groove is greater than the length of the second groove and less than the first preset interval.

[0080] The passivation layer 108 covers the p-type heavily doped germanium layer 107 and the inner walls of each groove.

[0081] P-type electrode 202 is connected to P-type heavily doped germanium layer 107; N-type electrode 201 is disposed in the second groove and connected to N-type heavily doped Si layer 102; readout circuit 203 is connected to N-type electrode 201 and P-type electrode 202 respectively. The readout circuit 203 (ROIC) is a circuit that exports images from an infrared imaging chip. It integrates various functions of the focal plane into a semiconductor chip, thereby realizing the conversion, amplification, and multiplexing of infrared detector signals.

[0082] Specifically, the planar sensor wafer has a planar structure, the P-type charge layer 104 does not completely cover the entire silicon-germanium multi-avalanche layer 103, and the first and second grooves form an inverted convex groove structure. Except for the N-type electrode 201 connected to the N-type heavily doped Si layer 102, the rest of the space in the groove is filled with the passivation layer 108.

[0083] Please refer to Figure 2. This application also provides a germanium-based SPADs sensor based on a silicon-germanium multi-avalanche layer, comprising:

[0084] The readout circuit 203, N-type electrode 201, P-type electrode 202, passivation layer 108, and mesa sensor wafer are included.

[0085] The mesa sensor wafer includes an N-type heavily doped Si layer 102, a silicon-germanium multi-avalanche layer 103, a P-type charge layer 104, a sensing layer and a P-type heavily doped germanium layer 107 stacked sequentially, as well as a plurality of grooves of equal length and distributed at a second preset interval.

[0086] The grooves sequentially penetrate the P-type heavily doped germanium layer 107, the sensing layer, the P-type charge layer 104, the silicon-germanium multi-avalanche layer 103, and the N-type heavily doped Si layer 102. The passivation layer 108 covers the P-type heavily doped germanium layer 107 and the inner walls of each groove.

[0087] P-type electrode 202 is connected to P-type heavily doped germanium layer 107; N-type electrode 201 is disposed in the groove and connected to N-type heavily doped Si layer 102; readout circuit 203 is connected to N-type electrode 201 and P-type electrode 202 respectively.

[0088] The silicon-germanium multi-avalanche layer 103 employs a silicon-germanium multilayer structure, including but not limited to silicon or silicon-germanium multi-quantum-well layers, silicon or silicon-germanium superlattice layers, and non-periodic composite structures composed of silicon or silicon-germanium materials. When the silicon-germanium multi-avalanche layer 103 adopts a superlattice layer structure, the total thickness of the silicon-germanium multi-avalanche layer 103 ranges from 0.1 to 3 micrometers, the number of periods is 60 to 400, the total thickness of a single period ranges from 8 to 40 nanometers, the thickness of the barrier layer ranges from 3 to 10 nanometers, and the thickness of the potential well layer ranges from 5 to 30 nanometers.

[0089] Specifically, the mesa sensor wafer has a mesa structure, that is, the P-type charge layer 104 and the silicon-germanium multi-avalanche layer 103 have the same size, and the groove has a rectangular structure that extends directly from the P-type heavily doped germanium layer 107 to the N-type heavily doped Si layer 102, and the passivation layer 108 on the inner wall of the groove has the same thickness as the passivation layer 108 on the P-type heavily doped germanium layer 107.

[0090] Because the sidewalls of pixels in mesa-structured germanium SPADs sensors are exposed, the surface effects of these sidewalls can easily lead to a higher dark count rate compared to planar sensors, making it difficult to operate normally at room temperature. In contrast, planar germanium SPADs sensors significantly reduce sidewall surface effects (the high electric field region of the pixel is far from the sidewalls), resulting in superior dark count rate performance and making them suitable for operation at room temperature.

[0091] The above embodiment provides a germanium-based SPADs sensor based on silicon-germanium multi-avalanche layer 103, which breaks through the theoretical limit of the intrinsic avalanche effect of silicon material. By using a silicon-germanium multilayer structure as the avalanche region, it significantly improves the avalanche gain of germanium SPADs devices, greatly reduces the operating voltage of devices, avoids the introduction of a large amount of excessive noise during device operation, thereby reducing avalanche noise, and further reduces the dark current and dark count rate of devices.

[0092] In addition, current single-photon avalanche diode (SPAD) devices using germanium and silicon as the photosensitive layer and avalanche layer have good performance in the 1310nm band, but their performance in the 1550nm band is extremely poor. Compared with the 1310nm band, the 1550nm band has the advantage of eye safety. Therefore, existing single-photon avalanche diode (SPAD) devices do not have an advantage in terms of eye safety.

[0093] To address the above issues, please refer to Figures 1 and 2. In some embodiments, the planar sensor wafer may further include a reflective layer 101, which is superimposed on an N-type heavily doped Si layer 102.

[0094] Similarly, the mesa sensor wafer may also include a reflective layer 101, which is superimposed on an N-type heavily doped Si layer 102. The reflective layer 101 may be made of monocrystalline silicon, amorphous silicon, or silicon oxide.

[0095] The above embodiment integrates a reflective layer 101 at the bottom of the germanium-based SPADs sensor, which enhances the interaction between the germanium-based sensing material and the 1550nm wavelength optical signal, and further promotes the important application of germanium-based SPADs sensors in the field of human eye safety.

[0096] Furthermore, the reflective layer 101 can have a periodic or non-periodic structure, with a periodic structure being more effective because it enhances the interaction between the germanium-based sensing material and the 1550nm optical signal, thereby further improving the single-photon detection efficiency of the germanium-based SPADs sensor in the 1550nm band. The thickness and number of periods of the reflective layer 101 can be adjusted according to the actual requirements of the 1310nm and 1550nm bands, with a typical number of periods ranging from 1 to 6.

[0097] Referring to Figures 1 and 2, in some embodiments, the sensing layer includes a germanium quantum well sensing layer 105 and a germanium sensing layer 106, with the germanium sensing layer 106 superimposed on the germanium quantum well sensing layer 105. It can be understood that the sensor, starting from the light incident surface, has the following structure in sequence: an N-type heavily doped Si layer 102, a silicon-germanium multi-avalanche layer 103, a P-type charge layer 104, a germanium quantum well sensing layer 105, a germanium sensing layer 106, and a P-type heavily doped germanium layer 107.

[0098] The total thickness of the germanium quantum well sensing layer 105 ranges from 0.1 to 3 micrometers, the number of periods ranges from 10 to 300, the thickness of a single period is greater than or equal to 15 nanometers, the thickness of the barrier layer is greater than or equal to 10 nanometers, and the thickness of the well layer ranges from 5 to 30 nanometers.

[0099] The above embodiments overcome the absorption limitations of intrinsic germanium photosensitive layers. By superimposing germanium quantum well sensing layer 105 and germanium sensing layer 106, the light absorption efficiency of germanium-based SPADs sensors in the 1310nm and 1550nm bands is improved, further enhancing the single-photon detection efficiency and response speed of germanium SPADs sensors.

[0100] In some embodiments, the planar sensor wafer may further include a substrate, which is superimposed on the reflective layer 101.

[0101] The substrate material includes, but is not limited to, Si, SOI, FD-SOI, or Silicon on Sapphire. SOI stands for Silicon-On-Insulator, which introduces a buried oxide layer between the top silicon layer and the back substrate. FD-SOI is a fully depleted silicon-on-insulator technology, which involves devices such as fully depleted field-effect transistors (FETs). Its characteristic is that the silicon film is very thin, much smaller than the gate length. This structure can significantly reduce parasitic capacitance and improve the electrical performance of transistors. Silicon on Sapphire, abbreviated as SOS, is a technology that epitaxially grows a single-crystal silicon thin film material on a sapphire substrate.

[0102] Specifically, the mesa sensor wafer may also include a substrate, the substrate material, the reflective layer 101 material, the thickness parameters of the reflective layer 101, and the periodic parameters of the reflective layer 101 being the same as those of the planar sensor wafer.

[0103] In some embodiments, the germanium content in the silicon-germanium multi-avalanche layer 103 ranges from 0% to 30%. This is because within this composition range, the silicon-germanium layer is more lattice-matched with the silicon layer, making it easier to form a high-quality silicon or silicon-germanium multi-avalanche layer 103.

[0104] The germanium content in the germanium sensing layer 106 or the germanium quantum well sensing layer 105 ranges from 0% to 30%. Within this composition range, the germanium layer and the germanium-silicon layer have a relatively good lattice match, making it easier to form high-quality germanium or germanium-silicon sensing layers. The parameters of the silicon-germanium multi-avalanche layer 103 and the germanium quantum well sensing layer 105 in the mesa sensor wafer are consistent with those in the planar sensor wafer.

[0105] In some embodiments, the P-type charge layer 104 is a multilayer silicon-germanium composite structure.

[0106] In the specific implementation process, the P-type charge layer 104 can also be made of silicon or silicon-germanium materials. However, the multi-layer silicon-germanium composite structure is used to realize the multi-layer stacked P-type charge layer 104, which has a stronger reverse breakdown voltage regulation capability, and can significantly improve the operating voltage and single-photon detection efficiency of SPADs devices.

[0107] Please refer to Figures 3-11. Embodiments of this application provide a method for fabricating a germanium-based SPADs sensor based on a silicon-germanium multi-avalanche layer, which may specifically include the following steps:

[0108] Step S11: Provide a substrate and sequentially stack a Si layer and an oxide layer on the substrate.

[0109] Step S12: Ion implantation is performed on the Si layer to form an N-type heavily doped Si layer 102.

[0110] Step S13: After removing the oxide layer, a silicon-germanium multi-avalanche layer 103 is sequentially stacked on the N-type heavily doped Si layer 102.

[0111] Step S14: Equal P-type charge layers are uniformly embedded on silicon-germanium multi-avalanche layer 103 at a first preset interval.

[0112] Step S15: A sensing layer and a P-type heavily doped germanium layer 107 are sequentially stacked on the silicon-germanium multi-avalanche layer 103.

[0113] After completing step S15, the planar sensor wafer is obtained. For detailed structural parameters of the substrate, silicon-germanium multi-avalanche layer 103, and sensing layer in the above steps, please refer to the various embodiments of the sensor structure described above, which will not be repeated here.

[0114] Step S16: Set multiple first grooves of equal length at a second preset interval.

[0115] The first groove passes through the P-type heavily doped germanium layer 107, the sensing layer and the silicon-germanium multi-avalanche layer 103 in sequence; the first groove is located between two adjacent P-type charge electron layers and the length of the first groove is less than the first preset interval.

[0116] After setting the first groove, a planar sensor wafer with a shallow mesa structure was obtained.

[0117] Step S17: A passivation layer 108 is formed on the p-type heavily doped germanium layer 107 and the first groove.

[0118] Specifically, after the passivation layer 108 is formed on the p-type heavily doped germanium layer 107 and the first groove, the surface of the passivation layer 108 may not be as shown in FIG. 7. The passivation layer 108 can be chemically mechanically polished before the second groove is set.

[0119] Step S18: A second groove is provided at the bottom of the first groove, and a passivation layer 108 is formed on the surface of the second groove.

[0120] The second groove penetrates the silicon-germanium multi-avalanche layer 103 and the N-type heavily doped Si layer 102, and its length is shorter than that of the first groove.

[0121] Both the first and second grooves are rectangular.

[0122] In step S19, a P-type electrode 202 is installed on the P-type heavily doped germanium layer 107, and an N-type electrode 201 is installed on the N-type heavily doped Si layer 102 at the bottom of the second groove. The readout circuit 203 is then connected to the P-type electrode 202 and the N-type electrode 201, respectively, and the substrate is removed. The installation of the P-type electrode 202 can be performed before setting the second groove, i.e., before step S18.

[0123] Specifically, the readout circuit 203 is connected to the P-type electrode 202 and the N-type electrode 201 via flip-chip bonding.

[0124] When removing the substrate, you can choose to remove all or part of the substrate.

[0125] The above-mentioned sensor fabrication method is a fabrication method for a planar germanium-based SPADs sensor, which includes the following steps: forming a planar germanium-based SPADs sensor wafer (as shown in Figure 5); forming a shallow mesa structure by setting a first groove (as shown in Figure 6); forming a passivation layer 108 (as shown in Figure 7); chemical mechanical polishing (CMP); forming a P-type electrode 202 (as shown in Figure 8); setting a second groove on the basis of the first groove filled with the passivation layer 108 (as shown in Figure 9); performing surface passivation treatment on the second groove (as shown in Figure 10); forming an N-type electrode 201 (as shown in Figure 11); using flip-chip bonding technology to bond the readout circuit 203 to the germanium-based SPADs focal plane array chip with In bumps or Cu bumps; and removing all or part of the Si substrate.

[0126] Please refer to Figures 3, 4, and 12-15. This application also provides a method for fabricating a germanium-based SPAD sensor based on a silicon-germanium multi-avalanche layer 103, which specifically includes the following steps:

[0127] Step S21: Provide a substrate and sequentially stack a Si layer and an oxide layer on the substrate.

[0128] Step S22: Ion implantation is performed on the Si layer to form an N-type heavily doped Si layer 102.

[0129] Step S23: After removing the oxide layer, a silicon-germanium multi-avalanche layer 103, a P-type charge layer 104, a sensing layer, and a P-type heavily doped germanium layer 107 are sequentially stacked on the N-type heavily doped Si layer 102.

[0130] As shown in Figure 12, after completing step S23, the mecha sensor wafer is obtained.

[0131] The structural parameters of the substrate, silicon-germanium multi-avalanche layer 103, and sensing layer in the mesa sensor wafer are the same as those in the planar sensor wafer. Please refer to the various embodiments of the sensor structure described above, and we will not go into further detail here.

[0132] Step S24: Multiple grooves of equal length are set at a second preset interval; the grooves sequentially penetrate the P-type heavily doped germanium layer 107, the sensing layer, the silicon-germanium multi-avalanche layer 103 and the N-type heavily doped Si layer 102.

[0133] The groove is rectangular. After the groove is set, a mesa sensor wafer with a mesa structure is obtained.

[0134] Step S25: A passivation layer 108 is formed on the p-type heavily doped germanium layer 107 and the inner wall of the groove.

[0135] The passivation layer 108 covering the inner wall and bottom of the groove and the P-type heavily doped germanium layer 107 has a uniform thickness.

[0136] Step S26: A P-type electrode 202 is mounted on the P-type heavily doped germanium layer 107, and an N-type electrode 201 is mounted on the N-type heavily doped Si layer 102 at the bottom of the trench. The readout circuit 203 is then connected to the P-type electrode 202 and the N-type electrode 201, respectively, and the substrate is removed. The readout circuit 203 is connected to the P-type electrode 202 and the N-type electrode 201 using flip-chip bonding technology.

[0137] The above-mentioned sensor fabrication method is a fabrication method for a mesa-structured germanium-based SPADs sensor, which includes the following steps: forming a mesa-structured germanium-based SPADs sensor wafer (as shown in Figure 12), forming a mesa structure through grooves (as shown in Figure 13), forming a passivation layer 108 (as shown in Figure 14), forming an N-type electrode 201, forming a P-type electrode 202 (as shown in Figure 15), using flip-chip technology to perform In bump bonding or Cu bump bonding on the readout circuit 203 and the germanium-based SPADs focal plane array chip, and removing all or part of the Si substrate.

[0138] In some embodiments, the methods for preparing planar sensor wafers and mesa sensor wafers described above may further include:

[0139] Before stacking the Si layer, a reflective layer 101 is formed on the substrate.

[0140] The structural parameters of the reflective layer 101 disposed in the planar sensor wafer and the mesa sensor wafer have been described in the embodiments of the above sensor structure, and will not be repeated here.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A Ge-based SPADs sensor based on a silicon-germanium multi-avalanche layer, characterized by, Comprising: a readout circuit, an N-type electrode, a P-type electrode, a passivation layer and a planar sensor wafer; the planar sensor wafer comprises an N-type heavily doped Si layer, a silicon-germanium multi-avalanche layer, a P-type charge layer, a sensing layer and a P-type heavily doped germanium layer which are sequentially stacked; the P-type charge layer comprises a plurality of P-type charge sub-layers with equal length, each of the P-type charge sub-layers is uniformly embedded on the silicon-germanium multi-avalanche layer with a first preset interval; the planar sensor wafer further comprises a plurality of grooves which are distributed with a second preset interval; the grooves are located between two adjacent P-type charge sub-layers and comprise a first groove and a second groove; the first groove penetrates the P-type heavily doped germanium layer, the sensing layer and the silicon-germanium multi-avalanche layer in sequence; the second groove penetrates the silicon-germanium multi-avalanche layer and the N-type heavily doped Si layer on the basis of the first groove; the length of the first groove is greater than the length of the second groove and less than the first preset interval; the passivation layer is covered on the P-type heavily doped germanium layer and the inner wall of each groove; the P-type electrode is connected to the P-type heavily doped germanium layer; the N-type electrode is arranged in the second groove and connected to the N-type heavily doped Si layer; the readout circuit is connected to the N-type electrode and the P-type electrode respectively.

2. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 1, characterized in that, The planar sensor wafer further comprises a reflection layer which is stacked below the N-type heavily doped Si layer.

3. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 1, characterized in that, The sensing layer comprises a germanium quantum well sensing layer and a germanium sensing layer, and the germanium sensing layer is stacked above the germanium quantum well sensing layer.

4. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 2, characterized in that, The planar sensor wafer further comprises a substrate which is stacked below the reflection layer.

5. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 2, characterized in that, The material of the reflection layer is single crystal silicon, amorphous silicon or silicon oxide; the reflection layer is a periodic structure with a period number of 1-6.

6. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 1, characterized in that, The total thickness of the silicon-germanium multi-avalanche layer ranges from 0.1 to 3 microns, the period number is 60-400, the total thickness of a single period ranges from 8 to 40 nanometers, the thickness of the barrier layer ranges from 3 to 10 nanometers, and the thickness of the well layer ranges from 5 to 30 nanometers.

7. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 3, characterized in that, The total thickness of the germanium quantum well sensing layer ranges from 0.1 to 3 microns, the period number is 10-300, the thickness of a single period is greater than or equal to 15 nanometers, the thickness of the barrier layer is greater than or equal to 10 nanometers, and the thickness of the well layer ranges from 5 to 30 nanometers.

8. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 1, characterized in that, The content of germanium in the silicon-germanium multi-avalanche layer ranges from 0 to 30%.

9. The Ge-based SPADs sensor based on a GeSi multi-avalanche layer according to claim 3, characterized in that, The content of germanium in the germanium sensing layer or the germanium quantum well sensing layer ranges from 0 to 30%.

10. A Ge-based SPADs sensor based on a silicon-germanium multi-avalanche layer, characterized by, Comprising: a readout circuit, an N-type electrode, a P-type electrode, a passivation layer and a mesa sensor wafer; the mesa sensor wafer comprises an N-type heavily doped Si layer, a silicon-germanium multi-avalanche layer, a P-type charge layer, a sensing layer and a P-type heavily doped germanium layer which are sequentially stacked, and a plurality of grooves with equal length and distributed with a second preset interval; the grooves penetrate the P-type heavily doped germanium layer, the sensing layer, the P-type charge layer, the silicon-germanium multi-avalanche layer and the N-type heavily doped Si layer in sequence; the passivation layer is covered on the P-type heavily doped germanium layer and the inner wall of each groove; The P-type electrode is connected to the P-type heavily doped germanium layer; the N-type electrode is arranged in the groove and connected to the N-type heavily doped Si layer; and the readout circuit is connected to the N-type electrode and the P-type electrode respectively.

11. The Ge-based SPADs sensor based on a SiGe multi-avalanche layer according to claim 10, characterized in that, The mesa sensor wafer further comprises a reflective layer, which is superimposed below the N-type heavily doped Si layer.

12. A method of manufacturing a Ge-based SPADs sensor based on a silicon-germanium multi-avalanche layer, characterized in that, The method comprises the following steps: a substrate is provided, and a Si layer and an oxide layer are superimposed on the substrate in sequence; ion implantation is performed on the Si layer to form an N-type heavily doped Si layer; after the oxide layer is removed, a silicon germanium multi-avalanche layer is superimposed on the N-type heavily doped Si layer in sequence; a plurality of P-type charge layers with equal length are uniformly embedded on the silicon germanium multi-avalanche layer at a first preset interval; a sensing layer and a P-type heavily doped germanium layer are superimposed on the silicon germanium multi-avalanche layer in sequence; a plurality of first grooves with equal length are arranged at a second preset interval; the first grooves sequentially penetrate the P-type heavily doped germanium layer, the sensing layer and the silicon germanium multi-avalanche layer; the first grooves are located between adjacent two P-type charge layers, and the length of the first grooves is smaller than the first preset interval; a passivation layer is formed on the P-type heavily doped germanium layer and the first grooves; a second groove is arranged at the bottom of the first groove, and the passivation layer is formed on the surface of the second groove; the second groove penetrates the silicon germanium multi-avalanche layer and the N-type heavily doped Si layer, and the length of the second groove is smaller than that of the first groove; a P-type electrode is mounted on the P-type heavily doped germanium layer, an N-type electrode is mounted on the N-type heavily doped Si layer at the bottom of the second groove, a readout circuit is connected to the P-type electrode and the N-type electrode respectively, and the substrate is removed.

13. A method for the production of a Ge-based SPADs sensor based on a SiGe multi- avalanche layer according to claim 12, characterized in that, Further comprising: a reflective layer is formed on the substrate before the Si layer is superimposed.

14. A method of manufacturing a Ge-based SPADs sensor based on a silicon-germanium multi-avalanche layer, characterized in that, The method comprises the following steps: a substrate is provided, and a Si layer and an oxide layer are superimposed on the substrate in sequence; ion implantation is performed on the Si layer to form an N-type heavily doped Si layer; after the oxide layer is removed, a silicon germanium multi-avalanche layer, a P-type charge layer, a sensing layer and a P-type heavily doped germanium layer are superimposed on the N-type heavily doped Si layer in sequence; a plurality of grooves with equal length are arranged at a second preset interval; the grooves sequentially penetrate the P-type heavily doped germanium layer, the sensing layer, the silicon germanium multi-avalanche layer and the N-type heavily doped Si layer; a passivation layer is formed on the P-type heavily doped germanium layer and the inner wall of the grooves; a P-type electrode is mounted on the P-type heavily doped germanium layer, an N-type electrode is mounted on the N-type heavily doped Si layer at the bottom of the grooves, a readout circuit is connected to the P-type electrode and the N-type electrode respectively, and the substrate is removed.

15. A method for the production of a Ge-based SPADs sensor based on a GeSi multi- avalanche layer according to claim 14, characterized in that, Further comprising: a reflective layer is formed on the substrate before the Si layer is superimposed.

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