Hybrid-passivated back-contact cell having passivation blocking layers and manufacturing and application thereof

Abstract

The embodiments of the present disclosure belong to the technical field of back-contact cells, and particularly relate to a hybrid-passivated back-contact cell having passivation blocking layers and the manufacturing and application thereof. The hybrid-passivated back-contact cell comprises first semiconductor layers and second semiconductor layers, which are alternately arranged on a back surface of a silicon wafer, wherein two ends of each of the second semiconductor layers each extend outward to cover the outside of part of a back surface of a first semiconductor layer adjacent thereto; and overlapping portions of the first semiconductor layers and the second semiconductor layers in the direction of thickness form overlapping regions. The hybrid-passivated back-contact cell further comprises passivation blocking layers, which are in the overlapping regions and are arranged between the first semiconductor layers and the second semiconductor layers, wherein no mask layer is provided between the passivation blocking layers and the second semiconductor layers, the passivation blocking layers are made of amorphous silicon, and the thickness ratio of the passivation blocking layers to first doped polycrystalline silicon layers to tunneling oxide layers is 2-8: 60-100: 1. The embodiments of the present disclosure can protect the tunneling oxide layers from being corroded, thereby synergistically enhancing a passivation effect, and increasing the conversion efficiency and production yield of the cell.

Description

Combined passivated back contact battery with passivation barrier layer, its fabrication and application

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 2024106670458, filed on May 28, 2024, entitled "Combined passivated back contact battery with passivation barrier layer and its fabrication and application", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure belongs to the field of back contact battery technology, specifically relating to a combined passivated back contact battery with a passivation barrier layer, its fabrication, and its application. Background Technology

[0004] Currently, in maskless co-passivated back contact solar cells, the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer, and the second semiconductor layer comprises an intrinsic silicon layer and a second doped silicon layer. During fabrication, a mask layer is formed after the first semiconductor layer, and then removed after texturing and cleaning. The mask layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide. Hydrofluoric acid is generally used to react with and etch the mask layer. However, voids can exist in the polycrystalline layer of the first semiconductor layer during fabrication. Polycrystalline layers deposited using PE-poly equipment have higher stress and more voids than those deposited using LPCVD. After removing the mask layer, hydrofluoric acid continues to penetrate these voids, corroding the tunneling oxide layer of the polycrystalline substrate, thus affecting cell passivation and reducing cell efficiency.

[0005] It should be noted that this part of the disclosure only provides background technology related to this disclosure, and does not necessarily constitute prior art or publicly known technology. Summary of the Invention

[0006] The purpose of the embodiments disclosed herein is to overcome the above-mentioned defects in the prior art, and to provide a combined passivated back contact battery with a passivation barrier layer, the fabrication and application thereof, which can protect the tunneling oxide layer from corrosion, thereby synergistically enhancing the passivation effect and improving battery conversion efficiency and production yield.

[0007] To achieve the above objectives, in a first aspect, embodiments of this disclosure provide a combined passivated back contact battery with a passivation barrier layer, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately disposed on the back side of the silicon wafer, the first semiconductor layer comprising a tunneling oxide layer and a first doped polycrystalline silicon layer, the second semiconductor layer comprising an intrinsic silicon layer and a second doped silicon layer, the two ends of the second semiconductor layer extending outward to cover portions of the back side of adjacent first semiconductor layers, the overlapping portions of the first semiconductor layer and the second semiconductor layer in the thickness direction forming an overlapping region, and further comprising a passivation barrier layer disposed between the first semiconductor layer and the second semiconductor layer within the overlapping region, wherein no mask layer is disposed between the passivation barrier layer and the second semiconductor layer, and the passivation barrier layer is amorphous silicon, and the thickness ratio of the passivation barrier layer to the first doped polycrystalline silicon layer and the tunneling oxide layer is 2-8:60-100:1.

[0008] In some preferred embodiments of this disclosure, the amorphous silicon is hydrogenated amorphous silicon, carbon-doped hydrogenated amorphous silicon, or intrinsic amorphous silicon.

[0009] In some preferred embodiments of this disclosure, the amorphous silicon is hydrogenated amorphous silicon.

[0010] In some preferred embodiments of this disclosure, the amorphous silicon is carbon-doped hydrogenated amorphous silicon with an effective carbon doping concentration of 5e18cm. -3 -5e20cm -3 .

[0011] In some preferred embodiments of this disclosure, the thickness of the passivation barrier layer is 2-10 nm.

[0012] In some preferred embodiments of this disclosure, the thickness of the tunneling oxide layer is 1.5-2.5 nm, the thickness of the first doped polysilicon layer is 50-150 nm, and the effective doping concentration is 5e19 cm⁻¹. -3 -5e20cm -3 The intrinsic silicon layer has a thickness of 5-15 nm, and the second doped silicon layer has a thickness of 8-15 nm and an effective doping concentration of 5e19 cm⁻¹. -3 -5e20cm -3 .

[0013] In some preferred embodiments of this disclosure, the combined passivated back contact cell with passivation barrier layer further includes a front passivation layer and an antireflection layer sequentially disposed on the front side of the silicon wafer, as well as a metal electrode and a conductive film layer disposed on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation trench is formed on the portion of the conductive film layer located in the overlapping area. A second semiconductor opening region is formed between adjacent first semiconductor layers, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back side of the first semiconductor layer. The metal electrode is disposed on the outer surface of the corresponding conductive film layer of the second semiconductor opening region and the first semiconductor opening region.

[0014] In some preferred embodiments of this disclosure, the portion of the silicon wafer containing the second semiconductor layer has a textured surface, and the portion of the silicon wafer containing the first semiconductor layer has a polished surface.

[0015] Secondly, embodiments of this disclosure provide a method for fabricating a combined passivated back contact battery, comprising the following steps:

[0016] S101, provides double-sided polished silicon wafers;

[0017] S102. A first semiconductor layer, a passivation barrier layer, and a mask layer are sequentially formed on the back side of the silicon wafer. The first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline silicon layer. The passivation barrier layer is amorphous silicon. The thickness ratio of the passivation barrier layer to the first doped polycrystalline silicon layer and the tunneling oxide layer is 2-8:60-100:1.

[0018] S103, the first semiconductor layer on the back side obtained in S102 and its corresponding passivation barrier layer and mask layer are etched to form a second semiconductor opening region with spaced distribution.

[0019] S104. By texturing and cleaning, the residual mask layer, passivation barrier layer and first semiconductor layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area.

[0020] Then remove the mask layer outside the second semiconductor opening area on the back of the silicon wafer;

[0021] S105. Deposit a second semiconductor layer on the back side obtained in S104. The second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer.

[0022] S106. A second etching is performed on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0023] In some preferred embodiments of this disclosure, the thickness ratio of the passivation barrier layer to the first doped polysilicon layer and the mask layer is 0.03-0.3:1-5:1.

[0024] In some preferred embodiments of this disclosure, the thickness of the mask layer is 30-90 nm, and the mask layer is at least one of silicon nitride, silicon oxynitride, or silicon oxide.

[0025] In some preferred embodiments of this disclosure, the passivation barrier layer in S102 is deposited using a tube furnace, and the mask layer used to remove the second semiconductor opening region on the back side of the silicon wafer in S104 is an aqueous solution of hydrofluoric acid, wherein the mass concentration of hydrofluoric acid in the aqueous solution is 1%-10%.

[0026] In some preferred embodiments of this disclosure, the method for fabricating the combined passivated back contact battery further includes:

[0027] S107. Deposit a conductive film layer on the back side obtained in S106;

[0028] S108. A third etching is performed on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0029] S109. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0030] Thirdly, embodiments of this disclosure provide a combined passivated back contact battery, which is manufactured by the method for manufacturing a combined passivated back contact battery described in the second aspect.

[0031] Fourthly, embodiments of this disclosure provide a photovoltaic module comprising a combined passivated back contact cell with a passivation barrier layer as described in the first aspect, or comprising a combined passivated back contact cell as described in the third aspect. Beneficial effects:

[0032] The embodiments of this disclosure, through the above-described technical solutions, particularly the provision of a specific passivation barrier layer with an appropriate thickness ratio, can passivate the polycrystalline pores present in the first doped polycrystalline silicon layer and protect the tunneling oxide layer corresponding to the polycrystalline pore region from corrosion by hydrofluoric acid, thereby significantly enhancing the passivation effect. Combined with a joint passivation structure, it can further prevent the tunneling oxide layer corresponding to the pore region of the first doped polycrystalline silicon layer from being corroded, and avoid the formation of a second semiconductor layer of opposite polarity in the pore region, which could lead to micro-short circuit problems, thereby improving battery conversion efficiency and production yield. Notably, the passivation barrier layer is made of amorphous silicon, which does not react with the hydrofluoric acid used to remove the mask layer, enhancing passivation efficiency. Furthermore, amorphous silicon can be deposited together with the mask layer in a tube furnace, resulting in low cost.

[0033] In the fabrication method of the embodiments disclosed herein, after forming the first semiconductor layer and before forming the mask layer, a passivation barrier layer is formed. The passivation barrier layer can prevent the hydrofluoric acid used to remove the mask layer from corroding and tunneling through the polycrystalline holes into the oxide layer. During texturing and cleaning, the hydrofluoric acid naturally stops corroding after removing the mask layer at the passivation barrier layer and no longer continues to corrode. Furthermore, the passivation barrier layer can further passivate the polycrystalline holes, thereby improving the passivation effect of the battery and thus improving the battery efficiency. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 is a schematic diagram of the structure of a silicon wafer provided in an embodiment of this disclosure;

[0036] Figure 2 is a schematic diagram of the structure in which a first semiconductor layer, a passivation barrier layer and a mask layer are sequentially formed on the back side of a silicon wafer according to an embodiment of the present disclosure.

[0037] Figure 3 is a schematic diagram of the structure of a second semiconductor opening region with spaced distribution on the back side according to an embodiment of the present disclosure;

[0038] Figure 4 is a schematic diagram of the structure of the back side texturing, cleaning and removal of the mask layer in an embodiment of the present disclosure;

[0039] Figure 5 is a schematic diagram of the structure of forming a second semiconductor layer, a front passivation layer, and an anti-reflection layer on the back side of a silicon wafer according to an embodiment of the present disclosure.

[0040] Figure 6 is a schematic diagram of the structure of the first semiconductor opening region formed on the back side according to an embodiment of the present disclosure;

[0041] Figure 7 is a schematic diagram of the structure of the conductive film layer formed on the back side in an embodiment of the present disclosure;

[0042] Figure 8 is a schematic diagram of the structure of the isolation groove formed on the back side according to an embodiment of the present disclosure;

[0043] Figure 9 shows a metal electrode formed on the back side according to an embodiment of this disclosure.

[0044] Explanation of reference numerals in the attached figures: 1. Silicon wafer; 2. Tunneling oxide layer; 3. First doped polycrystalline silicon layer; 4B. Passivation barrier layer; 4. Mask layer; 5. Front passivation layer; 6. Intrinsic amorphous silicon layer; 7. Second doped silicon layer; 8. Antireflection layer; 9. Conductive film layer; 10. Metal electrode. Detailed Implementation

[0045] In this disclosure, unless otherwise stated, directional terms such as "up," "down," "left," and "right" are generally used to refer to the orientation as shown in the accompanying drawings and in practical applications.

[0046] Furthermore, the terms "first" and "second" are configured for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0047] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0048] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "discretionary" mean that they may or may not be included (or may or may not be present).

[0049] In the embodiments disclosed herein, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside.

[0050] In a first aspect, embodiments of this disclosure provide a combined passivated back contact battery with a passivation barrier layer, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately disposed on the back side of the silicon wafer, the first semiconductor layer comprising a tunneling oxide layer and a first doped polycrystalline silicon layer, the second semiconductor layer comprising an intrinsic silicon layer and a second doped silicon layer, the two ends of the second semiconductor layer extending outward to cover the back side of a portion of the adjacent first semiconductor layer, the overlapping portion of the first semiconductor layer and the second semiconductor layer in the thickness direction forming an overlapping region, and further comprising a passivation barrier layer disposed between the first semiconductor layer and the second semiconductor layer within the overlapping region, wherein no mask layer is disposed between the passivation barrier layer and the second semiconductor layer, and the passivation barrier layer is amorphous silicon, the thickness ratio of the passivation barrier layer to the first doped polycrystalline silicon layer and the tunneling oxide layer is 2-8:60-100:1, optionally 2-5.5:60-100:1.

[0051] In some preferred embodiments of this disclosure, the amorphous silicon is hydrogenated amorphous silicon, carbon-doped hydrogenated amorphous silicon, or intrinsic amorphous silicon.

[0052] In some preferred embodiments of this disclosure, the amorphous silicon is hydrogenated amorphous silicon, which can provide more hydrogen sources and is more conducive to enhancing the passivation effect.

[0053] In some preferred embodiments of this disclosure, the amorphous silicon is carbon-doped hydrogenated amorphous silicon with an effective carbon doping concentration of 5e18cm. -3 -5e20cm -3 Using carbon-doped hydrogenated amorphous silicon with an appropriate carbon doping concentration can increase the band gap width of amorphous silicon, which is more conducive to reducing the absorption of amorphous silicon, thereby improving the battery current and battery conversion efficiency.

[0054] In some preferred embodiments of this disclosure, the thickness of the passivation barrier layer is 2-10 nm. Using a passivation barrier layer of suitable thickness can improve the passivation effect of the battery (optionally, it can also widen the process window for the second etching to form the first semiconductor opening region in fabrication process S106), which is more conducive to improving battery efficiency and production yield.

[0055] In some preferred embodiments of this disclosure, the thickness of the tunneling oxide layer is 1.5-2.5 nm, the thickness of the first doped polysilicon layer is 50-150 nm, and the effective doping concentration is 5e19 cm⁻¹. -3 -5e20cm -3 .

[0056] In some preferred embodiments of this disclosure, the thickness of the intrinsic silicon layer is 5-15 nm, and the thickness of the second doped silicon layer is 8-15 nm with an effective doping concentration of 5e19 cm⁻¹. -3 -5e20cm -3 The intrinsic silicon layer can be an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and can be selected as an intrinsic amorphous silicon layer. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon.

[0057] In this disclosure, one of the first doped polycrystalline silicon layer and the other of the second doped silicon layer are N-type and P-type, respectively.

[0058] In the preferred embodiment of this disclosure, using a suitable passivation barrier layer matched with a tunneling oxide layer of suitable thickness, an intrinsic silicon layer, and a first doped polycrystalline silicon layer and a second doped silicon layer of suitable doping concentration can improve the passivation of the battery surface, the production process window, and reduce the series resistance, which is more conducive to improving the battery conversion efficiency and production yield.

[0059] In some preferred embodiments of this disclosure, the combined passivated back contact cell with passivation barrier layer further includes a front passivation layer and an antireflection layer sequentially disposed on the front side of the silicon wafer, as well as a metal electrode and a conductive film layer disposed on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation trench is formed on the portion of the conductive film layer located in the overlapping area. A second semiconductor opening region is formed between adjacent first semiconductor layers, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back side of the first semiconductor layer. The metal electrode is disposed on the outer surface of the corresponding conductive film layer of the second semiconductor opening region and the first semiconductor opening region.

[0060] The types and thicknesses of the front passivation layer and antireflection layer described in this disclosure can refer to existing technologies. For example, the front passivation layer can be any one of the following: an intrinsic amorphous layer, a composite layer of an intrinsic amorphous layer and an N-type microcrystalline layer, a silicon oxide layer, a composite layer of a silicon oxide layer and an N-type polycrystalline layer, or an aluminum oxide layer, and any other passivation material. The thickness of the front passivation layer can be 3-20 nm. For example, the antireflection layer can be one or more combinations of silicon nitride, silicon oxynitride, or silicon oxide. The thickness of the antireflection layer can be 60-120 nm.

[0061] The widths of the first semiconductor opening region, the second semiconductor opening region, and the isolation trench disclosed herein can be determined with reference to the range of prior art and according to actual needs. For example, the width W1 of the second semiconductor opening region can be 400-800 μm, the width W2 of the first semiconductor opening region can be 100-250 μm, and the width W3 of the isolation trench can be 20-100 μm.

[0062] In some preferred embodiments of this disclosure, the portion of the silicon wafer containing the second semiconductor layer has a textured surface, and the portion of the silicon wafer containing the first semiconductor layer has a polished surface.

[0063] In the embodiments of this disclosure, the silicon wafer can be an N-type silicon wafer or a P-type silicon wafer.

[0064] Secondly, embodiments of this disclosure provide a method for fabricating a combined passivated back contact battery, comprising the following steps:

[0065] S101, provides double-sided polished silicon wafers;

[0066] S102. A first semiconductor layer, a passivation barrier layer, and a mask layer are sequentially formed on the back side of the silicon wafer. The first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline silicon layer. The passivation barrier layer is amorphous silicon. The thickness ratio of the passivation barrier layer to the first doped polycrystalline silicon layer and the tunneling oxide layer is 2-8:60-100:1.

[0067] S103, the first semiconductor layer on the back side obtained in S102 and its corresponding passivation barrier layer and mask layer are etched to form a second semiconductor opening region with spaced distribution.

[0068] S104. By texturing and cleaning, the residual mask layer, passivation barrier layer and first semiconductor layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area.

[0069] Then remove the mask layer outside the second semiconductor opening area on the back of the silicon wafer;

[0070] S105. Deposit a second semiconductor layer on the back side obtained in S104. The second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer.

[0071] S106. A second etching is performed on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0072] In some preferred embodiments of this disclosure, the thickness ratio of the passivation barrier layer to the first doped polysilicon layer and the mask layer is 0.03-0.3:1-5:1, optionally 0.07-0.3:1.4-5:1. Using a suitable thickness ratio for the passivation barrier layer, the first doped polysilicon layer, and the mask layer is more conducive to improving the passivation effect of the battery and the process window for forming the first semiconductor opening region in the second etching step S106, thereby improving battery conversion efficiency and production yield.

[0073] In some preferred embodiments of this disclosure, the thickness of the mask layer is 30-90 nm, and the mask layer is at least one of silicon nitride, silicon oxynitride, or silicon oxide.

[0074] In some preferred embodiments of this disclosure, the passivation barrier layer in S102 is deposited using a tubular furnace, which is more conducive to reducing equipment costs while also ensuring excellent battery performance.

[0075] Optionally, in step S104, the mask layer outside the second semiconductor opening region on the back side of the silicon wafer is removed using an aqueous solution of hydrofluoric acid, wherein the mass concentration of hydrofluoric acid in the aqueous solution is 1%-10%. The embodiments of this disclosure use an aqueous solution of hydrofluoric acid of suitable concentration to remove the mask layer, which does not corrode the passivation barrier layer and can completely and quickly remove the mask layer while ensuring the passivation effect.

[0076] In some preferred embodiments of this disclosure, the method for fabricating the combined passivated back contact battery further includes:

[0077] S107. Deposit a conductive film layer on the back side obtained in S106;

[0078] S108. A third etching is performed on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0079] S109. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0080] Thirdly, embodiments of this disclosure provide a combined passivated back contact battery, which is fabricated using the method for manufacturing a combined passivated back contact battery described in the second aspect. The structure and performance of the combined passivated back contact battery of the third aspect are the same as those of the combined passivated back contact battery of the first aspect, and will not be repeated here.

[0081] Fourthly, embodiments of this disclosure provide a photovoltaic module comprising a combined passivated back contact cell with a passivation barrier layer as described in the first aspect, or comprising a combined passivated back contact cell as described in the third aspect.

[0082] The embodiments of this disclosure described below are exemplary and configured only to explain this disclosure, and should not be construed as limiting this disclosure.

[0083] Example 1

[0084] A combined passivated back contact battery, as shown in Figure 9, is prepared by the following method:

[0085] S101. As shown in Figure 1, a silicon wafer 1 is provided, and the silicon wafer 1 is polished and cleaned in sequence.

[0086] S102, as shown in Figure 2, a first semiconductor layer, a passivation barrier layer 4B, and a mask layer 4 are sequentially formed on the back side of the silicon wafer 1. The first semiconductor layer includes a tunneling oxide layer 2 and an N-type first doped polysilicon layer 3 sequentially formed on the back side; the thickness of the tunneling oxide layer 2 is 1.5 nm, and the thickness of the first doped polysilicon layer 3 is 100 nm with an effective doping concentration of 9e19 cm⁻¹. -3 The passivation barrier layer 4B has a thickness of 5 nm and is made of amorphous silicon, specifically hydrogenated amorphous silicon; the mask layer 4 has a thickness of 60 nm and is made of silicon nitride.

[0087] S103, as shown in Figure 3, the first semiconductor layer and its corresponding passivation barrier layer 4B and mask layer 4 are etched on the back side obtained in S102 to form a second semiconductor opening region with spaced distribution. The width W1 of the second semiconductor opening region is 500μm.

[0088] S104. As shown in Figure 4, a texturing process is performed to form a textured surface in the second semiconductor opening area on the back side and on the front side. Then, a hydrofluoric acid aqueous solution with a mass concentration of 5% is used to remove the mask layer 4.

[0089] S105, as shown in Figure 5, then a second semiconductor layer is formed on the back side obtained in S105, and a front passivation layer 5 and an anti-reflection layer 8 are formed on the front side. The second semiconductor layer includes an intrinsic amorphous silicon layer 6 and a P-type second doped silicon layer 7 sequentially formed on the back side; the thickness of the intrinsic amorphous silicon layer 6 is 8 nm, and the thickness of the second doped silicon layer 7 is 10 nm with an effective doping concentration of 1e20 cm⁻¹. -3 The front passivation layer 5 is an intrinsic amorphous layer with a thickness of 8 nm, and the antireflection layer 8 is silicon nitride with a thickness of 75 nm.

[0090] S106, as shown in Figure 6, then a second etching is performed on the polished area on the back side obtained in S106 to expose the first semiconductor layer and form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. The width W2 of the first semiconductor opening region is 200μm.

[0091] S107, as shown in Figure 7, a conductive film layer 9 is formed on the back side of the obtained S107 in a fully covered manner.

[0092] S108, as shown in Figure 8, then the conductive film layer portion on the back side obtained in S108, located between the first semiconductor opening region and the second semiconductor opening region, is etched a third time to form an isolation trench with an isolation trench width W3 of 50μm.

[0093] S109, as shown in Figure 9, metal electrodes 10 are formed on the second semiconductor opening region and the first semiconductor opening region on the back side obtained in S109, respectively.

[0094] Example 2

[0095] The method is the same as in Example 1, except that the passivation barrier layer in S102 is carbon-doped hydrogenated amorphous silicon with an effective carbon doping concentration of 1e20cm. -3 .

[0096] Example 3

[0097] The method is carried out in accordance with Example 1, except that the passivation barrier layer in S102 is intrinsic amorphous silicon.

[0098] Example 4

[0099] The method is carried out in accordance with Example 1, except that the thickness of the passivation barrier layer in S102 is 9 nm, so that the ratio of the thickness of the passivation barrier layer to the thickness of the tunneling oxide layer is 6:1.

[0100] Example 5

[0101] The method described in Example 1 is followed, except that the thickness of the mask layer is increased to 90 nm. Furthermore, the mass concentration of hydrofluoric acid in the hydrofluoric acid aqueous solution is increased to 10% during the mask layer removal step.

[0102] Comparative Example 1

[0103] The method is carried out in accordance with Example 1, except that no passivation barrier layer is provided in S102.

[0104] Test case

[0105] The combined passivated back contact batteries obtained from the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The short-circuit currents of each embodiment and comparative example were calculated using Embodiment 1 as a reference. The short-circuit current data for Embodiment 1 is based on a normalized reference of 1. Other examples were calculated based on Embodiment 1; for instance, the ratio of the short-circuit current of Embodiment 2 to the short-circuit current of Embodiment 1 is 1.005.

[0106] Table 1

[0107] The results above show that, compared with the comparative example, the embodiment of this disclosure can protect the tunneling oxide layer from corrosion, thereby synergistically enhancing the passivation effect and improving battery conversion efficiency and production yield.

[0108] Optionally, as can be seen from Examples 1 and 2-5, the preferred battery structure of this disclosure is more conducive to enhancing the passivation effect and improving battery conversion efficiency and production yield.

[0109] The preferred embodiments of this disclosure have been described in detail above; however, this disclosure is not limited thereto. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, including combining the various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in this disclosure and are all within the protection scope of this disclosure. Industrial applicability

[0110] The embodiments of this disclosure, through the above-described technical solutions, particularly the provision of a specific passivation barrier layer with an appropriate thickness ratio, can passivate the polycrystalline pores present in the first doped polycrystalline silicon layer and protect the tunneling oxide layer corresponding to the polycrystalline pore region from corrosion by hydrofluoric acid, thereby significantly enhancing the passivation effect. Combined with a joint passivation structure, it can further prevent the tunneling oxide layer corresponding to the pore region of the first doped polycrystalline silicon layer from being corroded, and avoid the formation of a second semiconductor layer of opposite polarity in the pore region, which could lead to micro-short circuit problems, thereby improving battery conversion efficiency and production yield. Notably, the passivation barrier layer is made of amorphous silicon, which does not react with the hydrofluoric acid used to remove the mask layer, enhancing passivation efficiency. Furthermore, amorphous silicon can be deposited together with the mask layer in a tube furnace, resulting in low cost.

Claims

1. A back contact cell with passivation barrier, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, the first semiconductor layer comprising a tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer comprising an intrinsic silicon layer and a second doped silicon layer, the second semiconductor layer extending outwardly at both ends thereof to cover part of the back surface of the adjacent first semiconductor layer, and the superimposed part of the first semiconductor layer and the second semiconductor layer in the thickness direction forming an overlapping region, characterized in that, The passivation barrier layer is disposed between the first semiconductor layer and the second semiconductor layer in the overlapping area, no mask layer is disposed between the passivation barrier layer and the second semiconductor layer, the passivation barrier layer is amorphous silicon, and the thickness ratio of the passivation barrier layer to the first doped polysilicon layer and the tunneling oxide layer is 2-8:60-100:

1.

2. The back contact cell with passivating barrier layer according to claim 1, wherein, The amorphous silicon is hydrogenated amorphous silicon, carbon-doped hydrogenated amorphous silicon or intrinsic amorphous silicon.

3. The back contact cell with passivating barrier layer according to claim 2, wherein, The amorphous silicon is hydrogenated amorphous silicon. Alternatively, the amorphous silicon is carbon-doped hydrogenated amorphous silicon and the effective carbon-doping concentration is 5e18cm -3 -5e20cm -3 .

4. The back contact cell with passivating barrier layer of claim 1, wherein, The thickness of the passivation barrier layer is 2-10 nm. And / or, The thickness of the tunnel oxide layer is 1.5-2.5nm, the thickness of the first doped polysilicon layer is 50-150nm, and the effective doping concentration is 5e19cm -3 -5e20cm -3 The thickness of the intrinsic silicon layer is 5-15nm, the thickness of the second doped silicon layer is 8-15nm, and the effective doping concentration is 5e19cm -3 -5e20cm -3 .

5. The back contact cell with passivating barrier layer of claim 1, wherein, The joint passivation back contact cell with the passivation barrier layer further comprises a front passivation layer and an anti-reflection layer disposed on the front surface of the silicon wafer in sequence, a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is formed on the part of the conductive film layer in the overlapping area; the second semiconductor opening area is formed between adjacent first semiconductor layers, and the first semiconductor opening area not covering the second semiconductor layer is formed on the back surface of the first semiconductor layer, and the metal electrode is disposed on the outer surface of the respective conductive film layer of the second semiconductor opening area and the first semiconductor opening area; And / or, Part of the silicon wafer where the second semiconductor layer is located is a texturing surface, and part of the silicon wafer where the first semiconductor layer is located is a polishing surface.

6. A method of fabricating a co-passivated back contact cell, comprising: The method comprises the following steps: S101, providing a double-side polished silicon wafer; S102, sequentially forming a first semiconductor layer, a passivation barrier layer and a mask layer on the back surface of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer, the passivation barrier layer is amorphous silicon, and the thickness ratio of the passivation barrier layer to the first doped polysilicon layer and the tunneling oxide layer is 2-8:60-100:1; S103, performing first etching on the first semiconductor layer and the corresponding passivation barrier layer and mask layer on the back surface obtained in S102 to form a second semiconductor opening area arranged at intervals; S104, removing the residual mask layer, passivation barrier layer and first semiconductor layer in the second semiconductor opening area by texturing cleaning, and forming a textured surface on the front surface of the silicon wafer and the second semiconductor opening area; Then, the mask layer outside the second semiconductor opening area on the back surface of the silicon wafer is removed; S105, depositing a second semiconductor layer on the back surface obtained in S104, the second semiconductor layer comprising an intrinsic silicon layer and a second doped silicon layer; S106, performing second etching on part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area.

7. The method of fabricating a co-passivated back contact cell according to claim 6, wherein, The thickness ratio of the passivation barrier layer to the first doped polysilicon layer and the mask layer is 0.03-0.3:1-5:1, and / or The thickness of the mask layer is 30-90 nm, and the mask layer is at least one of silicon nitride, silicon oxynitride and silicon oxide.

8. The method of fabricating a co-passivated back contact cell of claim 6, wherein, In S102, the passivation barrier layer is deposited by a tube furnace, and in S104, the mask layer outside the second semiconductor opening area on the back surface of the silicon wafer is removed by using a hydrofluoric acid aqueous solution, and the mass concentration of hydrofluoric acid in the hydrofluoric acid aqueous solution is 1%-10%; And / or, the method for manufacturing the joint passivation back contact cell further comprises: S107, depositing a conductive film layer on the back surface obtained in S106; S108, performing third etching on the part of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S109, forming a metal electrode on the outer surface of the corresponding conductive film layer in the region where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

9. A co-passivated back contact cell characterized by, The combined passivated back contact cell is prepared by the method of any one of claims 6-8.

10. A photovoltaic module, characterized by, The combined passivated back contact cell comprises the combined passivated back contact cell with a passivation barrier layer of any one of claims 1-5, or the combined passivated back contact cell of claim 9.

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