Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises connecting electrodes. The connecting electrodes are located between a first insulating layer and a second insulating layer. The connecting electrodes are connected to pixel circuits by means of first via holes passing through the first insulating layer. First electrodes of light-emitting elements are connected to the connecting electrodes by means of second via holes passing through the second insulating layer. The ratio of the maximum size of each second through hole in a second direction to the maximum size of each of pixel openings in the second direction is larger than or equal to 0.05 and smaller than or equal to 0.48, thereby facilitating the flatness of sub-pixels, improving the display effect, and obtaining high-resolution products.

Description

Display panel and display device

[0001] Cross-references to related applications

[0002] This patent application claims priority to Chinese Patent Application No. 202410693493.5, filed on May 30, 2024, the disclosure of which is incorporated herein by reference in its entirety as part of the embodiments thereof. Technical Field

[0003] At least one embodiment of this disclosure relates to a display panel and a display device. Background Technology

[0004] With the rapid development of technology, display media have become an important part of people's lives. Organic light-emitting diode (OLED) display media possesses superior color and image quality due to its self-emissive properties. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a display panel and a display device that facilitates the flatness of subpixels, improves display performance, and facilitates the acquisition of high-resolution products.

[0006] At least one embodiment of this disclosure provides a display panel, including: a substrate and a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a pixel opening configured to define a light-emitting area. A first defining portion is disposed between two adjacent pixel openings in a first direction, and a second defining portion is disposed between two adjacent pixel openings in a second direction. The first direction intersects the second direction. The thicknesses of the first defining portion and the second defining portion are not equal. Each sub-pixel includes a pixel circuit and a light-emitting element connected to the pixel circuit. The light-emitting element has a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode. The first electrode of the light-emitting element is closer to the substrate than the light-emitting functional layer. The display panel further includes an insulating layer. The display panel includes an insulating material layer located on the side of the pixel circuit facing away from the substrate. The insulating material layer comprises a first insulating layer and a second insulating layer. The first insulating layer comprises an organic material, and the second insulating layer comprises an organic material. The first insulating layer is closer to the substrate than the second insulating layer. The display panel also includes a connection electrode located between the first insulating layer and the second insulating layer. The connection electrode is connected to the pixel circuit through a first via penetrating the first insulating layer. The first electrode of the light-emitting element is connected to the connection electrode through a second via penetrating the second insulating layer. The ratio of the maximum size of the second via along the second direction to the maximum size of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0007] For example, the ratio of the maximum size of the second via along the second direction to the maximum size of the pixel opening along the second direction is greater than or equal to 0.12 and less than or equal to 0.24.

[0008] For example, the ratio of the maximum size of the second via along the first direction to the maximum size of the pixel opening along the first direction is greater than or equal to 0.05 and less than or equal to 0.24.

[0009] For example, the ratio of the maximum size of the second via along the first direction to the maximum size of the pixel opening along the first direction is greater than or equal to 0.08 and less than or equal to 0.18.

[0010] For example, the thickness of the first defining portion is less than the thickness of the second defining portion.

[0011] For example, the thickness of the first insulating layer is less than or equal to the thickness of the second insulating layer.

[0012] For example, the thickness of the first insulating layer is less than or equal to 2 micrometers, and the thickness of the second insulating layer is less than or equal to 2 micrometers.

[0013] For example, the size of the first via is less than or equal to 10 micrometers, and the size of the second via is less than or equal to 10 micrometers.

[0014] For example, the size of the first via is less than or equal to 5 micrometers, and the size of the second via is less than or equal to 5 micrometers.

[0015] For example, the size of the first via is greater than or equal to 2 micrometers, and the size of the second via is greater than or equal to 2 micrometers.

[0016] For example, multiple second vias are provided, and the first electrode of the light-emitting element is connected to the connecting electrode through multiple second vias penetrating the second insulating layer. The multiple second vias are located at the edge of the pixel opening.

[0017] For example, the size of each of the multiple second vias is less than or equal to 10 micrometers.

[0018] For example, the orthographic projection of the connecting electrode on the substrate overlaps with the orthographic projection of the pixel opening of the sub-pixel on the substrate.

[0019] For example, the orthogonal projection of the connecting electrode on the substrate covers the orthogonal projection of the pixel opening of the sub-pixel on the substrate.

[0020] For example, the connecting electrode is in contact with the first insulating layer, and the connecting electrode has multiple openings that expose a portion of the first insulating layer, and a pixel opening of a sub-pixel overlaps with one or more openings of the connecting electrode.

[0021] For example, the pixel circuit includes a storage capacitor having a first plate and a second plate, the first plate and the second plate being insulated from each other, and the size of each opening of the connecting electrode being smaller than the size of the first plate and smaller than the size of the second plate.

[0022] For example, the display panel also includes at least two barrier dams and at least one isolation slot located between adjacent barrier dams, the isolation slot being configured to contain redundant ink.

[0023] For example, the at least two blocking dams include a first blocking dam and a second blocking dam, wherein the first blocking dam is closer to the display area of ​​the display panel than the second blocking dam, and the height of the first blocking dam is less than the height of the second blocking dam.

[0024] For example, the display panel further includes a pixel defining layer, which includes a defining portion and an isolation portion. The defining portion is configured to define a pixel opening of the sub-pixel, and at least one of the at least two blocking dams includes the isolation portion, the thickness of which is greater than the thickness of the defining portion.

[0025] For example, at least one partition structure is provided in the isolation groove, the partition structure being configured to isolate the light-emitting functional layer.

[0026] For example, the display panel also includes a conductive connection portion, which is located on the same layer as the connection electrode and is insulated from each other.

[0027] For example, the conductive connection portion has multiple hollow structures, and the connection electrode is located in one of the multiple hollow structures.

[0028] For example, in the hollow structure and the connecting electrode located therein, the ratio of the area of ​​the connecting electrode to the area of ​​the hollow structure is less than or equal to 10%.

[0029] For example, in the hollow structure and the connecting electrode located therein, the ratio of the area of ​​the connecting electrode to the area of ​​the hollow structure is greater than or equal to 70%.

[0030] For example, the conductive connection portion has multiple first conductive lines and multiple second conductive lines.

[0031] For example, each of the plurality of first conductive lines and each of the plurality of second conductive lines is insulated from each other, and the plurality of first conductive lines and the plurality of second conductive lines are alternately arranged in the first direction or the second direction.

[0032] For example, the connecting electrode is disposed between adjacent first and second conductive lines, with the first conductive line, the connecting electrode, and the second conductive line arranged in sequence.

[0033] For example, the display panel also includes a dummy block, which is floating and located on the same layer as the conductive connection portion.

[0034] For example, the area of ​​the dummy block is larger than the area of ​​the connecting electrode.

[0035] For example, the dummy block is disposed in the hollow structure.

[0036] For example, the display panel also includes a dummy block, which is floating and located on the same layer as the conductive connection portion.

[0037] For example, the area of ​​the dummy block is larger than the area of ​​the connecting electrode.

[0038] For example, the dummy block is set between adjacent first and second conductive lines.

[0039] For example, the display panel also includes a power line connected to the conductive connection portion, the power line being configured to provide a constant power supply voltage to the pixel circuit.

[0040] For example, the power line includes a first power line connected to the pixel circuit and configured to provide a constant first voltage signal to the pixel circuit.

[0041] For example, the first power line includes a first power signal line and a first power connection line, the first power signal line and the first power connection line are connected and cross each other, and the conductive connection part is connected to the first power connection line.

[0042] For example, the power line includes a second power line connected to the second electrode of the light-emitting element and configured to provide a constant second voltage signal.

[0043] For example, the display panel further includes a first power line and a second power line, the first power line being connected to the pixel circuit and configured to provide a constant first voltage signal to the pixel circuit, the second power line being connected to the second electrode of the light-emitting element and configured to provide a constant second voltage signal, the first conductive line being connected to the first power line, and the second conductive line being connected to the second power line.

[0044] For example, the display panel also includes a conductive bus, the conductive bus and the connecting electrode are located on the same layer, the conductive bus and the conductive connection are an integral structure, the conductive bus extends along the second direction, the size of the conductive bus in the second direction is larger than the size of the conductive connection in the second direction, and the orthographic projection of the conductive bus on the substrate overlaps with the orthographic projection of the pixel opening of the first row of sub-pixels on the substrate.

[0045] For example, the display panel also includes multiple signal generation circuits, wherein each of the multiple signal generation circuits is disposed between two adjacent columns of pixel circuits.

[0046] For example, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The area of ​​the pixel opening of the third sub-pixel is larger than the area of ​​the pixel opening of the second sub-pixel and larger than the area of ​​the pixel opening of the first sub-pixel. The number of signal generation circuits overlapping with the pixel opening of the third sub-pixel is greater than the number of signal generation circuits overlapping with the pixel opening of the first sub-pixel and greater than the number of signal generation circuits overlapping with the pixel opening of the second sub-pixel.

[0047] For example, the signal generation circuit includes a gate signal generation circuit and a light emission signal generation circuit, which are formed between two different columns of pixel circuits.

[0048] For example, the pixel circuits of the first sub-pixel, the second sub-pixel, and the third sub-pixel have different widths.

[0049] For example, the width of the pixel circuit of the first sub-pixel is greater than the width of the pixel circuit of the third sub-pixel, and the width of the pixel circuit of the third sub-pixel is greater than the width of the pixel circuit of the second sub-pixel.

[0050] For example, the display panel further includes an initialization line and a first power line, the initialization line being configured to provide a constant initialization voltage to the pixel circuit, the first power line being configured to provide a constant first voltage signal to the pixel circuit, the initialization line overlapping the pixel opening of the third sub-pixel, the first power line overlapping the pixel opening of the first sub-pixel, and the width of the initialization line being smaller than the width of the first power line.

[0051] For example, the orthographic projection of the pixel opening of the sub-pixel on the substrate overlaps with the orthographic projection of at least one pixel circuit on the substrate, and also overlaps with the orthographic projection of at least one signal generation circuit on the substrate.

[0052] For example, the display panel further includes data lines, a first gate line, a second gate line, a third gate line, a fourth gate line, a first power line, a first initialization voltage line, and a second initialization voltage line. The pixel circuit includes a driving transistor, a light-emitting control transistor, a data writing transistor, a first reset transistor, a second reset transistor, and a storage capacitor. The storage capacitor includes a first electrode and a second electrode. The first electrode of the storage capacitor is connected to the gate of the driving transistor, and the second electrode of the storage capacitor is connected to the first electrode of the driving transistor. The first electrode of the data writing transistor is connected to the data line, and the gate of the driving transistor is connected to the second electrode of the data writing transistor. The gate of the data writing transistor is connected to the first gate line. The first electrode of the first reset transistor is connected to the first initialization line, and the second electrode of the first reset transistor is connected to the gate of the driving transistor. The gate of the first reset transistor is connected to the second gate line, and the gate of the second reset transistor is connected to the third gate line. The first electrode of the second reset transistor is connected to the second initialization line. The second terminal of the second reset transistor is connected to the light-emitting element through the driving transistor. The gate of the light-emitting control transistor is connected to the fourth gate line. The first terminal of the light-emitting control transistor is connected to the first power line. The second terminal of the light-emitting control transistor is connected to the second terminal of the driving transistor. The plurality of signal generation circuits include a first gate signal generation circuit, a second gate signal generation circuit, a light-emitting control signal generation circuit, and an initialization voltage generation circuit. The first gate signal generation circuit is connected to the first gate line. The second gate signal generation circuit is connected to at least one of the second gate line and the third gate line. The light-emitting control signal generation circuit is connected to the fourth gate line. The initialization voltage generation circuit is connected to at least one of the first initialization line and the second initialization line. The width of the first gate signal generation circuit is greater than the width of the light-emitting control signal generation circuit. The width of the light-emitting control signal generation circuit is greater than the width of the second gate signal generation circuit. The width of the second gate signal generation circuit is greater than the width of the initialization voltage generation circuit.

[0053] For example, the display panel also includes data lines. The pixel circuit includes a driving transistor and a data writing transistor. The data lines are connected to a first terminal of the data writing transistor, and a second terminal of the data writing transistor is connected to the gate of the driving transistor. Multiple data lines are provided, including a first data line, a second data line, and a third data line. The first data line overlaps with the pixel opening of the first sub-pixel, the second data line overlaps with the pixel opening of the second sub-pixel, and the third data line overlaps with the pixel opening of the third sub-pixel. The first data line, the second data line, and the third data line are arranged sequentially. The ratio of a first spacing between the first data line and the second data line to a second spacing between the second data line and the third data line ranges from 0.8 to 1.2.

[0054] For example, the plurality of sub-pixels includes a middle sub-pixel near the center of the display panel and an edge sub-pixel near the edge of the display panel, wherein the refresh rate of the middle sub-pixel and the refresh rate of the edge sub-pixel are configured to be adjustable in a preset working mode.

[0055] For example, the refresh rate of the middle sub-pixel is greater than the refresh rate of the edge sub-pixel.

[0056] For example, the display panel further includes data lines, the pixel circuit includes a driving transistor and a data writing transistor, the data lines are connected to a first terminal of the data writing transistor, the second terminal of the data writing transistor is connected to the gate of the driving transistor, the data lines are configured as multiple lines, the display panel includes a display area and a peripheral area located on at least one side of the display area, the display panel further includes multiple fan-out lines, the data lines are connected to one of the multiple fan-out lines, the multiple fan-out lines gradually converge from near the connection position of the data line and the fan-out line to away from the connection position of the data line and the fan-out line, the multiple fan-out lines extend from the display area to the peripheral area, the multiple fan-out lines and the multiple data lines are located on different layers, and the multiple data lines are closer to the substrate than the multiple fan-out lines.

[0057] Embodiments of this disclosure also provide a display panel, including: a substrate and a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a pixel aperture, a pixel circuit, and a light-emitting element connected to the pixel circuit. The light-emitting element has a first electrode. The display panel further includes an insulating material layer located on the side of the pixel circuit facing away from the substrate. The insulating material layer includes a first insulating layer and a second insulating layer. The first insulating layer includes an organic material, and the second insulating layer includes an organic material. The first insulating layer is closer to the substrate than the second insulating layer. The display panel further includes a connecting electrode located between the first insulating layer and the second insulating layer. The connecting electrode is connected to the pixel circuit through a first via penetrating the first insulating layer. The first electrode of the light-emitting element is connected through a via penetrating the second insulating layer. The second via is connected to the connection electrode. The pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first electrode and a second electrode. The first electrode of the storage capacitor is connected to the gate of the driving transistor, and the second electrode of the storage capacitor is connected to the first electrode of the driving transistor. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode is disposed in the same layer as the channel of the driving transistor. The second electrode is closer to the substrate than the first electrode. The ratio of the maximum size of the second via along the second direction to the maximum size of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0058] For example, the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the pixel opening on the substrate.

[0059] For example, the pixel opening is configured to define the light-emitting area of ​​the sub-pixel, a first defining portion is provided between two adjacent pixel openings in a first direction, and a second defining portion is provided between two adjacent pixel openings in a second direction. The first direction intersects the second direction, and the thickness of the first defining portion is not equal to the thickness of the second defining portion. The light-emitting element also has a second electrode and a light-emitting functional layer located between the first electrode and the second electrode. The first electrode of the light-emitting element is closer to the substrate than at least a portion of the second electrode of the light-emitting element.

[0060] Embodiments of this disclosure also provide a display panel, including: a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a pixel aperture, a pixel circuit, and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, the display panel further including an insulating material layer, the insulating material layer being located on the side of the pixel circuit facing away from the substrate, the insulating material layer including a first insulating layer and a second insulating layer, the first insulating layer including an organic material, the second insulating layer including an organic material, the first insulating layer being closer to the substrate than the second insulating layer, the display panel further including a connecting electrode, the connecting electrode being located between the first insulating layer and the second insulating layer, the connecting electrode being connected to the pixel circuit through a first via penetrating the first insulating layer, the first electrode of the light-emitting element having a first electrode. The electrode is connected to the connecting electrode through a second via penetrating the second insulating layer. The display panel further includes a barrier dam and an encapsulation layer. The encapsulation layer is configured to encapsulate the light-emitting element. The encapsulation layer includes a stack of inorganic and organic encapsulation films. An encapsulating adhesive is provided on the outer side of the encapsulation layer. The second insulating layer includes a planarization layer. The planarization layer includes a first planar portion and a second planar portion. A groove is provided between the first planar portion and the second planar portion. The barrier dam is located outside the display area of ​​the display panel. The orthographic projection of the barrier dam on the substrate covers the orthographic projection of the groove on the substrate. The ratio of the maximum size of the second via along the second direction to the maximum size of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0061] Embodiments of this disclosure also provide a display panel, including: a substrate and a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a pixel aperture, a pixel circuit, and a light-emitting element connected to the pixel circuit. The light-emitting element has a first electrode. The display panel further includes an insulating material layer located on the side of the pixel circuit facing away from the substrate. The insulating material layer includes a first insulating layer and a second insulating layer. The first insulating layer includes an organic material, and the second insulating layer includes an organic material. The first insulating layer is closer to the substrate than the second insulating layer. The display panel further includes a connecting electrode located between the first insulating layer and the second insulating layer. The connecting electrode is connected to the pixel circuit through a first via penetrating the first insulating layer. The first electrode of the light-emitting element is connected to the connecting electrode through a second via penetrating the second insulating layer. The display panel also includes data lines, a first gate line, a second gate line, and a first initial... The pixel circuit further includes a data writing transistor and a first reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second terminal of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line. The first terminal of the first reset transistor is connected to the first initialization line, the second terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The display panel has a dummy sub-pixel near its edge. The dummy sub-pixel has a dummy driving transistor and a first dummy reset transistor. The gate of the first dummy reset transistor is connected to the gate of the dummy driving transistor, and the first dummy reset transistor is disconnected from the first initialization line. The ratio of the maximum size of the second via along the second direction to the maximum size of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0062] Embodiments of this disclosure also provide a display panel, including: a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a pixel opening, a pixel circuit, and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, the display panel further including an insulating material layer, the insulating material layer being located on the side of the pixel circuit facing away from the substrate, the insulating material layer including a first insulating layer and a second insulating layer, the first insulating layer including an organic material, the second insulating layer including an organic material, the first insulating layer being closer to the substrate than the second insulating layer, the display panel further including a connecting electrode, the connecting electrode being located between the first insulating layer and the second insulating layer, the connecting electrode being connected to the pixel circuit through a first via penetrating the first insulating layer, the first electrode of the light-emitting element being connected to the connecting electrode through a second via penetrating the second insulating layer, the light-emitting functional layer covering the sidewall of the first defining portion and covering the sidewall of the second defining portion, wherein the ratio of the maximum size of the second via along the second direction to the maximum size of the pixel opening along the second direction is greater than or equal to 0.05 and less than or equal to 0.48.

[0063] Embodiments of this disclosure also provide that the thickness of the first defining portion is less than the thickness of the second defining portion, and the light-emitting functional layer further includes a portion covering the top wall of the first defining portion. Embodiments of this disclosure also provide a display device including any of the above-described display panels. Attached Figure Description

[0064] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0065] Figure 1 is a schematic diagram of a via for connecting pixel circuits and light-emitting elements in a display panel.

[0066] Figure 2 is a schematic diagram of a via for connecting pixel circuits and light-emitting elements in a display panel according to an embodiment of the present disclosure.

[0067] Figure 3 is a plan view of a partial structure of a display panel provided in an embodiment of this disclosure.

[0068] Figure 4 is a plan view of a pixel delimiting layer in a display panel provided by an embodiment of the present disclosure.

[0069] Figure 5 is a schematic diagram of a display panel provided in an embodiment of this disclosure.

[0070] Figure 6 is a plan view of a pixel delimiting layer in another display panel provided by an embodiment of the present disclosure.

[0071] Figure 7 is a plan view of a partial structure of a display panel provided in an embodiment of this disclosure.

[0072] Figure 8 is a circuit diagram of a display panel provided in an embodiment of the present disclosure.

[0073] Figure 9 is a circuit diagram of a display panel provided in another embodiment of this disclosure.

[0074] Figure 10 is a layout diagram of a display panel provided in an embodiment of this disclosure.

[0075] Figures 11A to 11D are single-layer diagrams of the display panel shown in Figure 10.

[0076] Figure 12 shows a display panel provided in an embodiment of this disclosure.

[0077] Figure 13 is a plan view of the conductive pattern layer LYm, via VH1, via VH2, first electrode layer LY3, and pixel openings in the display panel shown in Figure 12.

[0078] Figure 14 is a schematic diagram of a partial structure of a display panel provided in an embodiment of this disclosure.

[0079] Figure 15 is a plan view of the connecting electrodes in the display panel shown in Figure 14.

[0080] Figure 16A is a schematic diagram of a partial structure of a display panel provided in an embodiment of this disclosure.

[0081] Figure 16B is a plan view of the connection electrodes in the display panel shown in Figure 16A.

[0082] Figure 17A is a schematic diagram of a partial structure of a display panel provided in an embodiment of this disclosure.

[0083] Figure 17B is a plan view of the connecting electrodes in the display panel shown in Figure 17A.

[0084] Figure 18 is a partial schematic diagram of the conductive pattern layer LYm of a display panel provided in an embodiment of the present disclosure.

[0085] Figure 19 is a partial schematic diagram of a conductive pattern layer LYm in a display panel according to an embodiment of the present disclosure.

[0086] Figure 20 is a plan view of a portion of the structure of a display panel provided in an embodiment of this disclosure.

[0087] Figure 21 is a plan view of a partial structure in a display panel according to another embodiment of the present disclosure.

[0088] Figure 22 is a partial schematic diagram of a conductive pattern layer LYm in a display panel according to an embodiment of the present disclosure.

[0089] Figure 23 is a partial schematic diagram of the conductive pattern layer LYm in another display panel provided in an embodiment of the present disclosure.

[0090] Figure 24 is a partial schematic diagram of the conductive pattern layer LYm in another display panel provided in an embodiment of the present disclosure.

[0091] Figure 25 is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure.

[0092] Figure 26 is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure.

[0093] Figure 27 is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure.

[0094] Figure 28 is a plan view of a partial structure of another display panel provided in an embodiment of the present disclosure.

[0095] Figure 29 is a plan view of a partial structure of another display panel provided in an embodiment of the present disclosure.

[0096] Figure 30 is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure.

[0097] Figure 31 is a plan view of a partial structure of another display panel provided in an embodiment of this disclosure.

[0098] Figure 32A is a plan view of a partial structure of another display panel provided in an embodiment of this disclosure.

[0099] Figure 32B is a plan view of a partial structure of another display panel provided in an embodiment of this disclosure.

[0100] Figure 33 is a layout diagram of another display panel provided in an embodiment of this disclosure.

[0101] Figures 34 to 41 are cross-sectional views of partial structures of several display panels provided in some embodiments of this disclosure.

[0102] Figure 42 is a plan view of a display panel provided in an embodiment of the present disclosure.

[0103] Figure 43 is a schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0104] Figure 44 is a schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0105] Figures 45 to 49 are schematic diagrams of several display panels provided in embodiments of this disclosure.

[0106] Figure 50 is a schematic diagram of a display panel provided in an embodiment of this disclosure.

[0107] Figure 51 is a schematic diagram of a display panel provided in an embodiment of this disclosure.

[0108] Figure 52 is a schematic diagram of a display panel provided in an embodiment of the present disclosure.

[0109] Figure 53 is a circuit diagram of a dummy sub-pixel in a display panel according to an embodiment of the present disclosure.

[0110] Figure 54 is a layout diagram of a dummy pixel circuit in a display panel according to an embodiment of the present disclosure.

[0111] Figure 55 is a schematic diagram of a display panel provided in an embodiment of this disclosure.

[0112] Figure 56 is a schematic diagram of a display panel provided in an embodiment of this disclosure. Detailed Implementation

[0113] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0114] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0115] In typical OLED display devices, the organic light-emitting layer needs to be deposited using a vapor deposition process, which has stringent requirements and is difficult to scale up to a large area.

[0116] Using inkjet printing to fabricate the OLED luminescent material layer is the best way to achieve low-cost OLED display panel production and enable OLED display devices to compete in the mid-to-high-end market. Inkjet printing is a highly efficient process; compared to vapor deposition, it wastes less material and is extremely fast.

[0117] In inkjet printing to form the light-emitting functional layer of an organic light-emitting diode (OLED), a solvent is primarily used to dissolve the organic material to form a solution (ink). This solution (ink) is then directly sprayed onto the surface of a substrate to form the light-emitting functional layer for sub-pixels such as red (R), green (G), and blue (B). Inkjet printing OLED technology has significant advantages over vapor deposition technology in terms of manufacturing process, yield, and cost. For example, the light-emitting functional layer includes multiple film layers, such as a light-emitting layer (light-emitting material layer). The light-emitting functional layer can also include other film layers, such as at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The film layers of the organic light-emitting functional layer can be selected as needed. At least one film layer in the light-emitting functional layer can be fabricated using an inkjet printing process.

[0118] Due to the large molecular weight of polymers, solution processing, such as spin coating or printing, is the primary method for forming films. Inkjet printing is the optimal method for preparing polymer solutions. In recent years, significant efforts have been made to improve the pixel resolution, film uniformity, and lifespan of display panels, leading to increasingly active research on inkjet printing for optoelectronic materials. For example, hole transport layers, hole injection layers, and light-emitting layers in display panels can all be prepared using inkjet printing technology, laying the foundation for the full printing method of display panel fabrication.

[0119] When using inkjet printing to fabricate the emissive layer, a high degree of flatness is required. The flatter the emissive layer in each sub-pixel, the less or no color shift can be achieved, resulting in a better display panel performance. Achieving a flat emissive layer can be done by adjusting the structure of the display panel.

[0120] Figure 1 is a schematic diagram of a via for connecting a pixel circuit and a light-emitting element in a display panel. As shown in Figure 1, a sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is electrically connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area.

[0121] As shown in Figure 1, the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The light-emitting element 100b is connected to the pixel circuit 100a through a via VH. As shown in Figure 1, the first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a through a via VH that penetrates the insulating layer ISL.

[0122] As shown in Figure 1, the insulating layer ISL comprises a planarization layer PLN and a passivation layer PVX. The passivation layer PVX is made of an inorganic insulating material, and the planarization layer PLN is made of an organic insulating material. For example, the thickness of the planarization layer PLN is 3-7 micrometers, and typically the thickness of the planarization layer PLN is about 4 micrometers. Figure 1 also shows other structures, for which reference can be made to the description of Figure 2 below.

[0123] Display panels manufactured using inkjet printing have a relatively thick planarization layer (PLN) and a large via size (VH). As shown in Figure 1, the size of the via VH is approximately 15-20 μm. This large VH size is detrimental to subpixel planarization and hinders the achievement of high-resolution products.

[0124] Embodiments of this disclosure provide a display panel and a display device including the display panel, reducing the size of vias used to connect pixel circuits and light-emitting elements to facilitate the flatness of sub-pixels and to facilitate obtaining high-resolution products.

[0125] Figure 2 is a schematic diagram of vias for connecting pixel circuits and light-emitting elements in a display panel according to an embodiment of the present disclosure. Figure 3 is a plan view of a partial structure of a display panel according to an embodiment of the present disclosure. The structure below the connecting electrode 80 is omitted in Figure 3. Figure 4 is a plan view of a pixel defining layer in a display panel according to an embodiment of the present disclosure. Figure 5 is a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0126] As shown in Figures 2 to 5, embodiments of this disclosure provide a display panel, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS. Each sub-pixel 100 includes a pixel opening P0, which is configured to define a light-emitting area of ​​the sub-pixel 100. A first defining portion 301 is disposed between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is disposed between two adjacent pixel openings P0 in a second direction X. The first direction Y intersects the second direction X. The thicknesses of the first defining portion 301 and the second defining portion 302 are not equal. As shown in Figure 2, the thickness of the first defining portion 301 is Ha, and the thickness of the second defining portion 302 is Hb, where Ha ≠ Hb.

[0127] As shown in Figure 2, the sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b connected to the pixel circuit 100a. The light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of the light-emitting element 100b is closer to the substrate BS than the light-emitting functional layer FL.

[0128] As shown in Figure 2, the display panel also includes an insulating material layer 60. The insulating material layer 60 is located on the side of the pixel circuit 100a away from the substrate BS. The insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602. The first insulating layer 601 includes an organic material, and the second insulating layer 602 includes an organic material. The first insulating layer 601 is closer to the substrate BS than the second insulating layer 602.

[0129] As shown in Figure 2, the display panel also includes a connection electrode 80, which is located between the first insulating layer 601 and the second insulating layer 602. The connection electrode 80 is connected to the pixel circuit 100a through a first via VH1 penetrating the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected to the connection electrode 80 through a second via VH2 penetrating the second insulating layer 602.

[0130] The display panel provided in the embodiments of this disclosure, by providing a first insulating layer 601 and a second insulating layer 602, and providing a connecting electrode 80 between the first insulating layer 601 and the second insulating layer 602, can reduce the size of the second via VH2, which is beneficial for the flatness of the sub-pixels, improving the display effect, and obtaining high-resolution products.

[0131] As shown in Figures 3 and 4, the ratio of the maximum size X22 of the second via VH2 along the second direction X to the maximum size DPX of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0132] For example, the ratio of the maximum size X22 of the second via VH2 along the second direction X to the maximum size DPX of the pixel opening P0 along the second direction X is greater than or equal to 0.12 and less than or equal to 0.24.

[0133] For example, the ratio of the maximum dimension Y22 of the second via VH2 along the first direction Y to the maximum dimension DPY of the pixel opening P0 along the first direction Y is greater than or equal to 0.05 and less than or equal to 0.24.

[0134] For example, the ratio of the maximum size of the second via VH2 along the first direction Y to the maximum size of the pixel opening P0 along the first direction Y is greater than or equal to 0.08 and less than or equal to 0.18.

[0135] For example, in some embodiments, the display panel includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel. For the blue sub-pixel, the red sub-pixel, and the green sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 7.7 μm. For the blue sub-pixel, the maximum dimension DPX of the pixel aperture P0 along the second direction X is 57 μm, and the maximum dimension DPY of the pixel aperture P0 along the first direction Y is 57 μm. For the red sub-pixel, the maximum dimension DPX of the pixel aperture P0 along the second direction X is 45 μm, and the maximum dimension DPY of the pixel aperture P0 along the first direction Y is 45 μm. For the green sub-pixel, the maximum dimension DPX of the pixel aperture P0 along the second direction X is 32 μm, and the maximum dimension DPY of the pixel aperture P0 along the first direction Y is 32 μm.

[0136] In some embodiments, as shown in Figures 3 and 4, the maximum dimension X22 of the second via VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 57 μm.

[0137] In some embodiments, as shown in Figures 3 and 4, the maximum dimension Y22 of the second via VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 57 μm.

[0138] In some embodiments, as shown in Figures 3 and 4, for the blue sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 57 μm. X22 / DPX = 7.7 / 57 = 0.135.

[0139] In some embodiments, as shown in Figures 3 and 4, for the red sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 45 μm. X22 / DPX = 7.7 / 45 = 0.171.

[0140] In some embodiments, as shown in Figures 3 and 4, for the green sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 7.7 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm. X22 / DPX = 7.7 / 32 = 0.241.

[0141] For example, as shown in Figures 3 and 4, for the blue sub-pixel, the maximum dimension Y22 of the second via VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 57 μm. Y22 / DPY = 7.7 / 57 = 0.135. For example, as shown in Figures 3 and 4, for the red sub-pixel, the maximum dimension Y22 of the second via VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 45 μm. Y22 / DPY = 7.7 / 45 = 0.171.

[0142] For example, as shown in Figures 3 and 4, for the green sub-pixel, the maximum dimension Y22 of the second via VH2 along the first direction Y is 7.7 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 32 μm. Y22 / DPY=7.7 / 32=0.241.

[0143] For example, in some embodiments, the display panel includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel. For the blue sub-pixel, the red sub-pixel, and the green sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 18.6 μm. For the blue sub-pixel, the maximum dimension DPX of the pixel aperture P0 along the second direction X is 65 μm, and the maximum dimension DPY of the pixel aperture P0 along the first direction Y is 145 μm. For the red sub-pixel, the maximum dimension DPX of the pixel aperture P0 along the second direction X is 32 μm, and the maximum dimension DPY of the pixel aperture P0 along the first direction Y is 145 μm. For the green sub-pixel, the maximum dimension DPX of the pixel aperture P0 along the second direction X is 32 μm, and the maximum dimension DPY of the pixel aperture P0 along the first direction Y is 145 μm.

[0144] In other embodiments, as shown in Figures 3 and 4, for the blue sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 18.6 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 65 μm. X22 / DPX = 18.6 / 65 = 0.286.

[0145] In other embodiments, as shown in Figures 3 and 4, for the red sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 18.6 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm. X22 / DPX = 18.6 / 32 = 0.581.

[0146] In other embodiments, as shown in Figures 3 and 4, for the green sub-pixel, the maximum dimension X22 of the second via VH2 along the second direction X is 18.6 μm, and the maximum dimension DPX of the pixel opening P0 along the second direction X is 32 μm. X22 / DPX = 18.6 / 32 = 0.581.

[0147] For example, as shown in Figures 3 and 4, for the blue sub-pixel, the maximum dimension Y22 of the second via VH2 along the first direction Y is 18.6 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm. Y22 / DPY=18.6 / 145=0.128.

[0148] For example, as shown in Figures 3 and 4, for the red sub-pixel, the maximum dimension Y22 of the second via VH2 along the first direction Y is 18.6 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm. Y22 / DPY=18.6 / 145=0.128.

[0149] For example, as shown in Figures 3 and 4, for the green sub-pixel, the maximum dimension Y22 of the second via VH2 along the first direction Y is 18.6 μm, and the maximum dimension DPY of the pixel opening P0 along the first direction Y is 145 μm. Y22 / DPY=18.6 / 145=0.128.

[0150] The above description uses a display panel comprising blue, red, and green sub-pixels as an example, but this disclosure is not limited thereto. The blue, red, and green sub-pixels can also be replaced with sub-pixels of other suitable colors. That is, the embodiments of this disclosure do not limit the emission color of the sub-pixels.

[0151] It should be noted that the pixel arrangement structure is not limited to that shown in Figure 4. The embodiments of this disclosure do not limit the pixel arrangement structure of the display panel.

[0152] Figure 4 illustrates an example where the maximum length of pixel opening P0 along the first direction Y is taken as the maximum length, and the maximum width of pixel opening P0 along the second direction X is taken as the maximum width. For example, in other pixel arrangements, the maximum size of pixel opening P0 along the first direction Y or the maximum size of pixel opening P0 along the second direction X DPX can also be the diagonal of pixel opening P0. Of course, embodiments of this disclosure include, but are not limited to, this.

[0153] In the embodiments of this disclosure, the second via VH2 may or may not overlap with the pixel opening P0. Whether the second via VH2 overlaps with the pixel opening P0 mainly depends on the flatness of the pixel opening P0 and the pixel density. Generally speaking, the flatness of the pixel opening P0 is given priority. For example, the second via VH2 may not overlap with the pixel opening P0, but the flatness of the pixel opening P0 may not be affected, in which case the second via VH2 may overlap with the pixel opening P0.

[0154] For example, as shown in Figures 2 to 5, the display panel also includes a pixel definition layer (PDL), which includes a definition portion 300. The pixel opening P0 is defined by the definition portion 300, and the definition portion 300 includes a first definition portion 301 and a second definition portion 302.

[0155] For example, as shown in Figure 2, the thickness of the first defining portion 301 is less than the thickness of the second defining portion 302. As shown in Figure 2, the thickness of the first defining portion 301 is Ha, and the thickness of the second defining portion 302 is Hb, where Ha is less than Hb.

[0156] In embodiments of this disclosure, the thickness of a component may refer to the dimension of the component in the third direction Z.

[0157] For example, the thickness of the first defining portion 301 is the maximum dimension of the first defining portion 301 in the third direction Z. For example, the thickness of the second defining portion 302 is the maximum dimension of the second defining portion 302 in the third direction Z.

[0158] In some of the accompanying drawings of embodiments of this disclosure, a plan view shows a first direction Y and a second direction X, and a cross-sectional view shows a third direction Z. The first direction Y intersects the second direction X; for example, the first direction Y is perpendicular to the second direction X. The third direction Z is perpendicular to the second direction X and perpendicular to the first direction Y. Both the first direction Y and the second direction X are parallel to the main surface of the substrate. The third direction Z may be perpendicular to the main surface of the substrate. The main surface of the substrate is the surface used to fabricate various components. In Figure 2, the upper surface of the substrate BS is the main surface of the substrate.

[0159] The display panel provided in the embodiments of this disclosure employs a first defining portion 301 and a second defining portion 302 of different thicknesses, which facilitates the fabrication of at least one film layer in the light-emitting functional layer using inkjet printing technology.

[0160] For example, as shown in Figure 2, the thickness of the first insulating layer 601 is less than or equal to the thickness of the second insulating layer 602.

[0161] In the display panel provided by the embodiments of this disclosure, the second insulating layer 602 may have the same thickness as the first insulating layer 601 or may have a thickness greater than the first insulating layer 601, so as to facilitate the flatness of the first electrode of the light-emitting element and improve the display effect.

[0162] For example, as shown in Figure 2, the thickness of the first insulating layer 601 is less than or equal to 2 micrometers, and the thickness of the second insulating layer 602 is less than or equal to 2 micrometers.

[0163] Figure 2 shows an example where the first insulating layer 601 includes a passivation layer PVX and a planarization layer PLN1. Figure 2 also shows an example where the second insulating layer 602 includes a planarization layer PLN2. In other embodiments, the second insulating layer 602 may also include a passivation layer located between the connecting electrode 80 and the planarization layer PLN2. The passivation layer protects the underlying conductive layer, while the planarization layer provides planarization. Of course, in other embodiments, the first insulating layer 601 may include a passivation layer, a planarization layer PLN1, and another passivation layer, while the second insulating layer 602 includes a planarization layer PLN2. That is, compared to the embodiment shown in Figure 2, a passivation layer is additionally provided between the connecting electrode 80 and the planarization layer PLN1.

[0164] The display panel provided in the embodiments of this disclosure has a first insulating layer 601, a connecting electrode 80, and a second insulating layer 602 disposed between the pixel circuit and the light-emitting element. Therefore, compared with the disposal of a single planarization layer, the thickness of the first insulating layer 601 and the thickness of the second insulating layer 602 can be set relatively small, which is beneficial for forming a smaller second via VH2.

[0165] Figure 2 also shows the substrate BS, barrier layer BR, buffer layer BF, gate insulating layer GI, and interlayer insulating layer ILD.

[0166] Figure 2 also shows the encapsulation layer EPS. The encapsulation layer EPS includes an inorganic encapsulation film EPS1, an organic encapsulation film EPS2, and an inorganic encapsulation film EPS3. As shown in Figure 2, the organic encapsulation film EPS2 is located between the inorganic encapsulation films EPS1 and EPS3. It should be noted that the stacking order of the organic and inorganic encapsulation films is not limited to that shown in the figure, and the structure of the encapsulation layer EPS is not limited to that shown in the figure.

[0167] For example, as shown in Figure 4, the size of the first via VH1 is less than or equal to 10 micrometers, and the size of the second via VH2 is less than or equal to 10 micrometers.

[0168] For example, as shown in Figure 4, the size of the first via VH1 is less than or equal to 5 micrometers, and the size of the second via VH2 is less than or equal to 5 micrometers.

[0169] For example, as shown in Figure 4, the size of the first via VH1 is greater than or equal to 2 micrometers, and the size of the second via VH2 is greater than or equal to 2 micrometers.

[0170] In some embodiments, the size of the first via VH1 is greater than or equal to 2 micrometers and less than or equal to 10 micrometers; the size of the second via VH2 is greater than or equal to 2 micrometers and less than or equal to 10 micrometers.

[0171] In some embodiments, the size of the first via VH1 is greater than or equal to 2 micrometers and less than or equal to 5 micrometers; the size of the second via VH2 is greater than or equal to 2 micrometers and less than or equal to 5 micrometers.

[0172] For example, in an embodiment of this disclosure, the size of the second via VH2 may be less than or equal to the size of the first via VH1.

[0173] The dimension of the first via VH1 can refer to the maximum dimension of the first via VH1. The dimension of the second via VH2 can refer to the maximum dimension of the second via VH2.

[0174] For example, as shown in Figures 4 and 5, the pixel definition layer (PDL) includes multiple first definition portions 301 and multiple second definition portions 302. The multiple second definition portions 302 are arranged along a second direction X and extend along a first direction Y. The multiple first definition portions 301 are configured as multiple groups 0301, with each group of first definition portions 0301 located between two adjacent second definition portions 302. The first definition portions 301 extend along the second direction X, and the first definition portions 301 in each group are arranged along the first direction Y. Figure 4 shows three groups of first definition portions 0301.

[0175] As shown in Figure 4, a groove G0 is formed between two adjacent second defining portions 302. Each groove G0 extends along the first direction Y, and ink flows in the groove during inkjet printing. Figure 4 shows three columns of grooves G0. Taking the first direction Y as the column direction and the second direction X as the row direction as an example, the display panel includes multiple columns of grooves. One column of grooves defines multiple pixel openings P0.

[0176] As shown in Figure 5, the substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. As shown in Figure 5, the orthographic projection of the portion DT01 of the data line DT located in the display area R01 onto the substrate BS lies within the orthographic projection of the second defining portion 302 onto the substrate BS. The orthographic projection of the data line DT onto the substrate BS overlaps with the orthographic projection of the second defining portion 302 of the pixel defining layer PDL onto the substrate BS, allowing the second defining portion 302 to have a protrusion, facilitating ink flow into the pixel opening P0 in the pixel defining layer during inkjet printing. As shown in Figure 5, the orthographic projection of the display area R01 onto the substrate BS overlaps with the orthographic projection of the pixel defining layer PDL onto the substrate BS. The orthographic projection of the pixel opening P0 of the pixel defining layer PDL onto the substrate BS falls within the orthographic projection of the display area R01 onto the substrate BS.

[0177] Figure 5 shows only two data lines DT. For example, a second defining part 302 may correspond to one data line, but is not limited to this.

[0178] For example, as shown in Figure 5, a first defining portion 301 is provided between two adjacent pixel openings P0 in the first direction Y, and a second defining portion 302 is provided between two adjacent pixel openings P0 in the second direction X, wherein the first direction Y intersects the second direction X.

[0179] As shown in Figures 4 and 5, the pixel opening P0 of sub-pixel 100 includes pixel opening P01 of first sub-pixel 101, pixel opening P02 of second sub-pixel 102, and pixel opening P03 of third sub-pixel 103. For example, as shown in Figures 4 and 5, the pixel opening P0 of each sub-pixel has the same shape and size. Of course, in other embodiments, the shape and size of the pixel opening P0 of different sub-pixels can be determined as needed.

[0180] Figure 6 is a plan view of a pixel demarcation layer in a display panel according to an embodiment of the present disclosure. Unlike Figure 4, in the embodiment shown in Figure 6, the pixel opening P01 of the first sub-pixel 101, the pixel opening P02 of the second sub-pixel 102, and the pixel opening P03 of the third sub-pixel 103 have different sizes. For example, the area of ​​the pixel opening P01 of the first sub-pixel 101 is smaller than the area of ​​the pixel opening P02 of the second sub-pixel 102, and the area of ​​the pixel opening P02 of the second sub-pixel 102 is smaller than the area of ​​the pixel opening P03 of the third sub-pixel 103.

[0181] As shown in Figures 4 and 6, the pixel openings P01 of multiple first sub-pixels 101 have the same area, the pixel openings P02 of multiple second sub-pixels 102 have the same area, and the pixel openings P03 of multiple third sub-pixels 103 have the same area. That is, the pixel openings P0 of sub-pixels emitting the same color of light have the same area, while the pixel openings P0 of sub-pixels emitting different colors of light can be the same or different.

[0182] The embodiments of this disclosure use a first sub-pixel 101 as a red sub-pixel, a second sub-pixel 102 as a green sub-pixel, and a third sub-pixel 103 as a blue sub-pixel as an example for illustration. Of course, the embodiments of this disclosure do not limit the light emission of each sub-pixel, and other colors of light can be emitted as needed.

[0183] Figure 7 is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure. The structure located below the connecting electrode 80 is omitted in Figure 7.

[0184] For example, referring to Figures 2 and 7, multiple second vias VH2 are provided. The first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through multiple second vias VH2 penetrating the second insulating layer 602. The multiple second vias VH2 are located at the edge of the pixel opening P0. As shown in Figure 7, the same first electrode E1 is connected to the same connecting electrode 80 through multiple second vias VH2 penetrating the second insulating layer 602. That is, compared with the embodiment shown in Figure 3, in the display panel provided by the embodiment shown in Figure 7, the same first electrode E1 is connected to the same connecting electrode 80 through multiple second vias VH2, and the multiple vias are located at the edge of the pixel opening P0.

[0185] Therefore, in the display panel provided in some embodiments of this disclosure, multiple second vias VH2 are provided for the same first electrode E1 to improve the stability of the connection, and the multiple second vias VH2 are distributed at the edge of the pixel opening P0 to reduce the impact of the second vias VH2 on the flatness of the sub-pixels, improve the display quality, and facilitate the acquisition of high-resolution products.

[0186] As shown in Figure 7, four second vias VH2 are provided for the same first electrode E1, and the four second vias VH2 are located at the four corners of the pixel opening P0.

[0187] In Figure 7, the second via VH2 slightly overlaps with the pixel opening P0. Of course, the second via VH2 may not overlap with the pixel opening P0, or it may have a larger overlap area. Depending on the wiring design around the second via VH2, the overlap between the second via VH2 and the pixel opening P0 can be designed independently to balance flatness.

[0188] In embodiments of this disclosure, when multiple second vias VH2 are provided for the same first electrode E1, the size of the second via VH2 can be the same as the size when only one second via VH2 is provided. The size of the second via VH2 is mainly limited by the thickness of the second insulating layer and the via formation process.

[0189] For example, as shown in Figure 7, the size of each of the multiple second vias VH2 is less than or equal to 10 micrometers.

[0190] For example, as shown in Figures 3 and 7, the orthographic projection of the connecting electrode 80 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 of the sub-pixel 100 on the substrate BS. Thus, the connecting electrode 80 can function as a light-emitting element for leveling the sub-pixel.

[0191] For example, as shown in Figures 3 and 7, the orthogonal projection of the connecting electrode 80 onto the substrate BS covers the orthogonal projection of the pixel opening P0 of the sub-pixel 100 onto the substrate BS. Therefore, the connecting electrode 80 can better function as a leveling element for the sub-pixel's light-emitting components.

[0192] Figure 8 is a circuit diagram of a display panel according to an embodiment of the present disclosure. Figure 9 is a circuit diagram of a display panel according to another embodiment of the present disclosure. Figure 10 is a layout diagram of a display panel according to an embodiment of the present disclosure. Figures 11A to 11D are single-layer diagrams of the display panel shown in Figure 10. Figure 11A is a plan view of the active layer LY0 in the display panel shown in Figure 10. Figure 11B is a plan view of the first conductive pattern layer LY1 in the display panel shown in Figure 10. Figure 11C is a plan view of the interlayer insulating layer ILD in the display panel shown in Figure 10. Figure 11D is a plan view of the second conductive pattern layer LY2 in the display panel shown in Figure 10. Figure 11C shows the interlayer insulating layer ILD with vias in the interlayer insulating layer ILD. Figure 1 is a cross-sectional view of the display panel shown in Figure 10 along line A3-A4.

[0193] As shown in Figures 8 and 9, each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is electrically connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area.

[0194] Figure 8 shows the pixel circuitry and light-emitting elements in a single sub-pixel. Figure 9 shows three sub-pixels. The three sub-pixels in Figure 9 are located in a row.

[0195] For example, as shown in Figures 8 and 9, in sub-pixel 100, pixel circuit 100a includes a data writing transistor T1, a reset transistor T2, a driving transistor T3, and a storage capacitor Cst. Light-emitting element 100b is connected to the driving transistor T3. The reset transistor T2 is configured to reset the gate T3g of the driving transistor T3. As shown in Figures 8 and 9, the storage capacitor Cst includes a first terminal C1 and a second terminal C2.

[0196] For example, as shown in Figures 8 and 9, the display panel includes gate line G1, gate line G2, data line DT, first power line PL1, second power line PL2, initialization line INT1, etc. Gate line G2 can also be called a reset control signal line. For example, the first power line PL1 is configured to provide a constant first voltage signal VDD to the sub-pixel 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the sub-pixel 100, for example, the first voltage signal VDD is greater than the second voltage signal VSS. Gate line G1 is configured to provide a scan signal SCAN to the sub-pixel 100, gate line G2 is configured to provide a reset control signal RESET1 to the sub-pixel 100, and data line DT is configured to provide a data signal (data voltage) DATA to the sub-pixel 100. Initialization line INT1 is configured to provide an initialization voltage Vinit1 to the sub-pixel 100.

[0197] As shown in Figures 8 and 9, the driving transistor T3 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0198] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), which emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100a.

[0199] As shown in Figures 8 and 9, the display panel also includes a gate line G5 and a light-emitting control transistor T5. The gate line G5 is configured to provide a light-emitting control signal EM to the light-emitting control transistor T5. The second terminal T3b of the driving transistor T3 is connected to the first power supply line PL1 through the light-emitting control transistor T5.

[0200] For example, as shown in Figures 8 and 9, the first terminal T5a of the light-emitting control transistor T5 is connected to the first power supply line PL1, the second terminal T5b of the light-emitting control transistor T5 is connected to the second terminal T3b of the driving transistor T3, and the gate T5g of the light-emitting control transistor T5 is connected to the gate line G5.

[0201] For example, as shown in Figures 8 and 9, the first electrode E1 of the light-emitting element 100b is connected to the first electrode T3a of the driving transistor T3, the second electrode E2 of the light-emitting element 100b is connected to the second power supply line PL2, the second electrode T3b of the driving transistor T3 is connected to the first power supply line PL1 through the light-emitting control transistor T5, the gate T3g of the driving transistor T3 is connected to the second electrode T1b of the data writing transistor T1, the first electrode T1a of the data writing transistor T1 is connected to the data line DT, and the gate T1g of the data writing transistor T1 is connected to the gate line G1. It should be noted that the pixel circuit may also omit the light-emitting control transistor T5; in this case, the second electrode T3b of the driving transistor T3 is directly connected to the first power supply line PL1.

[0202] For example, as shown in Figures 8 and 9, the gate T3g of the driving transistor T3 is connected to the first terminal C1 of the storage capacitor Cst, and the second terminal C2 of the storage capacitor Cst is connected to the first terminal T3a of the driving transistor T3. The first terminal C1 of the storage capacitor Cst is also connected to the second terminal T1b of the data writing transistor T1.

[0203] For example, as shown in Figures 8 and 9, the first terminal T2a of the reset transistor T2 is connected to the initialization line INT1, the second terminal T2b of the reset transistor T2 is connected to the gate T3g of the driving transistor T3, and the gate T2g of the reset transistor T2 is connected to the gate line G2. The first terminal C1 of the storage capacitor Cst is also connected to the second terminal T2b of the reset transistor T2.

[0204] For example, as shown in Figures 8 and 9, the display panel also includes a reset transistor T4, which is configured to reset the first electrode E1 of the light-emitting element 100b.

[0205] For example, as shown in Figures 8 and 9, the display panel also includes gate line G4, which can also be referred to as the reset control signal line. Gate line G4 is configured to provide a reset control signal RESET2 to the reset transistor T4.

[0206] For example, as shown in Figures 8 and 9, the display panel also includes an initialization line INT2, which is configured to provide an initialization voltage Vinit2 to the reset transistor T4.

[0207] For example, as shown in Figures 8 and 9, the first electrode T4a of the reset transistor T4 is connected to the initialization line INT2, the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b, and the gate T4g of the reset transistor T4 is connected to the gate line G4.

[0208] For example, as shown in Figures 8 and 9, the second terminal T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b through the driving transistor T3, the first terminal T3a of the driving transistor T3 is connected to the first electrode E1 of the light-emitting element 100b, and the second terminal T3b of the driving transistor T3 is connected to the second terminal T4b of the reset transistor T4.

[0209] For example, the initialization voltages Vinit1 and Vinit2 are constant voltage signals, and their magnitudes may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the initialization voltages Vinit1 and Vinit2 may both be less than or equal to the second voltage signal VSS.

[0210] For example, in some embodiments of this disclosure, initialization line INT1 and initialization line INT2 are connected and both are configured to provide the same initialization voltage, i.e., initialization voltage Vinit1 and initialization voltage Vinit2 are equal, but this is not a limitation. In other embodiments, initialization line INT1 and initialization line INT2 are insulated from each other to provide different initialization voltages.

[0211] For example, as shown in Figures 8 and 9, the gate T3g of the driving transistor T3, the first terminal C1 of the storage capacitor Cst, the second terminal T1b of the data writing transistor T1, and the second terminal T2b of the reset transistor T2 are connected to each other and are all connected to node N1 at the same potential.

[0212] For example, as shown in Figures 8 and 9, the second terminal C2 of the storage capacitor Cst, the first electrode E1 of the light-emitting element 100b, and the first terminal T3a of the driving transistor T3 are connected to each other and are all connected to node N2 at the same potential.

[0213] For example, as shown in Figures 8 and 9, the second terminal T5b of the light-emitting control transistor T5, the second terminal T4b of the reset transistor T4, and the second terminal T3b of the driving transistor T3 are connected to each other and are all connected to node N3 at the same potential.

[0214] For example, as shown in Figure 9, multiple sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged sequentially along the second direction X. Of course, sub-pixels within a pixel can also be arranged in other ways.

[0215] For example, as shown in Figure 9, the driving transistor T3 is a dual-gate transistor, including sub-transistors T31 and T32. As shown in Figure 9, sub-transistors T31 and T32 are connected in series. Figure 9 illustrates this using the example of a dual-gate driving transistor T3. In other embodiments, besides the driving transistor T3, other transistors can also be configured as dual-gate transistors. That is, each transistor in the pixel circuit can be configured as a single-gate transistor or a dual-gate transistor as needed.

[0216] For example, as shown in Figures 8 and 9, the display panel includes a reset signal transmission line INI. The second terminal T4b of the reset transistor T4 is connected to the second terminal T3b (node ​​N3) of the driving transistor via the reset signal transmission line INI. A reset transistor T4 can be connected to node N3 of a row of sub-pixels via the reset signal transmission line INI.

[0217] Figures 2, 8, and 10 show the first terminal C1 and the second terminal C2 of the storage capacitor Cst. The first terminal C1 includes a first plate Ca (as shown in Figures 10 and 11B), and the second terminal C2 includes a second plate Cb (as shown in Figures 10 and 11A) and a third plate Cc (as shown in Figures 10 and 11D).

[0218] For example, as shown in Figure 2, the first conductive pattern layer LY1 is closer to the substrate BS than the second conductive pattern layer LY2.

[0219] For example, as shown in Figures 4 and 5, a display panel according to an embodiment of the present disclosure includes a substrate BS and sub-pixels 100 disposed on the substrate BS. Multiple sub-pixels 100 may be provided.

[0220] For example, as shown in Figures 2 and 10, the display panel further includes a pixel defining layer (PDL), and the sub-pixel 100 includes a pixel opening (P0) configured to expose at least a portion of the first electrode (E1) and to define a light-emitting area of ​​the sub-pixel 100. For example, as shown in Figure 2, the slope angle of the portion of the pixel defining layer (PDL) defining the pixel opening (P0) is 40-65 degrees, but is not limited to this.

[0221] For example, as shown in Figures 2 and 10, the sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a storage capacitor Cst, a second electrode Cb is closer to the substrate BS than the first electrode Ca, and the first electrode Ca is closer to the substrate BS than the third electrode Cc. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The pixel circuit 100a is configured to drive the light-emitting element 100b.

[0222] Figure 2 shows an example where all layers of the light-emitting functional layer FL are formed using inkjet printing, meaning that each layer of the light-emitting functional layer FL is located within the pixel opening P0. However, in other implementations, some layers of the light-emitting functional layer FL can be formed using inkjet printing, while other layers can be formed using vapor deposition. The layers formed using vapor deposition can be common layers.

[0223] For example, as shown in Figure 10, the first power line PL1 includes a first power signal line PL11 extending along the second direction X and a first power connection line PL12 extending along the first direction Y. The first power signal line PL11 and the first power connection line PL12 are connected.

[0224] For example, as shown in Figures 10, 11B and 11D, the data line DT extends along the first direction Y. The data line DT is formed in segments. The data line DT includes a first part DTTa, a second part DTb and a third part DTc. The first part DTTa and the third part DTc are connected through the second part DTb. The first part DTTa and the third part DTc are located in the second conductive pattern layer LY2, and the second part DTb is located in the first conductive pattern layer LY1.

[0225] In embodiments of this disclosure, elements located in the second conductive pattern layer LY2 can be connected to elements located in the first conductive pattern layer LY1 and elements located in the active layer LY0 through vias, and elements located in the first conductive pattern layer LY1 and elements located in the active layer LY0 can be connected through elements located in the second conductive pattern layer LY2.

[0226] For example, the insulating layer through which the via penetrates can be determined based on the condition of the insulating layer between the two conductive pattern layers connected by the via.

[0227] As shown in Figures 10, 11B, and 11D, the display panel provided according to some embodiments of this disclosure uses an active layer LY0, a first conductive pattern layer LY1, and a second conductive pattern layer LY2 to form the pixel circuit 100a, thereby simplifying the manufacturing process and reducing the thickness of the display panel. The initialization line INT1 and / or the first power line PL1 can be referred to as the conductive structure 40. The conductive structure 40 includes a signal transmission line 411 and a signal connection line 412. The conductive structure 40 is configured to provide a voltage signal to the sub-pixel 100. The signal transmission line 411 extends along a second direction X, and the signal connection line 412 extends along a first direction Y. The signal connection line 412 is electrically connected to the signal transmission line 411.

[0228] As shown in Figure 10, the conductive structure 40 includes a conductive structure 400 and a conductive structure 401. As shown in Figure 10, the first power line PL1 can be referred to as the conductive structure 400, and the initialization line INT1 can be referred to as the conductive structure 401.

[0229] For example, as shown in Figure 10, the conductive structure 40 adopts a mesh structure, which includes a portion extending along the first direction Y (i.e., signal connection line 412) and a portion extending along the second direction X (i.e., signal transmission line 411).

[0230] For example, as shown in Figures 10, 11B, and 11D, the first power line PL1 of the pixel circuit 100a is formed using two conductive pattern layers. As shown in Figures 10, 11B, and 11D, the portion of the first power line PL1 extending along the first direction Y is formed in segments. As shown in Figures 10 and 11D, the portion of the first power line PL1 extending along the second direction X is located in the second conductive pattern layer LY2.

[0231] For example, as shown in Figures 10, 11B, and 11D, the signal connection line 412 includes a first portion 412a, a second portion 412b, and a third portion 412c. The first portion 412a and the third portion 412c are connected through the second portion 412b. The first portion 412a and the third portion 412c are located in the first conductive pattern layer LY1, and the second portion 412b is located in the second conductive pattern layer LY2. The signal connection line 412 also includes a first power connection line PL12.

[0232] For example, as shown in Figure 10, the first part PLA and the second part PLb of the first power connection line PL12 are connected through via Va, and the second part PLb and the third part PLc of the first power connection line PL12 are connected through via Vb.

[0233] For example, as shown in Figure 10, the first power signal line PL11 and the first power connection line PL12 are connected through via V0.

[0234] For example, as shown in Figure 10, the first part DTa and the second part DTb of the data line DT are connected through via Vc, and the second part DTb and the third part DTc of the data line DT are connected through via Vd.

[0235] Figure 11A shows the active layer LY0. Figure 11A shows the channel T1c of the data writing transistor T1, the channel T2c of the reset transistor T2, the channel T3c of the driving transistor T3, and the channel T5c of the light-emitting control transistor T5. Figure 11A also shows the second electrode Cb. As shown in Figure 11A, the second electrode Cb is directly connected to the first electrode T3a of the driving transistor T3, and the two are a single structure. As shown in Figure 11A, the second electrode T5b of the light-emitting control transistor T5 is directly connected to the second electrode T3b of the driving transistor T3, and the two are a single structure. In the graph of the active layer LY0 shown in Figure 11A, channels T1c, T2c, T3c, and T5c are semiconductors, and the region outside of channels T1c, T2c, T3c, and T5c is a conductor. The conductor can be obtained by doping the semiconductor. For example, the channel material of each transistor in the active layer LY0 is polysilicon, while the conductors other than the channels are doped polysilicon. Of course, the active layer LY0 is not limited to polysilicon.

[0236] As shown in Figure 11A, the second electrode Cb, the first electrode T3a of the driving transistor T3, the channel T3c of the driving transistor T3, the second electrode T3b of the driving transistor T3, the second electrode T5b of the light-emitting control transistor T5, the channel T5c of the light-emitting control transistor T5, and the first electrode T5a of the light-emitting control transistor T5 are all the same pattern.

[0237] As shown in Figure 11A, the second terminal T1b of the data writing transistor T1 and the second terminal T2b of the reset transistor T2 are directly connected, and the two are integrated into one structure.

[0238] As shown in Figure 11A, the second terminal T1b of the data writing transistor T1, the second terminal T2b of the reset transistor T2, the channel T1c of the data writing transistor T1, and the channel T2c of the reset transistor T2 are all the same shape.

[0239] As shown in Figure 11A, the data writing transistor T1, the reset transistor T2, and the light-emitting control transistor T5 are all dual-gate transistors. In the same dual-gate transistor, the part between the two channels is a conductor.

[0240] Figure 11B shows the first conductive pattern layer LY1. As shown in Figure 11B, the first conductive pattern layer LY1 includes a first terminal C1 (first electrode Ca), connecting electrode CEa, connecting electrode CEc, connecting electrode CEd, connecting electrode CEe, a first portion DTTa of data line DT, a third portion DTc of data line DT, a first portion PLA of first power connection line PL12, and a third portion PLC of first power connection line PL12.

[0241] Figure 11C shows the interlayer insulating layer (ILD), illustrated by vias within the ILD. Figure 11C shows vias V1 to V9, V11-V13, vias Va to Vd, and via V0.

[0242] Figure 11D shows the second conductive pattern layer LY2. As shown in Figure 11D, the second conductive pattern layer LY2 includes a third electrode Cc at the second terminal C2, a connecting electrode CEf, gate lines G1, G2, and G5, a reset signal transmission line INI, an initialization voltage line INT11, and a second portion PLb of the first power connection line PL12 of the first power signal line PL11.

[0243] Figure 10 shows the first electrode layer LY3 of the light-emitting element. The first electrode layer LY3 includes a first electrode E1. Figure 10 shows one first electrode E1. For example, each sub-pixel has one first electrode E1. The first electrode layer LY3 includes multiple first electrodes E1.

[0244] Figure 10 illustrates the pixel delimiting layer (PDL), shown as pixel opening P0 within the PDL. Pixel opening P0 corresponds to the effective light-emitting area of ​​a subpixel. When the display panel is fabricated using inkjet printing to create at least one layer in the light-emitting functional layer (FL), the inkjet-printed layer is located within the pixel opening P0 of the PDL.

[0245] Referring to Figures 10 to 11D, the first power signal line PL11 and the first power connection line PL12 are connected through via V0.

[0246] Referring to Figures 10 to 11D, the connecting electrode CEa is connected to the gate line G5 through the via V9, and the connecting electrode CEa serves as the gate of the light-emitting control transistor T5.

[0247] Referring to Figures 10 to 11D, the first terminal T5a of the light-emitting control transistor T5 is connected to the first power line PL1 (first power signal line PL11) through via V11, and the second terminal T5b of the light-emitting control transistor T5 is connected to the reset signal transmission line INI through via V1.

[0248] Referring to Figures 10 to 11D, the connecting electrode CEc is connected to the gate line G1 through the via V12, and the connecting electrode CEc serves as the gate of the data writing transistor T1.

[0249] Referring to Figures 10 to 11D, the data line DT is connected to the first terminal T1a of the data writing transistor T1 through via V4.

[0250] Referring to Figures 10 to 11D, the connecting electrode CEd is connected to the gate line G2 through the via V6, and the connecting electrode CEd serves as the gate of the reset transistor T2.

[0251] Referring to Figures 10 to 11D, one end of the connecting electrode CEe is connected to the initialization line INT1 (initialization voltage line INT11) through via V7, and the other end of the connecting electrode CEe is connected to the first terminal T2a of the reset transistor T2 through via V8.

[0252] Referring to Figures 10 to 11D, one end of the connecting electrode CEf is connected to the first terminal C1 (the first plate Ca, the gate of the driving transistor T3) through the via V3, and the other end of the connecting electrode CEf is connected to the first terminal T1b of the data writing transistor T1 (that is, the second terminal T2b of the reset transistor T2) through the via V5.

[0253] Referring to Figures 10 to 11D, the third electrode Cc of the second terminal C2 is connected to the second electrode Cb of the second terminal C2 (that is, the first electrode T3a of the driving transistor T3) through the via V2.

[0254] Referring to Figures 10 to 11D, the reset signal transmission line INI is connected to the second terminal T3b of the driving transistor T3 through the via V1. Since the second terminal T3b of the driving transistor T3 and the second terminal T5b of the light-emitting control transistor T5 are integrated, the reset signal transmission line INI is connected to the second terminal T5b of the light-emitting control transistor T5 through the via V1.

[0255] Referring to Figures 10 to 11D, the second terminal T5b of the light-emitting control transistor T5 and the second terminal T3b of the driving transistor T3 are both connected to the reset signal transmission line INI through via V1.

[0256] The display panel provided in the embodiments of this disclosure optimizes the light emission uniformity and power consumption balance by matching the pattern design of the active layer LY0 with the pattern design of the channel of the driving transistor and the capacitor plate located in the active layer, thereby improving the light emission uniformity of the display panel and reducing power consumption.

[0257] For example, referring to Figures 10, 11A, and 11D, the second electrode Cb and the channel of the driving transistor T3 are an integral structure, which can be formed from the same thin film using the same patterning process. The channel of the driving transistor T3 is made of semiconductor material, and the second electrode Cb is a conductor obtained by doping the semiconductor material.

[0258] Figure 12 shows a display panel provided according to an embodiment of this disclosure, with connecting electrodes 80 provided on the display panel shown in Figure 10. Figure 2 is a cross-sectional view of the display panel shown in Figure 12 along line A1-A2. Figure 13 is a plan view of the conductive pattern layer LYm, vias VH1 and VH2, the first electrode layer LY3, and the pixel openings in the display panel shown in Figure 12. The layout of the pixel circuit in the display panel shown in Figure 12 is the same as that in the display panel shown in Figure 10. The corresponding structure can be referred to the description in Figure 10, and will not be repeated here.

[0259] As shown in Figures 2 and 12, the first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through a second via VH2 penetrating the second insulating layer 602, and the connecting electrode 80 is connected to the pixel circuit 100a through a first via VH1 penetrating the first insulating layer 601. As shown in Figure 2, the connecting electrode 80 is located between the first insulating layer 601 and the second insulating layer 602.

[0260] As shown in Figures 12 and 13, the connecting electrode 80 is plate-shaped. The connecting electrode 80 overlaps with the pixel opening P0. The connecting electrode 80 can level the sub-pixel. The orthogonal projection of the connecting electrode 80 on the substrate can cover the orthogonal projection of the pixel opening P0 on the substrate, thus better achieving the leveling effect.

[0261] Of course, the connection electrode 80 is not limited to the cases shown in Figures 12 and 13. In other embodiments, the connection electrode 80 can take other forms. Several examples are listed below.

[0262] Figure 14 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present disclosure. Figure 15 is a plan view of the connecting electrodes in the display panel shown in Figure 14. As shown in Figures 14 and 15, the connecting electrode 80 includes an electrode body 806 and a plurality of openings 808. As shown in Figures 14 and 15, the plurality of openings 808 are arranged in an array in the first direction Y and the second direction X.

[0263] For example, referring to Figures 2, 14 and 15, the connecting electrode 80 is in contact with the first insulating layer 601, and the connecting electrode 80 has a plurality of openings 808 that expose a portion of the first insulating layer 601, and the pixel opening P0 of a sub-pixel 100 overlaps with one or more openings of the connecting electrode 80.

[0264] The display panel provided in the embodiments of this disclosure has a connecting electrode 80 widely distributed at the corresponding pixel opening P0 to level the sub-pixels. The connecting electrode 80 also has multiple openings 808 to facilitate the venting of the organic material in the underlying first insulating layer 601. For example, the multiple openings 808 in the connecting electrode 800 also facilitate the venting of the planarization layer PLN1.

[0265] Figure 16A is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present disclosure. Figure 16B is a plan view of the connecting electrodes in the display panel shown in Figure 16A. Compared with the display panels shown in Figures 14 and 15, the openings 808 in the display panels shown in Figures 16A and 16B are elongated. As shown in Figures 16A and 16B, a plurality of openings 808 are arranged sequentially in the second direction X, and each opening 808 extends along the first direction Y.

[0266] Figure 17A is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present disclosure. Figure 17B is a plan view of the connecting electrodes in the display panel shown in Figure 17A. Compared with the display panels shown in Figures 14 and 15, the opening 808 in the display panels shown in Figures 17A and 167 is circular.

[0267] It should be noted that the arrangement of the multiple openings 808 in the connecting electrode 80 is not limited to the above description and can be set as needed.

[0268] For example, as shown in Figures 14, 16A, and 17A, the pixel circuit 100a includes a storage capacitor Cst. The storage capacitor Cst has a first electrode Ca and a second electrode Cb, which are insulated from each other. The size of each opening of the connecting electrode 80 is smaller than the size of the first electrode Ca and smaller than the size of the second electrode Cb. Figure 14 shows the first electrode Ca and the second electrode Cb. The first electrode Ca and the second electrode Cb in Figures 16A and 17A can be seen with reference to Figure 14.

[0269] Figure 14 also shows the third electrode Cc. Referring to Figure 10, the third electrode Cc is connected to the second electrode Cb. The size of each opening of the connecting electrode 80 is smaller than the size of the third electrode Cc.

[0270] Figure 18 is a partial schematic diagram of the conductive pattern layer LYm of a display panel provided in an embodiment of this disclosure. As shown in Figure 18, a connection electrode 80 is provided in the area where a sub-pixel 100 is located. Figure 18 shows a total of nine connection electrodes 80 at the locations of six sub-pixels 100 in three rows and three columns. Of course, the arrangement of the connection electrodes 80 is not limited to this. The connection electrodes 80 may also have a relatively small area, while other conductive components may be provided at the remaining locations where no connection electrodes 80 are provided. For example, these conductive components may also be connected to conductive components located in other conductive pattern layers. The following description takes the example of providing other conductive components at the remaining locations where no connection electrodes 80 are provided, with components connected to the first power line PL1 and / or the second power line PL2 as an example. That is, the conductive pattern layer LYm can be laid out.

[0271] Figure 19 is a partial schematic diagram of a conductive pattern layer LYm in a display panel according to an embodiment of the present disclosure. Figure 20 is a plan view of a partial structure in a display panel according to an embodiment of the present disclosure. Figure 21 is a plan view of a partial structure in a display panel according to another embodiment of the present disclosure. Figure 22 is a partial schematic diagram of a conductive pattern layer LYm in a display panel according to an embodiment of the present disclosure. Figure 23 is a partial schematic diagram of a conductive pattern layer LYm in another display panel according to an embodiment of the present disclosure. Figure 24 is a partial schematic diagram of a conductive pattern layer LYm in another display panel according to an embodiment of the present disclosure. Figure 25 is a plan view of a partial structure in a display panel according to an embodiment of the present disclosure. Figure 26 is a plan view of a partial structure in a display panel according to an embodiment of the present disclosure. Figure 27 is a plan view of a partial structure in a display panel according to an embodiment of the present disclosure. Figure 28 is a plan view of a partial structure in another display panel according to an embodiment of the present disclosure. Figure 29 is a plan view of a partial structure in another display panel according to an embodiment of the present disclosure.

[0272] For example, as shown in Figures 19 to 29, the display panel also includes a conductive connection portion CC. The conductive connection portion CC and the connecting electrode 80 are located on the same layer, that is, both are located on the conductive pattern layer LYm. The conductive connection portion CC and the connecting electrode 80 are insulated from each other. The conductive connection portion CC and the connecting electrode 80 can be used to connect components that transmit different voltages. The conductive connection portion CC can be used to connect to components that transmit a fixed voltage to reduce resistance. The conductive connection portion CC can also serve to flatten sub-pixels.

[0273] For example, as shown in Figures 19 to 24, the conductive connection part CC has multiple hollow structures K0, and the connecting electrode 80 is located in one of the multiple hollow structures K0.

[0274] For example, as shown in Figure 22, in the hollow structure K0 and the connecting electrode 80 located therein, the area ratio of the connecting electrode 80 to the area of ​​the hollow structure K0 is less than or equal to 10%. The connecting electrode 80 occupies a small proportion in the hollow structure K0.

[0275] For example, as shown in Figures 19 to 21, in the hollow structure K0 and the connecting electrode 80 located therein, the area ratio of the connecting electrode 80 to the area of ​​the hollow structure K0 is greater than or equal to 70%. The connecting electrode 80 occupies a large proportion in the hollow structure K0.

[0276] For example, as shown in Figures 25 to 29, the conductive connection CC has multiple first conductive lines CC1 and multiple second conductive lines CC2.

[0277] For example, as shown in Figures 25 to 29, each of the plurality of first conductive lines CC1 and each of the plurality of second conductive lines CC2 is insulated from each other, and the plurality of first conductive lines CC1 and the plurality of second conductive lines CC2 are alternately arranged in the first direction Y or the second direction X. As shown in Figures 26 and 27, the plurality of first conductive lines CC1 and the plurality of second conductive lines CC2 are alternately arranged in the second direction X. As shown in Figures 28 and 29, the plurality of first conductive lines CC1 and the plurality of second conductive lines CC2 are alternately arranged in the first direction Y.

[0278] For example, as shown in Figure 25, the first conductive line CC1 and the second conductive line CC2 are arranged along the second direction X, and the connecting electrode 80 is located in the hollow structure K0 of the first conductive line CC1.

[0279] For example, as shown in Figures 26 to 29, the connecting electrode 80 is disposed between adjacent first conductive line CC1 and second conductive line CC2, and the first conductive line CC1, the connecting electrode 80, and the second conductive line CC2 are arranged in sequence.

[0280] As shown in Figures 26 and 27, the first conductive line CC1, the connecting electrode 80, and the second conductive line CC2 are arranged sequentially in the second direction X. As shown in Figures 28 and 29, the first conductive line CC1, the connecting electrode 80, and the second conductive line CC2 are arranged sequentially in the first direction Y.

[0281] For example, as shown in Figures 23 to 29, the display panel also includes a dummy block DM, which is floating and located on the same layer as the conductive connection part CC. The dummy block DM can serve to flatten the sub-pixels.

[0282] For example, as shown in Figures 23 and 24, the area of ​​the dummy block DM is larger than the area of ​​the connecting electrode 80.

[0283] For example, as shown in Figures 23 and 24, the dummy block DM is disposed in the hollow structure K0. As shown in Figures 23 and 24, the dummy block DM and the connecting electrode 80 are disposed in the same hollow structure K0. Figure 24 shows hollow structures K01 and K02. The dummy block DM is located in hollow structure K02, and the connecting electrode 80 is located in hollow structure K01.

[0284] For example, as shown in Figures 26 and 28, the display panel also includes a dummy block DM, which is floating and located on the same layer as the conductive connection part CC.

[0285] For example, as shown in Figures 26 and 28, the area of ​​the dummy block DM is larger than the area of ​​the connecting electrode 80.

[0286] For example, as shown in Figures 26 and 28, the dummy block DM is set between adjacent first conductive line CC1 and second conductive line CC2.

[0287] The first conductive line CC1 shown in Figure 27 can be a structure obtained by extending the dummy block DM in Figure 26 to the first conductive line CC1 and fusing it with the first conductive line CC1.

[0288] The first conductive line CC1 shown in Figure 29 can be obtained by widening the dummy block DM in Figure 26 to the first conductive line CC1 and merging it with the first conductive line CC1. The second conductive line CC2 shown in Figure 29 can be obtained by widening the dummy block DM in Figure 26 to the second conductive line CC2 and merging it with the second conductive line CC2.

[0289] For example, as shown in Figures 20, 21, 26 to 29, the display panel also includes a power line connected to the conductive connection CC, and the power line is configured to provide a constant power supply voltage to the pixel circuit 100a.

[0290] For example, as shown in Figures 20, 26 to 29, the power line includes a first power line PL1, which is connected to the pixel circuit 100a and configured to provide a constant first voltage signal to the pixel circuit 100a.

[0291] For example, referring to Figures 5, 20, and 26 to 29, the first power line PL1 includes a first power signal line PL11 and a first power connection line PL12. The first power signal line PL11 and the first power connection line PL12 are connected and intersected. The conductive connection part CC is connected to the first power connection line PL12. The first power line PL1 (first power connection line PL12) is connected to the first conductive line CC1 through a via H1.

[0292] For example, as shown in Figures 8, 21, 26 to 29, the power line includes a second power line PL2, which is connected to the second electrode E2 of the light-emitting element 100b and is configured to provide a constant second voltage signal.

[0293] For example, as shown in Figures 25 to 29, the display panel also includes a first power line PL1 and a second power line PL2. The first power line PL1 is connected to the pixel circuit 100a and configured to provide a constant first voltage signal to the pixel circuit 100a. The second power line PL2 is connected to the second electrode E2 of the light-emitting element 100b and configured to provide a constant second voltage signal. A first conductive line CC1 is connected to the first power line PL1, and a second conductive line CC2 is connected to the second power line PL2. The second conductive line CC2 is connected to the second power line PL2 through a via H2.

[0294] Figures 20, 21, 25 to 29 also show the first electrode E1 and the second via VH2.

[0295] Figure 30 is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure. Figure 31 is a plan view of a partial structure of another display panel provided in an embodiment of the present disclosure. Figure 32A is a plan view of a partial structure of another display panel provided in an embodiment of the present disclosure. Figure 32B is a plan view of a partial structure of another display panel provided in an embodiment of the present disclosure.

[0296] For example, as shown in Figures 30 to 32B, the display panel also includes a conductive bus LN. The conductive bus LN and the connecting electrode 80 are located on the same layer. The conductive bus LN and the conductive connection CC are an integral structure. The conductive bus LN extends along the second direction X, and the dimension of the conductive bus LN in the second direction X is larger than the dimension of the conductive connection CC in the second direction X. The conductive bus LN shown in Figures 30 to 32B can be connected to the first power line PL1 or the second power line PL2. That is, the conductive connection CC shown in Figures 30 to 32B can be the first conductive line CC1 connected to the first power line PL1, or the conductive connection CC shown in Figures 30 to 32B can be the second conductive line CC2.

[0297] For example, as shown in Figures 30 to 32B, the display panel includes a first row of sub-pixels R1 and a second row of sub-pixels R2. The conductive bus LN overlaps with the pixel opening P0 of the first row of sub-pixels R1. That is, the orthographic projection of the conductive bus LN onto the substrate overlaps with the orthographic projection of the pixel opening P0 of the first row of sub-pixels R1 onto the substrate. This arrangement allows the conductive bus LN to be positioned in the display area, reducing the bezel size and achieving a narrow bezel. A smaller bezel aligns with future trends and customer needs.

[0298] Figure 32B shows the connection electrode 801 of the first row sub-pixel R1 and the connection electrode 802 of the second row sub-pixel R2.

[0299] As shown in Figure 32B, the dimension of the connecting electrode 801 in the first direction Y is smaller than the dimension of the connecting electrode 802 in the first direction Y.

[0300] As shown in Figure 32B, the area of ​​the connecting electrode 801 is smaller than the area of ​​the connecting electrode 802.

[0301] The conductive connection CC in the display panel shown in Figures 32A and 32B can be a structure obtained by widening the dummy block DM in the display panel shown in Figure 31 to the right and merging it with the conductive connection CC.

[0302] For example, as shown in Figures 12, 14, 16A, 17A, 20, 21, 25 to 32B, in order to obtain a higher pixel density (Pixels Per Inch, PPI), the orthographic projection of the connecting electrode 80 on the substrate overlaps with the orthographic projection of the pixel opening P0 on the substrate.

[0303] Figure 33 is a layout diagram of another display panel provided in an embodiment of this disclosure. Compared with the layout shown in Figure 12, the first power connection line PL12 is not segmented, but formed using the same film layer, namely the first conductive pattern layer LY1. In other embodiments, the layout can also be changed so that the first power connection line PL12 is formed using the same film layer, namely the second conductive pattern layer LY2. Thus, the layout of the display panel provided in the embodiments of this disclosure can be adjusted as needed.

[0304] Figures 34 to 41 are cross-sectional views of partial structures of several display panels provided in some embodiments of the present disclosure. Figure 42 is a plan view of a display panel provided in an embodiment of the present disclosure.

[0305] For example, as shown in Figures 34 to 41, the display panel also includes at least two barrier dams DMM and at least one isolation groove G located between adjacent barrier dams DMM, the isolation groove G being configured to accommodate redundant ink.

[0306] For example, as shown in Figures 34 to 41, at least two barrier dams DMM include a first barrier dam DM1 and a second barrier dam DM2. The first barrier dam DM1 is closer to the display area R01 of the display panel than the second barrier dam DM2, and the height of the first barrier dam DM1 is less than the height of the second barrier dam DM2.

[0307] Figure 35 shows the height TK2 of the first barrier dam DM1 and the height TK3 of the second barrier dam DM2, with height TK2 being less than height TK3.

[0308] For example, as shown in Figures 34 to 41, the display panel further includes a pixel defining layer (PDL). The PDL includes a defining portion 3012 and an isolating portion 312. The defining portion 3012 is configured to define the pixel opening P0 of the sub-pixel 100. At least one of the at least two blocking dams (DMMs) includes the isolating portion 312. As shown in Figure 35, the thickness of the isolating portion 312 is greater than the thickness of the defining portion 3012. For example, the defining portion 3012 includes the aforementioned first defining portion 301 and second defining portion 302. Figure 35 also shows the maximum height TK1 of the defining portion 3012 of the PDL.

[0309] For example, as shown in Figures 34 to 41, at least one partition structure ST is provided in the isolation tank G. The partition structure ST is configured to block the light-emitting functional layer FL to prevent water and oxygen from damaging the light-emitting functional layer FL in the display area. One or more partition structures ST can be provided in the same isolation tank G.

[0310] Figure 37 shows two isolation grooves G. The two isolation grooves G can have different depths.

[0311] As shown in Figure 37, the depth of isolation groove G1 is less than the depth of isolation groove G2.

[0312] As shown in Figure 37, isolation slot G1 is closer to the display area than isolation slot G2.

[0313] Figure 39 shows barrier dams DM0, DM1, DM2, and DM3.

[0314] In Figures 34 to 41, the left side is the display area and the right side is the surrounding area.

[0315] Figures 34 to 41 also show the cutting line CL. The portion to the right of the cutting line CL will be removed after cutting. That is, the peripheral area of ​​the display panel can be cut when at least one film layer of the light-emitting functional layer is fabricated using the inkjet printing process.

[0316] Figures 34 to 41 illustrate planarization layers PLN1 and PLN2 in a display panel. The partition structure ST in Figures 34 to 39 is made using planarization layer PLN1, forming a T-shaped or half-T-shaped partition structure. The partition structure ST in Figure 40 is made using a film layer above planarization layer PLN1, forming a T-shaped partition structure. The partition structure ST in Figure 41 is made using a film layer above planarization layer PLN1, forming an I-shaped partition structure. The partition structure ST shown in Figure 40 can be made of metal and / or insulating materials. The partition structure ST shown in Figure 41 can be made of metallic materials.

[0317] It should be noted that the embodiments disclosed herein do not limit the shape of the partition structure or the composition of the film layer, nor are they limited to the form shown in the figure, as long as they can serve to block the light-emitting functional layer FL.

[0318] As shown in Figure 42, the display panel includes a display area R01 and a peripheral area R02 surrounding the display area R01. The display area R01 is the area where images can be displayed, and the peripheral area R02 is the border area.

[0319] Figure 42 shows the isolation channel G and the barrier dam DMM. As shown in Figure 42, the isolation channel G includes isolation channel G01 and isolation channel G02. The number of isolation channels G and the number of barrier dams DMM are not limited to those shown in the figure and can be determined as needed.

[0320] Figure 43 is a schematic diagram of a display panel provided in an embodiment of the present disclosure. Figure 44 is a schematic diagram of a display panel provided in an embodiment of the present disclosure. Figures 45 to 49 are schematic diagrams of several display panels provided in embodiments of the present disclosure.

[0321] For example, as shown in Figures 43 to 49, the display panel also includes multiple signal generation circuits (GDCs), each of which is positioned between two adjacent columns of pixel circuits (PDCs). This arrangement facilitates the achievement of a narrow bezel.

[0322] For example, as shown in Figures 44 to 49, the multiple sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. The area of ​​the pixel opening P0 of the third sub-pixel 103 is larger than the area of ​​the pixel opening P0 of the second sub-pixel 102, and also larger than the area of ​​the pixel opening P0 of the first sub-pixel 101. The number of signal generation circuits (GDCs) overlapping with the pixel opening P0 of the third sub-pixel 103 is greater than the number of signal generation circuits (GDCs) overlapping with the pixel opening P0 of the first sub-pixel 101, and also greater than the number of signal generation circuits (GDCs) overlapping with the pixel opening P0 of the second sub-pixel 102. This configuration facilitates the layout of the signal generation circuits (GDCs) and helps achieve a narrow bezel.

[0323] In the embodiments shown in Figures 44 to 49 of this disclosure, for clarity, the pixel opening P0 is placed below its corresponding pixel circuit PDC and / or signal generation circuit GDC. That is, in the actual display panel, the pixel opening P0 of the sub-pixel 100 overlaps with its corresponding pixel circuit PDC and / or signal generation circuit GDC.

[0324] For example, as shown in Figure 43, the signal generation circuit GDC includes a gate signal generation circuit GC and a light emission signal generation circuit EC, which are formed between two different columns of pixel circuits PDC. As shown in Figure 43, the pixel circuits PDC are located in the first setting area DA, and the signal generation circuit GDC is located in the second setting area SA. As shown in Figure 43, the signal generation circuit GDC includes signal generation circuits Dg1, Dg2, De1, and De2.

[0325] As shown in Figure 43, signal generation circuit Dg1 is located between two adjacent columns of pixel circuits PDC, signal generation circuit Dg2 is located between two adjacent columns of pixel circuits PDC, signal generation circuit De1 is located between two adjacent columns of pixel circuits PDC, and signal generation circuit De2 is located between two adjacent columns of pixel circuits PDC.

[0326] As shown in Figure 43, multiple signal generation circuits Dg1 and multiple pixel circuits PDC are arranged alternately in the second direction X.

[0327] Figure 43 also shows the gate line GL and the light emission control signal line EL. The gate line GL can be the gate line G1 or the gate line G2 mentioned above, and the light emission control signal line EL can be the gate line G5 mentioned above.

[0328] For example, as shown in Figures 46 to 48, the pixel circuit PDC of the first sub-pixel 101, the pixel circuit PDC of the second sub-pixel 102, and the pixel circuit PDC of the third sub-pixel 103 have different widths. The width of the pixel circuit PDC is its dimension in the second direction X. The different widths of the pixel circuit PDCs reserve space for setting the signal generation circuit GDC.

[0329] For example, as shown in Figures 46 to 48, the width of the pixel circuit PDC of the first sub-pixel 101 is greater than the width of the pixel circuit PDC of the third sub-pixel 103, and the width of the pixel circuit PDC of the third sub-pixel 103 is greater than the width of the pixel circuit PDC of the second sub-pixel 102.

[0330] For example, as shown in Figures 8, 9 and 47, the display panel also includes an initialization line INT1 and a first power line PL1. The initialization line INT1 is configured to provide a constant initialization voltage Vinit1 to the pixel circuit PDC, and the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit PDC. The initialization line INT1 overlaps with the pixel opening P0 of the third sub-pixel 103, and the first power line PL1 overlaps with the pixel opening P0 of the first sub-pixel 101. The width of the initialization line INT1 is smaller than the width of the first power line PL1.

[0331] For example, as shown in FIG47, the orthographic projection of the pixel opening P0 of sub-pixel 100 on the substrate BS overlaps with the orthographic projection of at least one pixel circuit PDC on the substrate BS, and also overlaps with the orthographic projection of at least one signal generation circuit GDC on the substrate BS.

[0332] For example, as shown in Figures 8 and 47, the display panel also includes a data line DT, gate lines G1, G2, G4, G5, a first power line PL1, a first initialization voltage line INT1, and a second initialization voltage line INT2. The pixel circuit PDC includes a driving transistor T3, a light-emitting control transistor T5, a data writing transistor T1, a reset transistor T2, a reset transistor T4, and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the first plate of the driving transistor T3. The first plate of the data writing transistor T1 is connected to the data line DT, the gate of the driving transistor T3 is connected to the second plate of the data writing transistor T1, and the gate of the data writing transistor T1 is connected to the gate line G1. The first plate of the reset transistor T2 is connected to the first initialization line INT1, and the second plate of the reset transistor T2 is connected to the gate of the driving transistor T3. The gate of reset transistor T2 is connected to gate line G2, the gate of reset transistor T4 is connected to gate line G4, the first terminal of reset transistor T4 is connected to the second initialization line INT1, the second terminal of reset transistor T4 is connected to the light-emitting element 100b through driving transistor T3, the gate of light-emitting control transistor T5 is connected to gate line G5, the first terminal of light-emitting control transistor T5 is connected to the first power supply line PL1, and the second terminal of light-emitting control transistor T5 is connected to the second terminal of driving transistor T3. Multiple signal generation circuits GDC include a first gate signal generation circuit G11, a second gate signal generation circuit G22, a light-emitting control signal generation circuit EN, and an initialization voltage generation circuit Vv. The first gate signal generation circuit G11 is connected to gate line G1, the second gate signal generation circuit G22 is connected to gate line G2 and / or gate line G4, the light-emitting control signal generation circuit EN is connected to gate line G5, and the initialization voltage generation circuit Vv is connected to the first initialization line INT1 and / or the second initialization line INT2.

[0333] For example, gate line G1 can be the first gate line, gate line G2 can be the second gate line, gate line G4 can be the third gate line, and gate line G5 can be the fourth gate line.

[0334] For example, reset transistor T2 can be the first reset transistor, and reset transistor T4 can be the second reset transistor.

[0335] As shown in Figures 8 and 47, the width of the first gate signal generation circuit G11 is greater than the width of the light emission control signal generation circuit EN, the width of the light emission control signal generation circuit EN is greater than the width of the second gate signal generation circuit G22, and the width of the second gate signal generation circuit G22 is greater than the width of the initialization voltage generation circuit Vv.

[0336] In embodiments of this disclosure, the pixel circuit PDC may be the pixel circuit 100a described above, but is not limited thereto.

[0337] For example, as shown in Figure 49, the display panel also includes a data line DT, and the pixel circuit PDC includes a driving transistor T3 and a data writing transistor T1. The data line DT is connected to the first terminal of the data writing transistor T1, and the second terminal of the data writing transistor T1 is connected to the gate of the driving transistor T3. The data line DT is configured as multiple lines, including a first data line DT1, a second data line DT2, and a third data line DT3. The first data line DT1 overlaps with the pixel opening P0 of the first sub-pixel 101, the second data line DT2 overlaps with the pixel opening P0 of the second sub-pixel 102, and the third data line DT3 overlaps with the pixel opening P0 of the third sub-pixel 103. The first data line DT1, the second data line DT2, and the third data line DT3 are arranged sequentially. The ratio of the first spacing SP1 between the first data line DT1 and the second data line DT2 to the second spacing SP2 between the second data line DT2 and the third data line DT3 is in the range of 0.8-1.2. With this configuration, the data line of each sub-pixel overlaps with its corresponding pixel circuit, avoiding interference with other sub-pixels and giving the display panel high wiring uniformity.

[0338] Figure 50 is a schematic diagram of a display panel according to an embodiment of this disclosure. For example, as shown in Figure 50, the display panel further includes a driving circuit CCT, which is located on one side of the display panel. The driving circuit CCT may be a driving integrated circuit (IC).

[0339] For example, as shown in Figure 50, the plurality of sub-pixels 100 include a middle sub-pixel 152 near the center of the display panel and an edge sub-pixel 151 near the edge of the display panel. The refresh rate of the middle sub-pixel 152 and the refresh rate of the edge sub-pixel 151 are configured to be adjustable in a preset working mode.

[0340] For example, the refresh rate of the middle sub-pixel 152 is greater than the refresh rate of the edge sub-pixel 151.

[0341] For example, the display panel also includes a data line DT, the pixel circuit PDC includes a driving transistor T3 and a data writing transistor T1, the data line DT is connected to the first terminal of the data writing transistor T1, the second terminal of the data writing transistor T1 is connected to the gate of the driving transistor T3, and multiple data lines DT are provided. The display panel includes a display area R01 and a peripheral area located on at least one side of the display area R01. The display panel also includes multiple fan-out lines, the data line DT is connected to one of the multiple fan-out lines, the multiple fan-out lines gradually converge from the connection position of the data line DT and the fan-out line to the direction away from the connection position of the data line DT and the fan-out line, the multiple fan-out lines extend from the display area R01 to the peripheral area, the multiple fan-out lines and the multiple data lines DT are located on different layers, and the multiple data lines DT are closer to the substrate BS than the multiple fan-out lines.

[0342] Figure 51 is a schematic diagram of a display panel provided in an embodiment of the present disclosure. For example, as shown in Figure 51, the display panel further includes multiple fan-out lines 86. The substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. A data line DT is connected to one of the multiple fan-out lines 86. The multiple fan-out lines 86 gradually converge from the connection position of the data line DT and the fan-out line 86 to the direction away from the connection position of the data line DT and the fan-out line 86. The multiple fan-out lines extend from the display area R01 to the peripheral area R02. The multiple fan-out lines 86 and the data line DT are located on different layers, as shown in Figures 2, 10 and 51. The data line DT is composed of a portion located on the first conductive pattern layer LY1 and / or a portion located on the second conductive pattern layer LY2. The multiple fan-out lines 86 are located on the conductive pattern layer LYm. Therefore, the data line DT is closer to the substrate BS than the multiple fan-out lines 86. Referring to Figures 2, 10, and 51, the second portion 412b of the data line DT is closer to the substrate BS than the multiple fan-out lines 86. The first portion 412a and the third portion 412c of the data line DT are also closer to the substrate BS than the multiple fan-out lines 86.

[0343] For example, as shown in Figure 51, the length of the portion of fan-out line 86 located in the display area R01 is greater than the length of the portion of fan-out line 86 located in the peripheral area R02. The display area is the area where the image is displayed. The peripheral area R02 is a non-display area.

[0344] Figure 51 also shows chips 98 and 99, which can be chip-on-flex (COF). The data line DT is connected to the chip via fan-out line 86.

[0345] As shown in Figure 51, a data line DT and a fan-out line 86 are connected through a via Vm, which penetrates the insulating layer between the data line DT and the fan-out line 86. For example, the via Vm penetrates the insulating layer 601.

[0346] As shown in Figures 2 to 8, 9, and 12 to 13, embodiments of this disclosure also provide a display panel, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS. Each sub-pixel 100 includes a pixel opening P0 configured to define a light-emitting area of ​​the sub-pixel 100. A first defining portion 301 is disposed between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is disposed between two adjacent pixel openings P0 in a second direction X. The first direction Y intersects the second direction X. The thickness of the first defining portion 301 and the thickness of the second defining portion 302 are not equal. Each sub-pixel 100 includes a pixel circuit 100a and a light-emitting portion connected to the pixel circuit 100a. The light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of the light-emitting element 100b is closer to the substrate BS than at least a portion of the second electrode E2 of the light-emitting element 100b. The display panel also includes an insulating material layer 60 located on the side of the pixel circuit 100a facing away from the substrate BS. The insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602. The first insulating layer 601 includes an organic material, and the second insulating layer 602 includes an organic material. The first insulating layer 601 is closer to the substrate BS than the second insulating layer 602. The display panel also... The pixel circuit 100a includes a connecting electrode 80 located between a first insulating layer 601 and a second insulating layer 602. The connecting electrode 80 is connected to the pixel circuit 100a through a first via VH1 penetrating the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through a second via VH2 penetrating the second insulating layer 602. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the first electrode of the driving transistor T3. The storage capacitor Cst is located on a substrate. The orthographic projection on BS overlaps with the orthographic projection of pixel opening P0 on substrate BS. The orthographic projection of the channel of driving transistor T3 on substrate BS overlaps with the orthographic projection of pixel opening P0 on substrate BS. The second electrode Cb is disposed in the same layer as the channel T3c of driving transistor T3 (as shown in Figures 11A and 12). The second electrode Cb is closer to substrate BS than the first electrode Ca. The orthographic projection of the second electrode Cb on substrate BS overlaps with the orthographic projection of pixel opening P0 on substrate BS. The ratio of the maximum size of the second via VH2 along the second direction X to the maximum size of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0347] The embodiments of this disclosure provide a display panel and a display device including the display panel, reducing the size of the vias used to connect pixel circuits and light-emitting elements to facilitate the flattening of sub-pixels and to facilitate obtaining high-resolution products. The orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, and the orthographic projection of the second electrode Cb on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, thereby playing the role of flattening the sub-pixels.

[0348] Embodiments of this disclosure also provide a display panel, as shown in Figures 2 to 8, 9, and 12 to 13, comprising: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS, wherein each sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is disposed between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is disposed between two adjacent pixel openings P0 in a second direction X, wherein the first direction Y intersects the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. Sub-pixel 100 includes pixel circuit 100a and light-emitting element 100b connected to pixel circuit 100a. Light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of light-emitting element 100b is closer to the substrate BS than at least a portion of the second electrode E2 of light-emitting element 100b. The display panel also includes an insulating material layer 60 located on the side of pixel circuit 100a facing away from the substrate BS. The insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602. The first insulating layer 601 includes an organic material, and the second insulating layer 602 includes an organic material. The first insulating layer 601 is closer to the substrate BS than the second insulating layer 602. It also includes a connecting electrode 80, which is located between the first insulating layer 601 and the second insulating layer 602. The connecting electrode 80 is connected to the pixel circuit 100a through a first via VH1 penetrating the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through a second via VH2 penetrating the second insulating layer 602. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the first plate of the driving transistor T3. The orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. For example, the orthographic projection of the channel of the driving transistor T3 onto the substrate BS overlaps with the orthographic projection of the pixel opening P0 onto the substrate BS. The second electrode Cb is disposed in the same layer as the channel of the driving transistor T3, and the second electrode Cb is closer to the substrate BS than the first electrode Ca (as shown in Figures 2, 11A, and 11B). The ratio of the maximum size of the second via VH2 along the second direction X to the maximum size of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0349] The embodiments of this disclosure provide a display panel and a display device including the display panel, reducing the size of the vias used to connect pixel circuits and light-emitting elements to facilitate the flattening of sub-pixels and to facilitate obtaining high-resolution products. The orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, and the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, thereby playing the role of flattening the sub-pixels.

[0350] Figure 52 is a schematic diagram of a display panel according to an embodiment of this disclosure. For example, as shown in Figure 52, the display panel further includes a barrier dam 701, and an encapsulating adhesive 702 is provided on the outer side of the encapsulation layer EPS, which serves as an adhesive. Figure 52 shows the boundary of the encapsulation layer EPS. As shown in Figures 2 and 52, the second insulating layer 602 includes a planarization layer PLN2, which includes a first planarization portion PLN11 and a second planarization portion PLN22. A groove GR is provided between the first planarization portion PLN11 and the second planarization portion PLN22. The barrier dam 701 is located around the display area R01 of the display panel. The orthographic projection of the barrier dam 701 on the substrate BS covers the orthographic projection of the groove GR on the substrate BS, so as to reduce or prevent water and oxygen from entering the display area R01 along the planarization layer PLN2 and avoid affecting the light-emitting elements in the display area R01. Of course, in some other embodiments, the orthographic projection of the barrier dam 701 on the substrate BS may not cover the orthographic projection of the groove GR on the substrate BS.

[0351] For example, the minimum distance from the edge of the display area R01 to the edge of the peripheral area R02 ranges from 1 to 5 millimeters. That is, the size of the bezel ranges from 1 to 5 millimeters.

[0352] For example, to achieve better water and oxygen blocking effect, the groove GR is a through-hole penetrating the planarization layer PLN2. As shown in Figure 52, the portion of the planarization layer PLN2 located inside the groove GR is the first planar portion PLN11, and the portion of the planarization layer PLN2 located outside the groove GR is the second planar portion PLN22. Figure 52 shows the first planar portion PLN11 with its boundary and the second planar portion PLN22 with its boundary. Figure 52 illustrates the example with one groove GR, but the number of grooves GR is not limited to one and can be set as needed. The number of grooves GR depends on the narrowness of the border. The narrower the border, the fewer grooves GR are required. Of course, in some other embodiments, grooves GR may not be provided.

[0353] Embodiments of this disclosure also provide a display panel, as shown in Figures 2 to 8, 9, 12 to 13, and 52, comprising: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS, wherein each sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is disposed between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is disposed between two adjacent pixel openings P0 in a second direction X, wherein the first direction Y intersects the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. Sub-pixel 100 includes pixel circuit 100a and light-emitting element 100b connected to pixel circuit 100a. Light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of light-emitting element 100b is closer to the substrate BS than at least a portion of the second electrode E2 of light-emitting element 100b. The display panel also includes an insulating material layer 60 located on the side of pixel circuit 100a facing away from substrate BS. Insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602. The first insulating layer 601 includes an organic material, and the second insulating layer 602 includes an organic material. The first insulating layer 601 is closer to the substrate BS than the second insulating layer 602. The display panel also includes a connecting electrode 80 located between the first insulating layer 601 and the second insulating layer 602. The connecting electrode 80 is connected to pixel circuit 100a through a first via VH1 penetrating the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through the second via VH2 penetrating the second insulating layer 602. The display panel also includes a barrier dam DMM and an encapsulation layer EPS. The encapsulation layer EPS is configured to encapsulate the light-emitting element 100b. The encapsulation layer EPS includes a stack of inorganic encapsulation film and organic encapsulation film. An encapsulating adhesive 702 is provided on the outer side of the encapsulation layer EPS. The second insulating layer 602 includes a planarization layer PLN2. The planarization layer PLN2 includes a first planarization portion PLN11 and a second planarization portion PLN22. A groove GR is provided between the first planarization portion PLN11 and the second planarization portion PLN22. The barrier dam DMM is located outside the display area R01 of the display panel. The orthographic projection of the barrier dam DMM on the substrate BS covers the orthographic projection of the groove GR on the substrate BS. The ratio of the maximum size of the second via VH2 along the second direction X to the maximum size of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0354] The embodiments of this disclosure provide a display panel and a display device including the display panel, reducing the size of the vias used to connect pixel circuits and light-emitting elements to facilitate the planarization of sub-pixels and to facilitate obtaining high-resolution products. The orthogonal projection of the barrier dam DMM on the substrate BS covers the orthogonal projection of the groove GR on the substrate BS to reduce or prevent water and oxygen from entering the display area R01 along the planarization layer PLN2, thereby avoiding affecting the light-emitting elements in the display area R01.

[0355] Figure 53 is a circuit diagram of a dummy sub-pixel in a display panel according to an embodiment of the present disclosure. Figure 54 is a layout diagram of a dummy pixel circuit in a display panel according to an embodiment of the present disclosure.

[0356] As shown in Figure 53, the dummy sub-pixel 100d has a dummy driving transistor dT3 and a dummy reset transistor dT2. The gates of the dummy reset transistor dT2 and the dummy driving transistor dT3 are connected. The dummy reset transistor dT2 is disconnected from the initialization line INT1 to reduce power consumption. The dummy sub-pixel 100d is set up to improve etching uniformity, rather than to achieve light emission. As shown in Figure 53, the dummy sub-pixel 100d includes a dummy pixel circuit 100da and a dummy light-emitting element 100db. As shown in Figure 53, the composition of the dummy pixel circuit 100da can be referenced to that of the pixel circuit 100a, and the composition of the dummy light-emitting element 100db can be referenced to that of the light-emitting element 100b. However, there may be broken lines in the dummy pixel circuit 100da. Figure 53 illustrates the dummy pixel circuit 100da with the example where the first electrode E1 of the dummy light-emitting element 100db is not connected to node N2 (the first electrode T3a of the dummy driving transistor dT3), and the dummy reset transistor dT2 is not connected to the initialization line INT1. In other embodiments, other disconnection methods can be used to prevent the dummy sub-pixel 100d from emitting light. The bold cross in Figure 53 indicates a disconnection. For example, to disconnect the dummy reset transistor dT2 of the dummy sub-pixel 100d from the initialization line INT1, a via can be omitted.

[0357] For example, as shown in Figures 53 and 54, the dummy sub-pixel 100d also includes a dummy light-emitting control transistor dT5. The first terminal of the dummy light-emitting control transistor dT5 is disconnected from the first power supply line PL1, and the second terminal of the dummy light-emitting control transistor dT5 is connected to or disconnected from the second terminal of the dummy driving transistor T3.

[0358] As shown in Figure 54, no via is provided within the dashed box F1 (corresponding to via V7 in Figure 12), thus disconnecting the dummy reset transistor dT2 from the initialization line INT1. As shown in Figure 54, no via is provided within the dashed box F2 (corresponding to via VH1 in Figure 12), thus disconnecting the dummy pixel circuit 100da from the dummy light-emitting element 100db. As shown in Figure 54, no via is provided within the dashed box F3 (corresponding to via V11 in Figure 12), thus disconnecting the first terminal of the dummy light-emitting control transistor dT5 from the first power supply line PL1. As shown in Figure 54, no via is provided within the dashed box F4 (corresponding to via V1 in Figure 12), thus disconnecting the second terminal of the dummy light-emitting control transistor dT5 from the second terminal of the dummy driving transistor T3. Of course, to make the second terminal of the dummy light-emitting control transistor dT5 connected to the second terminal of the dummy driving transistor T3, vias need to be provided at the corresponding positions, and the same applies to other positions.

[0359] Embodiments of this disclosure also provide a display panel, as shown in Figures 2 to 8, 9, 12 to 13, 53, and 54, comprising: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS, wherein each sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is disposed between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is disposed between two adjacent pixel openings P0 in a second direction X, wherein the first direction Y intersects the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. Sub-pixel 100 includes pixel circuit 100a and light-emitting element 100b connected to pixel circuit 100a. Light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of light-emitting element 100b is closer to the substrate BS than at least a portion of the second electrode E2 of light-emitting element 100b. The display panel also includes an insulating material layer 60, which is located on the side of pixel circuit 100a facing away from the substrate BS. The insulating material layer 60 covers... The display panel includes a first insulating layer 601 and a second insulating layer 602. Both the first insulating layer 601 and the second insulating layer 602 are made of organic materials. The first insulating layer 601 is closer to the substrate BS than the second insulating layer 602. The display panel also includes a connecting electrode 80 located between the first insulating layer 601 and the second insulating layer 602. The connecting electrode 80 is connected to the pixel circuit 100a through a first via VH1 penetrating the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected through a second via penetrating the second insulating layer 602. VH2 is connected to the connecting electrode 80. The display panel also includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1. The pixel circuit 100a also includes a data writing transistor T1 and a reset transistor T2. The first terminal of the data writing transistor T1 is connected to the data line DT. The gate of the driving transistor T3 is connected to the second terminal of the data writing transistor T1. The gate of the data writing transistor T1 is connected to the gate line G1. The first terminal of the reset transistor T2 is connected to the initialization line INT1. The second terminal of the reset transistor T2 is connected to the driving transistor T3. The gates of the reset transistor T2 are connected to the gate line G2. The display panel has a dummy sub-pixel 100 near its edge. The dummy sub-pixel 100 has a dummy driving transistor T3 and a dummy reset transistor dT2. The gates of the dummy reset transistor dT2 and the dummy driving transistor T3 are connected. The dummy reset transistor dT2 is disconnected from the initialization line INT1. The ratio of the maximum size of the second via VH2 along the second direction X to the maximum size of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0360] The embodiments of this disclosure provide a display panel and a display device including the display panel, reducing the size of the vias used to connect pixel circuits and light-emitting elements to facilitate the flatness of sub-pixels and to facilitate obtaining high-resolution products, and dummy reset transistor dT2 is disconnected from initialization line INT1 to reduce power consumption.

[0361] Embodiments of this disclosure also provide a display panel, as shown in Figures 2 to 8, 9, and 12 to 13, comprising: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS, wherein each sub-pixel 100 includes a pixel opening P0. For example, the pixel opening P0 is configured to define a light-emitting area of ​​the sub-pixel 100, a first defining portion 301 is disposed between two adjacent pixel openings P0 in a first direction Y, and a second defining portion 302 is disposed between two adjacent pixel openings P0 in a second direction X, wherein the first direction Y intersects the second direction X, and the thickness of the first defining portion 301 is not equal to the thickness of the second defining portion 302. Sub-pixel 100 includes pixel circuit 100a and light-emitting element 100b connected to pixel circuit 100a. Light-emitting element 100b has a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of light-emitting element 100b is closer to the substrate BS than at least a portion of the second electrode E2 of light-emitting element 100b. The display panel also includes an insulating material layer 60, which is located on the side of pixel circuit 100a facing away from the substrate BS. The insulating material layer 60 includes a first insulating layer 601 and a second insulating layer 602. The first insulating layer 601 includes an organic material, and the second insulating layer 602 includes an organic material. The first insulating layer 601 is closer to the substrate BS than the second electrode E2. The second insulating layer 602 is closer to the substrate BS. The display panel also includes a connecting electrode 80, which is located between the first insulating layer 601 and the second insulating layer 602. The connecting electrode 80 is connected to the pixel circuit 100a through a first via VH1 penetrating the first insulating layer 601. The first electrode E1 of the light-emitting element 100b is connected to the connecting electrode 80 through a second via VH2 penetrating the second insulating layer 602. The light-emitting functional layer FL covers the sidewall SW of the first defining portion 301 and the sidewall SW of the second defining portion 302. The ratio of the maximum size of the second via VH2 along the second direction X to the maximum size of the pixel opening P0 along the second direction X is greater than or equal to 0.05 and less than or equal to 0.48.

[0362] The embodiments of this disclosure provide a display panel and a display device including the display panel, reducing the size of the vias used to connect pixel circuits and light-emitting elements to facilitate the flatness of sub-pixels and to facilitate obtaining high-resolution products. The light-emitting functional layer FL is fabricated using an inkjet printing process. The light-emitting functional layer FL covers the sidewall of the first defining portion 301 and the sidewall of the second defining portion 302.

[0363] Figure 55 is a schematic diagram of a display panel provided in an embodiment of this disclosure.

[0364] As shown in Figures 2 and 55, the thickness of the first defining portion 301 is less than the thickness of the second defining portion 302, and the light-emitting functional layer FL also includes a portion covering the top wall TW of the first defining portion 301. In this case, each film layer of the light-emitting functional layer FL can be fabricated using inkjet printing. Because the thickness of the first defining portion 301 is less than the thickness of the second defining portion 302, the light-emitting functional layer FL covers the top wall TW of the first defining portion 301. The light-emitting functional layer FL covers the sidewalls of the first defining portion 301, the sidewalls of the second defining portion 302, and the top wall TW of the first defining portion 301. For example, the light-emitting functional layer FL does not cover the top wall of the second defining portion 302.

[0365] Figures 2 and 55 illustrate an example where all layers of the light-emitting functional layer FL are formed using inkjet printing, meaning each layer of the light-emitting functional layer FL is disposed within the pixel opening P0. However, in other embodiments, some layers of the light-emitting functional layer FL may be formed using inkjet printing, while others may be formed using vapor deposition. The layers formed using vapor deposition can be common layers. An example of this can be found in Figure 56. Figure 56 is a schematic diagram of a display panel provided according to an embodiment of this disclosure.

[0366] For example, as shown in Figures 2, 3 to 7, the display panel further includes a pixel defining layer (PDL). The PDL includes a defining portion 300, which defines a pixel opening P0. The light-emitting element 100b includes a first electrode E1 and a light-emitting functional layer FL. The PDL is configured to expose at least a portion of the first electrode E1, and at least a portion of the film layer in the light-emitting functional layer FL covers the sidewall SW of the defining portion 300 (as shown in Figure 2). Figure 2 illustrates an example where all light-emitting functional layers FL are located within the pixel opening P0. In other embodiments, the light-emitting functional layer FL may cover the top wall TW of the first defining portion 301, as shown in Figure 55.

[0367] For example, as shown in FIG2, the light-emitting element 100b further includes a second electrode E2, and the light-emitting functional layer FL is located between the first electrode E1 and the second electrode E2. The second electrode E2 is in contact with the top wall of the defining portion 300. Of course, as shown in FIG56, when the light-emitting functional layer FL includes a common layer, the second electrode E2 is in contact with the common layer in the light-emitting functional layer FL. For example, the second electrode E2 is in contact with the common layer in the light-emitting functional layer FL that is close to the second electrode E2. The common layer in FIG56 is the electron injection layer EIL, but it is not limited to this and can be determined as needed. As shown in FIG2 and FIG56, the orthographic projection of the second electrode E2 on the substrate BS overlaps with the orthographic projection of the top wall of the defining portion 300 on the substrate BS.

[0368] Figures 55 and 56 show the light-emitting layer EML, the hole injection layer HIL, and the hole transport layer HTL.

[0369] Figures 55 and 56 also show the light extraction layer CPL to improve light extraction efficiency.

[0370] Figures 10 and 54 also show the central axis C0. The pixel opening P0 has the central axis C0 extending along the first direction Y. The pixel opening P0 may be axially symmetrical with respect to the central axis C0.

[0371] Embodiments of this disclosure also provide a display device, including any of the above-described display panels.

[0372] For example, the display device may be a large-sized display device, and at least one film layer in the light-emitting functional layer may be fabricated using inkjet printing technology.

[0373] For example, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any product or component with a display function, including televisions, digital cameras, mobile phones, watches, tablets, laptops, navigators, etc., which include OLED display devices.

[0374] For example, inorganic encapsulation films EPS1 and EPS3 are made of inorganic insulating materials, while organic encapsulation film EPS2 is made of organic insulating materials.

[0375] For example, the passivation layer can be made of inorganic insulating materials, while the planarization layer can be made of organic insulating materials.

[0376] In embodiments of this disclosure, the inorganic insulating material includes, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the organic insulating material includes, but is not limited to, resin.

[0377] In the embodiments of this disclosure, the pixel circuit is not limited to the circuit diagram shown, and other suitable pixel circuits may be used. The layout diagram of the display panel is also not limited to the layout diagram shown, and may be adjusted based on the given layout diagram, or other layout methods may be used.

[0378] The following points need to be explained:

[0379] (1) In the accompanying drawings of the embodiments of this disclosure, some drawings show only a part of the structure of the display panel for the purpose of clarity, and do not show the entire structure.

[0380] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0381] (3) For clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0382] (4) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other.

[0383] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: A substrate and a plurality of sub-pixels disposed on the substrate, The sub-pixel includes a pixel opening configured to define a light-emitting region of the sub-pixel, a first boundary portion disposed between two pixel openings adjacent in a first direction, and a second boundary portion disposed between two pixel openings adjacent in a second direction, the first direction intersecting the second direction, a thickness of the first boundary portion being different from a thickness of the second boundary portion, The sub-pixel includes a pixel circuit and a light-emitting element connected to the pixel circuit, the light-emitting element having a first electrode, a second electrode, and a light-emitting functional layer between the first electrode and the second electrode, the first electrode of the light-emitting element being closer to the substrate than the light-emitting functional layer, The display panel further includes an insulating material layer on a side of the pixel circuit facing away from the substrate, the insulating material layer including a first insulating layer and a second insulating layer, the first insulating layer including an organic material, the second insulating layer including an organic material, the first insulating layer being closer to the substrate than the second insulating layer, The display panel further includes a connection electrode between the first insulating layer and the second insulating layer, The connection electrode is connected to the pixel circuit through a first via hole that penetrates the first insulating layer, and the first electrode of the light-emitting element is connected to the connection electrode through a second via hole that penetrates the second insulating layer, The ratio of the maximum dimension of the second via hole in the second direction to the maximum dimension of the pixel opening in the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

2. The display panel of claim 1, wherein, The ratio of the maximum dimension of the second via hole in the second direction to the maximum dimension of the pixel opening in the second direction is greater than or equal to 0.12 and less than or equal to 0.

24.

3. The display panel of claim 1 or 2, wherein, The ratio of the maximum dimension of the second via hole in the first direction to the maximum dimension of the pixel opening in the first direction is greater than or equal to 0.05 and less than or equal to 0.

24.

4. The display panel according to any one of claims 1-3, wherein, The ratio of the maximum dimension of the second via hole in the first direction to the maximum dimension of the pixel opening in the first direction is greater than or equal to 0.08 and less than or equal to 0.

18.

5. The display panel according to any one of claims 1-4, wherein, The thickness of the first boundary portion is less than the thickness of the second boundary portion.

6. The display panel according to any one of claims 1-5, wherein, The thickness of the first insulating layer is less than or equal to the thickness of the second insulating layer.

7. The display panel according to any one of claims 1-6, wherein, The thickness of the first insulating layer is less than or equal to 2 microns, and the thickness of the second insulating layer is less than or equal to 2 microns.

8. The display panel according to any one of claims 1-7, wherein, The size of the first via hole is less than or equal to 10 microns, and the size of the second via hole is less than or equal to 10 microns.

9. The display panel according to any one of claims 1-8, wherein, The size of the first via hole is less than or equal to 5 microns, and the size of the second via hole is less than or equal to 5 microns.

10. The display panel according to any one of claims 1-9, wherein, The size of the first via hole is greater than or equal to 2 microns, and the size of the second via hole is greater than or equal to 2 microns.

11. The display panel according to any one of claims 1-10, wherein, The second via is provided in a plurality, and the first electrode of the light emitting element is connected to the connection electrode through the plurality of second vias penetrating the second insulating layer, and the plurality of second vias are located at edges of the pixel opening.

12. The display panel of claim 11, wherein, Each of the plurality of second vias has a size less than or equal to 10 microns.

13. The display panel according to any one of claims 1-11, wherein, A projection of the connection electrode on the substrate substrate overlaps a projection of the pixel opening of the sub-pixel on the substrate substrate.

14. The display panel of claim 13, wherein, The projection of the connection electrode on the substrate substrate covers the projection of the pixel opening of the sub-pixel on the substrate substrate.

15. The display panel according to any one of claims 1-14, wherein, The connection electrode is in contact with the first insulating layer, and the connection electrode has a plurality of openings exposing a portion of the first insulating layer, and the pixel opening of one sub-pixel overlaps more than one opening of the connection electrode.

16. The display panel of claim 15, wherein, The pixel circuit includes a storage capacitor having a first plate and a second plate, the first plate and the second plate being insulated from each other, each opening of the connection electrode having a size smaller than a size of the first plate and smaller than a size of the second plate.

17. The display panel of any of claims 1-16, further comprising at least two barrier dams and at least one isolation slot located between adjacent barrier dams, wherein, The isolation groove is configured to accommodate redundant ink.

18. The display panel of claim 17, wherein, The at least two blocking dams include a first blocking dam and a second blocking dam, the first blocking dam being closer to the display area of the display panel than the second blocking dam, and the first blocking dam having a height smaller than a height of the second blocking dam.

19. The display panel of claim 17 or 18, further comprising a pixel defining layer, wherein, The pixel defining layer includes a defining portion and an isolation portion, the defining portion being configured to define the pixel opening of the sub-pixel, at least one of the at least two blocking dams including the isolation portion, and the isolation portion having a thickness greater than a thickness of the defining portion.

20. The display panel of any of claims 17-19, wherein, At least one partition structure is provided in the isolation groove, and the partition structure is configured to partition the light emitting functional layer.

21. The display panel of any of claims 1-20, further comprising a conductive connection portion, wherein, The conductive connection portion and the connection electrode are located in the same layer, and the conductive connection portion and the connection electrode are insulated from each other.

22. The display panel of claim 21, wherein, The conductive connection portion has a plurality of hollow structures, and the connection electrode is located in one of the plurality of hollow structures.

23. The display panel of claim 22, wherein, In the hollow structure and the connection electrode located therein, the area ratio of the connection electrode to the hollow structure is less than or equal to 10%.

24. The display panel of claim 22 or 23, wherein, In the hollow structure and the connection electrode located therein, the area ratio of the connection electrode to the hollow structure is greater than or equal to 70%.

25. The display panel of any of claims 21-24, wherein, The conductive connection portion has a plurality of first conductive lines and a plurality of second conductive lines.

26. The display panel of claim 25, wherein, Each of the plurality of first conductive lines and each of the plurality of second conductive lines are insulated from each other, and the plurality of first conductive lines and the plurality of second conductive lines are arranged alternately in the first direction or the second direction.

27. The display panel of claim 26, wherein, The connection electrode is arranged between adjacent first conductive lines and second conductive lines, and the first conductive line, the connection electrode, and the second conductive line are arranged in sequence.

28. The display panel of claim 23, further comprising dummy blocks, wherein, The dummy block is floating, and the dummy block is located in the same layer as the conductive connection portion.

29. The display panel of claim 28, wherein, The area of the dummy block is greater than the area of the connection electrode.

30. The display panel of claim 28, wherein, The dummy block is arranged in the hollow structure.

31. The display panel of claim 26, further comprising dummy blocks, wherein, The dummy block is floating, and the dummy block is located in the same layer as the conductive connection portion.

32. The display panel of claim 31, wherein, The area of the dummy block is greater than the area of the connection electrode.

33. The display panel of claim 31 or 32, wherein, The dummy block is arranged between the adjacent first conductive line and the second conductive line.

34. The display panel of any of claims 21-25, further comprising a power line, wherein the power line is connected to the conductive connection part, and the power line is configured to provide a constant power voltage to the pixel circuit.

35. The display panel of claim 34, wherein, The power line comprises a first power line connected to the pixel circuit and configured to provide a constant first voltage signal to the pixel circuit.

36. The display panel of claim 35, wherein, The first power line comprises a first power signal line and a first power connection line, the first power signal line and the first power connection line are connected and arranged in cross.

37. The display panel of claim 34, wherein, The power line comprises a second power line connected to the second electrode of the light emitting element and configured to provide a constant second voltage signal.

38. The display panel of any of claims 26-33, further comprising a first power line and a second power line, wherein, The first power line is connected to the pixel circuit and configured to provide a constant first voltage signal to the pixel circuit, the second power line is connected to the second electrode of the light emitting element and configured to provide a constant second voltage signal, the first conductive line is connected to the first power line, and the second conductive line is connected to the second power line.

39. The display panel of claim 21, further comprising a conductive bus, wherein, The conductive bus and the connection electrode are located in the same layer, the conductive bus and the conductive connection part are an integral structure, the conductive bus extends along the second direction, the size of the conductive bus in the second direction is greater than the size of the conductive connection part in the second direction, and the orthogonal projection of the conductive bus on the substrate substrate overlaps the orthogonal projection of the pixel opening of the first row of sub-pixels on the substrate substrate.

40. The display panel of any of claims 1-39, further comprising a plurality of signal generation circuits, wherein, Each of the plurality of signal generation circuits is arranged between two adjacent columns of pixel circuits.

41. The display panel of claim 40, wherein, The plurality of sub-pixels comprises first sub-pixels, second sub-pixels, and third sub-pixels, the area of the pixel opening of the third sub-pixel is greater than the area of the pixel opening of the second sub-pixel, and greater than the area of the pixel opening of the first sub-pixel, the number of signal generation circuits overlapping the pixel opening of the third sub-pixel is greater than the number of signal generation circuits overlapping the pixel opening of the first sub-pixel, and greater than the number of signal generation circuits overlapping the pixel opening of the second sub-pixel.

42. The display panel of claim 40 or 41, wherein, The signal generation circuit comprises a gate signal generation circuit and a light emitting signal generation circuit, and the signal generation circuit and the light emitting signal generation circuit are formed between two different columns of pixel circuits.

43. The display panel according to any one of claims 40-42, wherein, The widths of the pixel circuits of the first sub-pixels, the pixel circuits of the second sub-pixels, and the pixel circuits of the third sub-pixels are different.

44. The display panel of claim 43, wherein, The width of the pixel circuit of the first sub-pixel is greater than the width of the pixel circuit of the third sub-pixel, and the width of the pixel circuit of the third sub-pixel is greater than the width of the pixel circuit of the second sub-pixel.

45. The display panel of claim 43 or 44, further comprising an initialization line and a first power line, wherein, The initialization line is configured to provide a constant initialization voltage to the pixel circuit, the first power line is configured to provide a constant first voltage signal to the pixel circuit, the initialization line overlaps with the pixel opening of the third sub-pixel, the first power line overlaps with the pixel opening of the first sub-pixel, and the width of the initialization line is less than the width of the first power line.

46. The display panel of any of claims 40-45, wherein, The pixel opening of the sub-pixel is overlapped with the orthographic projection of at least one pixel circuit on the substrate and the orthographic projection of at least one signal generation circuit on the substrate.

47. The display panel of any of claims 40-46, further comprising a data line, a first gate line, a second gate line, a third gate line, a fourth gate line, a first power line, a first initialization voltage line, and a second initialization voltage line, wherein, The pixel circuit comprises a driving transistor, a light emitting control transistor, a data writing transistor, a first reset transistor, a second reset transistor and a storage capacitor, The storage capacitor comprises a first plate and a second plate, the first plate of the storage capacitor is connected with the gate of the driving transistor, and the second plate of the storage capacitor is connected with the first electrode of the driving transistor, The first electrode of the data writing transistor is connected with the data line, the gate of the driving transistor is connected with the second electrode of the data writing transistor, and the gate of the data writing transistor is connected with the first gate line, The first electrode of the first reset transistor is connected with the first initialization line, the second electrode of the first reset transistor is connected with the gate of the driving transistor, and the gate of the first reset transistor is connected with the second gate line, The gate of the second reset transistor is connected with the third gate line, the first electrode of the second reset transistor is connected with the second initialization line, and the second electrode of the second reset transistor is connected with the light emitting element through the driving transistor, The gate of the light emitting control transistor is connected with the fourth gate line, the first electrode of the light emitting control transistor is connected with the first power line, and the second electrode of the light emitting control transistor is connected with the second electrode of the driving transistor, The plurality of signal generation circuits comprises a first gate signal generation circuit, a second gate signal generation circuit, a light emitting control signal generation circuit and an initialization voltage generation circuit, The first gate signal generation circuit is connected with the first gate line, the second gate signal generation circuit is connected with at least one of the second gate line and the third gate line, the light emitting control signal generation circuit is connected with the fourth gate line, and the initialization voltage generation circuit is connected with at least one of the first initialization line and the second initialization line, The width of the first gate signal generation circuit is greater than the width of the light emitting control signal generation circuit, the width of the light emitting control signal generation circuit is greater than the width of the second gate signal generation circuit, and the width of the second gate signal generation circuit is greater than the width of the initialization voltage generation circuit.

48. The display panel of any of claims 41-46, further comprising a data line, wherein, The pixel circuit comprises a driving transistor and a data writing transistor, the data line is connected with the first electrode of the data writing transistor, the second electrode of the data writing transistor is connected with the gate of the driving transistor, and the data line is provided as a plurality of data lines. The plurality of data lines comprises a first data line, a second data line, and a third data line, the first data line overlaps with the pixel opening of the first sub-pixel, the second data line overlaps with the pixel opening of the second sub-pixel, and the third data line overlaps with the pixel opening of the third sub-pixel, The first data line, the second data line, and the third data line are arranged in sequence, The ratio of the first interval between the first data line and the second data line to the second interval between the second data line and the third data line ranges from 0.8 to 1.

2.

49. The display panel of any one of claims 1-48, wherein, The plurality of sub-pixels comprises intermediate sub-pixels close to the center of the display panel and edge sub-pixels close to the edge of the display panel, and the refresh frequency of the intermediate sub-pixels and the refresh frequency of the edge sub-pixels are configured to be adjustable in a preset working mode.

50. The display panel of claim 49, wherein, The refresh frequency of the intermediate sub-pixels is greater than the refresh frequency of the edge sub-pixels.

51. The display panel of any of claims 1-46, further comprising a data line, wherein, The pixel circuit comprises a driving transistor and a data writing transistor, the data line is connected to the first electrode of the data writing transistor, the second electrode of the data writing transistor is connected to the gate electrode of the driving transistor, the data line is provided in multiple, the display panel comprises a display area and a peripheral area located on at least one side of the display area, the display panel further comprises a plurality of fan-out lines, the data line is connected to one of the plurality of fan-out lines, the plurality of fan-out lines gradually converge from the connection position close to the data line and the fan-out line to the connection position away from the data line and the fan-out line, the plurality of fan-out lines extend from the display area to the peripheral area, the plurality of fan-out lines are located in different layers from the plurality of data lines, and the plurality of data lines are closer to the substrate than the plurality of fan-out lines.

52. A display panel comprising: A substrate and a plurality of sub-pixels provided on the substrate, The sub-pixel comprises a pixel opening, a pixel circuit, and a light-emitting element connected to the pixel circuit, the light-emitting element has a first electrode, The display panel further comprises an insulating material layer, the insulating material layer is located on the side of the pixel circuit away from the substrate, the insulating material layer comprises a first insulating layer and a second insulating layer, the first insulating layer comprises an organic material, the second insulating layer comprises an organic material, and the first insulating layer is closer to the substrate than the second insulating layer, The display panel further comprises a connection electrode, the connection electrode is located between the first insulating layer and the second insulating layer, The connection electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connection electrode through a second via hole penetrating the second insulating layer, The pixel circuit comprises a driving transistor and a storage capacitor, the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate of the storage capacitor is connected to the gate electrode of the driving transistor, and the second electrode plate of the storage capacitor is connected to the first electrode of the driving transistor, A projection of the storage capacitor on the substrate substrate overlaps with a projection of the pixel opening on the substrate substrate, a projection of the channel of the driving transistor on the substrate substrate overlaps with a projection of the pixel opening on the substrate substrate, The second plate is arranged in the same layer as the channel of the driving transistor, and the second plate is closer to the substrate substrate than the first plate, The ratio of the maximum dimension of the second via in the second direction to the maximum dimension of the pixel opening in the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

53. The display panel of claim 52, wherein, The projection of the second plate on the substrate substrate overlaps with the projection of the pixel opening on the substrate substrate.

54. The display panel of claim 52 or 53, wherein, The pixel opening is configured to define a light-emitting area of the sub-pixel, a first boundary portion is arranged between two pixel openings adjacent in a first direction, a second boundary portion is arranged between two pixel openings adjacent in a second direction, the first direction intersects the second direction, and the thickness of the first boundary portion is not equal to the thickness of the second boundary portion, The light-emitting element also has a second electrode and a light-emitting functional layer between the first electrode and the second electrode, and the first electrode of the light-emitting element is closer to the substrate substrate than at least part of the second electrode of the light-emitting element.

55. A display panel comprising: A substrate substrate and a plurality of sub-pixels arranged on the substrate substrate, The sub-pixel includes a pixel opening, a pixel circuit, and a light-emitting element connected to the pixel circuit, the light-emitting element has a first electrode, The display panel further includes an insulating material layer on the side of the pixel circuit away from the substrate substrate, the insulating material layer includes a first insulating layer and a second insulating layer, the first insulating layer includes an organic material, the second insulating layer includes an organic material, and the first insulating layer is closer to the substrate substrate than the second insulating layer, The display panel further includes a connection electrode between the first insulating layer and the second insulating layer, The connection electrode is connected to the pixel circuit through a first via penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connection electrode through a second via penetrating the second insulating layer, The display panel further includes a blocking dam and an encapsulation layer, wherein the encapsulation layer is configured to encapsulate the light-emitting element, and the encapsulation layer includes a stack of an inorganic encapsulation film and an organic encapsulation film, An encapsulation adhesive is provided on the outside of the encapsulation layer, The second insulating layer includes a planarization layer, the planarization layer includes a first planar portion and a second planar portion, and a groove is provided between the first planar portion and the second planar portion, The blocking dam is located at the periphery of the display area of the display panel, and a projection of the blocking dam on the substrate substrate covers a projection of the groove on the substrate substrate. The ratio of the maximum dimension of the second via in the second direction to the maximum dimension of the pixel opening in the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

56. A display panel comprising: A substrate substrate and a plurality of sub-pixels arranged on the substrate substrate, The sub-pixel comprises a pixel opening, a pixel circuit, and a light-emitting element connected to the pixel circuit, the light-emitting element has a first electrode, The display panel further comprises an insulating material layer on the side of the pixel circuit away from the substrate, the insulating material layer comprises a first insulating layer and a second insulating layer, the first insulating layer comprises an organic material, the second insulating layer comprises an organic material, and the first insulating layer is closer to the substrate than the second insulating layer, The display panel further comprises a connecting electrode between the first insulating layer and the second insulating layer, The connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer, The display panel further comprises a data line, a first gate line, a second gate line, and a first initialization line, wherein the pixel circuit further comprises a data writing transistor and a first reset transistor, the first electrode of the data writing transistor is connected to the data line, the gate electrode of the driving transistor is connected to the second electrode of the data writing transistor, and the gate electrode of the data writing transistor is connected to the first gate line, The first electrode of the first reset transistor is connected to the first initialization line, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, and the gate electrode of the first reset transistor is connected to the second gate line, The display panel is provided with a dummy sub-pixel near its edge, the dummy sub-pixel has a dummy driving transistor and a first dummy reset transistor, and the gate electrodes of the first dummy reset transistor and the dummy driving transistor are connected, The first dummy reset transistor is disconnected from the first initialization line; The ratio of the maximum size of the second via hole in the second direction to the maximum size of the pixel opening in the second direction is greater than or equal to 0.05 and less than or equal to 0.

48.

57. A display panel comprising: A substrate and a plurality of sub-pixels arranged on the substrate, The sub-pixel comprises a pixel opening, a pixel circuit, and a light-emitting element connected to the pixel circuit, the light-emitting element has a first electrode, The display panel further comprises an insulating material layer on the side of the pixel circuit away from the substrate, the insulating material layer comprises a first insulating layer and a second insulating layer, the first insulating layer comprises an organic material, the second insulating layer comprises an organic material, and the first insulating layer is closer to the substrate than the second insulating layer, The display panel further comprises a connecting electrode between the first insulating layer and the second insulating layer, The connecting electrode is connected to the pixel circuit through a first via hole penetrating the first insulating layer, and the first electrode of the light-emitting element is connected to the connecting electrode through a second via hole penetrating the second insulating layer, The light-emitting functional layer covers the side wall of the first defining part and covers the side wall of the second defining part, A ratio of a maximum dimension of the second via in the second direction to a maximum dimension of the pixel opening in the second direction ranges from greater than or equal to 0.05 and less than or equal to 0.

48.

58. The display panel of claim 57, wherein, The first defining portion has a thickness smaller than a thickness of the second defining portion, and the light-emitting functional layer further includes a portion covering a top wall of the first defining portion. 59.A display device comprising the display panel according to any one of claims 1-58.

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