Fault localization method and device

Abstract

The present application provides a fault localization method and device, applied to a receiving end device. The receiving end device can determine a first reconfigured link to be detected, wherein the first reconfigured link is a link obtained by reconfiguring a first sublink in a faulty first link and some of links in a fault-free second link. The first link, the second link, and the first reconfigured link are all links from a transmitting end device to the receiving end device, and the transmitting end device and the receiving end device communicate through an optical fiber link. Specifically, the first reconfigured link is a link formed by replacing a corresponding link in the second link with the first sublink. After determining the first reconfigured link, the receiving end device can perform fault detection on the first reconfigured link, and on the basis of a fault detection result of the first reconfigured link, the receiving end device localizes whether a fault location of the first link comprises the first sublink. Thus, by means of the present solution, a fault location of a first link can be localized when a fault occurs in the first link.

Description

A fault locating method and device

[0001] The present application claims priority from the Chinese Patent Application No. 202410696787.3 filed on May 30, 2024, and entitled "A fault locating method and device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication, in particular to a fault locating method and device. BACKGROUND

[0003] When data is transmitted in a communication network, if a communication link fails, it may affect the normal transmission of data, and accordingly, some negative effects will be brought. For example, in the scenario where the application of artificial intelligence (AI) technology is becoming more and more widespread, AI training data can be transmitted in a communication network, and once the communication link fails, it may cause abnormal transmission of AI training data, and accordingly, it will affect the accuracy and efficiency of AI training.

[0004] When the communication link fails, it is particularly important to locate the fault. The so-called fault locating can be understood as determining the fault point in the link that specifically causes the fault.

[0005] How to accurately locate the fault of the link that fails is a problem that needs to be solved at present. SUMMARY

[0006] The present application provides a fault locating method and device, which can locate the fault point in the link that specifically causes the fault after the link fails.

[0007] In a first aspect, an embodiment of the present application provides a fault locating method, which can be applied to a receiving end device. The receiving end device can determine a first recombined link to be detected, which is a link recombined by a first sub-link in a first link with a fault and a part of a second link without a fault. The first link, the second link and the first recombined link are all links from a sending end device to the receiving end device, and the sending end device and the receiving end device communicate through an optical fiber link. Specifically, the first recombined link is a link formed by replacing a corresponding link in the second link with the first sub-link. After determining the first recombined link, the receiving end device can perform fault detection on the first recombined link. Since the second link is fault-free, the fault detection result of the first recombined link can represent whether the first sub-link has a fault. Therefore, the receiving end device can determine whether the fault position of the first link includes the first sub-link according to the fault detection result of the first recombined link. As can be seen, by using the scheme of the embodiment of the present application, the fault position of the first link can be located after the first link has a fault.

[0008] In a possible implementation, the receiving end device can send a first frame including first indication information to the sending end device. The first indication information is used to indicate that fault locating is performed on the first sub-link. As an example, the foregoing first indication information can be used to indicate a stage of performing fault locating on the first link. Different stages require locating different sub-links, and each stage has a first sub-link corresponding to the stage. The receiving end device sends the first frame to the sending end device, so that the sending end device determines the stage of performing fault locating, so as to enable the sending end to perform corresponding measures to cooperate with the fault locating performed on the first sub-link.

[0009] In a possible implementation, the sending end device includes a first physical layer (physical, PHY) chip, the first sub-link is a link between the first PHY chip and a first mapping module, and the first mapping module is used to connect the first PHY chip and a sending end optical module. In this scenario, the first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, so as to obtain the foregoing first recombined link, where the second sub-link is a link from the first mapping module to the receiving end device. In this scenario, the first recombined link includes the second sub-link in addition to the first sub-link.

[0010] In a possible implementation, the sending-end device comprises a first PHY chip, and the receiving-end device comprises the second PHY chip. The first sub-link is a link from a first mapping module to a second mapping module, the first mapping module being configured to connect the first PHY chip and the sending-end optical module, and the second mapping module being configured to connect the second PHY chip and the receiving-end optical module. In this scenario, the first indication information triggers the first mapping module to switch a third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to a fourth sub-link in the second link, so as to obtain the first recombined link. The third sub-link is a link between the first PHY chip and the first mapping module, and the fourth sub-link is a link between the second mapping module and the second PHY chip. In this scenario, the first recombined link comprises the first sub-link, the third sub-link, and the fourth sub-link.

[0011] In a possible implementation, the first sub-link is a link between the second mapping module and the second PHY chip. In this scenario, the first indication information triggers the second mapping module to switch a fifth sub-link of the second link to the first sub-link, so as to obtain the first recombined link. The fifth sub-link is a link from the sending-end device to the second mapping module. In this scenario, the first recombined link comprises the first sub-link and the fifth sub-link.

[0012] In a possible implementation, the first frame can comprise at least one information field, and the first indication information can be carried in any one of the at least one information field. As a specific example, the at least one information field comprises a control field, and the first indication information is carried in the control field of the first frame.

[0013] In one possible implementation, the aforementioned at least one information field may further include a state field. In one example, the state field of the first frame may be used to indicate that the receiving device has completed the first preparatory operation required for the current fault location stage. In other words, the state field of the first frame may be used to indicate that the receiving device has completed the first preparatory operation for performing fault location on the first sub-link. The first preparatory operation may include a mapping relationship switching operation between the system-side channel unit and the line-side channel unit required by the second mapping module corresponding to the receiving device, so as to obtain the first reassembled link after performing the mapping relationship switching operation. As mentioned above, the first preparatory operation includes: the second mapping module corresponding to the receiving device switching the first sub-link to the fourth sub-link in the second link, the fourth sub-link being the link between the second mapping module and the second PHY chip included in the receiving device; or, the second mapping module switching the fifth sub-link of the second link to the first sub-link, the fifth sub-link being the link from the transmitting device to the second mapping module.

[0014] In one possible implementation, the receiving device performs fault detection on the first reconnection link. Specifically, the receiving device performs fault detection on the first reconnection link based on a second frame sent by the sending device to the receiving device through the first reconnection link. That is, the sending device can send a second frame to the receiving device through the first reconnection link. Correspondingly, the receiving device can perform fault detection on the first reconnection link based on this second frame.

[0015] In one possible implementation, the second frame may include a test data stream. The receiving device can determine whether the first reassembly link is faulty by measuring the bit error rate (BER) transmitted on the first reassembly link using this test data stream. For example, the receiving device can determine that the first reassembly link is faulty if the BER is greater than or equal to a preset BER threshold, and determine that the first reassembly link is fault-free if the BER is less than the preset BER threshold. In a specific example, the test data stream may be a pseudo-random binary sequence (PRBS). In other words, the second frame includes a PRBS, and the BER of the PRBS transmitted on the first reassembly link is used to determine the fault detection result.

[0016] In one possible implementation, the second frame may include a control field carrying second indication information, which indicates whether locating the fault location of the first link includes the first sub-link.

[0017] In one possible implementation, the second frame may also include a state field, which indicates that the transmitting device has completed a second preparatory operation for fault location of the first sub-link. The second preparatory operation may include a mapping relationship switching operation between the system-side channel unit and the line-side channel unit required by the first mapping module corresponding to the transmitting device, so that a first reassembled link can be obtained after performing this mapping relationship switching operation. As previously described, the second preparatory operation includes: the first mapping module corresponding to the transmitting device switching the first sub-link to a second sub-link in the second link, the second sub-link being the link from the first mapping module to the receiving device; or, the first mapping module switching a third sub-link in the second link to the first sub-link, the third sub-link being the link between the first PHY chip and the first mapping module, the transmitting device including the first PHY chip.

[0018] In one possible implementation, the transmitting device is a transmitting network device, and the first mapping module is located within the transmitting network device. In this scenario, when the first sub-link is the link between the first PHY chip and the first mapping module, if a fault is located in the first sub-link, it indicates that the transmitting network device is faulty.

[0019] In one possible implementation, the first mapping module is located in the transmitting optical module.

[0020] In one possible implementation, the first mapping module can perform a second preparatory operation to determine whether the fault location of the first link includes the first sub-link, based on the channel switching instruction sent by the first PHY chip. As an example, the first PHY chip can send a channel switching instruction to the first mapping module, which indicates the value of a register. Further, the first mapping module can complete the aforementioned second preparatory operation based on the register value indicated by the channel switching instruction. The register value mentioned here indicates the mapping relationship between the system-side channel unit and the line-side channel unit of the first mapping module.

[0021] In one possible implementation, the receiving device is a receiving network device, and the second mapping module is located within the receiving network device. In this scenario, when the first sub-link is the link between the second PHY chip and the second mapping module, if a fault is located in the first sub-link, it indicates that the receiving network device is faulty.

[0022] In one possible implementation, the second mapping module is located in the receiver optical module.

[0023] In one possible implementation, the second mapping module is used to perform a first preparatory operation for fault location of the first sub-link based on the channel switching instruction sent by the second PHY chip.

[0024] In one possible implementation, the first mapping module may be a first chip, for example, the first mapping module is a chip in the transmitting network device that is different from the first PHY chip.

[0025] In one possible implementation, the first mapping module may be a first functional circuit, for example, the first mapping module is a functional circuit in a first PHY chip.

[0026] In one possible implementation, the second mapping module may be a second chip, for example, the second mapping module is a chip in the receiving network device that is different from the second PHY chip.

[0027] In one possible implementation, the second mapping module may be a second functional circuit, for example, the second mapping module is a functional circuit in a second PHY chip.

[0028] In one possible implementation, since only the first sub-link originates from the faulty first link among the multiple sub-links included in the first reassembled link, and the other sub-links originate from the fault-free second link, in other words, in the first reassembled link, except for the first sub-link whose fault status is not yet clear, the other sub-links can be determined to be fault-free. Therefore, the fault detection result of the first reassembled link is also the fault detection result of the first sub-link. That is, if the fault detection result of the first reassembled link indicates that the first reassembled link is faulty, it means that the first sub-link is faulty. If the fault detection result of the first reassembled link indicates that the first reassembled link is not faulty, it means that the first sub-link is not faulty. Therefore, in the specific implementation of the receiving device "based on the fault detection result of the first reassembled link, determining whether the fault location of the first link includes the first sub-link", if the fault detection result indicates that the first reassembled link is faulty, then the receiving device determines that the fault location of the first link includes the first sub-link; if the fault detection result indicates that the first reassembled link is not faulty, then the receiving device determines that the fault location of the first link does not include the first sub-link.

[0029] Secondly, this application provides a fault location device applied to a receiving device. The device includes: a determining unit, configured to determine a first reassembled link to be detected, the first reassembled link including a first sub-link, the first sub-link being a faulty first link, the first reassembled link being a link formed by replacing a corresponding link in a fault-free second link with the first sub-link, the first link, the second link, and the first reassembled link being links from a transmitting device to the receiving device, the transmitting device and the receiving device communicating via an optical fiber link; and a processing unit, configured to: perform fault detection on the first reassembled link; and, based on the fault detection result of the first reassembled link, determine whether the fault location of the first link includes the first sub-link.

[0030] In one possible implementation, the determining unit specifically includes a sending unit; the sending unit is configured to send a first frame to the sending end device, the first frame including first indication information, the first indication information indicating fault location for the first sub-link.

[0031] In one possible implementation, the transmitting device includes a first physical layer PHY chip, the first sub-link is a link between the first PHY chip and a first mapping module, the first mapping module is used to connect the first PHY chip and the transmitting optical module; the first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, the second sub-link is a link from the first mapping module to the receiving device, and the first reconnection link further includes the second sub-link.

[0032] In one possible implementation, the first sub-link is the link from the first mapping module to the second mapping module. The first mapping module connects the first PHY chip and the transmitting optical module, and the second mapping module connects the second PHY chip and the receiving optical module. The transmitting device includes the first PHY chip, and the receiving device includes the second PHY chip. The first indication information triggers the first mapping module to switch the third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to the fourth sub-link in the second link. The first reconnected link also includes the third sub-link and the fourth sub-link. The third sub-link is the link between the first PHY chip and the first mapping module, and the fourth sub-link is the link between the second mapping module and the second PHY chip.

[0033] In one possible implementation, the first sub-link is a link between the second mapping module and the second PHY chip, the receiving device includes the second PHY chip, and the second mapping module is used to connect the second PHY chip and the receiving optical module; the first indication information triggers the second mapping module to switch the fifth sub-link of the second link to the first sub-link, the first reconnected link also includes the fifth sub-link, and the fifth sub-link is the link from the transmitting device to the second mapping module.

[0034] In one possible implementation, the first indication information is carried through the control field of the first frame.

[0035] In one possible implementation, the first frame further includes a state field, which indicates that the receiving device has completed a first preparatory operation for fault location of the first sub-link. The first preparatory operation includes: the second mapping module corresponding to the receiving device switching the first sub-link to a fourth sub-link in the second link, wherein the fourth sub-link is a link between the second mapping module and the second PHY chip included in the receiving device; or, the second mapping module switching the fifth sub-link of the second link to the first sub-link, wherein the fifth sub-link is a link from the transmitting device to the second mapping module.

[0036] In one possible implementation, the processing unit is configured to: perform fault detection on the first reconnection link based on a second frame sent by the transmitting device to the receiving device through the first reconnection link.

[0037] In one possible implementation, the second frame includes a pseudo-random binary sequence (PRBS), the bit error rate of which is transmitted on the first reassembly link, to determine the fault detection result.

[0038] In one possible implementation, the second frame further includes a control field, which includes second indication information indicating whether locating the fault location of the first link includes the first sub-link.

[0039] In one possible implementation, the second frame further includes a state field indicating that the transmitting device has completed a second preparatory operation for fault location of the first sub-link. The second preparatory operation includes: the first mapping module corresponding to the transmitting device switching the first sub-link to a second sub-link in the second link, the second sub-link being the link from the first mapping module to the receiving device; or, the first mapping module switching a third sub-link in the second link to the first sub-link, the third sub-link being the link between the first PHY chip and the first mapping module, the transmitting device including the first PHY chip.

[0040] In one possible implementation, the transmitting device is a transmitting network device, and the first mapping module is located in the transmitting network device.

[0041] In one possible implementation, the first mapping module is located in the transmitting optical module.

[0042] In one possible implementation, the first mapping module is used to perform a second preparation operation to determine whether the fault location of the first link includes the first sub-link, based on the channel switching instruction sent by the first PHY chip.

[0043] In one possible implementation, the receiving device is a receiving network device, and the second mapping module is located in the receiving network device.

[0044] In one possible implementation, the second mapping module is located in the receiver optical module.

[0045] In one possible implementation, the second mapping module is used to perform a first preparation operation to determine whether the fault location of the first link includes the first sub-link, based on the channel switching instruction sent by the second PHY chip.

[0046] In one possible implementation, the first mapping module includes a first chip or a first functional circuit; and / or, the second mapping module includes a second chip or a second functional circuit.

[0047] In one possible implementation, the processing unit is configured to: if the fault detection result indicates that the first reconnection link has a fault, then locate the fault location of the first link including the first sub-link; or, if the fault detection result indicates that the first reconnection link does not have a fault, then locate the fault location of the first link excluding the first sub-link.

[0048] Thirdly, embodiments of this application provide a communication device, including: a processor and a memory;

[0049] The memory is used to store instructions; the processor is used to execute the instructions, causing the communication device to perform the method described in the first aspect and any one of the first aspects.

[0050] Fourthly, embodiments of this application provide a communication device, including a communication interface and a processor connected to the communication interface. The communication interface is used to perform the transmit and receive operations in the methods described in the first aspect and any one of the methods described in the first aspect above, and the processor is used to perform other operations in the methods described in the first aspect and any one of the methods described in the first aspect above, excluding the transmit and receive operations.

[0051] Fifthly, this application provides a chip including an interface circuit and a processing circuit, the chip being used to perform the method described in the first aspect above and any one of the first aspects above; wherein, the interface circuit is used to receive and / or transmit data, and the processing circuit is used to perform data processing.

[0052] In a specific example, the interface circuit is used to determine a first reassembled link to be detected. The first reassembled link includes a first sub-link, which is a faulty first link. The first reassembled link is formed by replacing a corresponding link in a fault-free second link with the first sub-link. The first link, the second link, and the first reassembled link are all links from the transmitting device to the receiving device, and the transmitting device and the receiving device communicate via an optical fiber link. The processing circuit is used to perform fault detection on the first reassembled link and, based on the fault detection result of the first reassembled link, determine whether the fault location of the first link includes the first sub-link.

[0053] In a sixth aspect, embodiments of this application provide a computer-readable storage medium, including instructions or a computer program, which, when executed on a processor, implement the method described in the first aspect and any one of the first aspects.

[0054] In a seventh aspect, embodiments of this application provide a computer program product, including a computer program product that, when run on a processor, implements the method described in the first aspect and any one of the first aspects. Attached Figure Description

[0055] Figure 1a is a schematic diagram of an exemplary application scenario provided by an embodiment of this application;

[0056] Figure 1b is a schematic diagram of another exemplary application scenario provided by an embodiment of this application;

[0057] Figure 1c is a schematic diagram of another exemplary application scenario provided by the embodiments of this application;

[0058] Figure 2a is a schematic diagram of an exemplary application scenario provided by an embodiment of this application;

[0059] Figure 2b is a schematic diagram of another exemplary application scenario provided by an embodiment of this application;

[0060] Figure 2c is a schematic diagram of another exemplary application scenario provided by the embodiments of this application;

[0061] Figure 3 is a flowchart illustrating a fault location method provided in an embodiment of this application;

[0062] Figure 4a is a schematic diagram of a first reassembly link provided in an embodiment of this application;

[0063] Figure 4b is a schematic diagram of yet another first reassembly link provided in an embodiment of this application;

[0064] Figure 4c is a schematic diagram of yet another first reassembly link provided in an embodiment of this application;

[0065] Figure 4d is a schematic diagram of an exemplary application scenario provided by an embodiment of this application;

[0066] Figure 5a is a schematic diagram of an exemplary application scenario provided by an embodiment of this application;

[0067] Figure 5b is a schematic diagram of a fault location method provided in an embodiment of this application;

[0068] Figure 5c is a schematic diagram of a fault location method provided in an embodiment of this application;

[0069] Figure 5d is a schematic diagram of a fault location method provided in an embodiment of this application;

[0070] Figure 6a is a schematic diagram of another exemplary application scenario provided by an embodiment of this application;

[0071] Figure 6b is a schematic diagram of another exemplary application scenario provided by the embodiments of this application;

[0072] Figure 6c is a schematic diagram of another exemplary application scenario provided by the embodiments of this application;

[0073] Figure 7 is a structural schematic diagram of a fault location device provided in an embodiment of this application;

[0074] Figure 8 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0075] Figure 9 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0076] Figure 10 is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0077] This application provides a fault location method and apparatus, which can locate the specific fault point in the link after a link failure occurs.

[0078] To facilitate understanding of this solution, the application scenarios of this application will be introduced first.

[0079] Referring to Figure 1a, this figure is a schematic diagram of an exemplary application scenario provided by an embodiment of this application.

[0080] As shown in Figure 1a:

[0081] Network device 1 includes a PHY chip 1, an electrical signal processing unit 1, and an optical module 1. The electrical signal processing unit 1 connects the PHY chip 1 and the optical module 1. The side of the electrical signal processing unit 1 connected to the PHY chip 1 is the system side, and the side connected to the optical module 1 is the line side. The optical module 1 includes an optical transmitting unit for transmitting signals to the optical fiber and an optical receiving unit for receiving signals from the optical fiber. In one example, the electrical signal processing unit 1 may be located within network device 1. For example, the electrical signal processing unit 1 may be another chip in network device 1, different from the PHY chip 1 (e.g., a clock data recovery (CDR) chip). Alternatively, the electrical signal processing unit 1 may be a functional circuit located in network device 1, such as a functional circuit located in the PHY chip 1. In yet another example, the electrical signal processing unit 1 may be located within the optical module 1; for example, the electrical signal processing unit 1 may be a digital signal processor (DSP) within the optical module 1.

[0082] Network device 2 includes a PHY chip 2, an electrical signal processing unit 2, and an optical module 2. The electrical signal processing unit 2 connects the PHY chip 2 and the optical module 2. The side of the electrical signal processing unit 2 connected to the PHY chip 2 is the system side, and the side connected to the optical module 2 is the line side. The optical module 2 includes an optical transmitting unit for sending signals to the optical fiber and an optical receiving unit for receiving signals from the optical fiber. In one example, the electrical signal processing unit 2 may be located within network device 2. For example, the electrical signal processing unit 2 may be a separate chip from the PHY chip 2 located within network device 2. Alternatively, the electrical signal processing unit 2 may be a functional circuit located within network device 2, such as a functional circuit located within the PHY chip 2. In yet another example, the electrical signal processing unit 2 may be located within the optical module 2.

[0083] In some scenarios, an electrical signal processing unit can also be referred to as a mapping module. For example, electrical signal processing unit 1 can be called the first mapping module, and electrical signal processing unit 2 can be called the second mapping module. In this case, "electrical signal processing unit 1" and "first mapping module" refer to the same object, and they can be used interchangeably. Similarly, "electrical signal processing unit 2" and "second mapping module" refer to the same object, and they can be used interchangeably.

[0084] Currently, when a link fails, loopback technology can be used to pinpoint the specific point of failure. The link mentioned here could be, for example, the link between network device 1 and network device 2, the link between optical module 1 and network device 2, or the link between network device 1 and optical module 2.

[0085] Taking the link failure between network device 1 and network device 2 as an example, this paper introduces how to locate the specific fault point using loopback technology.

[0086] Currently, loopback can be configured at different locations in the link under offline conditions to achieve fault location in different link areas. Furthermore, by combining the fault location information corresponding to each location, the fault location area can be finally determined. As shown in Figure 1a:

[0087] Loopback configuration is supported at positions A1 and B1. For PHY chips (such as PHY chip 1 and PHY chip 2), there is a specific signal path dedicated to loopback inside the chip. When the PHY chip is configured to operate in loopback mode, the PHY chip guides the transmitting signal to the receiving end through its own specific path, forming a closed loop inside the PHY chip, ensuring the correct transmission of data inside the PHY chip.

[0088] The electrical signal processing units (e.g., electrical signal processing unit 1 and electrical signal processing unit 2) also support loopback configuration. These units can support both system-side and line-side loopbacks. The system-side loopbacks correspond to A2 and B2 in Figure 1a, while the line-side loopbacks correspond to A3 and B3 in Figure 1a.

[0089] In a specific example, service data signal loopback can be configured at location A2. If a service interruption occurs, the fault location can be determined to include the link between network device 1 and electrical signal processing unit 1. If no service interruption occurs after configuring service data signal loopback at location A2, the loopback configuration at location A2 is canceled, and service data signal loopback is configured at location B3. If a service interruption occurs after configuring service data signal loopback at location B3, the fault location can be determined to include the link between locations A2 and B3; that is, it can be determined that the optical module or fiber optic link is faulty. If no service interruption occurs after configuring service data signal loopback at location B3, the fault location can be determined to include the link between electrical signal processing unit 2 and network device 2.

[0090] Using loopback technology to locate faults often requires configuring loopbacks at multiple locations to pinpoint the specific fault point. For example, in the above example, loopbacks need to be configured at both locations A2 and B3. Configuring a loopback at only one location makes it difficult to locate the fault. Furthermore, loopbacks require manual configuration and cannot be automated, making it difficult to locate faults promptly after they occur using loopback technology. In other words, loopback technology is not an efficient method for fault location.

[0091] Furthermore, even using loopback technology for fault location cannot accurately pinpoint the fault. For example, for faults occurring in certain specific scenarios, loopback technology struggles to reproduce the fault scenario, thus making accurate fault location impossible. An example is given below, illustrated in Figure 1b. Figure 1b is a schematic diagram of another exemplary application scenario provided by an embodiment of this application.

[0092] A PHY chip consists of a transmitting section and a receiving section. Typically, the received signal undergoes analog-to-digital conversion, signal equalization, and decision-making processes. Different PHY chip manufacturers have different designs for the decision-making function, and the default configuration for the decision threshold can be either a fixed threshold or an adaptive threshold. If the decision threshold in the PHY chip is set to a fixed threshold mode and does not match the received signal, it may lead to link interruption.

[0093] For example, in the instance shown in Figure 1b, the PHY chip from manufacturer A sets the decision mode to a fixed threshold mode in its receiving section. Therefore, when the PHY chip from manufacturer A receives data from the PHY chip from manufacturer B, the set value of the decision threshold may not match the level of the received signal, leading to a link interruption. In other words, the link failure is caused by the unreasonable decision mode setting of the chip from manufacturer A.

[0094] If loopback technology is used for online fault localization, for example, loopback is performed at the location of electrical signal processing unit 1, as shown by the green arrow in Figure 1c. Figure 1c is a schematic diagram of another exemplary application scenario provided by the embodiments of this application. However, since the signals sent within the same chip match its own decision mode, the loopback test result is passed, thus the fault location result indicates that the PHY chip from manufacturer A is fault-free, and the fault location result is inaccurate.

[0095] Based on this, embodiments of this application provide a fault location method and apparatus that can accurately and efficiently locate faults.

[0096] Before introducing the solutions provided by the embodiments of this application, the application scenarios of the embodiments of this application are first introduced. The solutions provided by the embodiments of this application can be applied to the scenario shown in FIG1a. In one example, the internal structures of the PHY chip 1, electrical signal processing unit 1, and optical module 1 shown in FIG1a can be as shown in FIG2a. In another example, the internal structures of the PHY chip 2, electrical signal processing unit 2, and optical module 2 shown in FIG1a can also be as shown in FIG2a. FIG2a is a schematic diagram of an exemplary application scenario provided by the embodiments of this application.

[0097] In Figure 2a, the PHY chip can correspond to either PHY chip 1 or PHY chip 2 shown in Figure 1a, the electrical signal processing unit can correspond to either electrical signal processing unit 1 or electrical signal processing unit 2 shown in Figure 1a, and the optical module can correspond to either optical module 1 or optical module 2 shown in Figure 1a. In one example, when the PHY chip shown in Figure 2a corresponds to PHY chip 1 shown in Figure 1a, the electrical signal processing unit shown in Figure 2a can correspond to electrical signal processing unit 1 shown in Figure 1a, and the optical module shown in Figure 2a can correspond to optical module 1 shown in Figure 1a. In another example, when the PHY chip shown in Figure 2a corresponds to PHY chip 2 shown in Figure 1a, the electrical signal processing unit shown in Figure 2a can correspond to electrical signal processing unit 2 shown in Figure 1a, and the optical module shown in Figure 2a can correspond to optical module 2 shown in Figure 1a.

[0098] As shown in Figure 2a, the electrical signal processing unit includes a system-side channel unit, a mapping and switching unit, and a line-side channel unit. The system-side refers to the side of the electrical signal processing unit closer to the PHY chip, and the line-side refers to the side of the electrical signal processing unit closer to the optical module. That is, the system-side channel unit is used for communication with the PHY chip, and the line-side channel unit is used for communication with the optical module. The dashed arrows in the figure indicate that there may be other link segments between the electrical signal processing unit and the PHY chip, and between the electrical signal processing unit and the optical module.

[0099] The number of electrical signal transmission units (M Host TX) in the system-side channel unit shall not be less than two; Figure 2a shows four.

[0100] The number of electrical signal receiving units (M Host RX) in the system-side channel unit is no less than two; Figure 2a shows four.

[0101] The number of electrical signal transmission units (Line TX) in the line-side channel unit is no less than two; Figure 2a shows four.

[0102] The number of electrical signal receiving units (Line RX) in the line-side channel unit is no less than two; Figure 2a shows four.

[0103] The mapping switching unit supports crossing (or mapping) any electrical signal transmitting unit in the system-side channel unit to any electrical signal receiving unit in the line-side channel unit, and also supports crossing (or mapping) any electrical signal receiving unit in the system-side channel unit to any electrical signal transmitting unit in the line-side channel unit.

[0104] The PHY chip, also known as the service chip, has service forwarding and message processing functions. The PHY chip includes an electrical signal transmitting unit (C Host TX) and an electrical signal receiving unit (C Host RX).

[0105] In this application, after a failure occurs in the first link from the transmitting device to the receiving device, the receiving device can perform fault detection on the first reconstructed link. The first reconstructed link is a link reconstructed from a first sub-link of the faulty first link and a portion of a fault-free second link. The second link is also a link from the transmitting device to the receiving device. Since the second link is fault-free, the fault detection result of the first reconstructed link can characterize whether a fault exists in the first sub-link. Therefore, the receiving device can determine whether the fault location of the first link includes the first sub-link based on the fault detection result of the first reconstructed link.

[0106] The first link, the second link, and the first sub-link can be understood by referring to Figures 2b and 2c.

[0107] Referring to Figure 2b, which is a schematic diagram of another exemplary application scenario provided by an embodiment of this application. As shown in Figure 2b:

[0108] The PHY chip 1 of the network device 1 includes two electrical signal transmitting units and two electrical signal receiving units, namely electrical signal transmitting unit 1, electrical signal transmitting unit 2, electrical signal receiving unit 1 and electrical signal receiving unit 2.

[0109] The system-side channel unit of the electrical signal processing unit 1 includes: two system-side electrical signal receiving units (system-side electrical signal receiving unit 1 and system-side electrical signal receiving unit 2) and two system-side electrical signal transmitting units (system-side electrical signal transmitting unit 1 and system-side electrical signal transmitting unit 2). The line-side channel unit of the electrical signal processing unit 1 includes: two line-side electrical signal receiving units (line-side electrical signal receiving unit 1 and line-side electrical signal receiving unit 2) and two line-side electrical signal transmitting units (line-side electrical signal transmitting unit 1 and line-side electrical signal transmitting unit 2). The connection relationship between the system-side channel unit and the line-side channel unit of the electrical signal processing unit 1 is shown in Figure 2b, and will not be described in detail here.

[0110] Optical module 1 includes two optical transmitting units (optical transmitting unit 1 and optical transmitting unit 2) and two optical receiving units (optical receiving unit 1 and optical receiving unit 2). The connection relationship between each unit of optical module 1 and the line-side channel unit of electrical signal processing unit 1 is shown in Figure 2b, which will not be described in detail here.

[0111] The PHY chip 2 of the network device 2 includes two electrical signal transmitting units and two electrical signal receiving units, namely electrical signal transmitting unit 1, electrical signal transmitting unit 2, electrical signal receiving unit 1 and electrical signal receiving unit 2.

[0112] The system-side channel unit of the electrical signal processing unit 2 includes: two system-side electrical signal receiving units (system-side electrical signal receiving unit 1 and system-side electrical signal receiving unit 2) and two system-side electrical signal transmitting units (system-side electrical signal transmitting unit 1 and system-side electrical signal transmitting unit 2). The line-side channel unit of the electrical signal processing unit 2 includes: two line-side electrical signal receiving units (line-side electrical signal receiving unit 1 and line-side electrical signal receiving unit 2) and two line-side electrical signal transmitting units (line-side electrical signal transmitting unit 1 and line-side electrical signal transmitting unit 2). The connection relationship between the system-side channel unit and the line-side channel unit of the electrical signal processing unit 2 is shown in Figure 2b, and will not be described in detail here.

[0113] Optical module 2 includes two optical transmitting units (optical transmitting unit 1 and optical transmitting unit 2) and two optical receiving units (optical receiving unit 1 and optical receiving unit 2). The connection relationship between each unit of optical module 2 and the line-side channel unit of electrical signal processing unit 2 is shown in Figure 2b, and will not be described in detail here.

[0114] Optical module 1 and optical module 2 can be connected by optical fiber. The connection relationship between each unit of optical module 1 and each unit of optical module 2 is shown in Figure 2b, which will not be described in detail here.

[0115] As shown in Figure 2b, there are four links between PHY chip 1 and PHY chip 2. Links 1 and 3 connect PHY chip 1 to PHY chip 2, while links 2 and 4 connect PHY chip 2 to PHY chip 1. If PHY 1 is the transmitter and PHY 2 is the receiver, then links 1 and 3 can be called transmitting links, and links 2 and 4 can be called receiving links. In one example, links 1 and 2 form a transmit-receive link set, and links 3 and 4 also form a transmit-receive link set.

[0116] Figure 2c illustrates another exemplary application scenario provided by the embodiments of this application. The application scenario shown in Figure 2c is the same as that shown in Figure 2b, except that in Figure 2c, the optical transmitting unit in the optical module is further subdivided into two parts: the drive and the transmitter optical subassembly (TOSA), and the optical receiving unit in the optical module is further subdivided into two parts: the trans-impedance amplifier (TIA) and the receiver optical subassembly (ROSA).

[0117] As shown in Figure 2c, link 1 can include 3 sub-links, which correspond to sub-link 1, sub-link 2 and sub-link 3 shown in Figure 2c respectively.

[0118] Link 3 also includes three sub-links, corresponding to sub-link 1', sub-link 2', and sub-link 3' as shown in Figure 2c. Wherein:

[0119] Sub-link 1' corresponds to sub-link 1, both of which are links from PHY chip 1 to electrical signal processing unit 1.

[0120] Sub-link 2' and sub-link 2 correspond to each other, and both are links from electrical signal processing unit 1 to electrical signal processing unit 2.

[0121] Sub-link 3' and sub-link 3 correspond to each other, both of which are links from the electrical signal processing unit 2 to the PHY chip 2.

[0122] In scenario 1, the sending device is network device 1, and the receiving device is network device 2. In this case, the first link can be, for example, link 1 as shown in Figure 2b or Figure 2c, and the second link can be, for example, link 3 as shown in Figure 2b or Figure 2c. Correspondingly, the first sub-link can be any one of sub-link 1, sub-link 2, and sub-link 3.

[0123] In scenario 2, the transmitting device is network device 1, and the receiving device is optical module 2. In this case, the first link can be, for example, the portion of link 1 shown in Figure 2b or 2c that extends from network device 1 to optical module 2, and the second link can be, for example, the portion of link 3 shown in Figure 2b or 2c that extends from network device 1 to optical module 2. Correspondingly, the first sub-link can be sub-link 1. For a scenario where the electrical signal processing unit is located in optical module 2, the first sub-link can also be sub-link 2.

[0124] In scenario 3, the transmitting device is optical module 1, and the receiving device is network device 2. In this case, the first link can be, for example, the portion of link 1 shown in Figure 2b or 2c that extends from optical module 1 to network device 2, and the second link can be, for example, the portion of link 3 shown in Figure 2b or 2c that extends from optical module 1 to network device 2. Correspondingly, the first sub-link can be sub-link 3. For a scenario where the electrical signal processing unit 1 is located within optical module 1, the first sub-link can also be sub-link 2.

[0125] Next, taking the scenario shown in Figure 2c as an example and referring to the flowchart shown in Figure 3, the fault location method provided by the embodiments of this application will be introduced. Figure 3 is a flowchart illustrating a fault location method provided by an embodiment of this application.

[0126] The method shown in Figure 3 can be applied to a receiving device. The receiving device can be, for example, network device 2 or optical module 2 as shown in Figure 2c. The receiving device can locate the cause of a fault in the first link between the transmitting device and the receiving device. As described above, when the receiving device is network device 2, the transmitting device can be network device 1 or optical module 1; when the receiving device is optical module 2, the transmitting device is network device 1.

[0127] The method shown in Figure 3 may include the following steps S101-S103.

[0128] S101: The receiving device determines the first reassembled link to be detected. The first reassembled link includes a first sub-link. The first sub-link is a faulty first link. The first reassembled link is formed by replacing the corresponding link in the faultless second link with the first link. The first link, the second link, and the first reassembled link are all links from the transmitting device to the receiving device. The transmitting device and the receiving device communicate through an optical fiber link.

[0129] In this embodiment of the application, if the sending device is network device 1 and the receiving device is network device 2, then the first link can correspond to link 1 shown in Figure 2c, and the second link can correspond to link 2 in Figure 2c. In this case:

[0130] In one example, the first sub-link can be sub-link 1 in Figure 2c. Correspondingly, the first reassembled link can be a link formed by sub-link 1 replacing sub-link 1' in link 2. In this case, the first reassembled link can be understood with reference to Figure 4a, which is a schematic diagram of a first reassembled link provided by an embodiment of this application. The link indicated by the red arrow in Figure 4a is the first reassembled link.

[0131] In another example, the first sub-link can be sub-link 2 in Figure 2c. Correspondingly, the first reassembled link can be a link formed by sub-link 2 replacing sub-link 2' in link 2. In this case, the first reassembled link can be understood with reference to Figure 4b, which is a schematic diagram of another first reassembled link provided by an embodiment of this application. The link indicated by the red arrow in Figure 4b is the first reassembled link.

[0132] In another example, the first sub-link can be sub-link 3 in Figure 2c. Correspondingly, the first reassembled link can be a link formed by sub-link 3 replacing sub-link 3' in link 2. In this case, the first reassembled link can be understood with reference to Figure 4c, which is a schematic diagram of another first reassembled link provided by an embodiment of this application. The link indicated by the red arrow in Figure 4c is the first reassembled link.

[0133] In this embodiment of the application, if the transmitting device is network device 1 and the receiving device is optical module 2, then the first link can correspond to the portion of link 1 shown in Figure 2c from network device 1 to optical module 2, and the second link can correspond to the portion of link 2 shown in Figure 2c from network device 1 to optical module 2. In this case:

[0134] In one example, the first sub-link can be sub-link 1 in Figure 2c. Correspondingly, the first reassembled link can be the link formed by sub-link 1 replacing sub-link 1' in link 2. In this case, the first reassembled link can be the portion of the link indicated by the red arrow in Figure 4a that extends from network device 1 to optical module 2.

[0135] In this embodiment of the application, if the transmitting device is optical module 1 and the receiving device is network device 2, then the first link can correspond to the portion of link 1 shown in Figure 2c where optical module 1 reaches network device 2, and the second link can correspond to the portion of link 2 shown in Figure 2c where optical module 1 reaches network device 2. In this case:

[0136] In one example, the first sub-link can be sub-link 3 in Figure 2c. Correspondingly, the first reassembled link can be the link formed by sub-link 3 replacing sub-link 3' in link 2. In this case, the first reassembled link can be the portion of the link indicated by the red arrow in Figure 4c that extends from optical module 1 to network device 2.

[0137] In one example, the receiving device can locate the fault in the first link after determining that the first link is faulty. Specifically, the receiving device can execute S101-S103 to locate the fault in the first link.

[0138] In this embodiment, after determining that the first link is faulty, the receiving device can determine multiple sub-links included in the first link and select one of the sub-links as the first sub-link. This embodiment does not specifically limit the specific implementation method of the receiving device determining the first link fault. For example, the receiving device can determine that the first link is faulty when the bit error rate corresponding to the first link is higher than a certain threshold. Alternatively, the receiving device can select a fault-free link from other links (excluding the first link) from the transmitting device to the receiving device as the second link. Further, a first reassembled link is determined, formed by replacing the corresponding link in the second link with the first sub-link.

[0139] In one example, when the first link includes multiple sub-links, the receiving device can determine whether the fault location of the first link includes each of the aforementioned sub-links. For example, when the first link corresponds to link 1 shown in Figure 2c, the receiving device can determine whether the fault location of the first link includes sub-link 1 (in this case, sub-link 1 is the first sub-link), whether the fault location of the first link includes sub-link 2 (in this case, sub-link 2 is the first sub-link), and whether the fault location of the first link includes sub-link 3 (in this case, sub-link 3 is the first sub-link). In other words, locating the fault location of the first link can include multiple stages; for example, in the above example, locating the fault location of the first link can include three stages.

[0140] For ease of description, determining whether the fault location of the first link includes sub-link 1 is called stage 1; determining whether the fault location of the first link includes sub-link 3 is called stage 2; and determining whether the fault location of the first link includes sub-link 2 is called stage 3.

[0141] In one example, the receiving device may send a first frame to the sending device, the first frame including first indication information. The first indication information can be used to indicate the current stage of fault location for the first link. Different stages require locating different sub-links, and each stage has a corresponding first sub-link. For example, the first sub-link corresponding to stage 1 is sub-link 1, the first sub-link corresponding to stage 2 is sub-link 3, and the first sub-link corresponding to stage 3 is sub-link 2. Since there is a one-to-one correspondence between stages and first sub-links, the aforementioned first indication information can be used to indicate whether fault location is performed on the first sub-link. Performing fault location on the first sub-link can also be understood as determining whether the fault location of the first link includes the first sub-link.

[0142] In one example, the receiving device can send the first frame to the sending device via a third link. The third link can be any link from the receiving device to the sending device. In a specific example, the third link and the first link can be a set of transmit / receive links between the sending device and the receiving device. For example, if the first link corresponds to link 1 shown in Figure 2c, then the third link can correspond to link 2 shown in Figure 2c.

[0143] In one example, if the first sub-link is link 1 as shown in Figure 2c, the first indication information can be used to trigger the electrical signal processing unit 1 to switch the first sub-link to the second sub-link in the second link, so as to replace the corresponding sub-link 1' in the second link with sub-link 1, thereby obtaining a first reconstructed link that retains the first sub-link but avoids other sub-links in the first link except for the first sub-link. In this case, the first reconstructed link includes two sub-links, the first sub-link and the second sub-link. In other words, in the first reconstructed link, only the first sub-link comes from the faulty first link, and the other part (i.e., the second sub-link) comes from the fault-free second link. In this scenario, the second sub-link is the link from the electrical signal processing unit 1 to the receiving device. For example, when the receiving device is network device 2, the second sub-link is the link from the electrical signal processing unit 1 to network device 2. As another example, when the receiving device is optical module 2, the second sub-link is the link from the electrical signal processing unit 1 to optical module 2. Refer to Figure 4a for understanding. In this scenario, after receiving the first instruction information, the electrical signal processing unit 1 can map its own M Host RX1 to Line TX2 to switch the first sub-link to the second sub-link in the second link.

[0144] In one example, if the first sub-link is link 2 as shown in Figure 2c, the first indication information can be used to trigger the electrical signal processing unit 1 to switch the third sub-link in the second link to the first sub-link, and to trigger the electrical signal processing unit 2 to switch the first sub-link to the fourth sub-link in the second link, so as to replace the corresponding sub-link 1' in the second link with sub-link 1, thereby obtaining a first reconstructed link that retains the first sub-link but avoids other sub-links in the first link except for the first sub-link. In this case, the first reconstructed link may include three sub-links: the first sub-link, the third sub-link, and the fourth sub-link. In other words, in the first reconstructed link, only the first sub-link comes from the faulty first link, and the other parts (i.e., the third and fourth sub-links) come from the fault-free second link. In this scenario, the third sub-link is the link between PHY chip 1 and electrical signal processing unit 1, and the fourth sub-link is the link between electrical signal processing unit 2 and PHY chip 2. Referring to Figure 4b, in this scenario, after receiving the first instruction information, the electrical signal processing unit 2 can map its own M Host TX2 to Line RX1 to switch the first sub-link to the fourth sub-link in the second link. Similarly, after receiving the first instruction information, the electrical signal processing unit 1 can map its own M Host RX2 to Line TX1 to switch the third sub-link in the second link to the first sub-link.

[0145] In one example, if the first sub-link is link 3 as shown in Figure 2c, the first indication information can be used to trigger the electrical signal processing unit 2 to switch the fifth sub-link in the second link to the first sub-link. Alternatively, the first indication information can be used to trigger the electrical signal processing unit 2 to switch the first sub-link to the fifth sub-link in the second link, thereby replacing the corresponding sub-link 1' in the second link with sub-link 1, thus obtaining a first reconstructed link that retains the first sub-link but avoids other sub-links in the first link. In this case, the first reconstructed link includes both the first and fifth sub-links. In other words, in the first reconstructed link, only the first sub-link comes from the faulty first link, while the other part (i.e., the fifth sub-link) comes from the fault-free second link. In this scenario, the fifth sub-link is the link from the transmitting device to the electrical signal processing unit 2. For example, when the transmitting device is network device 1, the fifth sub-link is the link from network device 1 to the electrical signal processing unit 2. Similarly, when the transmitting device is optical module 1, the fifth sub-link is the link from optical module 1 to the electrical signal processing unit 2. Refer to Figure 4c for understanding. In this scenario, after receiving the first instruction information, the electrical signal processing unit 2 can map its own M Host TX1 to Line RX2 to switch the first sub-link to the fifth sub-link in the second link (or switch the fifth sub-link to the first sub-link).

[0146] In one example, the first frame may include at least one information field, and the aforementioned first indication information may be carried through any one of the aforementioned at least one information field. As a specific example, the aforementioned at least one information field includes a control field, and the aforementioned first indication information is carried through the control field in the first frame. In one possible implementation, the first indication information may be carried through two bits in the control field. Assuming that the first indication information is carried through the (X+1)th bit and the Xth bit of the control field, the specific meanings of the (X+1)th bit and the Xth bit can be understood through Table 1 below.

[0147] Table 1

[0148] In Table 1:

[0149] "Fault diagnosis of peer network equipment" corresponds to stage 1 mentioned above. Taking Figure 2c as an example, in this stage, it is used to determine whether the fault location of link 1 includes sub-link 1.

[0150] "Local network device fault diagnosis" corresponds to stage 2 mentioned above. Taking Figure 2c as an example, in this stage, it is used to determine whether the fault location of link 1 includes sub-link 3.

[0151] "Optical module or optical link fault diagnosis", corresponding to stage 3 mentioned above. Taking Figure 2c as an example, in this stage, it is used to determine whether the fault location of link 1 includes sub-link 2.

[0152] It should be noted that the contents shown in Table 1 are only for the convenience of understanding this solution and do not constitute a limitation on the embodiments of this application. The values ​​of X+1:X and their corresponding meanings are not limited to those shown in Table 1.

[0153] In one example, the aforementioned at least one information field may further include a state field. In one example, the state field of the first frame may be used to indicate that the receiving device has completed the first preparatory operation required for the current fault location stage. In other words, the state field of the first frame may be used to indicate that the receiving device has completed the first preparatory operation for performing fault location on the first sub-link. The first preparatory operation may include the mapping relationship switching operation between the system-side channel unit and the line-side channel unit required by the electrical signal processing unit 2 corresponding to the receiving device, so as to obtain the first reassembled link after performing the mapping relationship switching operation. As mentioned above, when the first sub-link corresponds to link 2 shown in FIG. 2c, the first preparatory operation may include the electrical signal processing unit 2 switching the first sub-link to the fourth sub-link in the second link. When the first sub-link corresponds to link 3 shown in FIG. 2c, the first preparatory operation may include the electrical signal processing unit 2 switching the fifth sub-link of the second link to the first sub-link.

[0154] In one example, the completion of the aforementioned first preparation operation can be indicated by one or more bits in the state field of the first frame. In one possible implementation, the completion of the aforementioned first preparation operation can be achieved by one bit in the state field. Assuming that the completion of the aforementioned first preparation operation is indicated by the Y-th bit in the control field, the specific meaning of the Y-th bit can be understood from Table 2 below.

[0155] Table 2

[0156] As shown in Table 1, if the value of the Y bit in the state field of the first frame is 1, it means that the receiving device has completed the aforementioned first preparation operation; if the value of the Y bit in the state field of the first frame is 0, it means that the receiving device has not yet completed the first preparation operation.

[0157] In one example, the receiving device may send the first frame to the sending device after the first preparation operation is completed.

[0158] In the embodiments of this application, the first frame may be a frame with a certain structure. In a specific example, the first frame may be a training frame. In addition to the control domain and the state domain, the training frame may also include, for example, a flag bit for identifying the training frame. This flag bit may be, for example, a specific 4-pulse amplitude modulation (PAM4) symbol sequence consisting of 16 consecutive "3"s and 16 consecutive "0"s.

[0159] In one example, the electrical signal processing unit 2 may include a register whose value indicates the mapping relationship between the system-side channel units and the line-side channel units of the electrical signal processing unit 2. The electrical signal processing unit 2 can adjust the value of the register itself to adjust the mapping relationship between its own system-side channel units and line-side channel units. In other words, the electrical signal processing unit 2 can adjust the value of the aforementioned register itself to complete the aforementioned first preparation operation.

[0160] In another example, the electrical signal processing unit 2 can also adjust the mapping relationship between its system-side channel unit and line-side channel unit based on the value of the register set by the PHY chip 2. In other words, the electrical signal processing unit 2 can complete the aforementioned first preparation operation based on the value of the register set by the PHY chip 2. As an example, the PHY chip 2 can send a channel switching instruction to the electrical signal processing unit 2, which is used to indicate the value of the aforementioned register. Further, the electrical signal processing unit 2 can complete the aforementioned first preparation operation based on the value of the register indicated by the aforementioned channel switching instruction. As described above, the receiving device can select one fault-free link from other links other than the first link that connect the transmitting device to the receiving device as the second link. In the embodiments of this application, the receiving device can also announce its selected second link to the transmitting device so that the transmitting device can perform the second preparation operation of fault location on the first sub-link to obtain the first reassembled link.

[0161] In one example, the receiving device can notify the sending device of the information of the second link through the state field of the aforementioned first frame, so that the sending device can determine the second link. For example, the information of the second link can be carried by at least two bits in the state field. For example, these two bits can be used to carry the channel number corresponding to the second link. For example, when the channel number is 3, it indicates that the second link is the third link in the links from the sending device to the receiving device; or, when the channel number is 5, it indicates that the second link is the fifth link in the links from the sending device to the receiving device.

[0162] In another example, the receiving device can send a third frame to the sending device via a fourth link. The state and control fields of this third frame do not carry any valid information. For example, the (X+1)th and Xth bits of the control field of the third frame are both 0, and the Yth bit of the state field is also 0. Here, the fourth link and the second link form a transceiver link between the sending and receiving devices. After receiving the third frame, since neither the state nor control fields carry valid information, the sending device can determine that the third frame is used to notify the reference link (i.e., the second link) involved in fault location. Therefore, the sending device can identify the other link that forms a transceiver link with the fourth link as the second link.

[0163] In another example, the transmitting device can also select a second link from among multiple links leading from the transmitting device to the receiving device. For instance, each of the multiple links from the transmitting device to the receiving device has a number, and both the transmitting and receiving devices can select the link with the number closest to the first link as the second link. For example, if the multiple links are numbered 1, 3, 5, and 7, and the first link is numbered 1, then both the transmitting and receiving devices would select the link numbered 3 as the second link.

[0164] In one example, after the sending device determines the second link, it can stop sending service data on the second link so that it can subsequently use the second link to locate the fault in the first link.

[0165] Regarding the second preparation operation, it should be noted that the second preparation operation may include the mapping relationship switching operation between the system-side channel unit and the line-side channel unit required by the electrical signal processing unit 1 corresponding to the transmitting device, so as to obtain the first reassembled link after performing the mapping relationship switching operation. As mentioned above, when the first sub-link corresponds to link 1 shown in Figure 2c, the second preparation operation may include the electrical signal processing unit 1 switching the first sub-link to the second sub-link in the second link. When the first sub-link corresponds to link 3 shown in Figure 2c, the second preparation operation may include the electrical signal processing unit 1 switching the third sub-link of the second link to the first sub-link.

[0166] In one example, the electrical signal processing unit 1 may include a register whose value indicates the mapping relationship between the system-side channel units and the line-side channel units of the electrical signal processing unit 1. The electrical signal processing unit 1 can adjust the value of the register itself to adjust the mapping relationship between its own system-side channel units and line-side channel units. In other words, the electrical signal processing unit 1 can adjust the value of the aforementioned register itself to complete the aforementioned second preparation operation.

[0167] In another example, the electrical signal processing unit 1 can also adjust the mapping relationship between its system-side channel units and line-side channel units based on the value of the register set by the PHY chip 1. In other words, the electrical signal processing unit 1 can complete the aforementioned second preparation operation based on the value of the register set by the PHY chip 1. As an example, the PHY chip 1 can send a channel switching instruction to the electrical signal processing unit 1, which indicates the value of the aforementioned register. Further, the electrical signal processing unit 1 can complete the aforementioned second preparation operation based on the value of the register indicated by the aforementioned channel switching instruction.

[0168] As described above, in a scenario where the receiving device is a receiving network device and the sending device is a sending network device, the path of the first frame sent from the receiving network device to the sending network device is: PHY chip 2 → electrical signal processing unit 2 → electrical signal processing unit 1 → PHY chip 1.

[0169] In one example, the aforementioned first preparation operation may include, in addition to the operation performed by the aforementioned electrical signal processing unit 2, the operation performed by the PHY chip 2. Similarly, the aforementioned second preparation operation may include, in addition to the operation performed by the aforementioned electrical signal processing unit 1, the operation performed by the PHY chip 1. As an example, after the PHY chip 2 completes its required operation, it can send a first frame to the electrical signal processing unit 2. The state field of the first frame indicates that the PHY chip 2 has completed its required operation. Further, after receiving the first frame, the electrical signal processing unit 2 can parse the first frame. After determining that the PHY chip 2 has completed its required operation based on the state field of the first frame, the electrical signal processing unit 2, in conjunction with the control field of the first frame, executes its required operation. Furthermore, after completing its required operation, the electrical signal processing unit 2 further sends a first frame to the electrical signal processing unit 1. Similarly, after receiving the first frame, the electrical signal processing unit 1 can parse the first frame. After determining that the electrical signal processing unit 2 has completed its required operation based on the state field of the first frame, the electrical signal processing unit 1, in conjunction with the control field of the first frame, executes its required operation. Furthermore, after completing the operations it needs to perform, the electrical signal processing unit 1 sends the first frame to the PHY chip 1 so that the PHY chip 1 can continue to perform the operations it needs to perform.

[0170] In one example, if the electrical signal processing unit 2 has not completed its required operation, it may discard the first frame. In another example, the electrical signal processing unit 2 may modify the state field of the first frame so that the modified state field indicates that the electrical signal processing unit 2 has not yet completed its required operation, and then send the first frame back to the electrical signal processing unit 1. In this scenario, after receiving the first frame, the electrical signal processing unit 1 can parse it. After determining, based on the state field of the first frame, that the electrical signal processing unit 2 has not yet completed its required operation, the electrical signal processing unit 1 can directly send the first frame to the PHY chip 1 without executing the step of combining the control field of the first frame to execute its own required operation. Similarly, after receiving the first frame, the PHY chip 1 can parse it. After determining, based on the state field of the first frame, that the electrical signal processing unit 2 has not yet completed its required operation, the PHY chip 1 may also refrain from executing the step of combining the control field of the first frame to execute its own required operation.

[0171] S102: The receiving device performs fault detection on the first reconnection link.

[0172] After the receiving device identifies the first reconnection link, it can perform fault detection on the first reconnection link.

[0173] In one example, the receiving device can perform fault detection on the first reassembly link based on the second frame sent by the sending device to the receiving device through the first reassembly link. That is, after the sending device completes the aforementioned second preparation operation, the sending device can send the second frame to the receiving device through the first reassembly link. Similar to the first frame, the second frame can be a frame with a certain structure; in a specific example, the second frame can be a training frame.

[0174] In one example, the second frame may include a test data stream, through which the receiving device can determine whether the first reassembly link is faulty based on the bit error rate transmitted on the first reassembly link. For example, the receiving device may determine that the first reassembly link is faulty if the bit error rate is greater than or equal to a preset bit error rate threshold, and determine that the first reassembly link is fault-free if the bit error rate is less than the preset bit error rate threshold. In a specific example, the test data stream may be a PRBS (Pre-Reassembly Bit Stream).

[0175] Similar to the first frame, the second frame may also include a control field. The control field of the second frame carries second indication information, which indicates whether locating the fault location of the first link includes the first sub-link. The way the second frame carries the second indication information is the same as the way the first frame carries the first indication information. Therefore, for details regarding the second indication information, please refer to the description of the first indication information above, and it will not be repeated here.

[0176] Similar to the first frame, the second frame may also include a state field, which indicates that the transmitting device has completed the aforementioned second preparation operation. Regarding the second preparation operation, please refer to the relevant description above; it will not be repeated here. Regarding the description of the second frame's state field indicating that the transmitting device has completed the aforementioned second preparation operation, please refer to the description of the first frame's state field indicating that the receiving device has completed the aforementioned first preparation operation; it will not be repeated here.

[0177] In addition, if the second frame is a training frame, the second frame may also include a flag bit for identifying the training frame. For details about the flag bit, please refer to the previous description, which will not be repeated here.

[0178] In another example, the receiving device may detect a fault in the first reconnection link by detecting whether a loss of signal (LOS) or loss of lock (LOL) alarm has occurred. For example, if an LOS or LOL alarm occurs in the first reconnection link, a fault in the first reconnection link is determined.

[0179] In another example, the receiving device determines the eye diagram height and / or noise of the electrical signal received through the first reassembly link, and determines that the first reassembly link is faulty when the eye diagram height and / or noise is greater than or equal to a preset threshold.

[0180] In yet another example, the receiving device can detect the optical power and / or signal-to-noise ratio (SNR) of the optical signal received through the first reassembly link, and determine that the first reassembly link is faulty when the optical power and / or SNR is lower than a preset threshold.

[0181] S103: The receiving device determines whether the fault location of the first link includes the first sub-link based on the fault detection result of the first reconnection link.

[0182] As described above, among the multiple sub-links included in the first reassembled link, only the first sub-link originates from the faulty first link, while the other sub-links originate from the fault-free second link. In other words, in the first reassembled link, except for the first sub-link whose fault status is not yet clear, all other sub-links can be determined to be fault-free. Therefore, the fault detection result of the first reassembled link is also the fault detection result of the first sub-link. That is, if the fault detection result of the first reassembled link indicates that the first reassembled link is faulty, it means that the first sub-link is faulty. If the fault detection result of the first reassembled link indicates that the first reassembled link is not faulty, it means that the first sub-link is not faulty. Therefore, in the specific implementation of S103, if the fault detection result indicates that the first reassembled link is faulty, the receiving device locates the fault location of the first link including the first sub-link; if the fault detection result indicates that the first reassembled link is not faulty, the receiving device locates the fault location of the first link excluding the first sub-link.

[0183] As described above, using the solution of this application embodiment, after a first link failure, the receiving device and the sending device can exchange information (e.g., the aforementioned first frame and second frame), thereby locating the fault location of the first link. No manual intervention is required, and compared to configuring a loopback, this solution is less efficient for fault location.

[0184] Moreover, this solution can apply its fault location method to each sub-link of the faulty link, so that the fault location scope can cover the entire faulty link (i.e., the first link).

[0185] Furthermore, in the scheme of fault detection of the first reassembled link through the second frame, since the sending and receiving devices involved in the information exchange link remain unchanged during the fault detection process, the problem that loopback technology cannot reproduce the fault scenario in certain specific scenarios, thus leading to inaccurate fault detection results, can be avoided. In other words, the scheme of this application embodiment provides more accurate fault location results. For example, please refer to Figure 4d for understanding, which is a schematic diagram of an exemplary application scenario provided by an embodiment of this application.

[0186] Figure 4d illustrates the application of this solution to the fault scenario shown in Figure 1b. In the scenario shown in Figure 4d, network device 1 corresponds to the transmitting device in the above embodiments, and correspondingly, network device 2 corresponds to the receiving device in the above embodiments. Accordingly, the link indicated by the red arrow in Figure 4d is the first reassembled link. Network device 2 sends the second frame to network device 1 through the first reassembled link. When the PHY chip from manufacturer A receives the second frame from the PHY chip from manufacturer B, a mismatch occurs between the set value of the decision threshold and the level of the received signal, which leads to a link interruption. That is, network device 1 can determine that the first reassembled link is faulty. Correspondingly, network device 1 can determine that the first sub-link in the first reassembled link (i.e., the link between the PHY chip from manufacturer A and the electrical signal processing unit 1 in Figure 4d) is faulty, thereby accurately locating the fault. For details shown in Figure 4d that are not in Figure 1b, such as the details of optical module 1, optical module 2, and electrical signal processing unit 1, please refer to the relevant descriptions in the other figures above, which will not be repeated here.

[0187] The solutions of the embodiments of this application have been introduced above. Next, the solutions of the embodiments of this application will be described in conjunction with specific scenarios.

[0188] Referring to Figure 5a, this figure is a schematic diagram of an exemplary application scenario provided by an embodiment of this application.

[0189] The application scenario shown in Figure 5a is a variation of the application scenario shown in Figure 2c. In Figure 5a, it is clearly stated that electrical signal processing unit 1 is located in optical module 1, and electrical signal processing unit 2 is located in optical module 2. Both optical module 1 and optical module 2 shown in Figure 5a can be ordinary optical modules that include an optical digital signal processing (oDSP) chip. The oDSP chip can include electrical signal processing units. That is, the oDSP of optical module 1 includes electrical signal processing unit 1, and the oDSP of optical module 2 includes electrical signal processing unit 2.

[0190] Additionally, although not shown in Figure 5a, a typical optical module also includes a microcontroller unit (MCU). Network devices (e.g., network device 1 and network device 2) may include a central processing unit (CPU) in addition to a PHY chip. The first side of the aforementioned oDSP chip is used to connect to the PHY chip; this first side can be referred to as the hostside. The second side of the oDSP chip is used to connect to the TOSA / ROSA of the optical module; this second side can be referred to as the mediaside. This application does not limit the devices included in the hostside and mediaside. The first side is used to communicate with the PHY chip via a telecommunication channel. For example, the serializer / deserializer (serdes) located on the first side of the oDSP chip communicates with the serdes located on the PHY chip (serdes not shown in Figure 5a) via a telecommunication channel. The second side is used to communicate with the TOSA / ROSA via a telecommunication channel. In one implementation, the TOSA / ROSA in optical module 1 and the TOSA / ROSA in optical module 2 are connected via an optical channel.

[0191] The optical module's MCU is connected to the CPU of the host-side device (i.e., the network device) via a management interface. After power-on, the optical module can report its linear operation capability and current operating mode to the host-side device through the management interface. For example, this management interface can be an inter-integrated circuit (IIC) interface, and the management protocol based on this management interface can be a common management interface specification (CMIS).

[0192] In the scenario shown in Figure 5a, after network device 2 determines that link 1 is faulty, the physical coding sublayer (PCS) corresponding to PHY chip 2 generates a local fault sequence and sends it to the local media access control (MAC) layer. Upon receiving this local fault sequence, the MAC layer of network device 2 can stop sending service data on service 2 and generate a remote fault sequence, which is sent to PHY chip 1 of network device 1. Upon receiving the remote fault sequence, PHY chip 1 determines that the link is faulty and thus stops sending service data on link 1.

[0193] Furthermore, PHY chip 2 triggers the fault location process.

[0194] First, PHY chip 2 triggers stage 1 of fault location. Stage 1 is used to determine whether the location of the link fault includes sub-link 1. The specific process can be understood with reference to Figure 5b. Figure 5b is a schematic diagram of a fault location method provided by an embodiment of this application. The fault location process shown in Figure 5b may include the following steps:

[0195] 1. PHY chip 2 sends the first training frame to electrical signal processing unit 2.

[0196] The PHY chip 2 sends the first training frame to the electrical signal processing unit 2 via C Host TX 1. The X:X+1 bits of the control field of the first training frame are set to 01, indicating that the current diagnostic stage is stage 1; the Y bit of the state field is set to 1, indicating that the PHY chip 2 has completed the diagnostic preparation process. 2. The electrical signal processing unit 2 identifies the first training frame and sends it to the electrical signal processing unit 1.

[0197] After identifying that the control domain X:X+1 bits are 0 or 1, the electrical signal processing unit 2 determines that the current diagnostic stage is stage 1, and that the mapping relationship between its own system-side channel unit and line-side channel unit does not need to be changed in this stage. The electrical signal processing unit 2 sends the first training frame to the electrical signal processing unit 1 through Line TX 1, keeping the control domain X:X+1 bit content and the state domain Y bit content of the first training frame unchanged.

[0198] 3. The electrical signal processing unit 1 identifies the first training frame and maps its own M Host RX1 to Line TX2 to form the first reconstructed path corresponding to the red arrow in Figure 5b. Furthermore, the electrical signal processing unit 1 continues to send the first training frame to the PHY chip 1.

[0199] The electrical signal processing unit 1 identifies that the control domain X:X+1 bit is 01, determines that the current fault diagnosis stage is stage 1, and therefore maps MHhost RX 1 to Line TX 2. For example, the electrical signal processing unit 1 can know from the pre-stored mapping table that a mapping switch is required in stage 1 and that MHhost RX 1 needs to be mapped to Line TX 2.

[0200] After completing the aforementioned mapping switch, the electrical signal processing unit 1 sends the first training frame to the PHY chip 1 via M Host TX 1, keeping the contents of the control domain and state domain of the training frame unchanged. 4. The PHY chip 1 identifies the first training frame and transmits a second training frame containing a known test data stream through the first reassembly link.

[0201] PHY chip 1 recognizes that the control field X:X+1 bits are 0 and 1, determining that the current fault diagnosis stage is stage 1. PHY chip 1 instructs C Host TX 1 to transmit the second training frame containing PRBS, keeping the control field content of the training frame unchanged, and setting the state field Y bits to 1, indicating that PHY chip 1 has completed the diagnostic preparation process.

[0202] Before PHY chip 1 sends the second training frame through the first reassembly link, PHY chip 1 also sends a control message to electrical signal processing unit 1 through the IIC interface based on the CMIS protocol, so that electrical signal processing unit 1 stops M Host RX2 from driving drive+TOSA, to prevent M Host RX2 and M Host RX1 from driving the same drive+TOSA simultaneously. 5. Electrical signal processing unit 1 and electrical signal processing unit 2 identify the content of the second training frame and forward it. PHY chip 2 identifies the second training frame and determines the fault detection result based on the test data stream in the second training frame.

[0203] In one example, the process of PHY chip 2 determining the fault detection result based on the test data stream in the second training frame lasts for T seconds. If a link fault occurs during the diagnosis process, it is determined that sub-link 1 is faulty. If no link fault occurs during the diagnosis process, it is determined that sub-link 1 is fault-free.

[0204] If PHY chip 2 does not receive the second training frame with bit 01 in control domain X:X+1 within T seconds, it is also determined that sublink 1 is faulty.

[0205] After the fault detection result corresponding to stage 1 is determined, PHY chip 2 triggers stage 2 of fault location. Stage 2 is used to determine whether the location of the link fault includes sub-link 3. The specific process can be understood with reference to Figure 5c. Figure 5c is a schematic diagram of a fault location method provided by an embodiment of this application. The fault location process shown in Figure 5c may include the following steps:

[0206] 6. PHY chip 2 sends the first training frame to electrical signal processing unit 2.

[0207] The PHY chip 2 sends the first training frame to the electrical signal processing unit 2 via C Host TX 1. The X:X+1 bit position of the control field of the first training frame is 10, indicating that the current diagnostic stage is stage 2; the Y bit position of the state field is 1, indicating that the PHY chip 2 has completed the diagnostic preparation process.

[0208] 7. The electrical signal processing unit 2 identifies the first training frame and sends the first training frame to the electrical signal processing unit 1.

[0209] After identifying that the control domain X:X+1 bits are 10, the electrical signal processing unit 2 determines that the current diagnostic stage is stage 2. In this stage, it needs to map its M Host TX1 to Line RX2. Therefore, the electrical signal processing unit 2 maps its own M Host TX1 to Line RX2 to form the first reconstructed path corresponding to the red arrow in Figure 5c. The electrical signal processing unit 2 sends the first training frame to the electrical signal processing unit 1 via Line TX1, keeping the control domain X:X+1 bit content and the state domain Y bit content unchanged.

[0210] In addition, PHY chip 2 also sends control messages to electrical signal processing unit 2 via IIC interface based on CMIS protocol, so that electrical signal processing unit 2 stops M Host TX2 from driving TIA+ROSA, so as to prevent M Host TX2 and M Host TX1 from driving the same TIA+ROSA at the same time.

[0211] 8. The electrical signal processing unit 1 identifies the first training frame and determines that the mapping relationship between its own system-side channel unit and line-side channel unit in the current stage needs to maintain its initial state. Since the electrical signal processing unit 1's own M Host RX1 is mapped to Line TX2 during stage 1, in this stage, the electrical signal processing unit 1 can map its own M Host RX1 to Line TX1 and its own M Host RX2 to Line TX2. Furthermore, the electrical signal processing unit 1 continues to send the first training frame to the PHY chip 1.

[0212] 9. PHY chip 1 identifies the first training frame and transmits a second training frame containing a known test data stream through the first reassembly link.

[0213] PHY chip 1 recognizes that the control field X:X+1 bit is 10, determining that the current fault diagnosis stage is stage 2. PHY chip 1 instructs C Host TX 2 to transmit the second training frame containing PRBS, keeping the control field content of the training frame unchanged, and setting the state field Y bit to 1, indicating that PHY chip 1 has completed the diagnostic preparation process.

[0214] 10. Electrical signal processing unit 1 and electrical signal processing unit 2 identify the content of the second training frame and forward it. PHY chip 2 identifies the second training frame and determines the fault detection result based on the test data stream in the second training frame.

[0215] In one example, the process of PHY chip 2 determining the fault detection result based on the test data stream in the second training frame lasts for T seconds. If a link fault occurs during the diagnosis process, it is determined that sub-link 3 is faulty. If no link fault occurs during the diagnosis process, it is determined that sub-link 3 is fault-free.

[0216] If PHY chip 2 does not receive the second training frame with control domain X:X+1 bits set to 10 within T seconds, it is also determined that sublink 3 is faulty.

[0217] After the fault detection result corresponding to stage 2 is determined, PHY chip 2 triggers stage 3 of fault location. Stage 3 is used to determine whether the location of the link fault includes sub-link 2. The specific process can be understood with reference to Figure 5d. Figure 5d is a schematic diagram of a fault location method provided by an embodiment of this application. The fault location process shown in Figure 5d may include the following steps:

[0218] 11. PHY chip 2 sends the first training frame to electrical signal processing unit 2.

[0219] The PHY chip 2 sends the first training frame to the electrical signal processing unit 2 via C Host TX 1. The X:X+1 bit position of the control field of the first training frame is 11, indicating that the current diagnostic stage is stage 3; the Y bit position of the state field is 1, indicating that the PHY chip 2 has completed the diagnostic preparation process.

[0220] 12. The electrical signal processing unit 2 identifies the first training frame and sends the first training frame to the electrical signal processing unit 1.

[0221] After identifying that the control domain X:X+1 bits are 11, the electrical signal processing unit 2 determines that the current diagnostic stage is stage 3. In this stage, it needs to map its M Host TX2 to Line RX1. Therefore, the electrical signal processing unit 2 maps its own M Host TX2 to Line RX1 to form the first reconstructed path corresponding to the red arrow in Figure 5d. The electrical signal processing unit 2 sends the first training frame to the electrical signal processing unit 1 via Line TX1, keeping the control domain X:X+1 bit content and the state domain Y bit content unchanged.

[0222] In addition, PHY chip 2 also sends control messages to electrical signal processing unit 2 via IIC interface based on CMIS protocol, so that electrical signal processing unit 2 stops M Host TX1 from driving TIA+ROSA, so as to prevent M Host TX1 and M Host TX2 from driving the same TIA+ROSA at the same time.

[0223] 13. The electrical signal processing unit 1 identifies the first training frame and sends the first training frame to the PHY chip 1.

[0224] After the electrical signal processing unit 1 identifies that the control domain X:X+1 bit is 11, it determines that the current diagnostic stage is stage 3. In this stage, it determines that it needs to map M Host RX2 to Line TX1. Therefore, the electrical signal processing unit 1 maps M Host RX2 to Line TX1. Furthermore, the electrical signal processing unit 1 continues to send the first training frame to the PHY chip 1.

[0225] 14. PHY chip 1 identifies the first training frame and transmits a second training frame containing a known test data stream through the first reassembly link.

[0226] PHY chip 1 recognizes that the control domain X:X+1 bit is 11, determining that the current fault diagnosis stage is stage 3. PHY chip 1 instructs C Host TX 2 to transmit the second training frame containing PRBS, keeping the control domain content of the training frame unchanged, and setting the Y bit of the status domain to 1, indicating that PHY chip 1 has completed the diagnostic preparation process.

[0227] Before PHY chip 1 sends the second training frame through the first reassembly link, PHY chip 1 also sends a control message to electrical signal processing unit 1 through the IIC interface based on the CMIS protocol, so that electrical signal processing unit 1 stops M Host RX1 from driving drive+TOSA, so as to prevent M Host RX1 and M Host RX2 from driving the same drive+TOSA at the same time.

[0228] 15. Electrical signal processing unit 1 and electrical signal processing unit 2 identify the content of the second training frame and forward it. PHY chip 2 identifies the second training frame and determines the fault detection result based on the test data stream in the second training frame.

[0229] In one example, the process of PHY chip 2 determining the fault detection result based on the test data stream in the second training frame lasts for T seconds. If a link fault occurs during the diagnosis process, it is determined that sub-link 2 is faulty. If no link fault occurs during the diagnosis process, it is determined that sub-link 2 is fault-free.

[0230] If PHY chip 2 does not receive the second training frame with control domain X:X+1 bits set to 11 within T seconds, it is also determined that sublink 2 is faulty.

[0231] At this point, the three-stage fault location process is complete, and PHY chip 2 can determine the specific fault location of link 1.

[0232] Figures 6a, 6b, and 6c are schematic diagrams of three other exemplary application scenarios provided in the embodiments of this application.

[0233] The application scenarios shown in Figures 6a, 6b, and 6c are all variations of the application scenario shown in Figure 2c.

[0234] In Figure 6a, it is clear that the electrical signal processing unit 1 is located in network device 1 and the electrical signal processing unit 2 is located in network device 2.

[0235] In Figure 6b, it is clear that the electrical signal processing unit 1 is located in the optical module 1 and the electrical signal processing unit 2 is located in the network device 2.

[0236] In Figure 6c, it is clear that the electrical signal processing unit 1 is located in the network device 1 and the electrical signal processing unit 2 is located in the optical module 2.

[0237] For the three application scenarios shown in Figures 6a to 6c, if link 1 fails, the corresponding fault location process is the same as that shown in Figure 5a. Therefore, the specific fault location process can be found in the description of Figures 5b to 5d above, and will not be repeated here.

[0238] Referring to Figure 7, this figure is a structural schematic diagram of a fault location device provided in an embodiment of this application. The fault location device 700 shown in Figure 7 can be applied to the receiving end device mentioned in the above method embodiments to execute the fault location method provided by the receiving end device in the above method embodiments.

[0239] As shown in Figure 7, the fault location device 700 includes a determination unit 701 and a processing unit 702.

[0240] The determining unit 701 is used to determine the first reassembled link to be detected. The first reassembled link includes a first sub-link. The first sub-link is a faulty first link. The first reassembled link is a link formed by replacing the corresponding link in the faultless second link with the first sub-link. The first link, the second link and the first reassembled link are all links from the transmitting device to the receiving device. The transmitting device and the receiving device communicate through an optical fiber link.

[0241] The processing unit 702 is configured to: perform fault detection on the first reconnected link; and, based on the fault detection result of the first reconnected link, determine whether the fault location of the first link includes the first sub-link.

[0242] In one possible implementation, the determining unit 701 specifically includes a sending unit; the sending unit is used to send a first frame to the sending end device, the first frame including first indication information, the first indication information indicating that fault location is performed on the first sub-link.

[0243] In one possible implementation, the transmitting device includes a first physical layer PHY chip, the first sub-link is a link between the first PHY chip and a first mapping module, the first mapping module is used to connect the first PHY chip and the transmitting optical module; the first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, the second sub-link is a link from the first mapping module to the receiving device, and the first reconnection link further includes the second sub-link.

[0244] In one possible implementation, the first sub-link is the link from the first mapping module to the second mapping module. The first mapping module connects the first PHY chip and the transmitting optical module, and the second mapping module connects the second PHY chip and the receiving optical module. The transmitting device includes the first PHY chip, and the receiving device includes the second PHY chip. The first indication information triggers the first mapping module to switch the third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to the fourth sub-link in the second link. The first reconnected link also includes the third sub-link and the fourth sub-link. The third sub-link is the link between the first PHY chip and the first mapping module, and the fourth sub-link is the link between the second mapping module and the second PHY chip.

[0245] In one possible implementation, the first sub-link is a link between the second mapping module and the second PHY chip, the receiving device includes the second PHY chip, and the second mapping module is used to connect the second PHY chip and the receiving optical module; the first indication information triggers the second mapping module to switch the fifth sub-link of the second link to the first sub-link, the first reconnected link also includes the fifth sub-link, and the fifth sub-link is the link from the transmitting device to the second mapping module.

[0246] In one possible implementation, the first indication information is carried through the control field of the first frame.

[0247] In one possible implementation, the first frame further includes a state field, which indicates that the receiving device has completed a first preparatory operation for fault location of the first sub-link. The first preparatory operation includes: the second mapping module corresponding to the receiving device switching the first sub-link to a fourth sub-link in the second link, wherein the fourth sub-link is a link between the second mapping module and the second PHY chip included in the receiving device; or, the second mapping module switching the fifth sub-link of the second link to the first sub-link, wherein the fifth sub-link is a link from the transmitting device to the second mapping module.

[0248] In one possible implementation, the processing unit 702 is configured to: perform fault detection on the first reconnection link based on the second frame sent by the transmitting device to the receiving device through the first reconnection link.

[0249] In one possible implementation, the second frame includes a pseudo-random binary sequence (PRBS), the bit error rate of which is transmitted on the first reassembly link, to determine the fault detection result.

[0250] In one possible implementation, the second frame further includes a control field, which includes second indication information indicating whether locating the fault location of the first link includes the first sub-link.

[0251] In one possible implementation, the second frame further includes a state field indicating that the transmitting device has completed a second preparatory operation for fault location of the first sub-link. The second preparatory operation includes: the first mapping module corresponding to the transmitting device switching the first sub-link to a second sub-link in the second link, the second sub-link being the link from the first mapping module to the receiving device; or, the first mapping module switching a third sub-link in the second link to the first sub-link, the third sub-link being the link between the first PHY chip and the first mapping module, the transmitting device including the first PHY chip.

[0252] In one possible implementation, the transmitting device is a transmitting network device, and the first mapping module is located in the transmitting network device.

[0253] In one possible implementation, the first mapping module is located in the transmitting optical module.

[0254] In one possible implementation, the first mapping module is used to perform a second preparation operation to determine whether the fault location of the first link includes the first sub-link, based on the channel switching instruction sent by the first PHY chip.

[0255] In one possible implementation, the receiving device is a receiving network device, and the second mapping module is located in the receiving network device.

[0256] In one possible implementation, the second mapping module is located in the receiver optical module.

[0257] In one possible implementation, the second mapping module is used to perform a first preparation operation to determine whether the fault location of the first link includes the first sub-link, based on the channel switching instruction sent by the second PHY chip.

[0258] In one possible implementation, the first mapping module includes a first chip or a first functional circuit; and / or, the second mapping module includes a second chip or a second functional circuit.

[0259] In one possible implementation, the processing unit 702 is configured to: if the fault detection result indicates that the first reconnection link has a fault, then locate the fault location of the first link including the first sub-link; or, if the fault detection result indicates that the first reconnection link does not have a fault, then locate the fault location of the first link excluding the first sub-link.

[0260] Furthermore, this application also provides a communication device 800, as shown in FIG8, which is a schematic diagram of the structure of a communication device provided in this application embodiment. The communication device 800 includes a communication interface 801 and a processor 802 connected to the communication interface 801. This communication device 800 can be applied to the receiving end device mentioned in the above embodiments to execute the methods executed by the receiving end device in the above embodiments.

[0261] Communication interface 801 is used to perform the receiving and / or transmitting operations in the method executed by the receiving device described above. Processor 802 is used to perform other operations in the method executed by the receiving device besides the receiving and / or transmitting operations. For example: communication interface 801 is used to send a first frame to the transmitting device, the first frame including first indication information, the first indication information indicating fault location for the first sub-link; processor 802 is used to perform fault detection on the first reassembled link, and based on the fault detection result of the first reassembled link, determine whether the fault location of the first link includes the first sub-link.

[0262] Furthermore, this application also provides a communication device 900, as shown in Figure 9, which is a schematic diagram of the structure of a communication device provided in this application embodiment. This communication device 900 can be used to execute the fault location method in the above embodiments.

[0263] As shown in Figure 9, the communication device 900 may include a processor 910, a communication interface 920, and a memory 930 coupled to the processor 910.

[0264] The processor mentioned in this application can be one or more processors. When there are multiple processors, the types of processors can be the same or different. A processor can be, for example, a CPU, a network processor (NP), or a combination of a CPU and an NP. A processor can also be one or more processing circuits. A processor can also be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0265] The memory 930 mentioned in this application may include volatile memory, such as random-access memory (RAM); the memory may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 930 may also include a combination of the above types of memory. The memory 930 may refer to a single memory or may include multiple memories. In one embodiment, the memory 930 stores computer-readable instructions, which include multiple software modules, such as a sending module 931, a processing module 932, and a receiving module 933. After executing each software module, the processor 910 can perform corresponding operations according to the instructions of each software module. In this embodiment, the operation performed by a software module actually refers to the operation performed by the processor 910 according to the instructions of the software module.

[0266] When the communication device 900 is used to execute the above fault location method, the communication interface 920 is used to perform the receiving and / or sending operations in the fault location method. The processor 910 is used to perform operations in the fault location method other than the receiving and / or sending operations. For example: the communication interface 920 is used to send a first frame to the transmitting device, the first frame including first indication information, the first indication information indicating that fault location should be performed on the first sub-link; the processor 910 is used to perform fault detection on the first reassembled link, and based on the fault detection result of the first reassembled link, determine whether the fault location of the first link includes the first sub-link.

[0267] Referring to Figure 10, this figure is a schematic diagram of the structure of a chip provided in an embodiment of this application. The chip 1000 shown in Figure 10 includes an interface circuit 1001 and a processing circuit 1002. The interface circuit 1001 is used to receive and / or transmit data, and the processing circuit 1002 is used to perform data processing.

[0268] In one example, the chip 1000 can be applied to the above receiving device to execute the method provided by the receiving device in the above method embodiments.

[0269] In a specific example, the interface circuit 1001 is used to determine a first reassembled link to be detected. The first reassembled link includes a first sub-link, which is a faulty first link. The first reassembled link is formed by replacing the corresponding link in a faultless second link with the first sub-link. The first link, the second link, and the first reassembled link are all links from the transmitting device to the receiving device. The transmitting device and the receiving device communicate via an optical fiber link. The processing circuit 1002 is used to perform fault detection on the first reassembled link and, based on the fault detection result of the first reassembled link, determine whether the fault location of the first link includes the first sub-link.

[0270] For details regarding the specific steps performed by the interface circuit 1001 and the processing circuit 1002, please refer to the description of the fault location method performed by the receiving device above; the description will not be repeated here.

[0271] This application also provides a computer-readable storage medium storing instructions or computer programs that, when executed on a processor, can perform any one or more of the operations described in the foregoing embodiments.

[0272] This application also provides a computer program product, including a computer program that, when run on a processor, can implement any one or more of the operations described in the foregoing embodiments.

[0273] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0274] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0275] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0276] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0277] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0278] If the integrated unit is implemented as a software business unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0279] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0280] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention.

[0281] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A fault location method characterized by, The method comprises: The receiving end device determines a first recombination link to be detected, the first recombination link comprising a first sub-link, the first sub-link belonging to a first link in failure, the first recombination link being formed by replacing a corresponding link in a second link without failure by the first sub-link, the first link, the second link and the first recombination link all being links from a sending end device to the receiving end device, the sending end device and the receiving end device communicating through a fiber link; The receiving end device performs failure detection on the first recombination link; The receiving end device locates whether the failure position of the first link includes the first sub-link according to the failure detection result of the first recombination link.

2. The method of claim 1, wherein, The receiving end device determines a first recombination link to be detected, comprising: The receiving end device sends a first frame to the sending end device, the first frame comprising first indication information, the first indication information indicating that failure positioning is performed on the first sub-link.

3. The method of claim 2, wherein: The sending end device comprises a first physical layer (PHY) chip, the first sub-link being a link between the first PHY chip and a first mapping module, the first mapping module being used to connect the first PHY chip and a sending end optical module; The first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, the second sub-link being a link from the first mapping module to the receiving end device, the first recombination link further comprising the second sub-link.

4. The method of claim 2, wherein: The first sub-link is a link from a first mapping module to a second mapping module, the first mapping module being used to connect a first PHY chip and a sending end optical module, the second mapping module being used to connect a second PHY chip and a receiving end optical module, the sending end device comprising the first PHY chip, and the receiving end device comprising the second PHY chip; The first indication information triggers the first mapping module to switch a third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to a fourth sub-link in the second link, the first recombination link further comprising the third sub-link and the fourth sub-link, the third sub-link being a link between the first PHY chip and the first mapping module, and the fourth sub-link being a link between the second mapping module and the second PHY chip.

5. The method of claim 2, wherein: The first sub-link is a link between a second mapping module and a second PHY chip, the receiving end device comprising the second PHY chip, and the second mapping module being used to connect the second PHY chip and a receiving end optical module; The first indication information triggers the second mapping module to switch a fifth sub-link of the second link to the first sub-link, the first recombined link further comprising the fifth sub-link, and the fifth sub-link being a link from the sending-end device to the second mapping module.

6. The method according to any one of claims 2-5, characterized in that, The first indication information is carried through a control field of the first frame.

7. The method of claim 6, wherein, The first frame further comprises a state field, and the state field of the first frame indicates that the receiving-end device has completed a first preparation operation of performing fault positioning on the first sub-link, wherein the first preparation operation comprises: The second mapping module corresponding to the receiving-end device switches the first sub-link to a fourth sub-link in the second link, the fourth sub-link being a link between the second mapping module and a second PHY chip included in the receiving-end device; or The second mapping module switches a fifth sub-link of the second link to the first sub-link, the fifth sub-link being a link from the sending-end device to the second mapping module.

8. The method according to any one of claims 1 to 7, characterized in that, The receiving-end device performs fault detection on the first recombined link, comprising: The receiving-end device performs fault detection on the first recombined link based on a second frame sent by the sending-end device to the receiving-end device through the first recombined link.

9. The method of claim 8, wherein, The second frame comprises a pseudo-random binary sequence (PRBS), and a bit error rate of the PRBS transmitted on the first recombined link is used to determine the fault detection result.

10. The method of claim 9, wherein, The second frame further comprises a control field, and the control field of the second frame comprises second indication information, the second indication information indicating whether the first sub-link is included in a fault position of the first link.

11. The method according to claim 9 or 10, characterized in that, The second frame further comprises a state field, and the state field of the second frame indicates that the sending-end device has completed a second preparation operation of performing fault positioning on the first sub-link, the second preparation operation comprising: The first mapping module corresponding to the sending-end device switches the first sub-link to a second sub-link in the second link, the second sub-link being a link from the first mapping module to the receiving-end device; or The first mapping module switches a third sub-link in the second link to the first sub-link, the third sub-link being a link between a first PHY chip and the first mapping module, and the sending-end device comprising the first PHY chip.

12. The method of claim 3 or 4, wherein, The sending-end device is a sending-end network device, and the first mapping module is located in the sending-end network device.

13. The method of claim 3 or 4, wherein, The first mapping module is located in a sending-end optical module.

14. The method according to claim 12 or 13, characterized in that, The first mapping module is configured to perform, based on a channel switching instruction sent by the first PHY chip, a second preparation operation of positioning whether the first sub-link is included in a fault position of the first link.

15. The method of claim 4 or 5, wherein, The receiving-end device is a receiving-end network device, and the second mapping module is located in the receiving-end network device.

16. The method of claim 4 or 5, wherein, The second mapping module is located in a receiving-end optical module.

17. The method according to claim 15 or 16, characterized in that, The second mapping module is configured to perform, based on a channel switching instruction sent by the second PHY chip, a first preparation operation of positioning whether the first sub-link is included in a fault position of the first link.

18. The method of any of claims 2-7, wherein the first mapping module comprises a first chip or a first functional circuit; and / or the second mapping module comprises a second chip or a second functional circuit. The receiving end device locates whether the fault position of the first link includes the first sub-link according to a fault detection result of the first recombined link, comprising: If the fault detection result indicates that the first recombined link has a fault, the receiving end device locates that the fault position of the first link includes the first sub-link; or 19. The method of any one of claims 1-18, wherein, If the fault detection result indicates that the first recombined link has no fault, the receiving end device locates that the fault position of the first link does not include the first sub-link. The chip applied to the receiving end device, comprising: An interface circuit, configured to determine a first recombined link to be detected, the first recombined link comprising a first sub-link, the first sub-link belonging to a first link having a fault, the first recombined link being a link formed by replacing a corresponding link in a second link without a fault by the first sub-link, the first link, the second link and the first recombined link all being links from a sending end device to the receiving end device, the sending end device and the receiving end device communicating through an optical fiber link; 20. A chip, characterized by A processing circuit, configured to perform fault detection on the first recombined link, and locate whether the fault position of the first link includes the first sub-link according to a fault detection result of the first recombined link. The interface circuit is configured to: Send a first frame to the sending end device, the first frame comprising first indication information, the first indication information indicating that fault positioning is performed on the first sub-link.

21. The chip of claim 20, wherein, 22. The chip of claim 21, wherein the sending end device comprises a first physical layer (PHY) chip, the first sub-link being a link between the first PHY chip and a first mapping module, the first mapping module being configured to connect the first PHY chip and a sending end optical module; and The first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, the second sub-link being a link from the first mapping module to the receiving end device, the first recombined link further comprising the second sub-link.

23. The chip of claim 21, wherein the first sub-link is a link from a first mapping module to a second mapping module, the first mapping module being configured to connect a first PHY chip and a sending end optical module, the second mapping module being configured to connect a second PHY chip and a receiving end optical module, the sending end device comprising the first PHY chip, and the receiving end device comprising the second PHY chip. ​ ​ ​ ​ The first indication information triggers the first mapping module to switch a third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to a fourth sub-link in the second link, the first recombined link further comprising the third sub-link and the fourth sub-link, the third sub-link being a link between the first PHY chip and the first mapping module, and the fourth sub-link being a link between the second mapping module and the second PHY chip.

24. The chip of claim 21, wherein, the first sub-link is a link between the second mapping module and the second PHY chip, the receiving end device comprising the second PHY chip, and the second mapping module being configured to connect the second PHY chip and the receiving end optical module; the first indication information triggers the second mapping module to switch a fifth sub-link of the second link to the first sub-link, the first recombined link further comprising the fifth sub-link, the fifth sub-link being a link from the sending end device to the second mapping module.

25. The chip of any of claims 20-24, wherein, The processing circuit is configured to: detect a fault of the first recombined link based on a second frame sent by the sending end device to the receiving end device through the first recombined link.

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