Chip and fabrication method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a chip and a fabrication method therefor, and an electronic device. Regions in a channel layer controlled by a gate increase, thereby enhancing the gate control capability; and a recess is reserved as an additional fabrication space for the gate, thereby expanding a process window of the gate. The chip comprises a substrate and a gate-all-around transistor arranged on the substrate, wherein the gate-all-around transistor comprises a channel layer, a gate structure, a source and a drain. The channel layer comprises a lower surface facing the substrate and an upper surface facing away from the substrate, wherein recesses are formed on both the lower surface and the upper surface. The gate structure protrudes outwards from the recesses. The gate structure comprises a gate surrounding the channel layer, and a gate dielectric layer used for isolating the gate from the channel layer. The source and the drain are respectively arranged at two ends of the channel layer, and a dielectric material is filled between the source and the gate structure and between the drain and the gate structure.

Description

Chips and their fabrication methods, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202410702472.5, filed on May 31, 2024, entitled "Chip and Method of Fabrication Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, and an electronic device. Background Technology

[0003] As transistor dimensions shrink, the short-channel effect (SCE) becomes increasingly pronounced. To suppress the SCE, it is necessary to improve the gate control capability of transistors, especially at very small process nodes (e.g., below 7nm). The SCE intensifies, prompting a shift to an all-gate architecture. Gate-around transistors (GOT) satisfy this all-gate architecture requirement. In a GOT, the gate can cover all four surfaces of the channel layer, improving gate control capability.

[0004] However, how to further improve the gate control capability of gate-around transistors is an urgent problem that needs to be solved and further improvement is needed. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a chip and its fabrication method, as well as an electronic device. On the one hand, the area controlled by the gate in the channel layer is increased, thereby improving the gate control capability and reducing the short-channel effect. On the other hand, an additional fabrication space, a recess, is reserved for the gate, thereby increasing the gate's process window.

[0006] In a first aspect, this application provides a chip including a substrate and a gate-around transistor disposed on the substrate. The gate-around transistor includes a channel layer, a gate structure, a source, and a drain. The channel layer includes a lower surface facing the substrate and an upper surface facing away from the substrate. Grooves are formed on both the lower and upper surfaces. The channel layer includes a first channel and a second channel. The orthographic projection of the first channel onto the substrate overlaps with the orthographic projection of the groove onto the substrate. The second channel is the portion of the channel layer other than the first channel, and the second channel is covered by a dielectric material.

[0007] The gate structure protrudes outward from the groove, and includes a gate surrounding the channel layer, and a gate dielectric layer for isolating the gate from the channel layer. The source and drain are located at opposite ends of the channel layer. The chip also includes dielectric material filling the space between the source and the gate structure, and between the drain and the gate structure.

[0008] In this way, the gate not only coincides with the first channel (the bottom surface of the groove in the channel layer) but also with a portion of the second channel (partial sidewalls in the channel layer). Specifically, the orthographic projection of the gate onto the substrate coincides with the orthographic projection of the first channel onto the substrate, and the orthographic projection of the gate onto the source coincides with the orthographic projection of a portion of the second channel onto the source. Compared to related technologies, with the gate length (source to drain direction) remaining constant, this application's solution adds the extra overlap between the gate and a portion of the second channel. Therefore, in this application, the area controlled by the gate in the channel layer increases, thereby improving gate control capability and reducing short-channel effects. Furthermore, compared to cases where the gate is only disposed between adjacent dielectric materials, in this application, the gate is not only disposed between adjacent dielectric materials but also within the groove of the channel layer. Therefore, before fabricating the gate, an additional fabrication space—the groove—is reserved, increasing the gate fabrication space and improving the gate's process window.

[0009] Furthermore, if the thickness of the first channel is the same as the thickness of the channel layer in the related technology, then the thickness of the second channel is greater than the thickness of the channel layer in the related technology. On the one hand, the thickness of the dielectric material covering the second channel decreases, and the capacitance values ​​of the parasitic capacitance formed by the gate, dielectric material, and source, as well as the parasitic capacitance formed by the gate, dielectric material, and drain, all decrease. On the other hand, due to the increased thickness of the second channel, the area S in contact with the source and drain in the second channel increases. According to the resistance formula R = ρL / S, when the gate-ring transistor is turned on, the resistance of the second channel decreases, thereby increasing the current flowing through the second channel.

[0010] If the thickness of the second channel is the same as the thickness of the channel layer in the related technology, then the thickness of the first channel is less than the thickness of the channel layer in the related technology. The first channel with a reduced thickness is more easily controlled by the gate, thus improving the gate control capability and reducing the short-channel effect.

[0011] In some possible implementations, the gate structure includes a first surface facing the substrate and a second surface facing away from the substrate. Due to the process of forming the dielectric material, sharp points with acute angles are easily formed between the first surface and the sidewall, and between the second surface and the sidewall in the gate structure. On the one hand, the sharp points of the gate are prone to short-circuiting with the source and drain; on the other hand, the discharge of the gate tip will cause a higher electric field.

[0012] Based on this, this application improves the fabrication process of the gate ring transistor so that the angle between the bottom surface of the groove and the sidewall of the groove is an obtuse angle. In this way, since the gate structure is filled in the groove, the angle between the sidewall of the gate structure and the first and second surfaces of the gate structure facing the groove is also an obtuse angle, which avoids the formation of a sharp gate structure, thereby avoiding short circuit between the gate tip and the source and drain, and avoiding gate tip discharge, which would result in a higher electric field.

[0013] As mentioned earlier, due to the manufacturing process of the dielectric material, sharp points with acute angles are easily formed between the first surface facing the groove and the sidewall, and between the second surface facing the groove and the sidewall, in the gate structure. In related technologies, the process for forming the dielectric material typically involves: first forming a sacrificial layer and a semiconductor layer (which, after processing, becomes the channel layer) on the substrate; then partially removing the sacrificial layer; finally forming the dielectric material at the location of the removed sacrificial layer; and finally removing the remaining sacrificial layer. Therefore, the thickness of the dielectric material is the same as the thickness of the sacrificial layer.

[0014] Therefore, in some possible implementations, the thickness of the channel layer is greater than the thickness of the dielectric material along the direction from the substrate to the gate-around transistor; that is, the thickness of the channel layer is greater than the thickness of the sacrificial layer. This way, after removing the remaining sacrificial layer, the channel layer itself is thick enough to prevent it from collapsing.

[0015] Optionally, when the total thickness of the dielectric material and the channel layer is the same, the thickness of the channel layer in this application can be greater than the thickness of the channel layer in related technologies, thereby reducing the thickness of the dielectric material.

[0016] For example, in related technologies, the thickness of the channel layer is 5 nm; while in this application, the thickness range of the first channel is [3 nm, 5 nm], and the thickness range of the second channel is (5 nm, 10 nm). By increasing the thickness of the channel layer and decreasing the thickness of the dielectric material, the capacitance value of the parasitic capacitance formed by the gate, dielectric material, and source can be reduced, as can the capacitance value of the parasitic capacitance formed by the gate, dielectric material, and drain. On the other hand, by reducing the thickness of the dielectric material, the dimension of the gate tip located between the dielectric materials extending along the sidewall of the dielectric material towards the source and drain sides can be reduced, which can improve the problem of short circuit between the gate and the source 12 and the drain.

[0017] In some possible implementations, the gate-around transistor includes multiple channel layers stacked along the direction from the substrate toward the gate-around transistor. Compared to a gate-around transistor with a single channel layer, a gate-around transistor with multiple channel layers can increase its driving capability.

[0018] In some possible implementations, the dielectric constant of the dielectric material is less than that of the gate dielectric layer. By placing a dielectric material with a smaller dielectric constant between the gate and the gate dielectric layer and the source and drain, the capacitance value of the parasitic capacitance formed between the gate and the source and drain can be reduced.

[0019] Secondly, this application provides an electronic device, which includes a circuit board and the chip described in the first aspect, the chip being disposed on the circuit board.

[0020] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0021] Thirdly, this application provides a method for fabricating a chip, comprising: forming a semiconductor layer, a dielectric material, a source electrode, and a drain electrode on a substrate; the source electrode and the drain electrode are respectively disposed at both ends of the semiconductor layer; the semiconductor layer includes a third surface facing the substrate and a fourth surface facing away from the substrate, and the dielectric material partially covers the third surface and the fourth surface. Under the protection of the dielectric material, the third surface and the fourth surface of the semiconductor layer are partially removed along the direction from the semiconductor layer to the substrate and the direction from the substrate to the semiconductor layer, forming grooves on the third surface and the fourth surface to obtain a channel layer. A gate structure is formed in the groove; the gate structure protrudes outward from the groove, and the gate structure includes a gate surrounding the channel layer, and a gate dielectric layer for isolating the gate and the channel layer; the dielectric material is filled between the source electrode and the gate structure, and between the drain electrode and the gate structure.

[0022] In this application, the gate not only coincides with the first channel (the bottom surface of the groove in the channel layer) but also with a portion of the second channel (a portion of the sidewall in the channel layer). Specifically, the orthographic projection of the gate onto the substrate coincides with the orthographic projection of the first channel onto the substrate, and the orthographic projection of the gate onto the source coincides with the orthographic projection of a portion of the second channel onto the source. Compared to related technologies, with the gate length (source to drain direction) remaining constant, this application's solution adds the extra overlap between the gate and a portion of the second channel. Therefore, in this application, the area controlled by the gate in the channel layer increases, thereby improving gate control capability. Furthermore, compared to cases where the gate is only disposed between adjacent dielectric materials, in this application, the gate is not only disposed between adjacent dielectric materials but also within the groove of the channel layer. Therefore, before fabricating the gate, an additional fabrication space—the groove—is reserved, increasing the gate fabrication space and improving the gate's process window.

[0023] Furthermore, if the thickness of the first channel is the same as the thickness of the channel layer in the related technology, then the thickness of the second channel is greater than the thickness of the channel layer in the related technology. On the one hand, the thickness of the dielectric material covering the second channel decreases, and the capacitance values ​​of the parasitic capacitance formed by the gate, dielectric material, and source, as well as the parasitic capacitance formed by the gate, dielectric material, and drain, all decrease. On the other hand, due to the increased thickness of the second channel, the area S in contact with the source and drain in the second channel increases. According to the resistance formula R = ρL / S, when the gate-ring transistor is turned on, the resistance of the second channel decreases, thereby increasing the current flowing through the second channel.

[0024] If the thickness of the second channel is the same as the thickness of the channel layer in the related technology, then the thickness of the first channel is less than the thickness of the channel layer in the related technology. The first channel with a reduced thickness is more easily controlled by the gate, thus improving the gate control capability.

[0025] In some possible implementations, under the protection of a dielectric material, the third and fourth surfaces of the semiconductor layer are partially removed along the direction from the semiconductor layer to the substrate and the direction from the substrate to the semiconductor layer to obtain a channel layer whose lower and upper surfaces both include grooves. This includes: under the protection of a dielectric material, oxidizing the semiconductor layer along the direction from the semiconductor layer to the substrate and the direction from the substrate to the semiconductor layer to obtain an oxide layer and a channel layer, wherein the oxide layer is located in the groove. Then, the oxide layer is removed.

[0026] During the oxidation process of the semiconductor layer, the portion of the sidewall of the trench further away from the bottom of the trench takes longer to oxidize, while the portion closer to the bottom of the trench takes shorter to oxidize. Therefore, the angle between the bottom surface of the trench and the sidewall is an obtuse angle. With an obtuse angle between the bottom surface of the trench and the sidewall, after the gate dielectric layer and the gate are formed in the trench, the angle between the sidewall of the gate and the first and second surfaces of the gate facing the trench is also an obtuse angle. This prevents the gate from forming a sharp structure, thereby avoiding short circuits between the gate tip and the source and drain, and preventing gate tip discharge that would result in a higher electric field.

[0027] In some possible implementations, forming a semiconductor layer, a dielectric material, a source electrode, and a drain electrode on a substrate includes: forming a sacrificial layer and a semiconductor layer on the substrate, with the semiconductor layer located between adjacent sacrificial layers; partially removing the sacrificial layer on its sidewall side and forming a dielectric material at the location where the sacrificial layer was removed; forming the source electrode and drain electrode; and removing the sacrificial layer.

[0028] In some possible implementations, the thickness of the sacrificial layer is less than the thickness of the semiconductor layer along the direction from the substrate to the semiconductor layer. This way, after removing the remaining sacrificial layer, the semiconductor layer itself is thick enough to prevent it from collapsing.

[0029] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0030] Figure 1a is a structural diagram of a planar transistor provided by related technologies;

[0031] Figure 1b is a structural diagram of a fin field-effect transistor provided by related technologies;

[0032] Figure 1c is a structural diagram of a gate-around transistor provided by related technologies;

[0033] Figure 2a is a structural diagram of a gate ring transistor provided in an embodiment of this application;

[0034] Figure 2b is a structural diagram of the gate ring transistor provided in an embodiment of this application;

[0035] Figure 3 is a cross-sectional view along the A1-A2 direction in Figure 1c;

[0036] Figure 4 is a structural diagram of the gate ring transistor provided in an embodiment of this application;

[0037] Figure 5 is a flowchart illustrating the fabrication process of the gate-ring transistor provided in an embodiment of this application;

[0038] Figure 6a is a diagram illustrating the fabrication process of the gate-ring transistor provided in an embodiment of this application;

[0039] Figure 6b is a diagram illustrating the fabrication process of the gate-ring transistor provided in an embodiment of this application;

[0040] Figure 6c is a diagram illustrating the fabrication process of the gate-ring transistor provided in an embodiment of this application;

[0041] Figure 6d is a diagram illustrating the fabrication process of the gate-ring transistor provided in the embodiment of this application;

[0042] Figure 6e is a diagram illustrating the fabrication process of the gate-ring transistor provided in an embodiment of this application;

[0043] Figure 7a is a diagram illustrating the fabrication process of the gate-ring transistor provided in an embodiment of this application;

[0044] Figure 7b is a diagram illustrating the fabrication process of the gate-ring transistor provided in an embodiment of this application.

[0045] Reference numerals: 10-substrate; 11-channel layer; 111-first channel; 112-second channel; 1111-semiconductor layer; 12-source; 13-drain; 14-gate dielectric layer; 15-gate; 16-dielectric material; 21-sacrificial layer; 22-oxide layer. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0048] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0049] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0050] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0051] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or any other device that includes a memory.

[0052] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory, radar, base stations, and other communication equipment containing gate-ring transistors.

[0053] For ease of explanation, the following description uses a mobile phone as an example. A mobile phone may include a circuit board, on which a processor and memory are disposed. The memory includes multiple storage cells, and each storage cell includes a transistor and a capacitor. The transistor includes a channel layer, a source, a drain, a gate, and a gate dielectric layer.

[0054] Figure 1a shows a planar transistor whose gate 15 covers one surface of the channel layer 11. Figure 1b shows a fin field-effect transistor (FinFET), in which the gate 15 spans three surfaces of the channel layer 11, improving the gate control capability. Figure 1c shows a gate-around transistor, whose gate 15 covers all four surfaces of the channel layer 11, addressing the problem of exacerbated short-channel effects in transistors due to very small process nodes (e.g., below 7nm). However, further improving the gate control capability of gate-around transistors remains a pressing issue.

[0055] Based on this, this application provides a chip including a substrate and a gate ring transistor disposed on the substrate, thereby improving gate control capability by changing the structure of the channel layer 11 in the gate ring transistor.

[0056] As shown in Figures 2a and 2b, the ring gate transistor includes a gate structure, the aforementioned channel layer 11, source 12, and drain. The gate structure includes the aforementioned gate dielectric layer 14 and gate.

[0057] The channel layer 11 includes a lower surface facing the substrate 10 and an upper surface facing away from the substrate 10, and grooves are formed on both the lower and upper surfaces. As shown in FIG2a, the channel layer 11 includes a first channel 111 and a second channel 112. The orthographic projection of the first channel 111 on the substrate 10 overlaps with the orthographic projection of the groove on the substrate 10. The second channel 112 is the portion of the channel layer 11 excluding the first channel 111, and the second channel 112 is covered by a dielectric material 16.

[0058] The gate structure protrudes outward from the groove. It should be understood that the groove contains an opening, so the gate structure protruding outward from the groove means that the gate structure protrudes beyond the opening in the groove. The gate 15 of the gate structure surrounds the channel layer 11, and the gate dielectric layer 14 of the gate structure is located between the gate 15 and the channel layer 11 to isolate the gate 15 and the channel layer 11.

[0059] The source 12 and drain 13 are respectively disposed at both ends of the channel layer 11. The chip also includes a dielectric material 16, which fills the space between the source 12 and the gate structure, and between the drain 13 and the gate structure. The source 12 and drain 13 are in contact with the sidewalls of the channel layer 11 and the sidewalls of the dielectric material 16. Apart from these two sidewalls, the other surfaces of the channel layer 11 are covered by the gate structure.

[0060] As shown in Figure 2a, the gate 15 not only coincides with the first channel 111 (the bottom surface of the groove in the channel layer 11) but also with a portion of the second channel 112 (a portion of the sidewall in the channel layer 11). Specifically, the orthographic projection of the gate 15 onto the substrate 10 coincides with the orthographic projection of the first channel 111 onto the substrate 10, and the orthographic projection of the gate 15 onto the source 12 coincides with the orthographic projection of a portion of the second channel 112 onto the source 12. Compared to related technologies, with the length of the gate 15 (in the direction from the source 12 to the drain 13) remaining unchanged, the solution in this embodiment adds the overlap of the gate 15 with a portion of the second channel 112. Therefore, in this embodiment, the area controlled by the gate 15 in the channel layer 11 increases, thereby improving gate control capability and reducing short-channel effects. Furthermore, compared to the case where the gate 15 is only disposed between adjacent dielectric materials 16, the gate 15 of this application is not only disposed between adjacent dielectric materials 16, but also disposed in a groove. Therefore, before fabricating the gate 15, an additional fabrication space of a groove is reserved for the gate 15, which increases the fabrication space of the gate and improves the process window of the gate 15.

[0061] Furthermore, if the thickness of the first channel 111 is the same as the thickness of the channel layer 11 in the related art, then the thickness of the second channel 112 is greater than the thickness of the channel layer 11 in the related art. On the one hand, the thickness of the dielectric material 16 covering the second channel 112 decreases, and the capacitance values ​​of the parasitic capacitance formed by the gate 15, the dielectric material 16, and the source 12, as well as the parasitic capacitance formed by the gate 15, the dielectric material 16, and the drain 13, all decrease. On the other hand, since the thickness of the second channel 112 increases, the area S in the second channel 112 that contacts the source 12 and the drain 13 increases. According to the resistance formula R = ρL / S, when the gate ring transistor is turned on, the resistance of the second channel 112 decreases, thereby increasing the current flowing through the second channel 112.

[0062] If the thickness of the second channel 112 is the same as the thickness of the channel layer 11 in the related technology, then the thickness of the first channel 111 is less than the thickness of the channel layer 11 in the related technology. The first channel 111 with a reduced thickness is more easily controlled by the gate 15, thus improving the gate control capability and reducing the short-channel effect.

[0063] The orthographic projection of the gate 15 onto the substrate 10 refers to the projection of the gate 15 perpendicularly onto the substrate 10. Other descriptions of "orthographic projection" above and below can be found in this explanation and will not be repeated here. Furthermore, in this application, the thickness directions of the channel layer 11, the gate 15, and the dielectric material 16 are all in the direction from the substrate 10 towards the gate-around transistor.

[0064] In some possible implementations, as shown in Figure 2a, the gate ring transistor may include a channel layer 11.

[0065] Alternatively, as shown in Figure 2b, the gate-around transistor can also include multiple channel layers 11 stacked along the direction from the substrate 10 toward the gate-around transistor. The dielectric material 16, the gate dielectric layer 14, and the gate 15 are not only disposed between adjacent channel layers 11, but also on the side of the channel layer 11 closest to the substrate 10 facing the substrate 10, and on the side of the channel layer 11 farthest from the substrate 10 away from the substrate 10. Compared to a gate-around transistor with only one channel layer 11, a gate-around transistor with multiple channel layers 11 can increase the driving capability of the gate-around transistor.

[0066] Based on this, regardless of whether the gate ring transistor includes one or more channel layers 11, the gate dielectric layer 14 can also be disposed between the gate 15 closest to the substrate 10 and the substrate 10, or a dielectric layer of other insulating material can be disposed between the gate 15 closest to the substrate 10 and the substrate 10 to prevent the gate 15 from short-circuiting with the substrate 10.

[0067] In some possible implementations, the gate structure includes a first surface and a second surface, the first surface being the side of the gate structure facing the substrate 10, and the second surface being the side of the gate structure facing away from the substrate 10.

[0068] Figure 3 shows a cross-sectional view of a gate ring transistor in the related art. Due to the process of forming the dielectric material 16, sharp points with acute angles are easily formed between the first surface and the sidewall and between the second surface and the sidewall in the gate 15. On the one hand, the sharp points of the gate 15 are easy to short-circuit with the source 12 and the drain 13; on the other hand, the discharge of the sharp points of the gate 15 will cause a higher electric field.

[0069] As shown in Figure 4, in order to solve the tip problem, the fabrication process of the gate ring transistor is improved so that the angle between the bottom surface of the groove and the sidewall of the groove is obtuse. In this way, since the gate structure is filled in the groove, the angle between the sidewall of the gate structure and the first and second surfaces of the gate structure facing the groove is also obtuse. This avoids the gate 15 from forming a tip structure, thereby avoiding the tip of the gate 15 from short-circuiting with the source 12 and the drain 13, and avoiding tip discharge of the gate 15, which would cause a higher electric field.

[0070] Here, this embodiment does not limit the specific angle between the sidewall of the gate structure and the first and second surfaces of the gate structure facing the groove. This angle is related to the process of preparing the groove in the channel layer 11. In some other possible implementations, by changing the process of preparing the groove in the channel layer 11, the angle between the sidewall of the gate structure and the first and second surfaces of the gate structure facing the groove can also be made to be a right angle.

[0071] As mentioned earlier, due to the process of forming the dielectric material 16, sharp points with acute angles are easily formed between the first surface facing the groove and the sidewall, and between the second surface facing the groove and the sidewall, in the gate structure. In related technologies, the process of forming the dielectric material 16 typically involves: first forming a sacrificial layer and a semiconductor layer (which, after processing, becomes the channel layer 11) on the substrate 10; then partially removing the sacrificial layer; finally forming the dielectric material 16 at the location of the removed sacrificial layer; and then removing the remaining sacrificial layer. Therefore, the thickness of the dielectric material 16 is the same as the thickness of the sacrificial layer.

[0072] In this embodiment, the thickness of the channel layer 11 is greater than the thickness of the dielectric material 16, that is, the thickness of the channel layer 11 is greater than the thickness of the sacrificial layer. In this way, after the remaining sacrificial layer is removed, the channel layer 11 itself is thick enough to prevent it from collapsing.

[0073] Optionally, when the total thickness of the dielectric material 16 and the channel layer 11 is the same, the thickness of the channel layer 11 in this embodiment of the application may be greater than the thickness of the channel layer 11 in the related art, thereby reducing the thickness of the dielectric material 16.

[0074] For example, in related technologies, the thickness of the channel layer 11 is 5 nm; while in the embodiments of this application, the thickness range of the first channel 111 is [3 nm, 5 nm], and the thickness range of the second channel 112 is (5 nm, 10 nm). By increasing the thickness of the channel layer 11 and decreasing the thickness of the dielectric material 16, the capacitance value of the parasitic capacitance formed by the gate 15, the dielectric material 16, and the source 12 can be reduced, and the capacitance value of the parasitic capacitance formed by the gate 15, the dielectric material 16, and the drain 13 can be reduced. On the other hand, by reducing the thickness of the dielectric material 16, the dimension of the tip of the gate 15 disposed between the dielectric materials 16 extending along the sidewall of the dielectric material 16 towards the source 12 and the drain 13 can be reduced, which can improve the problem of short circuit between the gate 15 and the source 12 and the drain 13.

[0075] In some possible implementations, completely removing the sacrificial layer reduces the spacing between the gate 15 and the source 12 and drain 13. According to the capacitance formula, the reduced spacing between the gate 15 and the source 12, and between the gate 15 and the drain 13, leads to a sharp increase in the capacitance formed between the gate 15 and the source 12, and between the gate 15 and the drain 13. Consequently, the AC electrical performance of the gate-around transistor decreases, and the resistive-capacitive delay (RC delay) of the gate-around transistor increases.

[0076] To ensure that the capacitance between the gate 15 and the source 12 and drain 13 is within a controllable range, an inner spacer process (ISP) is used between the source 12 and drain 13 and the gate 15. The main purpose of this process is to fill and replace a portion of the high-dielectric material (e.g., gate dielectric layer 14) close to the source 12 and drain 13 with a dielectric material of lower dielectric constant, thereby reducing capacitance and thus reducing RC delay. In this application, regardless of whether the gate-ring transistor includes one or more channel layers 11, the dielectric constant of the dielectric material 16 is lower than that of the gate dielectric layer 14.

[0077] In another embodiment, this application also provides a method for fabricating a chip, as shown in FIG5, which can be achieved through the following steps:

[0078] S110, as shown in FIG6a, a sacrificial layer 21 and a semiconductor layer 1111 are formed on the substrate 10, with the semiconductor layer 1111 located between adjacent sacrificial layers 21. The semiconductor layer 1111 includes a third surface facing the substrate 10 and a fourth surface facing away from the substrate 10, and the sacrificial layer 21 covers the third and fourth surfaces. Optionally, the material of the sacrificial layer 21 may include, for example, germanium-silicon.

[0079] S120, as shown in FIG6b, the sacrificial layer 21 is partially removed from its sidewall side. Next, as shown in FIG6c, a dielectric material 16 is formed at the removed location in the sacrificial layer 21. Therefore, a semiconductor layer 1111 is also disposed between adjacent dielectric materials 16, the dielectric materials 16 partially covering the third and fourth surfaces, and the thickness of the dielectric materials 16 is equal to the thickness of the sacrificial layer 21. Optionally, an etching process can be used to partially remove the sacrificial layer 21.

[0080] S130, as shown in FIG6d, forms a source 12 and a drain 13, which are respectively disposed at both ends of the semiconductor layer 1111 and are in contact with the sidewall of the semiconductor layer 1111 and the sidewall of the dielectric material 16.

[0081] S140, as shown in Figure 6e, remove the remaining sacrificial layer 21.

[0082] In some possible implementations, the thickness of the semiconductor layer 1111 can be greater than the thickness of the sacrificial layer 21 (dielectric material 16). In this way, after the remaining sacrificial layer 21 is removed, the semiconductor layer 1111 itself is thick enough to prevent it from collapsing.

[0083] Optionally, when the total thickness of the sacrificial layer 21 and the semiconductor layer 1111 is the same, the thickness of the semiconductor layer 1111 in this embodiment of the application may be greater than the thickness of the semiconductor layer 1111 in the related art, thereby reducing the thickness of the sacrificial layer 21 (dielectric material 16).

[0084] For example, in related technologies, the thickness of the semiconductor layer 1111 is 5 nm; while in the embodiments of this application, the thickness range of the first channel 111 to be formed is [3 nm, 5 nm], and the thickness range of the second channel 112 to be formed is (5 nm, 10 nm). By increasing the thickness of the semiconductor layer 1111 and decreasing the thickness of the dielectric material 16, the capacitance value of the parasitic capacitance formed by the gate 15, the dielectric material 16, and the source 12 can be reduced, and the capacitance value of the parasitic capacitance formed by the gate 15, the dielectric material 16, and the drain 13 can be reduced. On the other hand, by reducing the thickness of the dielectric material 16, the dimension of the tip of the gate 15 disposed between the dielectric materials 16 extending along the sidewall of the dielectric material 16 towards the source 12 and the drain 13 can be reduced, which can improve the problem of short circuit between the gate 15 and the source 12 and the drain 13.

[0085] Thus, a semiconductor layer 1111, a dielectric material 16, a source electrode 12, and a drain electrode 13 are formed on the substrate 10.

[0086] S150, as shown in Figure 7a, under the protection of the dielectric material 16, the third and fourth surfaces of the semiconductor layer 1111 are oxidized along the direction from the semiconductor layer 1111 to the substrate 10 and the direction from the substrate 10 to the semiconductor layer 1111, forming grooves on the third and fourth surfaces to obtain a channel layer 11 containing the grooves and an oxide layer 22 located in the grooves. The oxide layer 22 is obtained by reacting the material of the semiconductor layer 1111 with oxygen. By controlling factors such as the duration, temperature, and oxygen concentration of the oxidation process, the thickness of the oxide layer 22, i.e., the depth of the grooves, can be controlled.

[0087] S160, as shown in Figure 7b, remove the oxide layer 22 to expose the groove, which is located between adjacent dielectric materials 16.

[0088] In some other possible implementations, as an alternative to steps S150 and S160, an etching process can be used to partially etch the semiconductor layer 1111 to obtain a channel layer 11 containing grooves. Of course, other processes can also be used to obtain the channel layer 11 containing grooves, and this application embodiment does not limit this.

[0089] In some possible implementations, taking the process of forming the groove in steps S150 and S160 as an example, during the oxidation of the semiconductor layer 1111, the portion of the sidewall of the groove further away from the bottom of the groove is oxidized for a longer time; the portion of the sidewall of the groove closer to the bottom of the groove is oxidized for a shorter time. Therefore, the angle between the bottom surface of the groove and the sidewall is an obtuse angle. Of course, if other processes are used, the angle between the bottom surface of the groove and the sidewall can also be a right angle, and this application embodiment does not limit this.

[0090] S170, as shown in Figures 2a and 2b, a gate structure is sequentially formed in the groove, protruding outward from the groove. The gate structure includes a gate 15 surrounding the channel layer 11, and a gate dielectric layer 14 for isolating the gate 15 from the channel layer 11. The dielectric material formed in step S120 fills the space between the source 12 and the gate structure, and between the drain 13 and the gate structure.

[0091] As mentioned earlier, when the angle between the bottom surface of the groove and the sidewall is obtuse, after the gate structure is formed in the groove, the angle between the sidewall of the gate structure and the first and second surfaces of the gate structure facing the groove is also obtuse. This prevents the gate 15 from forming a pointed structure, thereby preventing the pointed end of the gate 15 from short-circuiting with the source 12 and the drain 13, and preventing the pointed end of the gate 15 from discharging and causing a higher electric field.

[0092] In this application, the gate 15 not only coincides with the first channel 111 (the bottom surface of the groove in the channel layer 11), but also with a portion of the second channel 112 (a portion of the sidewall in the channel layer 11). Specifically, the orthographic projection of the gate 15 onto the substrate 10 coincides with the orthographic projection of the first channel 111 onto the substrate 10, and the orthographic projection of the gate 15 onto the source 12 coincides with the orthographic projection of a portion of the second channel 112 onto the source 12. Compared to related technologies, with the length of the gate 15 (in the direction from the source 12 to the drain 13) remaining unchanged, the solution in this application embodiment has the additional overlap of the gate 15 with a portion of the second channel 112. Therefore, in this embodiment, the area controlled by the gate 15 in the channel layer 11 increases, thereby improving gate control capability. Furthermore, compared to the case where the gate 15 is only disposed between adjacent dielectric materials 16, the gate 15 of this application is not only disposed between adjacent dielectric materials 16, but also disposed in a groove. Therefore, a larger fabrication space is reserved for the gate 15 before fabrication, thereby increasing the process window of the gate 15.

[0093] Furthermore, if the thickness of the first channel 111 is the same as the thickness of the channel layer 11 in the related art, then the thickness of the second channel 112 is greater than the thickness of the channel layer 11 in the related art. On the one hand, the thickness of the dielectric material 16 covering the second channel 112 decreases, and the values ​​of the parasitic capacitance formed by the gate 15, the dielectric material 16, and the source 12, as well as the values ​​of the parasitic capacitance formed by the gate 15, the dielectric material, and the drain 16, all decrease. On the other hand, since the thickness of the second channel 112 increases, the area S in the second channel 112 that contacts the source 12 and the drain 13 increases. According to the resistance formula R = ρL / S, when the gate ring transistor is turned on, the resistance of the second channel 112 decreases, thereby increasing the current flowing through the second channel 112.

[0094] If the thickness of the second channel 112 is the same as the thickness of the channel layer 11 in the related technology, then the thickness of the first channel 111 is less than the thickness of the channel layer 11 in the related technology. The first channel 111 with a reduced thickness is more easily controlled by the gate 15, thus improving the gate control capability.

[0095] Furthermore, the other explanations and beneficial effects of the embodiments of this application are the same as those of the chip in the previous embodiment, and will not be repeated here.

[0096] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip, characterized by The device includes a substrate and a gate-around transistor disposed on the substrate, the gate-around transistor including a channel layer, a gate structure, a source, and a drain; The channel layer includes a lower surface facing the substrate and an upper surface facing away from the substrate, and grooves are formed on both the lower surface and the upper surface; The gate structure protrudes outward from the groove; the gate structure includes a gate surrounding the channel layer, and a gate dielectric layer for isolating the gate and the channel layer; The source and the drain are located at opposite ends of the channel layer, and dielectric material is filled between the source and the gate structure, and between the drain and the gate structure.

2. The chip according to claim 1, characterized in that, The gate structure includes a first surface facing the substrate and a second surface facing away from the substrate; The angle between the bottom surface and the sidewall of the groove is an obtuse angle, the angle between the sidewall of the grid structure and the first surface on which the groove is formed is an obtuse angle, and the angle between the sidewall of the grid structure and the second surface on which the groove is formed is also an obtuse angle.

3. The chip according to claim 1 or 2, characterized in that, Along the direction from the substrate toward the gate ring transistor, the thickness of the channel layer is greater than the thickness of the dielectric material.

4. The chip of claim 3, wherein Along the direction from the substrate to the gate ring transistor, the thickness of the portion of the channel layer outside the groove ranges from 5 nm to 10 nm.

5. The chip according to any one of claims 1-4, characterized in that, The gate ring transistor includes a plurality of channel layers arranged in a direction from the substrate toward the gate ring transistor, and the plurality of channel layers are stacked.

6. The chip according to any one of claims 1-5, characterized in that, The dielectric constant of the dielectric material is less than the dielectric constant of the gate dielectric layer.

7. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-6, wherein the chip is disposed on the circuit board.

8. A method for fabricating a chip, characterized in that, include: A semiconductor layer, dielectric material, source electrode, and drain electrode are formed on the substrate; The source and the drain are respectively disposed at both ends of the semiconductor layer; The semiconductor layer includes a third surface facing the substrate and a fourth surface facing away from the substrate, and the dielectric material partially covers the third surface and the fourth surface; Under the protection of the dielectric material, the third and fourth surfaces of the semiconductor layer are partially removed along the direction from the semiconductor layer to the substrate and the direction from the substrate to the semiconductor layer, and grooves are formed on the third and fourth surfaces to obtain a channel layer; A gate structure is formed in the groove; the gate structure protrudes outward from the groove, the gate structure including a gate surrounding the channel layer, and a gate dielectric layer for isolating the gate and the channel layer; the dielectric material is filled between the source and the gate structure, and between the drain and the gate structure.

9. The method for fabricating a chip according to claim 8, characterized in that, Under the protection of the dielectric material, the third and fourth surfaces of the semiconductor layer are partially removed along the direction from the semiconductor layer to the substrate and the direction from the substrate to the semiconductor layer to obtain a channel layer with grooves on both the lower and upper surfaces, including: Under the protection of the dielectric material, the semiconductor layer is oxidized along the direction from the semiconductor layer to the substrate and the direction from the substrate to the semiconductor layer to obtain an oxide layer and the channel layer, wherein the oxide layer is located in the trench; Remove the oxide layer.

10. The method for fabricating a chip according to claim 8 or 9, characterized in that, The process of forming a semiconductor layer, dielectric material, source electrode, and drain electrode on a substrate includes: A sacrificial layer and a semiconductor layer are formed on a substrate, wherein the semiconductor layer is located between adjacent sacrificial layers; On the sidewall side of the sacrificial layer, the sacrificial layer is partially removed, and the dielectric material is formed at the location where the sacrificial layer was removed. The source and the drain are formed; Remove the sacrificial layer.

11. The method for fabricating a chip according to claim 10, characterized in that, Along the direction from the substrate to the semiconductor layer, the thickness of the sacrificial layer is less than the thickness of the semiconductor layer.

Images