Field effect transistor with fin structure and drift region

Abstract

The invention relates to a field effect transistor (100), comprising: a first type of doped separating layer (103), a second type of doped first connection region (104a) and a second type of doped second connection region (104b) which are arranged on the first type of doped separating layer (103) and are laterally spaced apart from one another, one or more channel layers which are each in the form of a fin structure (110, 410), having an electrical connection to one of the first and second connection regions (104a), a second type of doped drift region (105) which is arranged on the first type of doped separating layer (103), wherein the one or more fin structures (110, 410) are laterally arranged between the first connection region (104a) and the second connection region (104b), further comprising a first type of doped boundary layer (108) arranged above the one or more channel layers formed as a fin structure (110, 410) and the drift region, further comprising, for the one or each of the plurality of fin structures, in each case a gate structure, each gate structure having a gate dielectric (106, 407) and a gate electrode (107, 407), wherein the gate electrode is insulated with respect to the fin structure by means of the gate dielectric.

Description

[0001] Description

[0002] title

[0003] Field-effect transistor with fin structure and drift range

[0004] The present invention relates to a field-effect transistor comprising one or more fin structures and a drift region for reducing electric fields at the surface.

[0005] Background of the invention

[0006] Field-effect transistors, especially MOSFETs and MISFETs, are used in various applications. One variant is the trench MOSFET or T-MOSFET, in which one channel is vertically oriented; these are known as vertical power transistors. There are also lateral field-effect transistors and power transistors.

[0007] Disclosure of the invention

[0008] According to the invention, a field-effect transistor with the features of the independent claim is proposed. Advantageous embodiments are the subject of the dependent claims and the following description.

[0009] The invention relates to field transistors, particularly power transistors. Different types of doping are used in the semiconductor materials for these transistors, namely n-type and p-type doping, whereby different components can be doped differently. For the sake of clarity, field-effect transistors will be described below using one specific type of doping: p-type doping and n-type doping. It should be understood, however, that n- and p-type doping can also be reversed, i.e., p-type doping could be type II and n-type doping type I.

[0010] Such a field-effect transistor can be used alone or in combination with others, for example as a power switch. Preferred applications include, for example, in the electric powertrain of a vehicle, such as in a current converter (DC / DC converter, inverter), in chargers for electric vehicles, or also in solar inverters or household appliances.

[0011] Semiconductor devices such as field-effect transistors or transistors can generally be based on gallium nitride (GaN). This offers the possibility of realizing components with lower on-resistance and simultaneously higher breakdown voltages than comparable components based on, for example, ferric oxide.

[0012] Silicon (Si). However, other semiconductor materials with a wide band gap are also suitable, such as SiC, gallium oxide, etc.

[0013] The field-effect transistor typically has a substrate layer followed by, for example, an undoped or only weakly doped layer, which serves for vertical electrical insulation and is usually contacted by an electrode so that this layer can be placed at a predetermined electrical potential.

[0014] A first-type doped separating layer positioned above or on top of this layer serves as electrical shielding and suppresses vertical charge transport. This separating layer features a first and a second terminal area, both of which are second-type doped and can each be electrically contacted by a corresponding electrode. In one embodiment, the first terminal area can be configured as a source area, and the second terminal area as a drain area.

[0015] Laterally between the first and second connection regions are one or more channel layers, each configured as a fin structure, as well as a drift region. A gate dielectric and a gate electrode are arranged around each fin structure, allowing the transport properties, particularly of the structure enclosed by the gate arrangement, to be modulated. A gate voltage can be applied via the gate electrode.

[0016] The channel layers (which are arranged in a fin structure) can be doped with type I doping, in which case an inversion channel is formed. Alternatively, a weak type II doping can be used, resulting in an accumulation channel. The width of the fin structure should be sufficiently narrow, especially in the range below 200 nm, so that without applying a gate voltage, the charge carriers are almost completely expelled from the fin and the transistor can be operated in the "normally off" state.

[0017] The use of the fin-like structure allows for a higher integration density of this structure, as well as a reduction in leakage currents compared to a conventional transistor geometry.

[0018] The one or more fin structures or the relevant channel areas are each electrically connected (in a lateral direction) to a first and second connection area doped with the second type, whereby this first and second connection area can each be electrically contacted via an electrode.

[0019] In one embodiment, exactly one channel layer designed as a fin structure is provided. This is then electrically connected to the first connection area, the first connection area being designed as a source area.

[0020] At the other lateral end of the fin structure is the drift region, which in turn is connected to the second-type doped terminal region. This second terminal region can be electrically contacted via an electrode. The second terminal region then functions as a drain region.

[0021] Both the fin structure and the drift region are electrically bounded at the top by a type I doped boundary layer. This boundary layer, together with the type I doped separating layer at the bottom, serves to generate a superjunction effect in the drift region.

[0022] When a voltage is applied to the first terminal region (e.g., as the source region) and the gate is off, the type I doped interface and the type I doped boundary layer deplete the drift region, causing the space charge region to extend across the entire drift region. This results in a continuous voltage drop along the entire length of the drift region, thus limiting the maximum electric field strength in the structure. This allows for a reduction in the length of the drift region, which in turn enables a higher integration density.

[0023] The first type of doped boundary layer primarily serves to reduce the electric field at the surface of the structure; in particular, the maximum electric field in the semiconductor material lies below this layer. This is a crucial advantage, as it increases the reliability of the component. Specifically, no electric field peaks occur outside the structure, thus preventing the influence of adjacent structures.

[0024] Additionally, the first-type doped separating layer and the first-type doped boundary layer, which generate the superjunction effect, can be electrically connected to the first terminal region by a further first-type doped region, a connection region, in order to prevent any shift in the threshold voltage (body effect). One embodiment relates to an arrangement with several such field-effect transistors connected in parallel, wherein the first and second terminal regions, or the electrodes connected thereto, as well as the individual gate electrodes, are each electrically connected. The increased surface area facilitates easy contact between the electrodes. This arrangement with several field-effect transistors connected in parallel can be used, in particular, in power electronic switching arrangements.

[0025] In addition to the unidirectional variant described above, a bidirectional variant of the field-effect transistor can be implemented in a further embodiment. In this embodiment, two fin structures are located laterally between the first and second terminal regions, each connected to the first and second terminal regions, respectively. The drift region is situated between these fin structures. The structure of the fin structures and the drift region corresponds to that of the unidirectional variant described above; in particular, the second fin structure is also surrounded by a gate structure comprising a gate dielectric and a gate electrode. However, unlike the unidirectional variant, the doped separating layer and the doped boundary layer are not rigidly connected to the first terminal region.Rather, another contact outside the field-effect transistor can be used to connect these first-type doped areas to the contact used as the first connection area.

[0026] In particular, either the first terminal area can be used as the source area and the second terminal area as the drain area, or vice versa. In other words, the field-effect transistor can be used in one configuration or the other, depending on the desired configuration, for example by simply swapping the terminals; the field-effect transistor itself remains unchanged.

[0027] The bidirectional variant can be used, for example, in power conversion circuits. In another embodiment, an arrangement with several bidirectional field-effect transistors connected in parallel can also be implemented. As in the unidirectional case, the first and second terminal regions, or rather the electrodes connected to them, and the gate electrodes are each electrically connected. Connecting the individual elements in parallel is particularly useful for implementing power-oriented applications.

[0028] Vertical power transistors can have the disadvantage that monolithic integration, for example, gate-driver integration on the same chip, is difficult or only possible with limited functionality. Furthermore, bidirectional devices are only achievable with considerable effort or reduced performance. Lateral power transistors, as proposed within the scope of the present invention, are, however, very well suited for monolithic integration and can also be implemented bidirectionally. However, the voltage withstand capability of lateral devices is limited because electric fields occur on the transistor's surface, and a higher voltage withstand capability due to the lateral extension of the drift region comes at the expense of the specific on-resistance. This is precisely what the present invention, as described, addresses.

[0029] The invention is schematically illustrated in the drawing using an exemplary embodiment and is described below with reference to the drawing.

[0030] Brief description of the drawings

[0031] Figures 1a and 1b show a schematic embodiment of a field-effect transistor according to the invention.

[0032] Figures 2a and 2b show a schematic cross-section of the field-effect transistor depicted in Figures 1a and 1b. Figure 3 shows an embodiment in which several unidirectional field-effect transistor structures are connected in parallel.

[0033] Figure 4 shows another embodiment of a field-effect transistor according to the invention, in cross-section.

[0034] Figure 5 shows an embodiment in which several bidirectional field-effect transistor structures are connected in parallel.

[0035] embodiment(s) of the invention

[0036] Figures 1a and 1b show an embodiment of a field-effect transistor 100 according to the invention, specifically a possible implementation in a unidirectional design. Figure 1a shows the field-effect transistor without a gate structure and electrical contacts, while Figure 1b shows it with a gate structure and electrical contacts.

[0037] The field-effect transistor 100, particularly in the form of a power transistor, is built on a lightly or undoped semiconductor layer 102, which is deposited on a suitable substrate 101. This layer 102 does not actively participate in switching but serves only as vertical electrical insulation. The undoped semiconductor layer 102 is additionally contacted on its back side by an electrode and can thus be brought to a predetermined electrical potential.

[0038] The actual active component is electrically shielded from the undoped semiconductor layer 102 by a first type of doped separating layer 103, which serves to suppress vertical current flow.

[0039] On this separating layer 103, a second type of doped first connection region 104a and a second type of doped second connection region 104b are arranged laterally. The first connection region is configured as a source region 104a, and the second connection region as a drain region 104b. Between the source region 104a and the drain region 104b are a fin structure 110 and a drift region 108. The fin structure 110 is connected to the source region 104a, while the drift region adjoins the drain region 104b. The source region 104a and the drain region 104b are each additionally electrically connected to a source electrode 111 and a drain electrode 112, respectively.

[0040] The fin structure itself exhibits a first-type doped channel region 110 – or rather, the channel region 100 is formed as a fin structure. It is also possible to use a second-type doping for the channel region 110, in which case an accumulation channel forms instead of an inversion channel.

[0041] A fin structure is understood to be, in particular, a narrow formation of the relevant area compared to the areas arranged laterally to its side, in front of it, and behind it. The width of the fin structure should be sufficiently narrow, especially narrower than 200 nm, so that even without an applied gate voltage, the charge carriers are almost completely expelled from the fin structure, enabling "normally-off" operation.

[0042] Using a fin structure offers several advantages over a conventional transistor structure, such as the realization of a higher integration density. Furthermore, lower gate voltages are required to control charge carrier transport, which in particular leads to lower leakage currents.

[0043] A gate electrode 107 is additionally arranged around the fin structure and is separated from the semiconductor structure by a gate dielectric 106. This gate structure allows modulation of the charge carrier transport in the layers enclosed by the gate structure.

[0044] The drift region 105 is located laterally between the highly doped drain region 104b and the fin structure. Both the fin structure and the drift region 105 are electrically bounded above by a type I doped region 108. Applying a voltage to the drain electrode 112 with the gate off leads to a depletion of the drift region by the two type I doped layers 103 and 108, so that the space charge region extends over the entire drift region 105 (so-called superjunction effect). This results in a continuous voltage drop over the entire length of the drift region 105, thus reducing the maximum strength of the electric field in the structure.

[0045] In particular, the type 1 doped layer 108 minimizes peaks of the electric field on the top side of the transistor; rather, the maximum of the electric field is always located within the semiconductor material below the type 1 doped layer 108. This leads, in particular, to increased reliability of the component, since peaks of the electric field in materials other than the semiconductor, or at interfaces to other materials, are avoided.

[0046] The first-type doped layers 103, 108, which serve to generate the superjunction effect, are additionally electrically connected to the source electrode 111 by another first-type doped region, the junction region 109. This prevents, in particular, a shift in the threshold voltage (so-called body effect).

[0047] Figure 2a shows a longitudinal section and Figure 2b shows a cross-section of the structure shown in Figure 1b. It can be seen that by applying an electrical voltage to the gate structure 106, 107, the conduction channel 110 of the fin structure can be opened, thus allowing electrical transport through the fin structure. The current path with the gate open is shown schematically by the dashed line in Figure 2a.

[0048] Figures 1a, 1b and 2a, 2b each show a field-effect transistor, or more specifically, a cell of the field-effect transistor. However, several unidirectional field-effect transistors or such cells can also be connected in parallel, particularly for scaling the power. Such an arrangement 300 with several field-effect transistors 100 connected in parallel is shown in Figure 3. The source electrodes 111 and drain electrodes 112 of the individual field-effect transistors, as well as the individual gate electrodes 107, are electrically connected. This results in extended electrode regions 107, 111, 112 that can be easily connected.

[0049] In addition to the unidirectional field-effect transistor shown in Figures 1a, 1b, 2a, 2b, and the corresponding arrangement shown in Figure 3, one embodiment relates to a bidirectional field-effect transistor or power transistor. Such a field-effect transistor 400 is shown schematically in Figure 4.

[0050] A second fin structure 410 is required, which is connected to the drain region 104a. The other fin structure 110 is connected to the source region 104a, as in the unidirectional arrangement. The drift region 105 is located laterally between the two fin structures 110 and 410.

[0051] The charge transport properties of the second fin structure 410 are, analogous to the first fin structure 110, electrically modulatable via a gate structure comprising a gate electrode 407 and a gate dielectric 406.

[0052] To enable bidirectional operation of the field-effect transistor 400, the gate electrodes of the first and second fin structure can be controlled independently of each other, so that blocking or conducting operation in both directions is possible.

[0053] Secondly, source electrode 111 and drain electrode 112 can alternately take over the function of the other electrode.

[0054] In contrast to the unidirectional version, in the bidirectional component the superjunction layers 103, 108 are not permanently connected to the source region 104a or the drain region 104b, respectively, or to the electrode in question. Instead, an external circuit – indicated here schematically by 420 – ensures that these superjunction layers 103, 108 are connected to the contact used as the source electrode. Therefore, instead of source region 104a and drain region 104b, one can also generally refer to the first and second connection regions 104a and 104b, respectively.

[0055] This variant of the field-effect transistor offers a simple way to implement bidirectional functionality in a monolithic transistor structure. This bidirectional variant is particularly suitable for power conversion circuits.

[0056] Figure 5 shows an arrangement 500 with several such bidirectional field-effect transistors 400. As can be seen, in this bidirectional arrangement, analogous to the unidirectional case, it is possible to connect several field-effect transistors or cells in parallel. The source 111, drain 112, and gate electrodes 107, 407 of the individual field-effect transistors are electrically connected, resulting in large-area electrodes that can be easily contacted. The parallel connection of the individual field-effect transistors or cells particularly allows for the realization of power-oriented applications.

Claims

1. Field-effect transistor (100, 400), comprising: a first-type doped separator (103), a second-type doped first terminal region (104a) and a second-type doped second terminal region (104b), which are arranged on the first-type doped separator (103) and laterally separated from each other, one or more channel layers, each formed as a fin structure (110, 410), having an electrical connection with one of the first and second terminal regions (104a), a second-type doped drift region (105) which is arranged on the first-type doped separator (103), wherein the one or more fin structures (110, 410) and the drift region are arranged laterally between the first terminal region (104a) and the second terminal region (104b), further comprising a layer above the one or more fin structures (110, 410).410) formed channel layers and the drift region arranged a first-type doped boundary layer (108), further comprising, for one or each of the multiple fin structures, a gate structure, each gate structure comprising a gate dielectric (106, 407) and a gate electrode (107, 407), wherein the gate electrode is insulated from the fin structure by means of the gate dielectric.

2. Field-effect transistor (100, 400) according to claim 1, wherein the channel layer of one or each of the multiple fin structures (110, 410) of the first kind is doped.

3. Field-effect transistor (100, 400) according to claim 1, wherein the channel layer (110) is endowed with one or each of the multiple fin structures (110, 410) of the second kind.

4. Field-effect transistor (100, 400) according to one of the preceding claims, further comprising an undoped semiconductor layer on which the separating layer (103) is arranged.

5. Field-effect transistor (100) according to one of the preceding claims, comprising exactly one fin structure (110).

6. Field-effect transistor (100) according to claim 5, wherein the first terminal area (104a) is a source area and wherein the second terminal area (104b) is a drain area.

7. Field-effect transistor (100) according to claim 5 or 6, comprising one or more first-type doped connection regions (109) by means of which the separating layer (103) and the boundary layer (108) are electrically connected to the first connection region (104a).

8. Arrangement (300) comprising several field-effect transistors (100) according to one of claims 5 to 7, wherein the several field-effect transistors are connected in parallel and wherein the connection areas of the first (104a) and second type (104b), as well as the gate electrodes (107) are each electrically connected and arranged to be controlled independently of one another.

9. Field-effect transistor (400) according to one of claims 1 to 4, comprising two fin structures (110, 410), wherein the drift region (105) is arranged between the two fin structures, wherein the channel layer of one fin structure is electrically connected to the first terminal region (104a), and wherein the channel layer of the second fin structure is electrically connected to the second terminal region (104b).

10. Field-effect transistor (400) according to claim 9, which is configured such that optionally a) the first terminal area can be used as a source area and the second terminal area as a drain area, or b) the first connection area can be used as a drain area and the second connection area as a source area.

11. Field-effect transistor (400) according to claim 9 or 10, comprising an electrical connection between the separating layer (103) and the boundary layer 108 with the first terminal area.

12. Arrangement (500) comprising several field-effect transistors (400) according to one of claims 9 to 11, wherein the first (104a) and second connection areas (104b), as well as the gate electrodes (107, 407) are each electrically connected and arranged to be controlled independently of each other.

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