Image sensor and photodetection device

Abstract

To improve image quality in an image sensor that simultaneously performs exposure in all pixels.　A conversion efficiency control transistor opens and closes a path between a floating diffusion (FD) and an additional capacitor. A discharge transistor discharges a charge from a photoelectric conversion element. A reset transistor is interposed between a power supply voltage and the discharge transistor. A transfer transistor transfers a charge from the photoelectric conversion element to the FD. An FD link gate transistor opens and closes a path between a connection point of the additional capacitor and the conversion efficiency control transistor and a connection point of the reset transistor and the discharge transistor. A plurality of capacitive elements holds a level corresponding to the voltage of the FD.

Description

IMAGE SENSOR AND PHOTODETECTION DEVICECROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP 2024-087451 filed on May 29, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present technology relates to an image sensor. Specifically, the present technology relates to a voltage domain type image sensor and a photodetection device.

[0003] A global shutter complementary MOS (CMOS) image sensor of a voltage domain system that converts signal charges into a voltage and holds the voltage has attracted attention. Such a sensor is hereinafter referred to as "VD.GS". For example, there has been proposed VD.GS in which conversion efficiency at the time of converting a charge into a voltage is switched in a plurality of stages, and a signal at each conversion efficiency is sampled by a sample and hold circuit (see, for example, PTL 1). In this image sensor, two conversion efficiency control transistors are interposed between a floating diffusion (FD) and an additional capacitor in a preceding stage of the sample and hold circuit. In addition, the overflow drain is interposed between the connection point of the additional capacitor and the conversion efficiency control transistor and the photoelectric conversion element, and the reset transistor is interposed between the connection point of the two conversion efficiency control transistors and the power supply voltage.

[0004] WO 2023 / 062947 ASummary

[0005] In the above-described technique in the related art, the dynamic range is expanded by switching the conversion efficiency. However, in the above-described image sensor, in a case where the illuminance is relatively high, there is a possibility that the charge overflowing from the photoelectric conversion element leaks to the FD during a period from when the charge is transferred to the floating diffusion layer to when the signal is sampled by the sample and hold circuit. As a result, there is a problem that the signal level held in the FD changes and the image quality of the image data deteriorates.

[0006] The present technology has been made in view of such a situation, and it is desirable to improve image quality in an image sensor that simultaneously performs exposure in all pixels.

[0007] The present technology has been made to solve the above-described problems, and a first aspect thereof is an image sensor including a conversion efficiency control transistor that opens and closes a path between an FD and an additional capacitor, a discharge transistor that discharges a charge from a photoelectric conversion element, a reset transistor interposed between a power supply voltage and the discharge transistor described above, a transfer transistor that transfers a charge from the photoelectric conversion element to the FD, an FD link gate transistor that opens and closes a path between a connection point of the additional capacitor and the conversion efficiency control transistor and a connection point of the reset transistor and the discharge transistor, and a plurality of capacitive elements that holds a level corresponding to a voltage of the FD. This brings about an effect that leakage of charges to the FD is prevented.

[0008] In addition, in the first aspect, the level may include a reset level when the FD is initialized and a signal level when the charge is transferred to the FD, the reset level may include a first reset level when the conversion efficiency control transistor is in an OFF state and a second reset level when the conversion efficiency control transistor is in an ON state, the signal level may include a first signal level when the conversion efficiency control transistor is in an OFF state and a second signal level when the conversion efficiency control transistor is in an ON state, the plurality of capacitive elements may include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, and a fourth capacitive element that holds the second signal level. This brings about an effect that the conversion efficiency of converting the charge into the voltage is switched in two stages.

[0009] In addition, in the first aspect, the conversion efficiency control transistor may include a first conversion efficiency control transistor and a second conversion efficiency control transistor connected in series, the level may include a reset level when the FD is initialized and a signal level when the charge is transferred to the FD, the reset level may include a first reset level when both the first conversion efficiency control transistor and the second conversion efficiency control transistor are in an OFF state, a second reset level when only one of the first conversion efficiency control transistor and the second conversion efficiency control transistor is in an ON state, and a third reset level when both the first conversion efficiency control transistor and the second conversion efficiency control transistor are in an ON state, the signal level may include a first signal level when both the first conversion efficiency control transistor and the second conversion efficiency control transistor are in an OFF state, a second signal level when only one of the first conversion efficiency control transistor and the second conversion efficiency control transistor is in an ON state, and a third signal level when both the first conversion efficiency control transistor and the second conversion efficiency control transistor are in an ON state, and the plurality of capacitive elements may include a first capacitive element that holds the first reset level, a second capacitive element that holds the first signal level, a third capacitive element that holds the second reset level, a fourth capacitive element that holds the second signal level, a fifth capacitive element that holds the third reset level, and a sixth capacitive element that holds the third signal level. This brings about an effect that the conversion efficiency is switched in three stages.

[0010] In addition, in the first aspect, the image sensor may further include a pre-stage amplification transistor that outputs the level to a pre-stage node to which one end of each of the plurality of capacitive elements is commonly connected, and a selection circuit that connects the other end of any of the plurality of capacitive elements to a predetermined post-stage node. This brings about an effect that the signal is sampled and held.

[0011] In addition, in the first aspect, the image sensor may further include a pre-stage amplification transistor that outputs the level to a predetermined node, and a selection circuit that connects one end of any of the plurality of capacitive elements to the node, in which the other end of each of the plurality of capacitive elements may be grounded. This brings about an effect that the signal is sampled and held.

[0012] In addition, in the first aspect, the image sensor may further include a vertical scanning circuit, in which the vertical scanning circuit may turn off the FD link gate transistor and may turn on the reset transistor and the discharge transistor immediately after turning on the transfer transistor and transferring the charge. This brings about an effect that charges due to blooming can be released via the reset transistor and the discharge transistor.

[0013] In addition, in the first aspect, the conversion efficiency control transistor, the reset transistor, the discharge transistor, the transfer transistor, and the FD link gate transistor may be arranged on a predetermined pixel chip, and the plurality of capacitive elements may be arranged on a predetermined circuit chip. This brings about an effect of facilitating miniaturization.

[0014] In addition, a second aspect of the present technology is a photodetection device including a conversion efficiency control transistor that opens and closes a path between an FD and an additional capacitor, a discharge transistor that discharges a charge from a photoelectric conversion element, a reset transistor interposed between a power supply voltage and the discharge transistor, a transfer transistor that transfers a charge from the photoelectric conversion element to the FD, an FD link gate transistor that opens and closes a path between a connection point of the additional capacitor and the conversion efficiency control transistor and a connection point of the reset transistor and the discharge transistor, a plurality of capacitive elements that holds a level corresponding to a voltage of the FD, and a signal processing circuit that processes a signal at the level. This brings about an effect that leakage of charges to the FD is prevented, and the image quality of the image data is improved.

[0015] Image quality of image data can be improved.

[0016] Fig. 1 is a block diagram depicting a configuration example of an imaging device according to the first embodiment of the present technology.Fig. 2 is a block diagram illustrating a configuration example of an image sensor according to the first embodiment of the present technology.Fig. 3 is a circuit diagram depicting a configuration example of a pixel according to the first embodiment of the present technology.Fig. 4 is a block diagram illustrating an example configuration of a load MOS circuit block and a column signal processing circuit according to the first embodiment of the present technology.Fig. 5 is a timing chart depicting an example of a global shutter operation according to the first embodiment of the present technology.Fig. 6 is a timing chart depicting an example of a read operation according to the first embodiment of the present technology.Fig. 7 is a circuit diagram depicting a configuration example of a pixel in a comparative example.Fig. 8 is a flowchart illustrating an example of the operation of the image sensor according to the first embodiment of the present technology.Fig. 9 is a circuit diagram depicting a configuration example of a pixel according to the second embodiment of the present technology.Fig. 10 is a timing chart depicting an example of a global shutter operation according to the second embodiment of the present technology.Fig. 11 is a timing chart depicting an example of a read operation according to the second embodiment of the present technology.Fig. 12 is a circuit diagram depicting a configuration example of a pixel according to the third embodiment of the present technology.Fig. 13 is a block diagram showing an example of a schematic configuration of a vehicle control system.Fig. 14 is an illustrative view illustrating an example of an installation position of an outside-vehicle information detecting section and an imaging section. [Description of Embodiments]

[0017] A mode for carrying out the present technology (hereinafter, referred to as an embodiment) is hereinafter described. The description will be given in the following order. 1. First embodiment (example of changing connection destination of reset transistor and adding FD link gate transistor) 2. Second embodiment (example of changing connection destination of reset transistor and adding FD link gate transistor to switch conversion efficiency in three stages) 3. Third Embodiment (example of changing the connection destination of the reset transistor and adding the FD link gate transistor to change the circuit configuration of the sample and hold circuit) 4. Example of Application to Mobile Object

[0018] <1. First Embodiment> (Configuration example of imaging device) Fig. 1 is a block diagram depicting a configuration example of an imaging device 100 according to the first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an imaging lens 110, an image sensor 200, a recording unit 120, and an imaging control section 130. As the imaging device 100, a digital camera, or an electronic device (a smartphone, a personal computer, or the like) having an imaging function is assumed.

[0019] The image sensor 200 captures image data under the control of the imaging control section 130. The image sensor 200 supplies the image data to the recording unit 120 via a signal line 209. The image sensor 200 can be provided in a photodetection device such as a sensing element or a light receiving element in addition to the imaging device 100. Note that the imaging device 100 is an example of a photodetection device recited in claims.

[0020] The imaging lens 110 condenses light and guides the light to the image sensor 200. The imaging control section 130 controls the image sensor 200 to capture image data. The imaging control section 130 supplies, for example, an imaging control signal including a vertical synchronization signal VSYNC to the image sensor 200 via a signal line 139. The recording unit 120 records the image data.

[0021] Here, the vertical synchronization signal VSYNC is a signal indicating imaging timing, and a periodic signal of a constant frequency (such as 60 hertz) is used as the vertical synchronization signal VSYNC.

[0022] Note that although the imaging device 100 records the image data, the image data may be transmitted to the outside of the imaging device 100. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display section is further provided.

[0023] (Configuration example of image sensor) Fig. 2 is a block diagram illustrating a configuration example of the image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a vertical scanning circuit 211, a pixel array unit 220, a timing control circuit 212, a digital to analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array unit 220, a plurality of the pixels 300 is arranged in a two-dimensional grid pattern.

[0024] Hereinafter, a set of pixels 300 arranged in a horizontal direction is referred to as a "row", and a set of pixels 300 arranged in a direction perpendicular to the row is referred to as a "column".

[0025] The timing control circuit 212 controls operation timing of each of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control section 130.

[0026] The DAC 213 generates a sawtooth wave-like ramp signal by digital-to-analog (DA) conversion. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.

[0027] The vertical scanning circuit 211 sequentially selects and drives rows to output analog pixel signals. The pixel 300 photoelectrically converts incident light to generate the analog pixel signal. This pixel 300 supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0028] In the load MOS circuit block 250, metal-oxide-semiconductor (MOS) transistors for supplying a constant current are provided for each column.

[0029] The column signal processing circuit 260 performs a signal process such as an analog to digital (AD) conversion processing and a correlated double sampling (CDS) process on the pixel signal for each column. The column signal processing circuit 260 supplies the image data including the processed signals to the recording unit 120.

[0030] (Configuration example of pixel) Fig. 3 is a circuit diagram depicting a configuration example of the pixel 300 according to the first embodiment of the present technology. The pixel 300 includes a pre-stage circuit 310, a switching transistor 329, capacitive elements 321, 322, 323, and 324, a selection circuit 330, a post-stage reset transistor 341, and a post-stage circuit 350. Note that, for example, n-channel MOS (nMOS) transistors are used as various transistors in the pixel 300.

[0031] The pre-stage circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a reset transistor 313, an FD 314, a pre-stage amplification transistor 315, a current source transistor 316, and a discharge transistor 317. Further, the pre-stage circuit 310 includes a conversion efficiency control transistor 361, an FD link gate transistor 363, and an additional capacitor 365.

[0032] The photoelectric conversion element 311 generates charges by the photoelectric conversion. The transfer transistor 312 transfers the charges from the photoelectric conversion element 311 to the FD 314 in accordance with a transfer signal TRG from the vertical scanning circuit 211.

[0033] The reset transistor 313 is turned on and off in accordance with a reset signal RST from the vertical scanning circuit 211, and extracts a charge from the FD 314 and initializes the FD. The FD 314 accumulates charges, and generates a voltage corresponding to a charge amount. In addition, the reset transistor 313 is interposed between a power supply voltage VDD and the discharge transistor 317.

[0034] The pre-stage amplification transistor 315 constitutes a source follower circuit to output a signal at a level corresponding to the voltage of the FD 314 to a pre-stage node 320.

[0035] The source of the pre-stage amplification transistor 315 is connected to the power supply voltage VDD. The current source transistor 316 is connected to a drain of the pre-stage amplification transistor 315. The current source transistor 316 supplies a current id1 under the control of the vertical scanning circuit 211.

[0036] The discharge transistor 317 is turned on and off in accordance with a discharge signal OFG from the vertical scanning circuit 211, and functions as an overflow drain for discharging charges from the photoelectric conversion element 311.

[0037] The conversion efficiency control transistor 361 is turned on and off in accordance with a control signal FCG from the vertical scanning circuit 211 to open and close a path between the FD 314 and the additional capacitor 365.

[0038] The FD link gate transistor 363 opens and closes a path between a connection point of the additional capacitor 365 and the conversion efficiency control transistor 361 and a connection point of the reset transistor 313 and the discharge transistor 317. The FD link gate transistor 363 is turned on and off in accordance with a control signal FLG from the vertical scanning circuit 211.

[0039] The switching transistor 329 short-circuits between the source and the drain of the pre-stage amplification transistor 315 in accordance with a switching signal SW from the vertical scanning circuit 211.

[0040] One end of each of the capacitive elements 321, 322, 323, and 324 is commonly connected to the pre-stage node 320, and the other end thereof is connected to the selection circuit 330.

[0041] The selection circuit 330 connects the other end of any of the capacitive elements 321, 322, 323, and 324 to a post-stage node 340. The selection circuit 330 includes selection transistors 331, 332, 333, and 334. The selection transistor 331 opens and closes a path between the capacitive element 321 and the post-stage node 340 in accordance with a selection signal S1 from the vertical scanning circuit 211. The selection transistor 332 opens and closes a path between the capacitive element 322 and the post-stage node 340 in accordance with a selection signal S2 from the vertical scanning circuit 211.

[0042] The selection transistor 333 opens and closes a path between the capacitive element 323 and the post-stage node 340 in accordance with a selection signal S3 from the vertical scanning circuit 211. The selection transistor 334 opens and closes a path between the capacitive element 324 and the post-stage node 340 in accordance with a selection signal S4 from the vertical scanning circuit 211.

[0043] Note that the capacitive elements 321, 322, 323, and 324 are examples of a first, second, third, and fourth capacitive element described in the claims.

[0044] The post-stage reset transistor 341 initializes the level of the post-stage node 340 in accordance with a post-stage reset signal RB from the vertical scanning circuit 211.

[0045] The post-stage circuit 350 includes a post-stage amplification transistor 351 and a selection transistor 352. The post-stage amplification transistor 351 constitutes a source follower circuit to output a signal at a level corresponding to the level of the post-stage node 340. The selection transistor 352 outputs a signal from the post-stage amplification transistor 351 to a vertical signal line 309 as a pixel signal in accordance with a selection signal SEL from the vertical scanning circuit 211. A load MOS transistor 251 to be described later is connected to the vertical signal line 309.

[0046] In addition, circuits and elements in the image sensor 200 are dispersedly arranged on a pixel chip 201 and a circuit chip 202 that are stacked. For example, the circuit at the preceding stage of the pre-stage amplification transistor 315 and the switching transistor 329 are arranged in the pixel chip 201. In addition, the current source transistor 316 and the circuits after the pre-stage node 320 are arranged in the circuit chip 202. Note that the circuits and elements arranged in the pixel chip 201 and the circuit chip 202 are not limited to those illustrated in the drawing. In addition, circuits and elements in the image sensor 200 can be arranged on a single semiconductor chip. In addition, the circuits and elements in the image sensor 200 can be dispersedly arranged on three or more semiconductor substrates.

[0047] The vertical scanning circuit 211 initializes the FDs 314 and the photoelectric conversion elements 311 of all the pixels at the start of exposure, and controls the transfer transistors 312 of all the pixels at the end of exposure to transfer signal charges from the photoelectric conversion elements 311 to the FDs 314. The exposure control of simultaneously starting and ending the exposure for all the pixels in this manner is referred to as a global shutter method.

[0048] The level of the FD 314 when the FD 314 is initialized and a level (holding level of capacitive element and level of vertical signal line 309) corresponding to the level are collectively referred to as a "P phase" or a "reset level" below.

[0049] In addition, the level of the FD 314 at the time of signal charge transfer and a level (holding level of capacitive element and level of vertical signal line 309) corresponding to the level are collectively referred to as a "D phase" or a "signal level" below.

[0050] In addition, the conversion efficiency in a case where the conversion efficiency control transistor 361 is in the OFF state is higher than the conversion efficiency in a case where the conversion efficiency control transistor 361 is in the ON state. Hereinafter, the higher conversion efficiency is referred to as a "high conversion gain (HCG)", and the lower conversion efficiency is referred to as a "low conversion gain (LCG)". At the end of the exposure by the global shutter method, the pre-stage circuit 310 converts the charge into a voltage by each of the HCG and the LCG and sequentially outputs the voltage to the pre-stage node 320. Since the voltage of the reset level or the signal level is generated, four of the reset level and the signal level generated by the HCG and the reset level and the signal level generated by the LCG are sequentially output.

[0051] When the reset level corresponding to the HCG is output, only the selection transistor 331 shifts to the ON state in the selection circuit 330, and the reset level is held in the capacitive element 321. When the signal level corresponding to the HCG is output, only the selection transistor 332 transitions to the ON state in the selection circuit 330, and the signal level is held in the capacitive element 322. In this manner, the voltage corresponding to the HCG is held in the capacitive elements 321 and 322.

[0052] In addition, when the reset level corresponding to the LCG is output, only the selection transistor 333 shifts to the ON state in the selection circuit 330, and the reset level is held in the capacitive element 323. When the signal level corresponding to LCG is output, only the selection transistor 334 shifts to the ON state in the selection circuit 330, and the signal level is held in the capacitive element 324. In this manner, the voltage corresponding to the LCG is held in the capacitive elements 323 and 324.

[0053] Here, it is assumed that the capacitance values of the capacitive elements 321 and 322 corresponding to the HCG are the same. In addition, the capacitance values of the capacitive elements 323 and 324 corresponding to the LCG are also assumed to be the same. In addition, the total capacitance value of the capacitive elements 321 and 322 corresponding to the HCG is larger than the total capacitance value of the capacitive elements 323 and 324 corresponding to the LCG. Optical shot noise is more dominant in a case where the LCG is set than in a case where the HCG is set, and kTC noise generated at the time of sample hold does not greatly contribute to image quality. On the other hand, when the HCG is set, the adverse effect due to the kTC noise is relatively large. In addition, normally, in a case where a signal is sampled in a capacitive element, as the capacitance value is increased, kTC noise at the time of sampling can be reduced. Therefore, by relatively increasing the capacitance value of the capacitive element corresponding to the HCG more influenced by the kTC noise, the kTC noise can be suppressed, and the image quality can be improved.

[0054] The post-stage circuit 350 sequentially reads a level (reset level and signal level) corresponding to the HCG and a level corresponding to the LCG via the post-stage node 340 after the exposure is completed.

[0055] The column signal processing circuit 260 at the subsequent stage performs CDS processing of obtaining a difference between the reset level corresponding to the HCG and the signal level corresponding to the HCG, and generates a digital signal corresponding to the HCG. In addition, the column signal processing circuit 260 performs CDS processing of obtaining a difference between the reset level corresponding to the LCG and the signal level corresponding to the LCG, and generates a digital signal corresponding to the LCG.

[0056] In addition, the column signal processing circuit 260 determines whether or not the illuminance is higher than a predetermined value in units of frames or in units of pixels. Then, the column signal processing circuit 260 outputs a digital signal corresponding to the LCG as a pixel signal of the pixel in a case where the illuminance is high, and outputs a digital signal corresponding to the HCG as a pixel signal in a case where the illuminance is low.

[0057] In a case where the conversion efficiency is switched in accordance with the illuminance in units of frames, it is possible to suppress an insufficient saturation charge amount and insufficient sensitivity. This can lead to an improvement in image quality. In addition, in a case where the conversion efficiency is switched according to the illuminance in units of pixels, the dynamic range can be expanded. In addition, since it is not necessary to capture two frames with different conversion efficiency for each frame, a decrease in the frame rate can be suppressed. As a result, when the conversion efficiency is switched in units of pixels, it is possible to improve the image quality while suppressing a decrease in the frame rate.

[0058] In addition, as described above, at the end of exposure, the vertical scanning circuit 211 controls the transfer transistor 312 to transfer signal charges, but in a case where the illuminance is relatively high, charges overflowing from the photoelectric conversion element 311 may leak through the discharge transistor 317. This phenomenon is referred to as blooming. The period from the time of transfer of the signal charge to when the signal level is sampled is relatively long in VD.GS, from a few microseconds to a few hundred microseconds. In a case where the charge generated by blooming leaks to the FD 314 within this period, the signal level changes and is destroyed, and as a result, there is a possibility that the image quality of the image data is deteriorated.

[0059] Therefore, immediately after the charge transfer, the vertical scanning circuit 211 changes the FD link gate transistor 363 from the ON state to the OFF state, and changes the reset transistor 313 and the discharge transistor 317 from the OFF state to the ON state. With this control, the charge generated by blooming can be released to the power supply side via the discharge transistor 317 and the reset transistor 313 in the ON state. A thick dotted line in the figure indicates a path through which the charge is released. In addition, at this time, since the FD link gate transistor 363 is in an OFF state, the charge does not leak to the FD 314. Therefore, it is possible to prevent contamination between the signal charge transferred by the transfer transistor 312 and the charge leaked due to blooming. As a result, image quality of image data can be improved.

[0060] (Configuration example of column signal processing circuit) Fig. 4 is a block diagram depicting a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0061] In the load MOS circuit block 250, the vertical signal line 309 is wired for each column. In a case where the number of columns is I (I is an integer), I vertical signal lines 309 are wired. In addition, a load MOS transistor 251 that supplies a constant current id2 is connected to each of the vertical signal lines 309.

[0062] In the column signal processing circuit 260, a plurality of analog to digital converters (ADCs) 261 and a digital signal processing unit 262 are arranged. The ADC 261 is arranged for each column. In a case where the number of columns is I, I ADCs 261 are arranged.

[0063] The ADC 261 converts an analog pixel signal from the corresponding column into a digital signal using a ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing unit 262. For example, a single-slope ADC including a comparator and a counter is arranged as the ADC 261.

[0064] The digital signal processing unit 262 performs a predetermined signal process such as a CDS process on the digital signal for each column. The digital signal processing unit 262 supplies image data including the processed digital signals to the recording unit 120.

[0065] (Operation example of image sensor) Fig. 5 is a timing chart depicting an example of a global shutter operation according to the first embodiment of the present technology. TRG_[1: N] and the like in the drawing indicate signals of the first row to the N-th row. N is an integer indicating the total number of rows.

[0066] The control signal FLG is controlled to a high level before the exposure is started. The vertical scanning circuit 211 supplies the transfer signals TRG, the reset signals RST, the control signal FCG, and the discharge signal OFG in high-level to all rows (in other words, all pixels) over the pulse period from the timing T0 immediately before the start of exposure. As a result, all the pixels are initialized, and exposure is simultaneously started in all the pixels.

[0067] Then, the vertical scanning circuit 211 sets the post-stage reset signal RB of all the rows to the high level at the timing T1 immediately before the end of the exposure. Furthermore, the vertical scanning circuit 211 supplies the high-level control signal FCG to all the rows over the pulse period from the timing T1.

[0068] Furthermore, the vertical scanning circuit 211 causes the current source transistors 316 of all rows (all pixels) to supply the current id1 after the timing T1. The larger the current id1, the larger IR drop is, so that it may be required that the current id1 be on the order of several nanoamperes (nA) to several tens of nanoamperes (nA). On the other hand, the load MOS transistors 251 of all the columns are in the OFF state, and the current id2 is not supplied to the vertical signal line 309.

[0069] Then, the vertical scanning circuit 211 supplies the high-level selection signal S1 to all the rows over the pulse period from the timing T2. At this time, since the conversion efficiency control transistor 361 is in an OFF state, the P-phase level (reset level) generated by the HCG is maintained. Note that this reset level is an example of a first reset level described in the claims.

[0070] Then, the vertical scanning circuit 211 supplies the high-level transfer signal TRG to all the rows over the pulse period from the timing T3 at the end of the exposure. As a result, the signal charges are transferred to the FD 314 in all the pixels, and the exposure of all the pixels ends. Here, each pixel may be required to sequentially sample two signal levels, that is, a signal level generated by the HCG and a signal level generated by the LCG. However, as illustrated in the drawing, it is assumed that there is only one transfer pulse, and the potential in the pixel is adjusted so that the charge of the photoelectric conversion element 311 can be transferred only by this one time transfer.

[0071] The vertical scanning circuit 211 sets the control signal FLG of all the rows to the low level at the timing T4 immediately after the timing T3, and sets the reset signal RST and the discharge signal OFG of all the rows to the high level at the timing T5 immediately after that. As a result, the FD link gate transistor 363 is turned off, and the reset transistor 313 and the discharge transistor 317 are turned on. With this control, the charge generated by blooming are released to the power supply side via the discharge transistor 317 and the reset transistor 313, and leakage of the charges to the FD 314 can be prevented.

[0072] Then, the vertical scanning circuit 211 supplies the high-level selection signal S2 to all the rows over the pulse period from the timing T6. At this time, since the conversion efficiency control transistor 361 is in an OFF state, the D-phase level (signal level) generated by the HCG is maintained. Note that this reset level is an example of a first signal level described in the claims.

[0073] Then, the vertical scanning circuit 211 sets the control signals FCG of all the rows to the high level at the timing T7, and supplies the high-level selection signal S4 to all the rows over the pulse period from the timing T8 immediately after that. At this time, since the conversion efficiency control transistor 361 is in an ON state, the signal level generated by the LCG is maintained. Note that this signal level is an example of a second signal level described in the claims.

[0074] Then, the vertical scanning circuit 211 supplies the high-level control signal FLG to all the rows over the pulse period from the timing T9. As a result, the FD 314 is initialized in all rows.

[0075] Then, the vertical scanning circuit 211 supplies the high-level selection signal S3 to all the rows over the pulse period from the timing T10. At this time, since the conversion efficiency control transistor 361 is in an ON state, the reset level generated by the LCG is maintained. Note that this reset level is an example of a second reset level described in the claims.

[0076] Then, the vertical scanning circuit 211 sets the reset signal RST and the control signal FCG of all the rows to the low level and sets the switching signal SW of all the rows to the high level at the timing T11.

[0077] In addition, the vertical scanning circuit 211 stops the supply of the current id1 in all the pixels and starts the supply of the current id2 in all the columns at the timing T11.

[0078] Fig. 6 is a timing chart depicting an example of a read operation according to the first embodiment of the present technology. In the read period of the n-th (n is an integer from 1 to N) row from the timing T20 to the timing T28, the vertical scanning circuit 211 sets the selection signal SEL of the n-th row to the high level. SEL_[n] and the like in the drawing indicate signals to pixels in the n-th row.

[0079] Over the pulse period from the timing T20, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row. As a result, in a case where a parasitic capacitance exists in the post-stage node 340, the history of the previous signal held in the parasitic capacitance can be erased.

[0080] Over the pulse period from the timing T21, the vertical scanning circuit 211 supplies the high-level selection signal S1 to the n-th row. Then, the P-phase level (reset level) generated by the HCG is read.

[0081] Over the pulse period from the timing T22, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T23, the vertical scanning circuit 211 supplies the high-level selection signal S2 to the n-th row. Then, the D-phase level (signal level) generated by the HCG is read.

[0082] Over the pulse period from the timing T24, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T25, the vertical scanning circuit 211 supplies the high-level selection signal S3 to the n-th row. Then, the reset level generated by the LCG is read.

[0083] Over the pulse period from the timing T26, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T27, the vertical scanning circuit 211 supplies the high-level selection signal S4 to the n-th row. Then, the signal level generated by the LCG is read.

[0084] In addition, during the read period, the vertical scanning circuit 211 sets the switching signals SW of all the rows to the high level, stops the current id1 of all the pixels, and supplies the current id2 of all the columns.

[0085] Note that the order of reading is not limited to that illustrated in the drawing.

[0086] Here, a configuration in which the FD link gate transistor 363 is not provided and the connection destination of the reset transistor 313 is different is assumed as a comparative example.

[0087] Fig. 7 is a circuit diagram depicting a configuration example of the pixel 300 in a comparative example. As illustrated in the drawing, the FD link gate transistor 363 is not arranged in the pixel 300, and the discharge transistor 317 is interposed between the additional capacitor 365 and the photoelectric conversion element 311. In addition, the reset transistor 313 is interposed between the connection point of the conversion efficiency control transistor 361 and the FD 314 and the power supply voltage VDD. As a method of driving the pixel 300 of this comparative example, for example, a method described in Fig. 46 of PTL 1 can be used. In the drawing, the control signal FDG may be replaced with the control signal FCG.

[0088] Returning to Fig. 7, in the comparative example, it is assumed that blooming occurs within a period from when signal charges are transferred to when the conversion efficiency control transistor 361 is turned on and a signal level corresponding to the LCG is sampled. In the circuit configuration of the comparative example, there is a possibility that charges generated by blooming leak to the FD 314 via the discharge transistor 317 and the conversion efficiency control transistor 361. A thick dotted line in the drawing indicates a path through which charges leak due to blooming.

[0089] On the other hand, in the circuit configuration illustrated in Fig. 3, the reset transistor 313 is moved to the power supply side of the discharge transistor 317, and the FD link gate transistor 363 is added. As a result, as described above, the charge generated by blooming can be released to the power supply side via the discharge transistor 317 and the reset transistor 313 in the ON state. In addition, at this time, since the FD link gate transistor 363 is in an OFF state, the charge does not leak to the FD 314. Therefore, contamination can be prevented, and the image quality of the image data can be improved.

[0090] Fig. 8 is a flowchart illustrating an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, in a case where a predetermined application for capturing image data is executed.

[0091] The vertical scanning circuit 211 exposes all the pixels (step S901). Then, the vertical scanning circuit 211 selects a row to be read (step S902). The column signal processing circuit 260 sequentially reads the pixel signals (that is, the reset level and the signal level) corresponding to the LCG of the row (step S903). Next, the column signal processing circuit 260 sequentially reads the pixel signals (reset level and signal level) corresponding to the HCG (step S904).

[0092] The image sensor 200 determines whether or not reading of all rows has been completed (step S905). In a case where the reading of all the rows has not been completed (step S905: No), the image sensor 200 repeats step S902 and the subsequent steps. On the other hand, in a case where the reading of all the rows has been completed (step S905: Yes), the image sensor 200 executes CDS processing or the like, and ends the operation for imaging. In a case where a plurality of pieces of image data is continuously captured, steps S901 to S905 are repeatedly executed in synchronization with the vertical synchronization signal.

[0093] As described above, in the first embodiment of the present technology, the reset transistor 313 is interposed between the power supply voltage and the discharge transistor 317 in the pixel 300, and the FD link gate transistor 363 is added. As a result, the charge generated by blooming are released to the power supply side via the discharge transistor 317 and the reset transistor 313, and leakage of charges to the FD 314 can be prevented, and image quality of image data can be improved.

[0094] <2. Second embodiment> The image sensor 200 switches the conversion efficiency in two stages in the first embodiment described above, but can switch the conversion efficiency in three stages. The second embodiment is different from the first embodiment in that the image sensor 200 switches conversion efficiency in three stages.

[0095] Fig. 9 is a circuit diagram depicting a configuration example of the pixel 300 according to the second embodiment of the present technology. The second embodiment is different from the first embodiment in that the pixel 300 further including a conversion efficiency control transistor 362, capacitive elements 325 and 326, and selection transistors 335 and 336.

[0096] The conversion efficiency control transistor 362 is interposed between the conversion efficiency control transistor 361 and the FD 314, and is turned on and off according to the control signal FDG from the vertical scanning circuit 211. As the conversion efficiency control transistor 362, for example, an nMOS transistor is used.

[0097] One end of each of the capacitive elements 325 and 326 is commonly connected to the pre-stage node 320. The selection transistor 335 opens and closes a path between the capacitive element 325 and the post-stage node 340 in accordance with a selection signal S5 from the vertical scanning circuit 211. The selection transistor 336 opens and closes a path between the capacitive element 326 and the post-stage node 340 in accordance with a selection signal S6 from the vertical scanning circuit 211. As the selection transistors 335 and 336, for example, nMOS transistors are used.

[0098] Conversion efficiency in a case where only the conversion efficiency control transistor 362 of the conversion efficiency control transistors 361 and 362 is in the ON state is lower than that in a case where both the conversion efficiency control transistors 361 and 362 are in the OFF state. In addition, conversion efficiency in a case where both the conversion efficiency control transistors 361 and 362 are in the ON state is lower than that in a case where only the conversion efficiency control transistor 362 is in the ON state. As described above, the conversion efficiency is controlled in three levels. Among the three levels, the highest conversion efficiency is referred to as HCG, and the lowest conversion efficiency is referred to as LCG. In addition, the conversion efficiency between the HCG and the LCG is referred to as a "middle conversion gain (MCG)". Switching the conversion efficiency in three levels allows control for more appropriate conversion efficiency as compared with a case where of the conversion efficiency is switched in two levels.

[0099] The capacitance values of the capacitive elements 321 and 322 corresponding to the HCG are larger than the capacitance values of the capacitive elements corresponding to the MCG and the LCG. In addition, the capacitance values of the capacitive elements 323 and 324 corresponding to the MCG are the same as those of the capacitive elements 325 and 326 corresponding to the LCG. Note that the capacitive elements 325 and 326 are examples of a fifth and sixth capacitive element described in the claims.

[0100] Note that although the conversion efficiency has three levels, the conversion efficiency may have four or more levels. In the case of four or more stages, a conversion efficiency control transistor, a capacitive element, and a selection transistor is only required to be added according to the number of stages.

[0101] Fig. 10 is a timing chart depicting an example of a global shutter operation according to the second embodiment of the present technology.

[0102] The control signal FLG is controlled to a high level before the exposure is started. The vertical scanning circuit 211 supplies the transfer signal TRG, the reset signal RST, the control signal FCG, the control signal FDG, and the discharge signal OFG in high-level to all rows (all pixels) over the pulse period from the timing T0 immediately before the start of exposure. As a result, all the pixels are initialized, and exposure is simultaneously started in all the pixels.

[0103] Then, the vertical scanning circuit 211 sets the post-stage reset signal RB and the control signal FDG of all the rows to the high level at the timing T1 immediately before the end of the exposure. Furthermore, the vertical scanning circuit 211 supplies the high-level control signal FCG to all the rows over the pulse period from the timing T1.

[0104] Furthermore, the vertical scanning circuit 211 causes the current source transistors 316 of all rows (all pixels) to supply the current id1 after the timing T1. On the other hand, the load MOS transistors 251 of all the columns are in the OFF state, and the current id2 is not supplied to the vertical signal line 309.

[0105] Then, the vertical scanning circuit 211 supplies the high-level selection signal S3 to all the rows over the pulse period from the timing T2. At this time, since only the conversion efficiency control transistor 362 is in an ON state, the P-phase level (reset level) generated by the MCG is maintained. Note that this reset level is an example of a second reset level described in the claims.

[0106] Then, the vertical scanning circuit 211 sets the control signals FDG of all the rows to the low level at the timing T3, and supplies the high-level selection signal S1 to all the rows over the pulse period from the timing T4. At this time, since both the conversion efficiency control transistors 361 and 362 are in an OFF state, the reset level generated by the HCG is maintained.

[0107] Then, the vertical scanning circuit 211 supplies the high-level transfer signal TRG to all the rows over the pulse period from the timing T5 at the end of the exposure. As a result, the signal charges are transferred to the FD 314 in all the pixels, and the exposure of all the pixels ends.

[0108] The vertical scanning circuit 211 sets the control signal FLG of all the rows to the low level at the timing T6 immediately after the timing T5, and sets the reset signal RST and the discharge signal OFG of all the rows to the high level at the timing T7 immediately after that.

[0109] Then, the vertical scanning circuit 211 supplies the high-level selection signal S2 to all the rows over the pulse period from the timing T8. At this time, since both the conversion efficiency control transistors 361 and 362 are in an OFF state, the D-phase level (signal level) generated by the HCG is maintained.

[0110] Then, the vertical scanning circuit 211 sets the control signals FDG of all the rows to the high level at the timing T9, and supplies the high-level selection signal S4 to all the rows over the pulse period from the timing T10 immediately after that. At this time, since only the conversion efficiency control transistor 362 is in an ON state, the signal level generated by the MCG is maintained. Note that this signal level is an example of a second signal level described in the claims.

[0111] Then, the vertical scanning circuit 211 sets the control signals FCG of all the rows to the high level at the timing T11, and supplies the high-level selection signal S6 to all the rows over the pulse period from the timing T12 immediately after that. At this time, since both the conversion efficiency control transistors 361 and 362 are in an ON state, the signal level generated by the LCG is maintained. Note that this signal level is an example of a third signal level described in the claims.

[0112] Then, the vertical scanning circuit 211 supplies the high-level control signal FLG to all the rows over the pulse period from the timing T13, and supplies the high-level selection signal S5 to all the rows over the pulse period from the timing T14. At this time, since both the conversion efficiency control transistors 361 and 362 are in an ON state, the reset level generated by the LCG is maintained. Note that this reset level is an example of a third reset level described in the claims.

[0113] Then, the vertical scanning circuit 211 sets the reset signal RST and the control signal FCG of all the rows to the low level and sets the switching signal SW of all the rows to the high level at the timing T15.

[0114] In addition, the vertical scanning circuit 211 stops the supply of the current id1 in all the pixels at the timing T15 and starts the supply of the current id2 in all the columns.

[0115] Fig. 11 is a timing chart illustrating an example of a read operation according to the first embodiment of the present technology. In the read period of the n-th row from the timing T20 to the timing T32, the vertical scanning circuit 211 sets the selection signal SEL of the n-th row to the high level.

[0116] Over the pulse period from the timing T20, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T21, the vertical scanning circuit 211 supplies the high-level selection signal S1 to the n-th row. Then, the P-phase level (reset level) generated by the HCG is read.

[0117] Over the pulse period from the timing T22, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T23, the vertical scanning circuit 211 supplies the high-level selection signal S2 to the n-th row. Then, the D-phase level (signal level) generated by the HCG is read.

[0118] Over the pulse period from the timing T24, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T25, the vertical scanning circuit 211 supplies the high-level selection signal S3 to the n-th row. Then, the reset level generated by the MCG is read.

[0119] Over the pulse period from the timing T26, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T27, the vertical scanning circuit 211 supplies the high-level selection signal S4 to the n-th row. Then, the signal level generated by the MCG is read.

[0120] Over the pulse period from the timing T28, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T29, the vertical scanning circuit 211 supplies the high-level selection signal S5 to the n-th row. Then, the reset level generated by the LCG is read.

[0121] Over the pulse period from the timing T30, the vertical scanning circuit 211 supplies the high-level post-stage reset signal RB to the n-th row, and over the pulse period from the timing T31, the vertical scanning circuit 211 supplies the high-level selection signal S6 to the n-th row. Then, the signal level generated by the LCG is read.

[0122] In addition, during the read period, the vertical scanning circuit 211 sets the switching signals SW of all the rows to the high level, stops the current id1 of all the pixels, and supplies the current id2 of all the columns.

[0123] Note that the order of reading is not limited to that illustrated in the drawing.

[0124] As described above, according to the second embodiment of the present technology, since the conversion efficiency control transistor 362, the capacitive elements 325 and 326, and the selection transistors 335 and 336 are added, the conversion efficiency can be switched in three stages.

[0125] <3. Third embodiment> In the second embodiment described above, one end of each of the six capacitive elements is connected to the pre-stage node 320, and any of the other ends is connected to the post-stage node 340 by the selection circuit 330, but the circuit that samples and holds the signal is not limited to this circuit configuration. The image sensor 200 in the third embodiment is different from that in the second embodiment in that circuit configurations of the capacitive element and the selection circuit 330 are different.

[0126] Fig. 12 is a circuit diagram depicting a configuration example of the pixel 300 according to the third embodiment of the present technology. In the third embodiment, the selection circuit 330 connects one end of any of the capacitive elements 321, 322, 323, 324, 325, and 326 to the pre-stage node 320. In addition, the other ends of the capacitive elements 321, 322, 323, 324, 325, and 326 are grounded. Further, the post-stage reset transistor 341 is interposed between the pre-stage node 320 and the power supply voltage VDD.

[0127] In the selection circuit 330, the selection transistor 331 opens and closes a path between the capacitive element 321 and the pre-stage node 320 according to the selection signal S1. The selection transistor 332 opens and closes a path between the capacitive element 322 and the pre-stage node 320 according to the selection signal S2. The selection transistor 333 opens and closes a path between the capacitive element 323 and the pre-stage node 320 according to the selection signal S3, and the selection transistor 334 opens and closes a path between the capacitive element 324 and the pre-stage node 320 according to the selection signal S4. The selection transistor 335 opens and closes a path between the capacitive element 325 and the pre-stage node 320 according to the selection signal S5, and the selection transistor 336 opens and closes a path between the capacitive element 326 and the pre-stage node 320 according to the selection signal S6.

[0128] Furthermore, a method of driving the pixel 300 in the third embodiment is similar to that in the second embodiment.

[0129] Note that although the conversion efficiency has three levels, the conversion efficiency may have four or more levels. In the case of four or more stages, a conversion efficiency control transistor, a capacitive element, and a selection transistor is only required to be added according to the number of stages. In addition, the conversion efficiency can be in two stages. In the case of two stages, the conversion efficiency control transistor 362, the capacitive elements 325 and 326, and the selection transistors 335 and 336 are deleted.

[0130] As described above, according to the third embodiment of the present technology, the reset level and the signal level corresponding to each of the multi-stage conversion efficiencies can be held by the circuit in which the selection circuit 330 connects any of the six capacitive elements to the pre-stage node 320 and the other end thereof is grounded.

[0131] <4. Example of Application to Mobile Object> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure may be achieved in the form of a device to be mounted on a mobile object of any kind, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, or a robot.

[0132] Fig. 13 is a block diagram illustrating a schematic configuration example of a vehicle control system being an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0133] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 13, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0134] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0135] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0136] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0137] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0138] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0139] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0140] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0141] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0142] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 13, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0143] Fig. 14 is a diagram illustrating an example of an installation position of the imaging section 12031.

[0144] In Fig. 14, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0145] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0146] Note that Fig. 14 illustrates an example of imaging ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0147] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0148] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0149] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0150] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0151] An example of the vehicle control system to which the technology according to the present disclosure can be applied is described above. The technology according to the present disclosure can be applied to, for example, the imaging section 12031 among the constituents described above. Specifically, for example, the imaging device 100 in Fig. 1 can be applied to the imaging section 12031. By applying the technology of the present disclosure to the imaging section 12031, a more easily viewable captured image can be obtained, by which fatigue of the driver can be reduced. Note that the embodiments described above show examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present disclosure in the claims have correspondence relationships. Similarly, the matters specifying the present disclosure in the claims and matters with the same names in the embodiments of the present technology have correspondence relationships. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the scope of the present technology.

[0152] Note that advantageous effects described in the present description are merely examples and are not limited, and other advantageous effects may be provided.

[0153] Note that the present technology may also have the following configurations. (1)　　A light detecting device comprising: a transfer transistor, a first end of the transfer transistor is connected to a floating diffusion, and a second end of the transfer transistor is connected to a first node; a discharge transistor, a first end of the discharge transistor is connected to the first node and a second end of the discharge transistor is connected to a second node; a reset transistor, a first end of the reset transistor is connected to the second node, and a second end of the reset transistor is connected to a power supply; a floating diffusion link gate transistor, a first end of the floating diffusion link gate transistor is connected to the second node; a plurality of capacitive elements each connected to a third node to receive and store a signal proportional to a voltage of the floating diffusion; and 　　a selection circuit connected to the plurality of capacitive elements to output, to a readout node, the signal stored by selected ones of the plurality of capacitive elements. (2)　　The light detecting device of (1), wherein control of the floating diffusion link gate transistor to an OFF state and control of the reset transistor to an ON state causes blooming charges accumulated in the first node to be released to the power supply via the discharge transistor. (3)　　The light detecting device of (1), further comprising: a photoelectric conversion element connected to the first node, at an exposure end time, the transfer transistor is pulsed to an ON state to transfer charges from the photoelectric conversion element to the floating diffusion. (4)　　The light detecting device of (2), wherein 　　after transferring the charges with the transfer transistor, the floating diffusion link gate transistor is controlled to an OFF state, and the discharge transistor and the reset transistor are controlled to an ON state to cause the blooming charges accumulated in the first node to be released to the power supply. (5)　　The light detecting device of (3), further comprising: an amplification transistor connected to the third node to output, to the plurality of capacitive elements, the signal proportional to the voltage of the floating diffusion. (6)　　The light detecting device of (3), further comprising: a conversion gain switching transistor, a first end of the conversion gain switching transistor is connected to the floating diffusion, and a second end of the conversion gain switching transistor is connected to the second end of the floating diffusion link gate transistor,　　wherein, control of the conversion gain switching transistor to an OFF state causes the charges to be converted to a voltage at a first conversion efficiency, and control of the conversion gain switching transistor to an ON state causes the charges to be converted at second conversion efficiency that is lower than the first conversion efficiency. (7)　　The light detecting device of (6), wherein, prior to an exposure start time, the floating diffusion link gate transistor is controlled to an ON state, and the reset transistor, the discharge transistor, and the conversion gain switching transistor are pulsed to a ON state to initialize the floating diffusion. (8)　　The light detecting device of (6), wherein 　　the plurality of capacitive elements include four capacitive elements and the selection circuit includes four selection switches such that, for each exposure, the plurality of capacitive elements store a P-phase signal associated with the first conversion efficiency, a P-phase signal associated with the second conversion efficiency, a D-phase signal associated with the first conversion efficiency, and a D-phase signal associate with the second conversion efficiency. (9)　　The light detecting device of (8), wherein the conversion gain switching transistor is a first conversion gain switching transistor, and the light detecting device further comprises: a second conversion gain switching transistor, a first end of the second conversion gain switching transistor is connected to the floating diffusion, and a second end of the second conversion gain switching transistor is connected to the second end of the floating diffusion link gate transistor via the first conversion gain switching transistor, wherein, control of the first conversion gain switching transistor to an OFF state and the second conversion gain switching transistor to an ON state causes the charges to be converted to a voltage at a third conversion efficiency that is lower than the first conversion efficiency and higher than the third conversion efficiency. (10)　　The light detecting device of (9), wherein the plurality of capacitive elements include six capacitive elements and the selection circuit includes six selection switches such that, for each exposure, the plurality of capacitive elements further store a P-phase signal associated with the third conversion efficiency and a D-phase signal associate with the third conversion efficiency. (11)　　The light detecting device of (1), wherein a first end of each of the plurality of capacitive elements is connected to the third node, and a second end of each of the plurality of capacitive elements is connected to a respective selection switch of the selection circuit. (12)　　The light detecting device of (1), wherein a first end of each of the plurality of capacitive elements is connected to the third node and to the readout node via a respective selection switch of the selection circuit, and 　　a second end of each of the plurality of capacitive elements is connected to a ground node. (13)　　The light detecting device of (1), wherein the transfer transistor, the discharge transistor, the reset transistor, and the floating diffusion link gate transistor are arranged on a first substrate, and the plurality of capacitive elements and the selection circuit are arranged on a second substrate different from the first substrate. (14)　　A light detecting device comprising: a first transistor having a first end connected to a floating diffusion and a second end connected to a first node; a second transistor having a first end connected to the first node and a second end connected to a second node; a third transistor having a first end of the third transistor is connected to the second node and a second end connected to a power supply; a fourth transistor having a first end connected to the second node; a plurality of capacitive elements each connected to a third node to receive and store a signal proportional to a voltage of the floating diffusion; and a selection circuit connected to the plurality of capacitive elements to output, to a readout node, the signal stored by selected ones of the plurality of capacitive elements. wherein deactivation of the fourth transistor and activation of the third transistor causes blooming charges accumulated in the first node to be released to the power supply via the second transistor. (15)　　The light detecting device of (14), further comprising: a photoelectric conversion element connected to the first node, at an exposure end time, the first transistor is activated for a pulse duration to transfer charges from the photoelectric conversion element to the floating diffusion. (16)　　The light detecting device of (15), wherein 　　after transferring the charges with the first transistor, the fourth transistor is deactivated, and the second transistor and the third transistor are activated to cause the blooming charges accumulated in the first node to be released to the power supply. (17)　　The light detecting device of (15), further comprising: a fifth transistor connected to the third node to output, to the plurality of capacitive elements, the signal proportional to the voltage of the floating diffusion. (18)　　The light detecting device of (15), further comprising: a sixth transistor having a first end connected to the floating diffusion and a second end connected to the second end of the fourth transistor, wherein, deactivation of the sixth transistor causes the charges to be converted to a voltage at a first conversion efficiency, and activation of the sixth transistor causes the charges to be converted at second conversion efficiency that is lower than the first conversion efficiency. (19)　　The light detecting device of (18), wherein, prior to an exposure start time, the fourth transistor is activated, and the third transistor, the second transistor, and the sixth transistor are activated for a pulse duration to initialize the floating diffusion. (20)　　The light detecting device of (18), wherein the plurality of capacitive elements include four capacitive elements and the selection circuit includes four selection switches such that, for each exposure, the plurality of capacitive elements store a P-phase signal associated with the first conversion efficiency, a P-phase signal associated with the second conversion efficiency, a D-phase signal associated with the first conversion efficiency, and a D-phase signal associate with the second conversion efficiency. (21)　　The light detecting device of (20), further comprising: a seventh transistor, a first end of the seventh transistor is connected to the floating diffusion, and a second end of the seventh transistor is connected to the second end of the fourth transistor via the sixth transistor, wherein, deactivation of the sixth transistor and activation of the seventh transistor causes the charges to be converted to a voltage at a third conversion efficiency that is lower than the first conversion efficiency and higher than the third conversion efficiency.

[0154] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

[0155] 100　　Imaging device 110　　Imaging lens 120　　Storage unit 130　　Imaging control section 200　　Image sensor 201　　Pixel chip 202　　Circuit chip 211　　Vertical scanning circuit 212　　Timing control circuit 213　　DAC 220　　Pixel array unit 250　　Load MOS circuit block 251　　Load MOS transistor 260　　Column signal processing circuit 261　　ADC 262　　Digital signal processing unit 300　　Pixel 310　　Pre-stage circuit 311　　Photoelectric conversion element 312　　Transfer transistor 313　　Reset transistor 314　　FD 315　　Pre-stage amplification transistor 316　　Current source transistor 317　　Discharge transistor 320　　Pre-stage node 321, 322, 323, 324, 325, 326　　Capacitive element 329　　Switching transistor 330　　Selection circuit 331, 332, 333, 334, 335, 336　　Selection transistor 340　　Post-stage node 341　　Post-stage reset transistor 350　　Post-stage circuit 351　　Post-stage amplification transistor 352　　Selection transistor 361, 362　　Conversion efficiency control transistor 363　　FD link gate transistor 365　　Additional capacitor 12031　　Imaging section

Claims

1. A light detecting device comprising: 　　a transfer transistor, a first end of the transfer transistor is connected to a floating diffusion, and a second end of the transfer transistor is connected to a first node; 　　a discharge transistor, a first end of the discharge transistor is connected to the first node and a second end of the discharge transistor is connected to a second node; 　　a reset transistor, a first end of the reset transistor is connected to the second node, and a second end of the reset transistor is connected to a power supply; 　　a floating diffusion link gate transistor, a first end of the floating diffusion link gate transistor is connected to the second node; 　　a plurality of capacitive elements each connected to a third node to receive and store a signal proportional to a voltage of the floating diffusion; and 　　a selection circuit connected to the plurality of capacitive elements to output, to a readout node, the signal stored by selected ones of the plurality of capacitive elements.

2. The light detecting device of claim 1, wherein control of the floating diffusion link gate transistor to an OFF state and control of the reset transistor to an ON state causes blooming charges accumulated in the first node to be released to the power supply via the discharge transistor.

3. The light detecting device of claim 1, further comprising: 　　a photoelectric conversion element connected to the first node, 　　at an exposure end time, the transfer transistor is pulsed to an ON state to transfer charges from the photoelectric conversion element to the floating diffusion.

4. The light detecting device of claim 3, wherein 　　after transferring the charges with the transfer transistor, the floating diffusion link gate transistor is controlled to an OFF state, and the discharge transistor and the reset transistor are controlled to an ON state to cause the blooming charges accumulated in the first node to be released to the power supply.

5. The light detecting device of claim 3, further comprising: 　　an amplification transistor connected to the third node to output, to the plurality of capacitive elements, the signal proportional to the voltage of the floating diffusion.

6. The light detecting device of claim 3, further comprising: 　　a conversion gain switching transistor, a first end of the conversion gain switching transistor is connected to the floating diffusion, and a second end of the conversion gain switching transistor is connected to the second end of the floating diffusion link gate transistor, 　　wherein, control of the conversion gain switching transistor to an OFF state causes the charges to be converted to a voltage at a first conversion efficiency, and control of the conversion gain switching transistor to an ON state causes the charges to be converted at second conversion efficiency that is lower than the first conversion efficiency.

7. The light detecting device of claim 6, wherein, prior to an exposure start time, the floating diffusion link gate transistor is controlled to an ON state, and the reset transistor, the discharge transistor, and the conversion gain switching transistor are pulsed to a ON state to initialize the floating diffusion.

8. The light detecting device of claim 6, wherein 　　the plurality of capacitive elements include four capacitive elements and the selection circuit includes four selection switches such that, for each exposure, the plurality of capacitive elements store a P-phase signal associated with the first conversion efficiency, a P-phase signal associated with the second conversion efficiency, a D-phase signal associated with the first conversion efficiency, and a D-phase signal associate with the second conversion efficiency.

9. The light detecting device of claim 8, wherein the conversion gain switching transistor is a first conversion gain switching transistor, and the light detecting device further comprises: 　　a second conversion gain switching transistor, a first end of the second conversion gain switching transistor is connected to the floating diffusion, and a second end of the second conversion gain switching transistor is connected to the second end of the floating diffusion link gate transistor via the first conversion gain switching transistor, 　　wherein, control of the first conversion gain switching transistor to an OFF state and the second conversion gain switching transistor to an ON state causes the charges to be converted to a voltage at a third conversion efficiency that is lower than the first conversion efficiency and higher than the third conversion efficiency.

10. The light detecting device of claim 9, wherein 　　the plurality of capacitive elements include six capacitive elements and the selection circuit includes six selection switches such that, for each exposure, the plurality of capacitive elements further store a P-phase signal associated with the third conversion efficiency and a D-phase signal associate with the third conversion efficiency.

11. The light detecting device of claim 1, wherein 　　a first end of each of the plurality of capacitive elements is connected to the third node, and 　　a second end of each of the plurality of capacitive elements is connected to a respective selection switch of the selection circuit.

12. The light detecting device of claim 1, wherein 　　a first end of each of the plurality of capacitive elements is connected to the third node and to the readout node via a respective selection switch of the selection circuit, and 　　a second end of each of the plurality of capacitive elements is connected to a ground node.

13. The light detecting device of claim 1, wherein 　　the transfer transistor, the discharge transistor, the reset transistor, and the floating diffusion link gate transistor are arranged on a first substrate, and 　　the plurality of capacitive elements and the selection circuit are arranged on a second substrate different from the first substrate.

14. A light detecting device comprising: 　　a first transistor having a first end connected to a floating diffusion and a second end connected to a first node; 　　a second transistor having a first end connected to the first node and a second end connected to a second node; 　　a third transistor having a first end of the third transistor is connected to the second node and a second end connected to a power supply; 　　a fourth transistor having a first end connected to the second node; 　　a plurality of capacitive elements each connected to a third node to receive and store a signal proportional to a voltage of the floating diffusion; and 　　a selection circuit connected to the plurality of capacitive elements to output, to a readout node, the signal stored by selected ones of the plurality of capacitive elements. 　　wherein deactivation of the fourth transistor and activation of the third transistor causes blooming charges accumulated in the first node to be released to the power supply via the second transistor.

15. The light detecting device of claim 14, further comprising: 　　a photoelectric conversion element connected to the first node, 　　at an exposure end time, the first transistor is activated for a pulse duration to transfer charges from the photoelectric conversion element to the floating diffusion.

16. The light detecting device of claim 15, wherein 　　after transferring the charges with the first transistor, the fourth transistor is deactivated, and the second transistor and the third transistor are activated to cause the blooming charges accumulated in the first node to be released to the power supply.

17. The light detecting device of claim 15, further comprising: 　　a fifth transistor connected to the third node to output, to the plurality of capacitive elements, the signal proportional to the voltage of the floating diffusion.

18. The light detecting device of claim 15, further comprising: 　　a sixth transistor having a first end connected to the floating diffusion and a second end connected to the second end of the fourth transistor, 　　wherein, deactivation of the sixth transistor causes the charges to be converted to a voltage at a first conversion efficiency, and activation of the sixth transistor causes the charges to be converted at second conversion efficiency that is lower than the first conversion efficiency.

19. The light detecting device of claim 18, wherein, prior to an exposure start time, the fourth transistor is activated, and 　　the third transistor, the second transistor, and the sixth transistor are activated for a pulse duration to initialize the floating diffusion.

20. The light detecting device of claim 18, wherein 　　the plurality of capacitive elements include four capacitive elements and the selection circuit includes four selection switches such that, for each exposure, the plurality of capacitive elements store a P-phase signal associated with the first conversion efficiency, a P-phase signal associated with the second conversion efficiency, a D-phase signal associated with the first conversion efficiency, and a D-phase signal associate with the second conversion efficiency.

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