Switching element drive circuit and power conversion device

Abstract

The present invention addresses the problem of suppressing a decrease in the voltage of a capacitor of a bootstrap circuit. A switching element drive circuit (2) comprises an auxiliary circuit (5) that is connected to a plurality of third bootstrap circuits (73). The auxiliary circuit (5) includes: a fifth switching element (Q5); a fifth gate driver (65); a fourth bootstrap circuit (75); a plurality of first auxiliary diodes (D7); and a plurality of second auxiliary diodes (D8). The fifth switching element (Q5) has a first main terminal, a second main terminal, and a gate terminal. The first main terminal is connected to an intermediate potential point (M1). The fifth gate driver (65) is connected to the gate terminal and second main terminal of the fifth switching element (Q5) and drives the fifth switching element (Q5). The fourth bootstrap circuit (75) includes a fourth capacitor (C5) and a diode (D9).

Description

Switching element drive circuit and power conversion device

[0001] The present disclosure relates to a switching element drive circuit and a power conversion device, and more particularly to a switching element drive circuit that drives four switching elements of a diode-clamped three-level inverter, and a power conversion device including the switching element drive circuit.

[0002] Patent Document 1 discloses a three-phase multilevel power converter as a power conversion device, which includes three diode-clamped multilevel power conversion circuits (diode-clamped three-level inverters), three individual gate drive units, a shared power supply, and a signal output unit.

[0003] Each of the multiple diode-clamped multilevel power conversion circuits has four switches connected in series. Each of the multiple individual gate drive units is composed of four gate drivers connected to the four switches and four interface circuits. Patent Document 1 describes that a common power supply can be shared by three individual gate drive units. Patent Document 1 also discloses an example in which each of the four interface circuits is implemented by a bootstrap circuit. The bootstrap circuit uses a combination of a diode and a capacitor to charge a high-voltage side capacitor from the common power supply or a low-voltage side capacitor.

[0004] In the power conversion device disclosed in Patent Document 1, in a circuit (switching element drive circuit) that includes three individual gate drive units, a common power supply, and a signal output unit, there are periods during which the capacitor of the bootstrap circuit cannot be charged, and the voltage of the capacitor may become too low.

[0005] Japanese Patent Application Laid-Open No. 2009-177951

[0006] An object of the present disclosure is to provide a switching element drive circuit and a power conversion device that are capable of suppressing a voltage drop in a capacitor of a bootstrap circuit.

[0007] A switching element drive circuit according to one aspect of the present disclosure drives a plurality of diode-clamped three-level inverters. The plurality of diode-clamped three-level inverters include a plurality of first switching elements, a plurality of second switching elements, a plurality of third switching elements, a plurality of fourth switching elements, a plurality of first clamp diodes, and a plurality of second clamp diodes. The plurality of first switching elements are connected to the positive electrode of a DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point. The plurality of second switching elements are connected in series with the plurality of first switching elements, respectively. The plurality of third switching elements are connected in series with the plurality of second switching elements, respectively. The plurality of fourth switching elements are connected in series with the plurality of third switching elements, respectively, and to the negative electrode of the DC power supply unit. The plurality of first clamp diodes have cathodes connected to a plurality of first connection points between the plurality of first switching elements and the plurality of second switching elements, respectively, and anodes connected to the intermediate potential point. The second clamp diodes have anodes connected to second connection points between the third switching elements and the fourth switching elements, respectively, and cathodes connected to the intermediate potential point. The switching element drive circuit includes first gate drivers, second gate drivers, third gate drivers, fourth gate drivers, first bootstrap circuits, second bootstrap circuits, third bootstrap circuits, a DC voltage source, a control device, and an auxiliary circuit. The first gate drivers drive the first switching elements, respectively. The second gate drivers drive the second switching elements, respectively. The third gate drivers drive the third switching elements, respectively. The fourth gate drivers drive the fourth switching elements, respectively. The first bootstrap circuits correspond one-to-one to the first gate drivers. Each of the first bootstrap circuits includes a first capacitor connected in parallel to a corresponding first gate driver.The second bootstrap circuits correspond one-to-one to the second gate drivers. Each of the second bootstrap circuits includes a second capacitor connected in parallel to a corresponding second gate driver. The third bootstrap circuits correspond one-to-one to the third gate drivers. Each of the third bootstrap circuits includes a third capacitor connected in parallel to a corresponding third gate driver. The DC voltage source is connected in parallel to the fourth gate drivers. The control device outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to the first gate drivers, the second gate drivers, the third gate drivers, and the fourth gate drivers, respectively. The auxiliary circuit is connected to the third bootstrap circuits. The auxiliary circuit includes a fifth switching element, a fifth gate driver, a fourth bootstrap circuit, a plurality of first auxiliary diodes, and a plurality of second auxiliary diodes. The fifth switching element has a first main terminal, a second main terminal, and a gate terminal, and the first main terminal is connected to the intermediate potential point. The fifth gate driver is connected to the gate terminal and the second main terminal of the fifth switching element and drives the fifth switching element. The fourth bootstrap circuit includes a fourth capacitor and a diode. The fourth capacitor is connected in parallel to the fifth gate driver. The diode has a cathode connected to the high potential end of the fourth capacitor and an anode connected to the positive terminal of the DC voltage source. The plurality of first auxiliary diodes have cathodes connected to the high potential ends of the third capacitors of the plurality of third bootstrap circuits and anodes connected to the high potential end of the fourth capacitor. The plurality of second auxiliary diodes have cathodes connected to the low potential ends of the third capacitors of the plurality of third bootstrap circuits and anodes connected to the low potential end of the fourth capacitor.

[0008] A power conversion device according to one aspect of the present disclosure includes the switching element drive circuit according to the above aspect and the plurality of diode-clamped three-level inverters.

[0009] FIG. 1 is a circuit diagram of a power conversion device including a switching element drive circuit according to a first embodiment. FIG. 2 is an explanatory diagram of a current path when a switching circuit in the power conversion device is in a first switching state. FIG. 3 is an explanatory diagram of a switching circuit in the power conversion device when in the first switching state. FIG. 4 is an explanatory diagram of a current path when a switching circuit in the power conversion device is in a second switching state. FIG. 5 is an explanatory diagram of a charging path when a switching circuit in the power conversion device is in the second switching state. FIG. 6 is an explanatory diagram of a current path when a switching circuit in the power conversion device is in a third switching state. FIG. 7 is an explanatory diagram of a charging path when a switching circuit in the power conversion device is in the third switching state. FIG. 8 is an explanatory diagram of voltage command values ​​for each phase in the power conversion device. FIG. 9 is an explanatory diagram of a group of voltage vectors related to the power conversion device. FIG. 10 is a more detailed explanatory diagram of a group of voltage vectors related to the power conversion device. FIG. 11 is a vector diagram for explaining the operation of a control device in the power conversion device. FIG. 12 is a time chart of the switching states of each phase of the power conversion device of the same. FIG. 13 is a time chart of the on / off states of the first to fourth switching elements of the power conversion device of the same. FIG. 14 is a waveform diagram of the output current of the power conversion device of the same. FIG. 15 is an operational waveform diagram of the power conversion device of the same. FIG. 16 is an explanatory diagram of a charging path when a fifth switching element in an auxiliary circuit of a switching element drive circuit in the same power conversion device is off. FIG. 17 is an explanatory diagram of a charging path when a fifth switching element in an auxiliary circuit of a switching element drive circuit in the same power conversion device is on. FIG. 18 is an explanatory diagram of the operation of the power conversion device of the same. FIG. 19 is a circuit diagram of a power conversion device including a switching element drive circuit according to a second embodiment. FIG. 20 is an operational waveform diagram of the switching element drive circuit of the same. FIG. 21 is a circuit diagram of a power conversion device including a switching element drive circuit according to a third embodiment. FIG. 22 is an operational waveform diagram of the switching element drive circuit of the same. FIG. 23 is an explanatory diagram of the operation of a switching element drive circuit according to a fourth embodiment.

[0010] First Embodiment A power conversion device 100 including a switching element drive circuit according to a first embodiment will be described below with reference to FIGS. 1 to 18. FIG.

[0011] (1) Configuration of the Switching Element Drive Circuit and the Power Conversion Device The switching element drive circuit 2 according to the first embodiment is a circuit that drives a plurality of (three in the example of FIG. 1 ) diode-clamped three-level inverters 1 (hereinafter also referred to as inverter circuits 1).

[0012] The multiple (three in the example of FIG. 1 ) inverter circuits 1 include multiple (three in the example of FIG. 1 ) first switching elements Q1, multiple (three in the example of FIG. 1 ) second switching elements Q2, multiple (three in the example of FIG. 1 ) third switching elements Q3, multiple (three in the example of FIG. 1 ) fourth switching elements Q4, multiple (three in the example of FIG. 1 ) first clamp diodes D5, and multiple (three in the example of FIG. 1 ) second clamp diodes D6. The multiple first switching elements Q1 are connected to a positive electrode P1 of a DC power supply unit 3 having a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. The multiple second switching elements Q2 are connected in series to the multiple first switching elements Q1, respectively. The multiple third switching elements Q3 are connected in series to the multiple second switching elements Q2, respectively. The plurality of fourth switching elements Q4 are respectively connected in series to the plurality of third switching elements Q3 and connected to the negative electrode N1 of the DC power supply unit 3. The plurality of first clamp diodes D5 have cathodes connected to the plurality of first connection points 11 between the plurality of first switching elements Q1 and the plurality of second switching elements Q2 and have anodes connected to the intermediate potential point M1. The plurality of second clamp diodes D6 have anodes connected to the plurality of second connection points 12 between the plurality of third switching elements Q3 and the plurality of fourth switching elements Q4 and have cathodes connected to the intermediate potential point M1.

[0013] The switching element drive circuit 2 includes a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, a plurality of first bootstrap circuits 71, a plurality of second bootstrap circuits 72, a plurality of third bootstrap circuits 73, a DC voltage source 6, a control device 4, and an auxiliary circuit 5.

[0014] The plurality of first gate drivers 61 respectively drive the plurality of first switching elements Q1. The plurality of second gate drivers 62 respectively drive the plurality of second switching elements Q2. The plurality of third gate drivers 63 respectively drive the plurality of third switching elements Q3. The plurality of fourth gate drivers 64 respectively drive the plurality of fourth switching elements Q4.

[0015] The plurality of first bootstrap circuits 71 correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first bootstrap circuits 71 includes a first capacitor C1 connected in parallel to the corresponding first gate driver 61. The plurality of second bootstrap circuits 72 correspond one-to-one to the plurality of second gate drivers 62. Each of the plurality of second bootstrap circuits 72 includes a second capacitor C2 connected in parallel to the corresponding second gate driver 62. The plurality of third bootstrap circuits 73 correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third bootstrap circuits 73 includes a third capacitor C3 connected in parallel to the corresponding third gate driver 63.

[0016] The DC voltage source 6 is connected in parallel to a plurality of fourth gate drivers 64 .

[0017] The control device 4 outputs a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3 and a plurality of fourth control signals S4 to be given to a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64, respectively.

[0018] The auxiliary circuit 5 includes a fifth switching element Q5, a fifth gate driver 65, a fourth bootstrap circuit 75, a plurality of first auxiliary diodes D7, and a plurality of second auxiliary diodes D8. The fifth switching element Q5 has a first main terminal, a second main terminal, and a gate terminal, with the first main terminal connected to the intermediate potential point M1. The fifth gate driver 65 is connected to the gate terminal and the second main terminal of the fifth switching element Q5 and drives the fifth switching element Q5. The fourth bootstrap circuit 75 includes a fourth capacitor C5 and a diode D9. The fourth capacitor C5 is connected in parallel with the fifth gate driver 65. The diode D9 has a cathode connected to the high-potential end of the fourth capacitor C5 and an anode connected to the positive terminal of the DC voltage source 6. The cathodes of the first auxiliary diodes D7 are connected to the high potential ends of the third capacitors C3 of the third bootstrap circuits 73, and the anodes of the second auxiliary diodes D8 are connected to the low potential ends of the third capacitors C3 of the third bootstrap circuits 73, and the anodes of the second auxiliary diodes D8 are connected to the low potential ends of the fourth capacitor C5.

[0019] The power conversion device 100 according to the first embodiment includes a switching element drive circuit 2 and a plurality of (three in FIG. 1 ) diode-clamped three-level inverters 1 .

[0020] (2) Details of the Switching Element Drive Circuit and the Power Conversion Device As shown in Fig. 1 , the power conversion device 100 includes, for example, a DC power supply unit 3, a plurality of (three in the example of Fig. 1 ) inverter circuits 1, and a switching element drive circuit 2. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3.

[0021] The DC power supply unit 3 includes a fifth capacitor C31 and a sixth capacitor C32. The fifth capacitor C31 and the sixth capacitor C32 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 (see FIG. 2 ) connected to the positive electrode P1 and a second DC terminal 32 (see FIG. 2 ) connected to the negative electrode N1. In the DC power supply unit 3, a first end of the fifth capacitor C31 is connected to the first DC terminal 31, a second end of the fifth capacitor C31 is connected to a first end of the sixth capacitor C32, and a second end of the sixth capacitor C32 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the fifth capacitor C31 and the sixth capacitor C32 is an intermediate potential point M1. For example, an external power supply that outputs a DC output voltage is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage of the external power supply is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the sixth capacitor C32 is the same as the capacitance of the fifth capacitor C31. The phrase "the capacitance of the sixth capacitor C32 is the same as the capacitance of the fifth capacitor C31" does not necessarily mean that the capacitance of the sixth capacitor C32 exactly matches the capacitance of the fifth capacitor C31, but may mean that the capacitance of the sixth capacitor C32 is within a range of 90% to 110% of the capacitance of the fifth capacitor C31.

[0022] The power conversion device 100 is a diode-clamped three-level three-phase inverter. In the power conversion device 100, each of a plurality of inverter circuits 1 has an output terminal 8. In the power conversion device 100, AC loads are connected to a plurality of (three in the example of FIG. 1 ) output terminals 8.

[0023] The AC load is, for example, a three-phase servo motor. In the power conversion device 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage. For convenience of explanation, hereinafter, of the multiple output terminals 8, the output terminal 8 included in the inverter circuit 1U will be referred to as the output terminal 8U, the output terminal 8 included in the inverter circuit 1V will be referred to as the output terminal 8V, and the output terminal 8 included in the inverter circuit 1W will be referred to as the output terminal 8W.

[0024] Each of the inverter circuits 1 includes a switching circuit 10 (see FIG. 2), a first clamp diode D5, and a second clamp diode D6. In the power conversion device 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.

[0025] Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive electrode P1 side to the negative electrode N1 side of the DC power supply unit 3 in the order of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4.

[0026] Each switching circuit 10 further includes four diodes D1 to D4. Diode D1 is connected in anti-parallel to the first switching element Q1. Diode D2 is connected in anti-parallel to the second switching element Q2. Diode D3 is connected in anti-parallel to the third switching element Q3. Diode D4 is connected in anti-parallel to the fourth switching element Q4. A first clamp diode D5 is connected between a first connection point 11 between the first switching element Q1 and the second switching element Q2 and an intermediate potential point M1. A second clamp diode D6 is connected between a second connection point 12 between the third switching element Q3 and the fourth switching element Q4 and the intermediate potential point M1.

[0027] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, insulated gate bipolar transistors (IGBTs). Therefore, the control terminal, the first main terminal, and the second main terminal of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, respectively, a gate terminal, a collector terminal, and an emitter terminal.

[0028] A control terminal of the first switching element Q1 of each switching circuit 10 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0029] In each switching circuit 10, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of the DC power supply 3, and a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2. In each switching circuit 10, a second main terminal of the second switching element Q2 is connected to a first main terminal of a third switching element Q3. In each switching circuit 10, a second main terminal of the third switching element Q3 is connected to a first main terminal of a fourth switching element Q4, and a second main terminal of the fourth switching element Q4 is connected to a negative electrode N1 of the DC power supply 3.

[0030] In the inverter circuit 1U, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10 is connected to the output terminal 8U. In the inverter circuit 1V, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10 is connected to the output terminal 8V. In the inverter circuit 1W, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10 is connected to the output terminal 8W. For example, a U-phase terminal of an AC load is connected to the third connection point 13 of the inverter circuit 1U via the output terminal 8U. For example, a V-phase terminal of an AC load is connected to the third connection point 13 of the inverter circuit 1V via the output terminal 8V. For example, a W-phase terminal of an AC load is connected to the third connection point 13 of the inverter circuit 1W via the output terminal 8W.

[0031] In each switching circuit 10, the anode of diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In each switching circuit 10, the anode of diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In each switching circuit 10, the anode of diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. In each switching circuit 10, the anode of the diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0032] In each switching circuit 10, the diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In each switching circuit 10, the diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In each switching circuit 10, the diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In each switching circuit 10, the diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0033] In each inverter circuit 1, the cathode of the first clamp diode D5 is connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the first clamp diode D5 is connected to an intermediate potential point M1 of the DC power supply unit 3. In the first embodiment, when the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc and the potential of the negative electrode N1 is 0 V. In the first embodiment, the intermediate potential point M1 is not connected to ground, but it may be connected to ground. When the intermediate potential point M1 is connected to ground, the potential of the intermediate potential point M1 is 0 V. In this case, when the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2 and the potential of the negative electrode N1 is −Vdc / 2.

[0034] The cathode of the second clamp diode D6 is connected to the intermediate potential point M1, and the anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0035] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element Q1. The plurality of first gate drivers 61 are connected to a control device 4. The control device 4 outputs a plurality of first control signals S1 that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0036] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of a corresponding second switching element Q2. Each of the second gate drivers 62 drives a corresponding second switching element Q2. The second gate drivers 62 are connected to a control device 4. The control device 4 outputs second control signals S2 that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0037] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding third switching element Q3. Each of the plurality of third gate drivers 63 drives a corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control device 4. The control device 4 outputs a plurality of third control signals S3 corresponding one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0038] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding fourth switching element Q4. Each of the plurality of fourth gate drivers 64 drives a corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to a control device 4. The control device 4 outputs a plurality of fourth control signals S4 that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0039] Each of the multiple first bootstrap circuits 71 supplies a voltage to a corresponding first gate driver 61 of the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 has a first diode D11 in addition to a first capacitor C1. Each of the multiple second bootstrap circuits 72 supplies a voltage to a corresponding second gate driver 62 of the multiple second gate drivers 62. Each of the multiple second bootstrap circuits 72 has a second diode D12 in addition to a second capacitor C2. Each of the multiple third bootstrap circuits 73 supplies a voltage to a corresponding third gate driver 63 of the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 has a third diode D13 in addition to a third capacitor C3.

[0040] In each first bootstrap circuit 71, the anode of the first diode D11 is connected to the positive terminal of the DC voltage source 6 via the second diode D12 and the third diode D13. In each first bootstrap circuit 71, the cathode of the first diode D11 is connected to the high potential end (first end) of the first capacitor C1. The high potential end of the first capacitor C1 is connected to the high potential side power supply terminal 61H (see FIG. 3 ) of the first gate driver 61. The low potential end (second end) of the first capacitor C1 is connected to the low potential side power supply terminal 61L (see FIG. 3 ) of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with a voltage (a voltage greater than the threshold voltage of the first switching element Q1) required to turn on the first switching element Q1 in the first gate driver 61.

[0041] Each of the multiple second bootstrap circuits 72 supplies a voltage to a corresponding one of the multiple second gate drivers 62. In each second bootstrap circuit 72, the anode of the second diode D12 is connected to the positive terminal of the DC voltage source 6 via a third diode D13. In each second bootstrap circuit 72, the cathode of the second diode D12 is connected to the high-potential end (first end) of the second capacitor C2. The high-potential end of the second capacitor C2 is connected to a high-potential power supply terminal 62H (see FIG. 3 ) of the second gate driver 62. The low-potential end (second end) of the second capacitor C2 is connected to a low-potential power supply terminal 62L (see FIG. 3 ) of the second gate driver 62. The second bootstrap circuit 72 supplies the second gate driver 62 with a voltage (a voltage greater than the threshold voltage of the second switching element Q2) required to turn on the second switching element Q2 in the second gate driver 62.

[0042] Each of the multiple third bootstrap circuits 73 supplies a voltage to a corresponding one of the multiple third gate drivers 63. In each third bootstrap circuit 73, the anode of the third diode D13 is connected to the positive terminal of the DC voltage source 6. In each third bootstrap circuit 73, the cathode of the third diode D13 is connected to the high-potential end (first end) of the third capacitor C3. The high-potential end of the third capacitor C3 is connected to the high-potential power supply terminal 63H (see FIG. 3 ) of the third gate driver 63. The low-potential end (second end) of the third capacitor C3 is connected to the low-potential power supply terminal 63L (see FIG. 3 ) of the third gate driver 63. The third bootstrap circuit 73 supplies the third gate driver 63 with a voltage required to turn on the third switching element Q3 in the third gate driver 63 (a voltage greater than the threshold voltage of the third switching element Q3).

[0043] The DC voltage source 6 is, for example, a DC power supply including an isolated DC-DC converter 60. In this embodiment, the positive terminal of the DC voltage source 6 is connected to the high-potential power supply terminals 64H (see FIG. 3 ) of the plurality of fourth gate drivers 64. The positive terminal of the DC voltage source 6 is connected to the high-potential end of the third capacitor C3 via the third diode D13 for each of the plurality of third bootstrap circuits 73. The positive terminal of the DC voltage source 6 is connected to the high-potential end of the second capacitor C2 via the third diode D13 of the third bootstrap circuit 73 and the second diode D12 of the second bootstrap circuit 72 for each of the plurality of second bootstrap circuits 72. The positive terminal of the DC voltage source 6 is connected to the high-potential end of the first capacitor C1 via the third diode D13 of the third bootstrap circuit 73, the second diode D12 of the second bootstrap circuit 72, and the first diode D11 of the first bootstrap circuit 71 for each of the plurality of first bootstrap circuits 71. The negative terminal of the DC voltage source 6 is connected to the low potential power supply terminals 64L (see FIG. 3) of the plurality of fourth gate drivers 64. The negative terminal of the DC voltage source 6 is also connected to the negative electrode N1 of the DC power supply unit 3.

[0044] The control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control device 4 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control device 4 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control device 4 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0045] The control device 4 outputs a plurality (three) of first control signals S1 for controlling a plurality (three) of first switching elements Q1. The control device 4 also outputs a plurality (three) of second control signals S2 for controlling a plurality (three) of second switching elements Q2. The control device 4 also outputs a plurality (three) of third control signals S3 for controlling a plurality of third switching elements Q3. The control device 4 also outputs a plurality (three) of fourth control signals S4 for controlling a plurality (three) of fourth switching elements Q4. Note that FIG. 2 illustrates only one of the three inverter circuits 1 (see FIG. 1 ), and the remaining two inverter circuits 1 are not shown. 2 omits the illustration of the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, the plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the plurality of third bootstrap circuits 73, the DC voltage source 6, and the auxiliary circuit 5 shown in FIG. 1 . Also, in FIG. 3 , only one inverter circuit 1 of the three inverter circuits 1 (see FIG. 1 ) is shown, and the illustration of the remaining two inverter circuits 1 is omitted. Also, in FIG. 3 , the illustration of the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, the two second bootstrap circuits 72, the two third bootstrap circuits 73, and the auxiliary circuit 5 shown in FIG. 1 is omitted.

[0046] The three first control signals S1 include a first control signal US1 that controls the first switching element Q1 of the inverter circuit 1U, a first control signal VS1 that controls the first switching element Q1 of the inverter circuit 1V, and a first control signal WS1 that controls the first switching element Q1 of the inverter circuit 1W.

[0047] The three second control signals S2 include a second control signal US2 that controls the second switching element Q2 of the inverter circuit 1U, a second control signal VS2 that controls the second switching element Q2 of the inverter circuit 1V, and a second control signal WS2 that controls the second switching element Q2 of the inverter circuit 1W.

[0048] The three third control signals S3 include a third control signal US3 that controls the third switching element Q3 of the inverter circuit 1U, a third control signal VS3 that controls the third switching element Q3 of the inverter circuit 1V, and a third control signal WS3 that controls the third switching element Q3 of the inverter circuit 1W.

[0049] The three fourth control signals S4 include a fourth control signal US4 that controls the fourth switching element Q4 of the inverter circuit 1U, a fourth control signal VS4 that controls the fourth switching element Q4 of the inverter circuit 1V, and a fourth control signal WS4 that controls the fourth switching element Q4 of the inverter circuit 1W.

[0050] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3 and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.

[0051] The first potential level is, for example, 0 V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. That is, for each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off the switching element corresponding to that control signal, and the second potential level is a potential level for turning on the switching element corresponding to that control signal.

[0052] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0053] As described above, the auxiliary circuit 5 includes the fifth switching element Q5, the fifth gate driver 65, the fourth bootstrap circuit 75, the plurality of first auxiliary diodes D7, and the plurality of second auxiliary diodes D8. The auxiliary circuit 5 also includes a logical product element (AND element) 51.

[0054] The fifth switching element Q5 has a first main terminal, a second main terminal, and a gate terminal, and the first main terminal is connected to the intermediate potential point M1. The fifth switching element Q5 is, for example, an insulated gate bipolar transistor (IGBT). Therefore, the control terminal, the first main terminal, and the second main terminal of the fifth switching element Q5 are the gate terminal, the collector terminal, and the emitter terminal, respectively.

[0055] The fifth gate driver 65 has a high-potential side power supply terminal and a low-potential side power supply terminal, the high-potential side power supply terminal is connected to the gate terminal of the fifth switching element Q5, and the low-potential side output terminal is connected to the second main terminal of the fifth switching element Q5. The fifth gate driver 65 drives the fifth switching element Q5.

[0056] The fourth bootstrap circuit 75 includes a fourth capacitor C5 and a diode D9. The fourth capacitor C5 is connected in parallel to the fifth gate driver 65. The cathode of the diode D9 is connected to the high-potential end of the fourth capacitor C5 and the anode is connected to the positive terminal of the DC voltage source 6. The low-potential end of the fourth capacitor C5 is connected to the low-potential power supply terminal of the fifth gate driver 65 and the second main terminal of the fifth switching element Q5. The fourth capacitor C5 supplies the fifth gate driver 65 with a voltage (a voltage greater than the threshold voltage of the fifth switching element Q5) required to turn on the fifth switching element Q5 in the fifth gate driver 65.

[0057] The anodes of the first auxiliary diodes D7 are connected to the high potential end of the fourth capacitor C5, and the cathodes of the first auxiliary diodes D7 are connected to the high potential end of the third capacitor C3 of the third bootstrap circuits 73.

[0058] The second auxiliary diodes D8 have their anodes connected to the low potential end of the fourth capacitor C5, and their cathodes connected to the low potential ends of the third capacitors C3 of the third bootstrap circuits 73.

[0059] The AND element 51 has a plurality of input terminals (three in the example of FIG. 1 ) and one output terminal. The input terminals of the AND element 51 are connected to the control device 4. The output terminal of the AND element 51 is connected to the fifth gate driver 65. A plurality of second control signals S2 are input to the input terminals of the AND element 51 from the control device 4.

[0060] (3) Operation of the Power Conversion Device In the power conversion device 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the power conversion device 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Regarding the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0061] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the ON state and both the third switching element Q3 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the third connection point 13 becomes the potential level (e.g., Vdc) of the positive electrode P1 of the DC power supply unit 3.

[0062] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the OFF state and both the second switching element Q2 and the third switching element Q3 are in the ON state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 in the second switching state, the potential of the third connection point 13 becomes the potential level of the intermediate potential point M1 (e.g., Vdc / 2).

[0063] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the third connection point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., 0).

[0064] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in FIG. 2, a current I1 flows through the path of the positive electrode P1 of the DC power supply unit 3, the first switching element Q1, the second switching element Q2, the third connection point 13, and the output terminal 8, and the voltage value of the output voltage to the AC load becomes approximately Vdc.

[0065] Furthermore, when the inverter circuit 1 is in the first switching state, a voltage required for the first gate driver 61 to turn on the first switching element Q1 is supplied from the first capacitor C1 of the first bootstrap circuit 71 to the first gate driver 61. Therefore, as shown in FIG. 3 , the charge in the first capacitor C1 of the first bootstrap circuit 71 is discharged along a discharge path Ru1 that runs from the first capacitor C1 to the high-potential power supply terminal 61H of the first gate driver 61 to the low-potential power supply terminal 61L of the first gate driver 61 and back to the first capacitor C1. As a result, in the first bootstrap circuit 71, the voltage VC1 between the high-potential end and low-potential end of the first capacitor C1 decreases over time.

[0066] Furthermore, when the inverter circuit 1 is in the first switching state, the second capacitor C2 of the second bootstrap circuit 72 supplies to the second gate driver 62 a voltage required for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge in the second capacitor C2 of the second bootstrap circuit 72 is discharged via a discharge path Ru2 that runs from the second capacitor C2 to the high-potential power supply terminal 62H of the second gate driver 62 to the low-potential power supply terminal 62L of the second gate driver 62 and back to the second capacitor C2. As a result, in the second bootstrap circuit 72, the voltage VC2 between the high-potential end and low-potential end of the second capacitor C2 decreases over time.

[0067] 3 , if the voltage between the anode and cathode of the first diode D11 is Vd1 and the voltage between the first and second main terminals of the second switching element Q2 is Vf2, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the first capacitor C1 is charged by the second capacitor C2 if a first condition is met. The first condition is VC2>(VC1+Vd1+Vf2). A charging path Ru21 along which the first capacitor C1 is charged by the second capacitor C2 is the path from the second capacitor C2 to the first diode D11, the first capacitor C1, the first node 11, the second switching element Q2, and the second capacitor C2.

[0068] 4, for example, current I1 flows through a path (indicated by a thick solid arrow) of intermediate potential point M1 of DC power supply unit 3, first clamp diode D5, second switching element Q2, third connection point 13, and output terminal 8, and the voltage value of the output voltage to the AC load becomes approximately Vdc / 2. More specifically, when inverter circuits 1U, 1V, and 1W are in the second switching state, third switching state, and third switching state, respectively, current I1 flows through a path of intermediate potential point M1 of DC power supply unit 3, first clamp diode D5, second switching element Q2 of inverter circuit 1U, third connection point 13, and output terminal 8.

[0069] Furthermore, when the inverter circuit 1 is in the second switching state, for example, as shown in Fig. 4, a current I1 flows through a path (indicated by a thick dashed arrow) of the output terminal 8 - the third node 13 - the third switching element Q3 - the second node 12 - and the second clamp diode D6, and the voltage value of the output voltage to the AC load may be approximately Vdc / 2. More specifically, when the inverter circuits 1U, 1V, and 1W are in the second switching state, the second switching state, and the first switching state, respectively, a current I1 flows through a path (indicated by a thick dashed arrow) of the output terminal 8 of the inverter circuit 1U - the third node 13 - the third switching element Q3 - the second node 12 - and the second clamp diode D6, and the voltage value of the output voltage to the AC load may be approximately Vdc / 2.

[0070] Furthermore, when the inverter circuit 1 is in the second switching state, a voltage required to turn on the second switching element Q2 is supplied from the second capacitor C2 of the second bootstrap circuit 72 to the second gate driver 62 by the second gate driver 62. Therefore, the charge in the second capacitor C2 of the second bootstrap circuit 72 is discharged via a discharge path Ru2 that runs from the second capacitor C2 to the high-potential power supply terminal 62H of the second gate driver 62 to the low-potential power supply terminal 62L of the second gate driver 62 and back to the second capacitor C2, as shown in FIG. 5 . Furthermore, when the inverter circuit 1 is in the second switching state, a voltage required to turn on the third switching element Q3 is supplied from the third capacitor C3 of the third bootstrap circuit 73 to the third gate driver 63 by the third gate driver 63. Therefore, the charge in the third capacitor C3 of the third bootstrap circuit 73 is discharged via a discharge path Ru3 that runs from the third capacitor C3 to the high potential side power supply terminal 63H of the third gate driver 63 to the low potential side power supply terminal 63L of the third gate driver 63 to the third capacitor C3.

[0071] As shown in FIG. 5 , if the voltage between the first and second main terminals of the second switching element Q2 is Vf2, the voltage between the first and second main terminals of the third switching element Q3 is Vf3, and the voltage between the anode and cathode of the second diode D12 is Vd2, when the inverter circuit 1 is in the second switching state, the second capacitor C2 is charged by the third capacitor C3 if the second condition is met, and the first capacitor C1 is charged by the second capacitor C2 if the third condition is met. The second condition is VC3 > (VC2 + Vd2 + Vf3). The third condition is VC2 > (VC1 + Vd1 + Vf2). A charging path Ru32 along which the second capacitor C2 is charged by the third capacitor C3 is the path from the third capacitor C3 to the second diode D12, the second capacitor C2, the third node 13, the third switching element Q3, and the third capacitor C3. A charging path Ru21 through which the first capacitor C1 is charged by the second capacitor C2 is a path from the second capacitor C2 to the first diode D11, the first capacitor C1, the first node 11, the second switching element Q2, and the second capacitor C2. A charging path Ru32 through which the second capacitor C2 is charged by the third capacitor C3 is a path from the third capacitor C3 to the second diode D12, the second capacitor C2, the third node 13, the third switching element Q3, and the third capacitor C3.

[0072] Furthermore, when the inverter circuit 1 is in the third switching state, as shown in FIG. 6 , a current I1 flows through the path from the negative pole N1 of the DC power supply unit 3 to the fourth switching element Q4, the third switching element Q3, the third connection point 13, and the output terminal 8, and the voltage value of the output voltage to the AC load becomes 0. Furthermore, when the inverter circuit 1 is in the third switching state, the first capacitor C1 of the first bootstrap circuit 71 is charged, so that the voltage of the first capacitor C1 increases over time, and the first capacitor C1 is fully charged. Furthermore, when the inverter circuit 1 is in the third switching state, the second capacitor C2 of the second bootstrap circuit 72 is charged, so that the voltage VC2 of the second capacitor C2 increases over time, and the second capacitor C2 is fully charged. Furthermore, when the inverter circuit 1 is in the third switching state, the third capacitor C3 of the third bootstrap circuit 73 supplies the third gate driver 63 with the voltage required to turn on the third switching element Q3. Therefore, as shown in FIG. 7 , the charge in the third capacitor C3 of the third bootstrap circuit 73 is discharged along a discharge path Ru3 that runs from the third capacitor C3 to the high-side power supply terminal 63H of the third gate driver 63 to the low-side power supply terminal 63L of the third gate driver 63 to the third capacitor C3. Also, as shown in FIG. 7 , assuming that the voltage between the positive and negative terminals of the DC voltage source 6 is V60, the voltage between the anode and cathode of the third diode D13 is Vd3, the voltage between the first and second main terminals of the third switching element Q3 is Vf3, and the voltage between the first and second main terminals of the fourth switching element Q4 is Vf4, when the inverter circuit 1 is in the third switching state, the third capacitor C3 is charged by the DC voltage source 6 if a fourth condition is satisfied, and the second capacitor C2 is charged by the third capacitor C3 if a fifth condition is satisfied. The fourth condition is V60 > (VC3 + Vd3 + Vf4). The fifth condition is VC3>(VC2+Vd2+Vf3). A charging path Ru63 along which the third capacitor C3 is charged by the DC voltage source 6 is the path from the positive terminal of the DC voltage source 6 to the third diode D13, the third capacitor C3, the second connection point 12, the fourth switching element Q4, and the negative terminal of the DC voltage source 6.A charging path Ru32 for charging the second capacitor C2 by the third capacitor C3 is a path from the third capacitor C3 to the second diode D12, the second capacitor C2, the third connection point 13, the third switching element Q3 and the third capacitor C3.

[0073] The control device 4 (see FIG. 1) generates first to fourth control signals S1 to S4 (US1 to US4) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U, first to fourth control signals S1 to S4 (VS1 to VS4) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V, and first to fourth control signals S1 to S4 (WS1 to WS4) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W, based on voltage commands Vu, Vv, and Vw (see FIG. 8) related to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0074] As shown in FIG. 8 , the voltage commands Vu, Vv, and Vw are sinusoidal signals whose phases are, for example, 120° apart, and whose values ​​(voltage command values) change over time. The voltage commands Vu, Vv, and Vw have the same cycle length. The control device 4 (see FIG. 1 ) may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detector that detects the state of the AC load. When the AC load is a three-phase servo motor, the information output from the detector includes, for example, at least one of the following: information on the detection results from multiple current sensors that detect the output currents flowing through the U, V, and W phases of the AC load; and information on the detection results from an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0075] The output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0076] In this embodiment, the control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing space vector modulation (hereinafter also referred to as voltage vector control).

[0077] The voltage vector control by the control device 4 will be described in more detail below.

[0078] The control device 4 stores a group of voltage vectors in advance. Each of the group of voltage vectors is determined by a combination of the potential levels of the third connection point 13 between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the inverter circuit 1U corresponding to the U phase, the switching state of the inverter circuit 1V corresponding to the V phase, and the switching state of the inverter circuit 1W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3. ３ = 27 pieces.

[0079] The group of voltage vectors includes three zero vectors V0p, V0z, and V0n, each of which has a magnitude of zero, as shown in the three-level space vector diagram (space vector modulation diagram) in Figure 9. The group of voltage vectors also includes three zero vectors V0p, V0z, and V0n, each of which has a magnitude of (2 / 3) １／２ The group of voltage vectors includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which is 2 Vdc and points in different directions. The magnitude of each of the voltage vectors is (2 / 3) １／２ The group of voltage vectors includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3) １／２ ・3 １／２ Six voltage vectors V13, V14, V15, V16, V17, and V18 are Vdc and have different directions. １／２ Vdc is the reference magnitude. In Figure 9, the angle between two adjacent voltage vectors of the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between two adjacent voltage vectors of the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 9 is a three-level space vector diagram illustrating a group of voltage vectors on an orthogonal α-β coordinate system.

[0080] A group of voltage vectors can be expressed as a three-level space vector diagram (space vector modulation diagram) shown in FIG. 10 by expressing the first switching state, the second switching state, and the third switching state with the symbols "P," "0," and "N," respectively, and notating them in the order of U phase, V phase, and W phase.

[0081] 10 , the three zero vectors V0p, V0z, and V0n can be expressed as V0p[PPP], V0z

[000] , and V0n[NNN], respectively. For example, V0p[PPP] represents that, with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1U is "P," the switching state of the V-phase inverter circuit 1V is "P," and the switching state of the W-phase inverter circuit 1W is "P." Furthermore, V0z

[000] represents that, with respect to the zero vector V0z, the switching state of the U-phase inverter circuit 1U is "0," the switching state of the V-phase inverter circuit 1V is "0," and the switching state of the W-phase inverter circuit 1W is "0." Furthermore, V0n[NNN] represents that, with respect to the zero vector V0n, the switching state of the U-phase inverter circuit 1U is "N", the switching state of the V-phase inverter circuit 1V is "N", and the switching state of the W-phase inverter circuit 1W is "N". When the switching state of the inverter circuit 1 is "P", the potential of the third connection point 13 in the inverter circuit 1 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the inverter circuit 1 is "N", the potential of the third connection point 13 in the inverter circuit 1 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the inverter circuit 1 is "0", the potential of the third connection point 13 in the inverter circuit 1 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0082] Furthermore, a voltage vector with a "p" suffix, such as V10p, includes a "P" but does not include an "N". This also applies below. Furthermore, a voltage vector with an "n" suffix, such as V10n, includes an "N" but does not include a "P". This also applies below.

[0083] The six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors without "p," "n," or "z" after the number attached to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases. A group of voltage vectors includes six voltage vectors, V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], each of which has a magnitude twice the reference magnitude.

[0084] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively. Therefore, the group of voltage vectors includes 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], each of which has a reference magnitude as a voltage vector (reference vector).

[0085] The six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively. １／２ The voltage vectors having double the magnitude include six voltage vectors V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0].

[0086] The control device 4 converts into a command voltage vector Vref (see FIG. 11 ) the instantaneous value of the command voltage related to the output voltage of each of the multiple inverter circuits 1. If the α-axis component of the command voltage vector Vref on the orthogonal α-β coordinate system (see FIGS. 9 to 11 ) is Vα and the β-axis component of the command voltage vector Vref on the orthogonal α-β coordinate system is Vβ, the command voltage vector Vref can be calculated using equation (1).

[0087]

[0088] The control device 4 selects a first voltage vector Va, a second voltage vector Vb, and a third voltage vector Vc corresponding to the vertices of an equilateral triangle surrounding the command voltage vector Vref as multiple voltage vectors to be used within the control period Ts (see Figures 12 and 13) from the group of voltage vectors, and determines a first allocation time T0 for the first voltage vector Va, a second allocation time T1 for the second voltage vector Vb, and a third allocation time T2 for the third voltage vector Vc so that the composite vector of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc matches the command voltage vector Vref.

[0089] The control device 4 determines the first allocated time T0, the second allocated time T1, and the third allocated time T2 so as to satisfy equations (2) and (3), where the voltage vectors at the vertices of an equilateral triangle surrounding the command voltage vector Vref are the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc, and the magnitude and angle of the command voltage vector Vref are V and θ, respectively. "j" in equation (2) is the imaginary unit. The angle between the first voltage vector Va, which is closest to the command voltage vector Vref, and the command voltage vector Vref is smaller than 30 degrees.

[0090]

[0091]

[0092] In addition, the control device 4 distributes the first distribution time T0 to each first voltage vector Va based on the number of times the first voltage vector Va is used within the control period Ts, distributes the second distribution time T1 to each second voltage vector Vb based on the number of times the second voltage vector Vb is used within the control period Ts, and distributes the third distribution time T2 to each third voltage vector Vc based on the number of times the third voltage vector Vc is used within the control period Ts.

[0093] In the example shown in Fig. 11, the first voltage vector Va is a voltage vector V8p[PP0] and a voltage vector V8n[00N], the second voltage vector Vb is a voltage vector V13[P0N], and the third voltage vector Vc is a voltage vector V7p[P00]. Fig. 12 shows the switching states of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W when the control device 4 sequentially uses eight voltage vectors within a control period Ts. Fig. 13 shows the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the U-phase inverter circuit 1U when the control device 4 sequentially uses eight voltage vectors within a control period Ts. 12 illustrates an example in which the allocation time of the first voltage vector Va (voltage vector V8p[PP0] and voltage vector V8n[00N]) is T0, the allocation time of the second voltage vector Vb (voltage vector V13[P0N]) is T1, and the allocation time of the third voltage vector Vc (voltage vector V7p[P00]) is T2 during a control period Ts. The control period Ts is one period of the carrier signal.

[0094] When changing the switching state of two adjacent voltage vectors among the eight voltage vectors arranged in time series within a control period Ts, the control device 4 changes the switching state of the inverter circuit 1 of only one phase among the U phase, V phase, and W phase between "P" and "0" or between "0" and "N", and uses the same voltage vector twice. In Fig. 12, the control device 4 uses the voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N] in this order. 12 , the control device 4 uses the first voltage vector Va four times, and therefore the allocation time for each of the first voltage vector Va (voltage vector V8n[00N]) used first within the control period Ts, the first voltage vector Va (voltage vector V8p[PP0]) used fourth, the first voltage vector Va (voltage vector V8p[PP0]) used fifth, and the first voltage vector Va (voltage vector V8n[00N]) used eighth within the control period Ts is set to T0 / 4. Also, in the example of FIG. 12 , the control device 4 uses the second voltage vector Vb twice, and therefore the allocation time for each of the second voltage vector Vb (voltage vector V13[P0N]) used second within the control period Ts and the second voltage vector Vb (voltage vector V13[P0N]) used seventh within the control period Ts is set to T1 / 2. 12, the control device 4 uses the third voltage vector Vc twice, and therefore the allocation time of each of the third voltage vector Vc (voltage vector V7p[P00]) used third and the third voltage vector Vc (voltage vector V7p[P00]) used sixth within the control period Ts is set to T2 / 2. Note that even if the command voltage vector Vref is the same as in FIG. 11, the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.

[0095] The control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 within a predetermined control period Ts (see FIG. 12) so as to match the resultant vector of the first voltage vector Va (in the example shown in FIG. 11, the voltage vector V8p[PP0] and the voltage vector V8n[00N]), the second voltage vector Vb (in the example shown in FIG. 11, the voltage vector V13[P0N]), and the third voltage vector Vc (in the example shown in FIG. 11, the voltage vector V7p[P00]) with the command voltage vector Vref.

[0096] The output current of the inverter circuit 1 has a sinusoidal waveform as shown in Figure 14. The polarity of the output current of the inverter circuit 1 is defined as positive when it flows from the third connection point 13 to the output terminal 8, and negative when it flows from the output terminal 8 to the third connection point 13. During a period in which the polarity of the output current of the inverter circuit 1 is positive, the control device 4 may control the inverter circuit 1 to the first switching state or the second switching state, but never to the third switching state. Furthermore, during a period in which the polarity of the output current of the inverter circuit 1 is negative, the control device 4 may control the inverter circuit 1 to the second switching state or the third switching state, but never to the first switching state.

[0097] In the comparative example switching drive circuit that does not include the auxiliary circuit 5, during the period when the polarity of the output current of the inverter circuit is positive, the third capacitor of the third bootstrap circuit corresponding to the third switching element of that inverter circuit cannot be charged from the DC voltage source, and the voltage of the third capacitor drops below the threshold voltage of the third switching element, making it impossible to stably drive the third switching element.

[0098] In contrast, the power conversion device 100 of this embodiment (see Figure 1) is equipped with an auxiliary circuit 5, which makes it possible to charge the third capacitor C3 even during periods when the polarity of the output current of the inverter circuit 1 is positive, thereby making it possible to stably drive the third switching element Q3.

[0099] The operation of the auxiliary circuit 5 will be described below in relation to the operation of the control device 4.

[0100] 15 illustrates voltage commands Vu, Vv, and Vw for each phase (U-phase, V-phase, and W-phase), three second control signals US2, VS2, and WS2 output from the control device 4, and a fifth control signal S5 output from the output terminal of the AND element 51. The fifth control signal S5 is provided to the fifth gate driver 65. Note that in FIG. 15, for each of the three second control signals US2, VS2, and WS2 and the fifth control signal S5, a high level is represented as "H" and a low level is represented as "L."

[0101] In the auxiliary circuit 5, the second control signal US2 is input to one of the multiple input terminals (three in the example of FIG. 1 ) of the AND element 51, the second control signal VS2 is input to another input terminal, and the second control signal WS2 is input to the remaining input terminal. In the auxiliary circuit 5, when all of the multiple second control signals US2, VS2, and WS2 are at high level H, the fifth control signal S5 goes to high level H. In addition, in the auxiliary circuit 5, when at least one of the multiple second control signals US2, VS2, and WS2 is at low level, the fifth control signal S5 goes to low level L.

[0102] In the power conversion device 100, when the fifth control signal S5 is at low level L, the fifth switching element Q5 is turned off and the fourth switching element Q4 is turned on in any one of the three inverter circuits 1, and power is supplied from the DC voltage source 6 to the fourth capacitor C5 of the fourth bootstrap circuit 75. In the power conversion device 100, for example, when the fourth switching element Q4 is turned on in the U-phase inverter circuit 1U, as shown in FIG. 16 , a charging path Ru65 that charges the fourth capacitor C5 from the DC voltage source 6 is a path from the positive terminal of the DC voltage source 6 to the diode D9, the fourth capacitor C5, the second auxiliary diode D8, the fourth switching element Q4, and the negative terminal of the DC voltage source 6.

[0103] In the power conversion device 100, when the fifth control signal S5 is at high level H, the fifth switching element Q5 is turned on and the fourth switching element Q4 is turned on in all three inverter circuits 1, and power is supplied from the fourth capacitor C5 of the fourth bootstrap circuit 75 to the third capacitor C3 of the three third bootstrap circuits 73. As shown in FIG. 17 , a charging path Ru53 that charges the third capacitor C3 of the third bootstrap circuit 73 corresponding to the U-phase inverter circuit 1U from the fourth capacitor C5 of the fourth bootstrap circuit 75 is a path from the high potential end of the fourth capacitor C5 to the first auxiliary diode D7, the third capacitor C3, the second connection point 12, the second clamp diode D6, the fifth switching element Q5, and the low potential end of the fourth capacitor C5.

[0104] FIG. 18 shows the waveforms of the output current of the U-phase inverter circuit 1U, the voltage VC1 of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the first switching element Q1 of the inverter circuit 1U, the voltage VC2 of the second capacitor C2 of the second bootstrap circuit 72 corresponding to the second switching element Q2 of the inverter circuit 1U, and the voltage VC3 of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the third switching element Q3 of the inverter circuit 1U.

[0105] 18 shows that in the switching element drive circuit 2 according to the first embodiment, the second capacitor C2 and the third capacitor C3 are each charged during a period in which the output current of the inverter circuit 1U is positive, thereby suppressing a decrease in the voltage VC2 of the second capacitor C2 and the voltage VC3 of the third capacitor C3. Note that, during a period in which the output current of the inverter circuit 1V is positive and a period in which the output current of the inverter circuit 1W is positive, the second capacitor C2 and the third capacitor C3 are each charged, similar to the period in which the output current of the inverter circuit 1U is positive.

[0106] (4) Advantages The switching element drive circuit 2 according to the first embodiment includes an auxiliary circuit 5 connected to multiple third bootstrap circuits 73. The auxiliary circuit 5 includes a fifth switching element Q5, a fifth gate driver 65, a fourth bootstrap circuit 75, multiple first auxiliary diodes D7, and multiple second auxiliary diodes D8. The fifth switching element Q5 has a first main terminal, a second main terminal, and a gate terminal, and the first main terminal is connected to the intermediate potential point M1. The fifth gate driver 65 is connected to the gate terminal and the second main terminal of the fifth switching element Q5 to drive the fifth switching element Q5. The fourth bootstrap circuit 75 includes a fourth capacitor C5 connected in parallel to the fifth gate driver 65, and a diode D9 having a cathode connected to the high-potential end of the fourth capacitor C5 and an anode connected to the positive terminal of the DC voltage source 6. The cathodes of the first auxiliary diodes D7 are connected to the high potential ends of the third capacitors C3 of the third bootstrap circuits 73, and the anodes of the second auxiliary diodes D8 are connected to the low potential ends of the third capacitors C3 of the third bootstrap circuits 73, and the anodes of the second auxiliary diodes D8 are connected to the low potential ends of the fourth capacitor C5.

[0107] According to the above configuration, it is possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0108] In the switching element drive circuit 2 according to the first embodiment, the auxiliary circuit 5 further includes an AND element 51. The AND element 51 has a plurality of input terminals and an output terminal, the plurality of input terminals being connected to the control device 4, and the output terminal being connected to the fifth gate driver 65. In the auxiliary circuit 5, a plurality of second control signals S2 are input to the plurality of input terminals of the AND element 51.

[0109] According to the above configuration, it is possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73 without performing any special control in the control device 4.

[0110] The power conversion device 100 according to the first embodiment also includes a switching element drive circuit 2 and a plurality of diode-clamped three-level inverters 1 .

[0111] According to the above configuration, it is possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0112] Second Embodiment A power conversion device 100A according to a second embodiment will be described with reference to FIG.

[0113] (1) Configuration The power conversion device 100A according to the second embodiment is substantially the same as the power conversion device 100 according to the first embodiment (see FIG. 1), but differs from the power conversion device 100 according to the first embodiment in that it includes a switching element drive circuit 2A instead of the switching element drive circuit 2 according to the first embodiment (see FIG. 1). Note that, with respect to the power conversion device 100A according to the second embodiment, components similar to those of the power conversion device 100 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted. Also, with respect to the switching element drive circuit 2A according to the second embodiment, components similar to those of the switching element drive circuit 2 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0114] The switching element drive circuit 2A of the second embodiment differs from the switching element drive circuit 2 of the first embodiment in that the switching element drive circuit 2A of the second embodiment does not include the third diode D13 in each of the plurality of third bootstrap circuits 73 of the switching element drive circuit 2 of the first embodiment.

[0115] (2) Operation of the Power Conversion Device Figure 20 shows waveforms of the voltage VC1 of the first capacitor C1, the voltage VC2 of the second capacitor C2, the voltage VC3 of the third capacitor C3, and the voltage VC5 of the fourth capacitor C5 when the power conversion device 100A including the switching element drive circuit 2A according to embodiment 2 is operated. The voltage VC1 of the first capacitor C1 is smaller than the voltage VC2 of the second capacitor C2, the voltage VC3 of the third capacitor C3, and the voltage VC5 of the fourth capacitor C5. In the example of Figure 20, the minimum value of the voltage VC1 of the first capacitor C1 is 12.75 V, which is larger than the threshold voltage of the first switching element Q1.

[0116] (3) Advantages The switching element drive circuit 2A according to the second embodiment includes the auxiliary circuit 5, similar to the switching element drive circuit 2 according to the first embodiment. This makes it possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0117] In the switching element drive circuit 2A according to the second embodiment, each of the first bootstrap circuits 71 includes a first diode D11. The first diode D11 has a first cathode and a first anode. The first cathode of the first diode D11 is connected to the high potential end of the first capacitor C1. Each of the second bootstrap circuits 72 includes a second diode D12. The second diode D12 has a second cathode and a second anode. The second cathode of the second diode D12 is connected to the high potential end of the second capacitor C2. Each of the third bootstrap circuits 73 includes only a third capacitor C3. The second anode of the second diode D12 is connected to the high potential end of the third capacitor C3. The first anode of the first diode D11 is connected to the second cathode of the second diode D12.

[0118] According to the above configuration, the number of components can be reduced compared to the switching element drive circuit 2 according to the first embodiment, and miniaturization can be achieved.

[0119] Moreover, the power conversion device 100A according to the second embodiment includes a switching element drive circuit 2A and a plurality of diode-clamped three-level inverters 1.

[0120] According to the above configuration, it is possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0121] Third Embodiment A power conversion device 100B according to a third embodiment will be described with reference to FIG.

[0122] (1) Configuration The power conversion device 100B according to the third embodiment is substantially the same as the power conversion device 100 according to the first embodiment (see FIG. 1), but differs from the power conversion device 100 according to the first embodiment in that it includes a switching element drive circuit 2B instead of the switching element drive circuit 2 according to the first embodiment (see FIG. 1). Note that, with respect to the power conversion device 100B according to the third embodiment, components similar to those of the power conversion device 100 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted. Also, with respect to the switching element drive circuit 2B according to the third embodiment, components similar to those of the switching element drive circuit 2 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0123] The switching element drive circuit 2B according to the third embodiment differs from the switching element drive circuit 2 according to the first embodiment in that the switching element drive circuit 2B according to the third embodiment does not include the third diode D13 in each of the plurality of third bootstrap circuits 73 of the switching element drive circuit 2 according to the first embodiment. The switching element drive circuit 2B according to the third embodiment also differs from the switching element drive circuit 2 according to the first embodiment in that the first diode D11 in each of the plurality of first bootstrap circuits 71 is connected to the first auxiliary diode D7 without passing through the second diode D12.

[0124] (2) Operation of the Power Conversion Device FIG. 22 shows waveforms of the voltage VC1 of the first capacitor C1, the voltage VC2 of the second capacitor C2, the voltage VC3 of the third capacitor C3, and the voltage VC5 of the fourth capacitor C5 when a power conversion device 100B including a switching element drive circuit 2B according to the third embodiment is operated. The voltage VC1 of the first capacitor C1 is lower than the voltage VC2 of the second capacitor C2, the voltage VC3 of the third capacitor C3, and the voltage VC5 of the fourth capacitor C5. In the example shown in FIG. 22, the minimum value of the voltage VC1 of the first capacitor C1 is 13.675 V, which is higher than the threshold voltage of the first switching element Q1. Furthermore, in the third embodiment, the minimum value of the voltage VC1 of the first capacitor C1 is higher than in the second embodiment.

[0125] (3) Advantages The switching element drive circuit 2B according to the third embodiment includes the auxiliary circuit 5, similar to the switching element drive circuit 2 according to the first embodiment. This makes it possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0126] Furthermore, in the switching element drive circuit 2B according to the third embodiment, each of the multiple first bootstrap circuits 71 includes a first diode D11. The first diode D11 has a first cathode and a first anode. The first cathode of the first diode D11 is connected to the high potential end of the first capacitor C1. Each of the multiple second bootstrap circuits 72 includes a second diode D12. The second diode D12 has a second cathode and a second anode. The second cathode of the second diode D12 is connected to the high potential end of the second capacitor C2. Each of the multiple third bootstrap circuits 73 includes only the third capacitor C3. The first anode of the first diode D11 of each of the plurality of first bootstrap circuits 71 is connected to the high potential end of the third capacitor C3 of a corresponding one of the plurality of third bootstrap circuits 73 and to the cathode of a corresponding one of the plurality of first auxiliary diodes D7, without passing through the second diode D12 of a corresponding one of the plurality of second bootstrap circuits 72. The second anode of the second diode D12 of each of the plurality of second bootstrap circuits 72 is connected to the high potential end of the third capacitor C3 of a corresponding one of the plurality of third bootstrap circuits 73 and to the cathode of a corresponding one of the plurality of first auxiliary diodes D7.

[0127] According to the above configuration, it is possible to suppress a drop in voltage of the first capacitor C1 of each of the multiple first bootstrap circuits 71, compared to the switching element drive circuit 2 of embodiment 1 and the switching element drive circuit 2A of embodiment 2.

[0128] Moreover, the power conversion device 100B according to the third embodiment includes a switching element drive circuit 2B and a plurality of diode-clamped three-level inverters 1.

[0129] According to the above configuration, it is possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0130] Fourth Embodiment A switching element drive circuit 2 and a power conversion device 100 according to a fourth embodiment will be described with reference to FIGS. 1 and 23. FIG.

[0131] (1) Configuration The circuit configuration of the switching element drive circuit 2 and the power conversion device 100 according to the fourth embodiment is the same as the circuit configuration of the switching element drive circuit 2 and the power conversion device 100 according to the first embodiment (see FIG. 1).

[0132] (2) Operation of the Power Conversion Device The switching element drive circuit 2 according to the fourth embodiment differs from the switching element drive circuit 2 according to the first embodiment in that the control device 4 performs triangular wave PWM control instead of voltage vector control.

[0133] As shown in FIG. 23 , for each diode-clamped three-level inverter 1 (inverter circuit 1), the control device 4 compares the output voltage command value Vout at the output terminal 8 (see FIG. 1 ) with a triangular-wave first carrier wave CA1 to generate a first control signal S1 consisting of a PWM signal. The control device 4 also generates a third control signal S3 consisting of a PWM signal obtained by inverting the PWM signal constituting the first control signal S1. Therefore, in the inverter circuit 1, the first switching element Q1 and the third switching element Q3 operate complementarily. As shown in FIG. 23 , the control device 4 also compares the output voltage command value Vout at the output terminal 8 (see FIG. 1 ) with a triangular-wave second carrier wave CA2 to generate a second control signal S2 consisting of a PWM signal. The control device 4 also generates a fourth control signal S4 consisting of a PWM signal obtained by inverting the PWM signal constituting the second control signal S2. Therefore, in the inverter circuit 1, the second switching element Q2 and the fourth switching element Q4 operate complementarily. In FIG. 23, regarding the potential levels of each of the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4, a low level is represented as "L" and a high level is represented as "H".

[0134] (3) Advantages The switching element drive circuit 2 according to the fourth embodiment includes the auxiliary circuit 5, similar to the switching element drive circuit 2 according to the first embodiment. This makes it possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0135] Moreover, the power conversion device 100 according to the fourth embodiment includes a switching element drive circuit 2 and a plurality of diode-clamped three-level inverters 1 .

[0136] According to the above configuration, it is possible to suppress a decrease in the voltage VC3 of the third capacitor C3 of each of the plurality of third bootstrap circuits 73.

[0137] (Modifications) The above-described first to fourth embodiments are merely examples of various embodiments of the present disclosure. The above-described first to fourth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0138] For example, in the switching element drive circuit 2A according to the second embodiment or the switching element drive circuit 2B according to the third embodiment, the control device 4 may be configured to perform triangular wave PWM control instead of voltage vector control.

[0139] In any one of the first to fourth embodiments, the control device 4 may include the logical product element 51, or the control device 4 may have a function similar to that of the logical product element 51.

[0140] Furthermore, the fourth capacitor C5 of the auxiliary circuit 5 is not limited to one capacitor, and may be configured by connecting two capacitors in parallel, for example.

[0141] Furthermore, each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, the fourth switching elements Q4, and the fifth switching elements Q5 is not limited to an IGBT but may be a MOSFET. In this case, the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, the fourth switching elements Q4, and the fifth switching elements Q5 are a gate terminal, a drain terminal, and a source terminal, respectively. Each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, the fourth switching elements Q4, and the fifth switching elements Q5 may be a gate injection transistor (GIT). The GIT is, for example, a GaN-based GIT.

[0142] Each of the first bootstrap circuits 71 may further include a first Zener diode connected in parallel to the first capacitor C1. In this case, the cathode of the first Zener diode is connected to the high potential end of the first capacitor C1, and the anode of the first Zener diode is connected to the low potential end of the first capacitor C1. Each of the second bootstrap circuits 72 may further include a second Zener diode connected in parallel to the second capacitor C2. In this case, the cathode of the second Zener diode is connected to the high potential end of the second capacitor C2, and the anode of the second Zener diode is connected to the low potential end of the second capacitor C2. Each of the third bootstrap circuits 73 may further include a third Zener diode connected in parallel to the third capacitor C3. In this case, the cathode of the third Zener diode is connected to the high potential end of the third capacitor C3, and the anode of the third Zener diode is connected to the low potential end of the third capacitor C3.

[0143] Each of the first bootstrap circuits 71 may include a resistor (first resistor) connected between the cathode of the first diode D11 and the high potential end of the first capacitor C1. Each of the second bootstrap circuits 72 may include a resistor (second resistor) connected between the cathode of the second diode D12 and the high potential end of the second capacitor C2. Each of the third bootstrap circuits 73 may include a resistor (third resistor) connected between the cathode of the third diode D13 and the high potential end of the third capacitor C3.

[0144] Furthermore, the power conversion device 100 is not limited to a configuration having three inverter circuits 1, but may be a configuration having two inverter circuits 1, or a configuration having four or more inverter circuits 1.

[0145] (Aspects) The following aspects are disclosed in this specification.

[0146] A switching element drive circuit (2; 2A; 2B) according to a first aspect drives a plurality of diode-clamped three-level inverters (1). The plurality of diode-clamped three-level inverters (1) include a plurality of first switching elements (Q1), a plurality of second switching elements (Q2), a plurality of third switching elements (Q3), a plurality of fourth switching elements (Q4), a plurality of first clamp diodes (D5), and a plurality of second clamp diodes (D6). The plurality of first switching elements (Q1) are connected to a positive electrode (P1) of a DC power supply unit (3) having a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of second switching elements (Q2) are connected in series with the plurality of first switching elements (Q1). The plurality of third switching elements (Q3) are connected in series with the plurality of second switching elements (Q2). The plurality of fourth switching elements (Q4) are connected in series with the plurality of third switching elements (Q3) and connected to the negative pole (N1) of the DC power supply unit (3). The plurality of first clamp diodes (D5) have cathodes connected to the plurality of first connection points (11) between the plurality of first switching elements (Q1) and the plurality of second switching elements (Q2) and have anodes connected to the intermediate potential point (M1). The plurality of second clamp diodes (D6) have anodes connected to the plurality of second connection points (12) between the plurality of third switching elements (Q3) and the plurality of fourth switching elements (Q4) and have cathodes connected to the intermediate potential point (M1). The switching element drive circuit (2; 2A; 2B) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a plurality of third bootstrap circuits (73), a DC voltage source (6), a control device (4), and an auxiliary circuit (5). The plurality of first gate drivers (61) drive a plurality of first switching elements (Q1), respectively. The plurality of second gate drivers (62) drive a plurality of second switching elements (Q2), respectively.The plurality of third gate drivers (63) respectively drive the plurality of third switching elements (Q3). The plurality of fourth gate drivers (64) respectively drive the plurality of fourth switching elements (Q4). The plurality of first bootstrap circuits (71) correspond one-to-one to the plurality of first gate drivers (61). Each of the plurality of first bootstrap circuits (71) includes a first capacitor (C1) connected in parallel to the corresponding first gate driver (61). The plurality of second bootstrap circuits (72) correspond one-to-one to the plurality of second gate drivers (62). Each of the plurality of second bootstrap circuits (72) includes a second capacitor (C2) connected in parallel to the corresponding second gate driver (62). The plurality of third bootstrap circuits (73) correspond one-to-one to the plurality of third gate drivers (63). Each of the plurality of third bootstrap circuits (73) includes a third capacitor (C3) connected in parallel to the corresponding third gate driver (63). The DC voltage source (6) is connected in parallel to the plurality of fourth gate drivers (64). The control device (4) outputs a plurality of first control signals (S1), a plurality of second control signals (S2), a plurality of third control signals (S3), and a plurality of fourth control signals (S4) to the plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64), respectively. The auxiliary circuit (5) is connected to the plurality of third bootstrap circuits (73). The auxiliary circuit (5) includes a fifth switching element (Q5), a fifth gate driver (65), a fourth bootstrap circuit (75), a plurality of first auxiliary diodes (D7), and a plurality of second auxiliary diodes (D8). The fifth switching element (Q5) has a first main terminal, a second main terminal, and a gate terminal, and the first main terminal is connected to an intermediate potential point (M1). The fifth gate driver (65) is connected to the gate terminal and the second main terminal of the fifth switching element (Q5) to drive the fifth switching element (Q5). The fourth bootstrap circuit (75) includes a fourth capacitor (C5) and a diode (D9). The fourth capacitor (C5) is connected in parallel to the fifth gate driver (65).The diode (D9) has its cathode connected to the high potential end of the fourth capacitor (C5) and its anode connected to the positive terminal of the DC voltage source (6). The plurality of first auxiliary diodes (D7) have their cathodes connected to the high potential ends of the third capacitors (C3) of the plurality of third bootstrap circuits (73) and their anodes connected to the high potential ends of the fourth capacitors (C5). The plurality of second auxiliary diodes (D8) have their cathodes connected to the low potential ends of the third capacitors (C3) of the plurality of third bootstrap circuits (73) and their anodes connected to the low potential ends of the fourth capacitors (C5).

[0147] According to this aspect, it is possible to suppress a drop in the voltage of the third capacitor (C3) of each of the plurality of third bootstrap circuits (73).

[0148] In the switching element drive circuit (2) according to the second aspect, in the first aspect, each of the plurality of first bootstrap circuits (71) includes a first diode (D11). The first diode (D11) has a first cathode and a first anode. The first cathode of the first diode (D11) is connected to the high potential end of the first capacitor (C1). Each of the plurality of second bootstrap circuits (72) includes a second diode (D12). The second diode (D12) has a second cathode and a second anode. The second cathode of the second diode (D12) is connected to the high potential end of the second capacitor (C2). Each of the plurality of third bootstrap circuits (73) includes a third diode (D13). The third diode (D13) has a third cathode and a third anode. The third cathode of the third diode (D13) is connected to the high potential end of the third capacitor (C3). The third anode of the third diode (D13) is connected to the positive terminal of the DC voltage source (6). The second anode of the second diode (D12) is connected to the third cathode of the third diode (D13). The first anode of the first diode (D11) is connected to the second cathode of the second diode (D12).

[0149] In a switching element drive circuit (2A) according to a third aspect, in the first aspect, each of the plurality of first bootstrap circuits (71) includes a first diode (D11). The first diode (D11) has a first cathode and a first anode. The first cathode of the first diode (D11) is connected to the high potential end of the first capacitor (C1). Each of the plurality of second bootstrap circuits (72) includes a second diode (D12). The second diode (D12) has a second cathode and a second anode. The second cathode of the second diode (D12) is connected to the high potential end of the second capacitor (C2). Each of the plurality of third bootstrap circuits (73) includes only a third capacitor (C3). The second anode of the second diode (D12) is connected to the high potential end of the third capacitor (C3). The first anode of the first diode (D11) is connected to the second cathode of the second diode (D12).

[0150] According to this aspect, the number of components can be reduced compared to the switching element drive circuit (2) according to the second aspect, and miniaturization can be achieved.

[0151] In a switching element drive circuit (2B) according to a fourth aspect, in the first aspect, each of the plurality of first bootstrap circuits (71) includes a first diode (D11). The first diode (D11) has a first cathode and a first anode. The first cathode of the first diode (D11) is connected to the high potential end of the first capacitor (C1). Each of the plurality of second bootstrap circuits (72) includes a second diode (D12). The second diode (D12) has a second cathode and a second anode. The second cathode of the second diode (D12) is connected to the high potential end of the second capacitor (C2). Each of the plurality of third bootstrap circuits (73) includes only a third capacitor (C3). The first anode of the first diode (D11) of each of the plurality of first bootstrap circuits (71) is connected to the high potential end of the third capacitor (C3) of a corresponding one of the plurality of third bootstrap circuits (73) and to the cathode of the corresponding one of the plurality of first auxiliary diodes (D7) without passing through the second diode (D12) of the corresponding one of the plurality of second bootstrap circuits (72). The second anode of the second diode (D12) of each of the plurality of second bootstrap circuits (72) is connected to the high potential end of the third capacitor (C3) of the corresponding one of the plurality of third bootstrap circuits (73) and to the cathode of the corresponding one of the plurality of first auxiliary diodes (D7).

[0152] According to this aspect, it is possible to suppress a decrease in voltage of the first capacitor (C1) of each of the plurality of first bootstrap circuits (71), compared to the switching element drive circuit (2) according to the second aspect and the switching element drive circuit (2A) according to the third aspect.

[0153] In a switching element drive circuit (2; 2A; 2B) according to a fifth aspect, in any one of the first to fourth aspects, the auxiliary circuit (5) further includes a logical product element (51). The logical product element (51) has a plurality of input terminals and an output terminal, the plurality of input terminals being connected to the control device (4) and the output terminal being connected to a fifth gate driver (65). In the auxiliary circuit (5), a plurality of second control signals (S2) are input to the plurality of input terminals of the logical product element (51).

[0154] According to this aspect, it is possible to suppress a decrease in the voltage (VC3) of the third capacitor (C3) of each of the plurality of third bootstrap circuits (73) without performing any special control in the control device (4).

[0155] In a switching element drive circuit (2; 2A; 2B) according to a sixth aspect, in any one of the first to fifth aspects, the control device (4) generates a plurality of first control signals (S1), a plurality of second control signals (S2), a plurality of third control signals (S3), and a plurality of fourth control signals (S4) by space vector modulation.

[0156] In the switching element drive circuit (2; 2A; 2B) according to the seventh aspect, in any one of the first to fifth aspects, the control device (4) generates a plurality of first control signals (S1), a plurality of second control signals (S2), a plurality of third control signals (S3), and a plurality of fourth control signals (S4) by triangular wave PWM control.

[0157] In a switching element drive circuit (2; 2A; 2B) according to an eighth aspect, in any one of the first to seventh aspects, the fifth switching element (Q5) is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

[0158] In a switching element drive circuit (2; 2A; 2B) according to a ninth aspect, in any one of the first to eighth aspects, the direct current voltage source (6) includes a DC-DC converter (60).

[0159] A power conversion device (100; 100A; 100B) according to a tenth aspect includes a switching element drive circuit (2; 2A; 2B) according to any one of the first to ninth aspects, and a plurality of diode-clamped three-level inverters (1).

[0160] According to this aspect, it is possible to suppress a drop in the voltage of the third capacitor (C3) of each of the plurality of third bootstrap circuits (73).

[0161] In the power conversion device (100; 100A; 100B) according to the eleventh aspect, in the tenth aspect, each of the plurality of first switching elements (Q1), the plurality of second switching elements (Q2), the plurality of third switching elements (Q3), and the plurality of fourth switching elements (Q4) is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

[0162] REFERENCE SIGNS LIST 1 Diode clamp type three-level inverter 2, 2A, 2B Switching element drive circuit 3 DC power supply unit 4 Control device 5 Auxiliary circuit 51 Logical AND element 6 DC voltage source 60 DC-DC converter 61 First gate driver 62 Second gate driver 63 Third gate driver 64 Fourth gate driver 65 Fifth gate driver 11 First connection point 12 Second connection point 13 Third connection point 71 First bootstrap circuit 72 Second bootstrap circuit 73 Third bootstrap circuit 75 Fourth bootstrap circuit 100, 100A, 100B Power conversion device C1 First capacitor C2 Second capacitor C3 Third capacitor C5 Fourth capacitor D5 First clamp diode D6 Second clamp diode D7 First auxiliary diode D8 Second auxiliary diode D9 Diode D11 First diode D12 Second diode D13 Third diode P1 Positive electrode Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element Q5 Fifth switching element M1 Midpoint potential point N1 Negative electrode

Claims

1. A switching element drive circuit for driving a plurality of diode-clamped three-level inverters, wherein the plurality of diode-clamped three-level inverters comprise: a plurality of first switching elements connected to the positive electrode of a DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point; a plurality of second switching elements connected in series to the plurality of first switching elements respectively; a plurality of third switching elements connected in series to the plurality of second switching elements respectively; a plurality of fourth switching elements connected in series to the plurality of third switching elements respectively and connected to the negative electrode of the DC power supply unit; a plurality of first clamp diodes having cathodes connected to a plurality of first connection points between the plurality of first switching elements and the plurality of second switching elements and having anodes connected to the intermediate potential point; and a plurality of second clamp diodes having anodes connected to a plurality of second connection points between the plurality of third switching elements and the plurality of fourth switching elements respectively and having cathodes connected to the intermediate potential point; a plurality of second gate drivers each driving the plurality of second switching elements; a plurality of third gate drivers each driving the plurality of third switching elements; a plurality of fourth gate drivers each driving the plurality of fourth switching elements; a plurality of first bootstrap circuits each corresponding to the plurality of first gate drivers and including a first capacitor connected in parallel to the corresponding first gate driver; a plurality of second bootstrap circuits each corresponding to the plurality of second gate drivers and including a second capacitor connected in parallel to the corresponding second gate driver; a plurality of third bootstrap circuits each corresponding to the plurality of third gate drivers and including a third capacitor connected in parallel to the corresponding third gate driver; and a DC voltage source connected in parallel to the plurality of fourth gate drivers.a control device that outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to be provided to the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, respectively; and an auxiliary circuit connected to the plurality of third bootstrap circuits, wherein the auxiliary circuit comprises: a fifth switching element having a first main terminal, a second main terminal, and a gate terminal, the first main terminal being connected to the intermediate potential point; a fifth gate driver that is connected to the gate terminal and the second main terminal of the fifth switching element and drives the fifth switching element; a fourth bootstrap circuit that includes a fourth capacitor connected in parallel to the fifth gate driver and a diode having a cathode connected to a high potential end of the fourth capacitor and an anode connected to a positive terminal of the DC voltage source; and a plurality of first auxiliary diodes each having a cathode connected to a high potential end of the third capacitor of the plurality of third bootstrap circuits and anode connected to the high potential end of the fourth capacitor. a plurality of second auxiliary diodes, each having a cathode connected to the low potential end of the third capacitor of each of the third bootstrap circuits and anode connected to the low potential end of the fourth capacitor.

2. The switching element drive circuit according to claim 1, wherein each of the plurality of first bootstrap circuits includes a first diode having a first cathode and a first anode, with the first cathode connected to the high potential end of the first capacitor; each of the plurality of second bootstrap circuits includes a second diode having a second cathode and a second anode, with the second cathode connected to the high potential end of the second capacitor; each of the plurality of third bootstrap circuits includes a third diode having a third cathode and a third anode, with the third cathode connected to the high potential end of the third capacitor, the third anode of the third diode being connected to the positive terminal of the DC voltage source; the second anode of the second diode being connected to the third cathode of the third diode; and the first anode of the first diode being connected to the second cathode of the second diode.

3. The switching element drive circuit according to claim 1, wherein each of the plurality of first bootstrap circuits includes a first diode having a first cathode and a first anode, with the first cathode connected to the high potential end of the first capacitor; each of the plurality of second bootstrap circuits includes a second diode having a second cathode and a second anode, with the second cathode connected to the high potential end of the second capacitor; each of the plurality of third bootstrap circuits includes only the third capacitor; the second anode of the second diode is connected to the high potential end of the third capacitor; and the first anode of the first diode is connected to the second cathode of the second diode.

4. Each of the plurality of first bootstrap circuits includes a first diode having a first cathode and a first anode, with the first cathode connected to the high potential end of the first capacitor; each of the plurality of second bootstrap circuits includes a second diode having a second cathode and a second anode, with the second cathode connected to the high potential end of the second capacitor; each of the plurality of third bootstrap circuits includes only the third capacitor; the first anode of the first diode of each of the plurality of first bootstrap circuits is connected to the high potential end of the third capacitor of a corresponding third bootstrap circuit of the plurality of third bootstrap circuits and to the cathode of a corresponding first auxiliary diode of the plurality of first auxiliary diodes, without passing through the second diode of a corresponding second bootstrap circuit of the plurality of second bootstrap circuits; and the second anode of the second diode of each of the plurality of second bootstrap circuits is 2. The switching element drive circuit according to claim 1, wherein the high potential end of the third capacitor of a corresponding one of the plurality of third bootstrap circuits is connected to the cathode of a corresponding one of the plurality of first auxiliary diodes.

5. The switching element drive circuit according to any one of claims 1 to 4, wherein the auxiliary circuit further includes an AND element having a plurality of input terminals and an output terminal, the plurality of input terminals being connected to the control device and the output terminal being connected to the fifth gate driver, and the plurality of second control signals are input to the plurality of input terminals of the AND element.

6. The switching element drive circuit according to any one of claims 1 to 5, wherein the control device generates the plurality of first control signals, the plurality of second control signals, the plurality of third control signals, and the plurality of fourth control signals by space vector modulation.

7. The switching element drive circuit according to any one of claims 1 to 5, wherein the control device generates the plurality of first control signals, the plurality of second control signals, the plurality of third control signals, and the plurality of fourth control signals by triangular wave PWM control.

8. The switching element drive circuit according to any one of claims 1 to 7, wherein the fifth switching element is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

9. The switching element drive circuit according to any one of claims 1 to 8, wherein the DC voltage source includes a DC-DC converter.

10. A power conversion device comprising: the switching element drive circuit according to any one of claims 1 to 9; and a plurality of diode-clamped three-level inverters.

11. The power conversion device according to claim 10, wherein each of the plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, and the plurality of fourth switching elements is an insulated gate bipolar transistor, a MOSFET, or a gate injection transistor.

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