Flexible circuit board, cof module, and electronic device comprising same

Abstract

A flexible circuit board according to one embodiment comprises: a substrate; a first wiring pattern portion disposed on the substrate; and a protective layer disposed on the first wiring pattern portion and including an open region, wherein the first wiring pattern portion includes a 1-1 wiring pattern portion including a plurality of first pads disposed in the open region, the plurality of first pads include alternately disposed 1-1 pads and 1-2 pads, the front ends of the 1-1 pads and the front ends of the 1-2 pads are not aligned on the same line, the 1-1 pads include first coupling portions adjacent to the front ends of the 1-1 pads and first extension portions extending from the first coupling portions, and the first coupling portions are wider than the first extension portions.

Description

Flexible circuit boards, COF modules and electronic devices including the same

[0001] The embodiments relate to a flexible circuit board, a COF module and an electronic device including the same.

[0002] Recently, various electronic products are becoming thinner and smaller. Consequently, there is a growing demand for high-density semiconductor chips to be mounted within the narrow spaces of these electronic products.

[0003] A COF (Chip-On-Film) includes a circuit board and a chip arranged on the circuit board. The circuit board is flexible, meaning that the COF is a flexible circuit board. Accordingly, the COF is applicable to flexible displays. For example, the COF can be applied to various wearable electronic devices. Furthermore, the COF has a fine pitch, meaning that the COF is applicable to high-resolution displays.

[0004] A chip includes a semiconductor chip. For example, the chip may be an integrated circuit (IC) chip or a large-scale integrated circuit (LSI) chip.

[0005] The chip is connected to an external circuit board and display panel through a circuit pattern. For example, pads are provided at one end and the other end of the circuit pattern. One pad is electrically connected to a terminal on the chip. The other pad is connected to a terminal on the external circuit board and display panel. Accordingly, the chip, the external circuit board, and the display panel are electrically connected through the COF. As a result, signals are transmitted to the display panel through the circuit pattern.

[0006] Recently, display panel specifications have been advancing toward higher resolution and higher integration, leading to a shrinking pitch between circuit patterns on flexible circuit boards. As the pitch between circuit patterns decreases, so too does the pitch between the pads connecting the chip, external circuit board, and display panel.

[0007] Accordingly, the width of the pads is adjusted while maintaining the pitch of each pad within a limited space.

[0008] At this time, if the width of the pads becomes narrower, the gap between the pads may increase, but the contact area between the pad and the adhesive material (e.g., solder ball) may decrease, making it difficult to achieve stable bonding with the chip, external circuit board, and display panel.

[0009] Furthermore, while increasing the width of the pads may increase the contact area between the pads and the adhesive, it may not secure sufficient process margins during the bonding process with the chip, external circuit board, and display panel. This increases the likelihood of defects depending on process capability, and further reduces product yield.

[0010] The embodiment provides a flexible circuit board having a novel pad structure, a COF module, and an electronic device including the same.

[0011] In addition, the embodiment provides a flexible circuit board, a COF module, and an electronic device including the same, which can secure a process margin in a bonding process while securing a contact area between a pad and an adhesive member.

[0012] Additionally, the embodiment provides a flexible circuit board, a COF module and an electronic device including the same with further improved electrical reliability.

[0013] In addition, the embodiment provides a flexible circuit board, a COF module, and an electronic device including the same, which can be subjected to various tests such as electrical reliability and performance.

[0014] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0015] A flexible circuit board according to an embodiment comprises: a substrate; a first wiring pattern portion disposed on the substrate; and a protective layer disposed on the first wiring pattern portion and including an open area, wherein the first wiring pattern portion includes a first-first wiring pattern portion including a plurality of first pads disposed within the open area, wherein the plurality of first pads include 1-1 pads and 1-2 pads that are alternately disposed, and a leading edge of the 1-1 pad and a leading edge of the 1-2 pad are not aligned on the same line, and the 1-1 pad includes a first coupling portion adjacent to a leading edge of the 1-1 pad, and a first extension portion extending from the first coupling portion, and a width of the first coupling portion is greater than a width of the first extension portion.

[0016] In addition, the 1-2 pad includes a second connecting portion adjacent to the tip of the 1-2 pad, and a second extension portion extending from the second connecting portion, wherein the first connecting portion does not overlap with the second connecting portion and the second extension portion along the separation direction of the 1-1 pad and the 1-2 pad, and the second connecting portion overlaps with the first extension portion along the separation direction.

[0017] Additionally, the width of the second connecting portion is smaller than the width of the first connecting portion.

[0018] Additionally, the width of the second connecting portion corresponds to the width of the first extension portion and the width of the second extension portion.

[0019] In addition, the first-first wiring pattern portion includes a plurality of second pads disposed adjacent to the first side end of the substrate and not covered with the protective layer; and a plurality of first connection patterns connecting between the plurality of first pads and the plurality of second pads, wherein the plurality of second pads include a second-first pad connected to the first-first pad and a second-second pad connected to the first-second pad, the second-first pad includes a third coupling portion and a third extension portion having a width smaller than a width of the third coupling portion, the second-second pad includes a fourth coupling portion and a fourth extension portion having a width smaller than a width of the fourth coupling portion, and the second-first pad and the second-second pad are alternately disposed such that the fourth coupling portion is located between the third coupling portions of two adjacent second-first pads.

[0020] In addition, the first wiring pattern portion includes a plurality of third pads arranged within the open area, a plurality of fourth pads arranged adjacent to the first side end of the substrate, and a second connection pattern connecting the plurality of third pads and the plurality of fourth pads and including a plurality of branch lines, wherein the second connection pattern connects the plurality of third pads and the plurality of fourth pads via the plurality of branch lines.

[0021] In addition, the plurality of third pads include third-1 pads and third-2 pads that are alternately arranged, and the leading edge of the third-1 pad and the leading edge of the third-2 pad are not aligned on the same line, and the third-1 pad includes a fifth connecting portion adjacent to the leading edge of the third-1 pad, and a fifth extension portion extending from the fifth connecting portion and having a width smaller than the width of the fifth connecting portion.

[0022] Additionally, the leading edges of the plurality of third pads are aligned on the same line, and the plurality of third pads include a region whose width increases from the leading edge of each of the plurality of third pads toward the second connection pattern.

[0023] In addition, the flexible circuit board further includes a second wiring pattern portion arranged on the substrate, the second wiring pattern portion including a plurality of fifth pads arranged in the open area, a plurality of sixth pads arranged adjacent to the second side end of the substrate and not covered by the protective layer, and a third connection pattern connecting the plurality of fifth pads and the plurality of sixth pads.

[0024] In addition, the plurality of fifth pads include a fifth-first pad and a fifth-second pad that are alternately arranged, and a leading edge of the fifth-first pad and a leading edge of the fifth-second pad are not aligned on the same line, and the fifth-first pad includes a ninth connecting portion adjacent to the leading edge of the fifth-first pad, and a ninth extension portion extending from the ninth connecting portion and having a width smaller than a width of the ninth connecting portion.

[0025] In addition, the plurality of sixth pads include 6-1 pads and 6-2 pads that are alternately arranged, the 6-1 pad includes an eleventh connecting portion and an eleventh extension portion having a width smaller than a width of the eleventh connecting portion, the 6-2 pad includes a twelfth connecting portion and a twelfth extension portion having a width smaller than a width of the twelfth connecting portion, and the 6-1 pads and the 6-2 pads are alternately arranged such that the twelfth connecting portion is positioned between the eleventh connecting portions of two adjacent 6-1 pads.

[0026] Additionally, the 6-1 pad and the 6-2 pad are arranged diagonally on the substrate.

[0027] In addition, the flexible circuit board further includes a third wiring pattern portion arranged on the substrate, the third wiring pattern portion including a plurality of seventh pads arranged adjacent to a first side end of the substrate and not covered with the protective layer, an eighth pad arranged adjacent to a second side end different from the first side end of the substrate and not covered with the protective layer, and a fourth connection pattern connecting the seventh pad and the eighth pad.

[0028] Additionally, the flexible circuit board further includes a first dummy pattern portion arranged on the substrate, the first dummy pattern portion including a plurality of ninth pads arranged in the open area, and a fifth connection pattern connected to the plurality of ninth pads and having a tip covered with the protective layer.

[0029] Additionally, the flexible circuit board further includes a second dummy pattern portion disposed on the substrate, the second dummy pattern portion including a tenth pad disposed adjacent to a first end of the substrate and not covered with the protective layer, and a sixth connection pattern connected to the tenth pad and having a tip covered with the protective layer.

[0030] In addition, the flexible circuit board further includes a third dummy pattern portion arranged on the substrate, the third dummy pattern portion including an 11th pad arranged adjacent to a second side end of the substrate and not covered with the protective layer, and a seventh connection pattern connected to the 11th pad and having a tip covered with the protective layer.

[0031] Meanwhile, according to another embodiment, a flexible circuit board includes a substrate; a wiring pattern portion disposed on the substrate; and a protective layer disposed on the wiring pattern portion and including a first open area and a second open area, wherein the wiring pattern portion includes a first wiring pattern portion including a plurality of first wiring patterns, at least a portion of which is disposed within the first open area and the second open area and spaced apart from each other, and wherein the first wiring pattern portion includes a first test pattern connected to at least one first wiring pattern among the plurality of first wiring patterns, wherein the first test pattern does not overlap the first open area and the second open area along a thickness direction of the substrate.

[0032] Additionally, the plurality of first wiring patterns include a 1-1 wiring pattern that is not connected to the first test pattern, and a 1-2 wiring pattern that is connected to the first test pattern.

[0033] In addition, the 1-1 wiring pattern includes a 1-1 inner pad arranged in the first open area, a 1-1 outer pad arranged in the second open area, and a 1-1 wiring line connecting the 1-1 inner pad and the 1-1 outer pad, the 1-2 wiring pattern includes a 1-2 inner pad arranged in the first open area, a 1-2 outer pad arranged in the second open area, and a 1-2 wiring line connecting the 1-2 inner pad and the 1-2 outer pad, and the first test pattern includes a first test connection line extending from the 1-2 wiring line, and a first test pad connected to the first test connection line.

[0034] Additionally, the gap between the 1-1 wiring line closest to the 1-2 wiring line and the 1-2 wiring line is smaller than the width of the 1-2 wiring line.

[0035] Additionally, the spacing between the 1-1 wiring line closest to the 1-2 wiring line and the 1-2 wiring line has a range of 5 μm to 20 μm.

[0036] Additionally, the width of the above 1-2 wiring line is greater than the width of the above 1-1 wiring line.

[0037] Additionally, the width of the first-second wiring line has a range of 1.2 to 15 times the width of the first-first wiring line.

[0038] Additionally, the length of the first test connection line is smaller than the width of the first test pad and larger than the gap between the 1-1 wiring line closest to the 1-2 wiring line and the 1-2 wiring line.

[0039] Additionally, the length of the first test connection line has a range of 5% to 60% of the width of the first test pad.

[0040] Additionally, the length of the first test connection line has a range of 2 to 20 times the distance between the 1-1 wiring line closest to the 1-2 wiring line and the 1-2 wiring line.

[0041] Additionally, the width of the first test connection line has a range of 1.2 to 15 times the width of the first-1 wiring line.

[0042] In addition, the first test connection line includes a first portion connected to the first-second wiring line, and a second portion connected to the first test pad, and at least one of the first portion and the second portion of the first test connection line has a curved surface having a specific curvature along an extension direction.

[0043] Additionally, the first test connection line and the first test pad are entirely covered with the protective layer.

[0044] Additionally, the protective layer further includes a third open area, and the wiring pattern portion further includes a second wiring pattern portion including a plurality of second wiring patterns, at least some of which are disposed within the first open area and the third open area and spaced apart from each other, and the second wiring pattern portion includes a second test pattern connected to at least one second wiring pattern among the plurality of second wiring patterns.

[0045] In addition, the wiring pattern portion further includes a third wiring pattern portion including a plurality of third wiring patterns, at least some of which are disposed within the second open area and the third open area and spaced apart from each other, and the third wiring pattern portion includes a third test pattern connected to at least one third wiring pattern among the plurality of third wiring patterns.

[0046] In addition, either one of the first wiring pattern portion and the second wiring pattern portion further includes an upper wiring disposed on an upper surface of the substrate, a lower wiring disposed on a lower surface of the substrate, and a via penetrating the upper surface and the lower surface of the substrate and connecting between the upper wiring and the lower wiring, and the first test pattern or the second test pattern is connected to the upper wiring or the lower wiring.

[0047] In addition, the flexible circuit board further includes a dummy pattern portion disposed on the substrate and electrically separated from the first wiring pattern portion and the second wiring pattern portion, wherein the dummy pattern portion includes at least one of first to third dummy pattern portions, wherein the first dummy pattern portion includes a first dummy pad disposed in the first open area, a first dummy wiring line connected to the first dummy pad, and a first dummy test pad connected to one end of the first dummy wiring line, the second dummy pattern portion includes a second dummy pad disposed in the second open area, a second dummy wiring line connected to the second dummy pad, and a second dummy test pad connected to one end of the second dummy wiring line, and the third dummy pattern portion includes a third dummy pad disposed in the third open area, a third dummy wiring line connected to the third dummy pad, and a third dummy test pad connected to one end of the third dummy wiring line.

[0048]

[0049] The embodiment includes a conductive pattern portion arranged on a substrate. The conductive pattern portion includes inner pads arranged in a chip mounting area. At this time, the inner pads include first inner pads and second inner pads that are alternately arranged. In addition, the leading edge of the first inner pad is not aligned with the leading edge of the second inner pad. For example, the leading edge of the first inner pad and the leading edge of the second inner pad may be arranged in a zigzag shape.

[0050] At this time, the width of the joint portion of the first inner pad is larger than the width of the extension portion. That is, the joint portion of the first inner pad does not overlap with the second inner pad. Accordingly, in the embodiment, the spacing between adjacent joint portions in the area where the first inner pad is arranged can correspond to the spacing between the joint portions of adjacent first inner pads. Accordingly, in the embodiment, the joint portion of the first inner pad has a width larger than the width of the joint portion of the second inner pad. Through this, the embodiment can improve the contact area between the joint portion of the first inner pad and the contact member, thereby enabling the chip to be stably mounted on the joint portion of the first inner pad. Furthermore, since the joint portion of the second inner pad adjacent to the joint portion of the first inner pad does not exist, the spacing between the joint portions of the plurality of first inner pads can be maintained at a certain level or more. Accordingly, in the embodiment, even if the width of the joint portion of the first inner pad is increased, the process margin can be secured in the process of mounting the chip, thereby improving the product yield.

[0051] In addition, the width of the joint portion of the second inner pad may be different from the width of the joint portion of the first inner pad. For example, the width of the joint portion of the second inner pad may be smaller than the width of the joint portion of the first inner pad, and may correspond to the width of the extension portions of each of the first and second inner pads. That is, the joint portion of the second inner pad is located between the extension portions of the adjacent first inner pad. Through this, in the embodiment, the joint portion of the second inner pad has a relatively smaller width than the joint portion of the first inner pad. Therefore, the embodiment can maintain the gap between the joint portion of the second inner pad and the extension portion of the first inner pad at a certain level or more. Accordingly, the embodiment can secure a process margin in the process of mounting a chip, and thus can improve the product yield.

[0052] The embodiment forms a test pattern on at least one of the wiring lines of the conductive pattern portion. The test pattern may be covered with a protective layer. Accordingly, the embodiment can enable probing of a probe pin for testing using the test pattern after manufacturing the flexible circuit board.

[0053] Accordingly, the embodiment can test the electrical reliability of the conductive pattern portion even after the flexible circuit board is manufactured or after the chip and / or display panel and the external circuit board are connected, and further can test the performance of the chip, the display panel, and the external circuit board.

[0054] Therefore, the embodiment can improve the electrical reliability of a flexible circuit board. This allows the embodiment to enable the flexible circuit board and the COF module including the flexible circuit board to operate more stably. Consequently, product reliability can be improved.

[0055] Additionally, the conductive pattern portion includes a wiring pattern portion and a dummy pattern portion. Furthermore, test patterns may be provided not only in the wiring pattern portion but also in the dummy pattern portion. Therefore, the embodiment can more easily test the performance of chips, display panels, and external circuit boards.

[0056] Additionally, the embodiment can arrange the wiring pattern equipped with the test pattern among each wiring pattern to be positioned further outward than the other wiring patterns. Accordingly, the embodiment can arrange the test pattern without affecting the line width and / or spacing of the wiring patterns. Therefore, the embodiment can further improve product reliability.

[0057] Additionally, the wiring lines connected to the test pattern are wider than the other wiring lines. This facilitates easier testing. Furthermore, the rigidity of the flexible circuit board can be improved. Therefore, the embodiment can improve the electrical reliability of the flexible circuit board. Consequently, the embodiment can enable the flexible circuit board and the COF module including it to operate more stably. Consequently, product reliability can be improved.

[0058] Furthermore, the test pattern includes a test pad connected to a wiring line and a test connection line positioned between the test pad and the wiring line. The test connection line may have a width smaller than the test pad and may connect the test pad and the wiring line. Therefore, the embodiment can further improve the electrical reliability of the flexible circuit board.

[0059] Specifically, in a process of exposing and developing a dry film for forming a wiring pattern portion, it is difficult to control the flow rate of the developer in the area where the test pad is placed, and thus, overdevelopment may occur due to rapid movement of the developer. This may result in an electrical short circuit in which adjacent wiring patterns are electrically connected to each other. Therefore, the embodiment places a test connection line between the test pad and the wiring line. The test connection line can prevent overdevelopment due to the flow rate of the developer, and thus prevent reliability problems such as electrical open and / or electrical short circuit from occurring in the process of forming wiring patterns.

[0060] FIG. 1a and FIG. 1b are schematic plan views showing a flexible circuit board according to the first embodiment.

[0061] Figure 2 is an enlarged plan view of the first region (R1) of Figure 1B.

[0062] Figure 3 is an enlarged plan view of the second region (R2) of Figure 1B.

[0063] Figure 4 is a drawing showing a modified example of Figure 3.

[0064] FIG. 5 is an enlarged plan view of the third area (R3) of FIG. 1B according to the first embodiment.

[0065] FIG. 6 is an enlarged plan view of the third area (R3) of FIG. 1B according to the second embodiment.

[0066] Figure 7 is an enlarged plan view of the fourth region (R4) of Figure 1B.

[0067] Figure 8 is an enlarged plan view of the fifth region (R5) of Figure 1B.

[0068] Figure 9 is an enlarged plan view of the sixth region (R6) of Figure 1B.

[0069] Figure 10 is an enlarged plan view of the seventh region (R7) of Figure 1B.

[0070] Figure 11 is an enlarged plan view of the 8th area (R8) of Figure 1B.

[0071] Fig. 12 is an enlarged plan view of the first dummy pattern section according to the embodiment.

[0072] Fig. 13 is a cross-sectional view showing the layer structure of a conductive pattern portion according to the first embodiment.

[0073] Fig. 14 describes the layer structure of the conductive pattern portion according to the second embodiment.

[0074] FIGS. 15a and 15b are schematic plan views of a flexible circuit board according to a third embodiment.

[0075] Figure 16 is an enlarged plan view of the first region (R1) of Figure 15b.

[0076] Fig. 17a is an enlarged plan view of the first region (R1) of Fig. 15b according to the first comparative example.

[0077] Fig. 17b is an enlarged plan view of the first region (R1) of Fig. 15b according to the second comparative example.

[0078] Fig. 18 is an enlarged plan view of the second region (R2) of Fig. 15b according to an embodiment.

[0079] Fig. 19 is an enlarged plan view of the third region (R3) of Fig. 15b according to an embodiment.

[0080] Fig. 20 is an enlarged plan view of a portion of the first dummy pattern portion illustrated in Fig. 15b.

[0081] Fig. 21 is an enlarged plan view of a portion of the second dummy pattern portion illustrated in Fig. 15b.

[0082] Fig. 22 is an enlarged plan view of a portion of the third dummy pattern portion illustrated in Fig. 15b.

[0083] Fig. 23 is an enlarged plan view of the first region (R1) of Fig. 15b according to the fourth embodiment.

[0084] FIG. 24a, FIG. 24b and FIG. 25 are schematic plan views of a flexible circuit board according to the fourth embodiment.

[0085] FIGS. 26 and 27 are drawings for explaining the connection of a COF module and other members according to an embodiment.

[0086] FIGS. 28 to 30 are drawings of electronic devices including flexible circuit boards according to embodiments.

[0087] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0088] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0089] In addition, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0090] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0091] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0092] Additionally, when described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0093] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0094]

[0095] Below, with reference to the drawings, a flexible circuit board and a COF module including the same according to an embodiment are described.

[0096]

[0097] FIG. 1A and FIG. 1B are schematic plan views of a flexible circuit board according to a first embodiment. Specifically, FIG. 1A is a schematic plan view of one side of a flexible circuit board according to the first embodiment with a protective layer removed, and FIG. 1B is a schematic plan view of one side of a flexible circuit board according to the first embodiment with a protective layer disposed thereon.

[0098] Referring to FIGS. 1A and 1B, a flexible circuit board (1000) according to the first embodiment includes a substrate (100), a conductive pattern portion (CP), a dummy pattern portion (DP), and a protective layer (800).

[0099] The substrate (100) includes one side and a second side opposite to the first side. In this case, the first side of the substrate (100) may refer to the upper side of the substrate (100) on which the conductive pattern portion (CP), the dummy pattern portion (DP), and the protective layer (800) are arranged. The second side of the substrate (100) may refer to the lower side of the substrate (100).

[0100] A conductive pattern portion (WP, DP) and a protective layer (800) are arranged on one side of the substrate (100).

[0101] The substrate (100) may not represent the final manufactured flexible circuit board (1000). For example, the final manufactured flexible circuit board (1000) may not include some areas of the substrate (100) illustrated in FIGS. 1A and 1B. For example, some areas of the substrate (100) illustrated in FIGS. 1A and 1B may be removed by cutting along a cutting line.

[0102] For example, a conductive pattern portion (WP, DP), a protective layer (800), and a chip (not shown) are arranged on a substrate (100). Thereafter, the substrate (100) can be cut based on a cutting line, and a COF module can be manufactured accordingly. Accordingly, the perimeter of the final manufactured COF module can correspond to the cutting line of the substrate (100) in FIGS. 1A and 1B. In addition, a conductive pattern portion (WP, DP) and a protective layer (800) that are located outside the cutting line and are removed may be provided on the substrate (100), but FIGS. 1A and 1B may only show the conductive pattern portion (WP, DP) and the protective layer (800) located inside the cutting line.

[0103] The substrate (100) includes an effective area (AA) and an ineffective area (UA). In detail, one side of the substrate (100) includes an effective area (AA) and an ineffective area (UA) excluding the effective area (AA).

[0104] The valid area (AA) and the invalid area (UA) are separated by a cutting line. The valid area (AA) is the inner area of ​​the area separated by the cutting line. The invalid area (UA) is the outer area of ​​the area separated by the cutting line.

[0105] A conductive pattern portion (WP, DP), a protective layer (800), and a chip (not shown) may be arranged on the active area (AA). In addition, a dummy pattern (not shown) and a sprocket hole (SH) may be provided on the inactive area (UA). The dummy pattern provided on the inactive area (UA) increases the strength of the substrate (100).

[0106] Additionally, the flexible circuit board (1000) can be manufactured by being rolled or unrolled in a roll-to-roll manner by means of a sprocket hole (SH).

[0107] The substrate (100) includes a chip mounting area (CHA). The chip mounting area (CHA) may be provided on one surface of the substrate (100). The chip mounting area (CHA) may be located in the effective area (AA) of the substrate (100). A chip (not shown) may be mounted on the chip mounting area (CHA). At this time, the pads of the conductive pattern portion (WP, DP) may be located within the chip mounting area (CHA).

[0108] The protective layer (800) may not be disposed on the chip mounting area (CHA). For example, the protective layer (800) may include a first open area (OR) that overlaps the chip mounting area (CHA) in a vertical direction. The planar area of ​​the first open area (OR) of the protective layer (800) may be larger than the planar area of ​​the chip mounting area (CHA). For example, the perimeter of the inner surface of the first open area (OR) of the protective layer (800) may be provided to surround the chip mounting area (CHA) at a position spaced apart from the chip mounting area (CHA). Through this, the process characteristics in the process of mounting a chip on the chip mounting area (CHA) can be improved, and the chip can be mounted more stably.

[0109] The protective layer (800) may further include a second open area and a third open area. That is, the substrate (100) may include a substrate connection area (not shown) to which an external circuit board is connected. In addition, the substrate (100) may include a panel connection area (not shown) to which a display panel is connected. For example, the substrate (100) may include a first side end (110E1) and a second side end (110E2) facing each other in a first direction (1D). In addition, the substrate (100) may include a substrate area provided in an area adjacent to the first side end (110E1). In addition, the substrate (100) may include a panel connection area provided in an area adjacent to the second side end (110E2).

[0110] The protective layer (800) may not be disposed on the substrate connection area. That is, the protective layer (800) may include a second open area that overlaps the substrate connection area in a vertical direction. In addition, the protective layer (800) may not be disposed on the panel connection area. That is, the protective layer (800) may include a third open area that overlaps the panel connection area in a vertical direction.

[0111] The substrate (100) includes a flexible material. For example, the substrate (100) may include polyimide (PI). However, the embodiment is not limited thereto. The substrate (100) may include a polymer material including polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board (1000) can be applied to various electronic devices, including curved display devices.

[0112] The substrate (100) may have a thickness of 20 μm to 100 μm. For example, the substrate (100) may have a thickness of 25 μm to 50 μm. For example, the substrate (100) may have a thickness of 30 μm to 40 μm. If the thickness of the substrate (100) exceeds 100 μm, the overall thickness of the flexible circuit board increases. As a result, the flexible characteristics of the flexible circuit board (1000) may be degraded. In addition, if the thickness of the substrate (100) is less than 20 μm, the substrate (100) may be damaged by heat and pressure applied during the process of mounting a chip on the flexible circuit board (1000).

[0113] The conductive pattern portion (WP, DP) and the protective layer (800) are disposed on the substrate (100). The conductive pattern portion (CP), the circuit pattern, and the protective layer (800) are disposed on one surface of the substrate (100). For example, the conductive pattern portion (WP, DP) and the protective layer (800) may be disposed on the effective area (AA) of the substrate (100). In addition, the conductive pattern portion (WP, DP) and the protective layer (800) may be selectively disposed on the uneffective area (UA) of the substrate (100).

[0114] The conductive pattern portion (WP, DP) may include a wiring pattern portion (WP) and a dummy pattern portion (DP) depending on the function. The wiring pattern portion (WP) and the dummy pattern portion (DP) may include the same metal material. The wiring pattern portion (WP) and the dummy pattern portion (DP) may have the same layer structure. Here, the wiring pattern portion (WP) and the dummy pattern portion (DP) may be distinguished depending on whether a valid signal is transmitted. Alternatively, the wiring pattern portion (WP) and the dummy pattern portion (DP) may be distinguished depending on whether a signal is transmitted and / or received between a plurality of components.

[0115] The wiring pattern portion (WP) may refer to a conductive pattern through which a valid signal is transmitted. Here, the valid signal may include a control signal transmitted to control a specific component, a signal acquired from a specific component, and / or a power signal. In addition, the wiring pattern portion (WP) may refer to a conductive pattern through which signals are transmitted and / or received between a plurality of components. For example, the wiring pattern portion (WP) may electrically connect between a chip and an external circuit board, between a chip and a display panel, or between an external circuit board and a display panel.

[0116] The dummy pattern portion (DP) may refer to a conductive pattern through which no valid signal is transmitted. Alternatively, the dummy pattern portion (DP) may refer to a conductive pattern that is not electrically connected between a plurality of components. For example, the dummy pattern portion (DP) may refer to a conductive pattern through which a valid signal (e.g., a test signal, etc.) is transmitted, but which does not electrically connect between a chip and an external circuit board, or between a chip and a display panel, or between an external circuit board and a display panel. For example, the dummy pattern portion (DP) may be electrically connected to one of the components among the chip, the external circuit board, and the display panel, but not electrically connected to the other components. The dummy pattern portion (DP) may refer to a conductive pattern that performs at least one of a test function, a dummy function, a heat dissipation function, and a rigidity reinforcement function.

[0117] At least one of the wiring pattern portion (WP) and the dummy pattern portion (DP) may include pads arranged within the open area (OR) of the protective layer (800). In this case, the pads arranged within the open area (OR) of the protective layer (800) may be referred to as inner pads. In addition, at least one of the wiring pattern portion (WP) and the dummy pattern portion (DP) may include pads that are arranged between the first side end of the protective layer (800) and the first side end of the substrate (100) and are not covered by the protective layer (800), which may be referred to as first outer pads. In addition, at least one of the wiring pattern portion (WP) and the dummy pattern portion (DP) may include pads that are arranged between the second side end of the protective layer (800) and the second side end of the substrate (100) and are not covered by the protective layer (800), which may be referred to as second outer pads.

[0118] The wiring pattern section (WP) may include a first wiring pattern section (200), a second wiring pattern section (300), and a third wiring pattern section (400) depending on the placement location and / or function.

[0119] The first wiring pattern portion (200) may have one end positioned within the first open area (OR) of the protective layer (800) and the other end positioned within the second open area of ​​the protective layer (800). For example, one end of the first wiring pattern portion (200) may be connected to a chip, and the other end of the first wiring pattern portion (200) may be connected to an external circuit board. That is, the first wiring pattern portion (200) may refer to a wiring pattern that electrically connects between a chip and an external circuit board. For example, the first wiring pattern portion (200) may include a first pad positioned within the first open area (OR), a second pad positioned within the second open area, and a connection wiring connecting the first pad and the second pad.

[0120] The first wiring pattern section (200) may include a first-first wiring pattern section (210) and a first-second wiring pattern section (220) depending on the arrangement structure and / or connection structure. The first-first wiring pattern section (210) may be arranged such that one connection wire connects between one first pad and one second pad. The first-second wiring pattern section (220) may be arranged such that one connection wire connects between a plurality of first pads and / or a plurality of second pads.

[0121] For example, the number of interconnected connection wires, first pads, and second pads may be the same in the first-1 wiring pattern section (210). For example, the number of interconnected connection wires, first pads, and second pads may be different in the first-2 wiring pattern section (220). For example, the first-2 wiring section (220) may have one connection pattern connect two or more first pads and one second pad. Alternatively, the first-2 wiring section (220) may have one connection pattern connect one first pad and two or more second pads. Alternatively, the first-2 wiring section (220) may have one connection pattern connect two or more first pads and two or more second pads.

[0122] The first-first wiring pattern portion (210) may include a first pad (210P1) disposed within a first open area (OR). The first pad (210P1) of the first-first wiring pattern portion (210) may be connected to a chip. The first-first wiring pattern portion (210) may include a second pad (210P2) disposed within a second open area. The second pad (210P2) of the first-first wiring pattern portion (210) may be connected to an external circuit board. The first-first wiring pattern portion (210) may include a first connection pattern (210T) connecting the first pad (210P1) and the second pad (210P2). The first connection pattern (210T) of the first-first wiring pattern portion (210) may be covered with a protective layer (800). At this time, the first connection pattern (210T) of the 1-1 wiring pattern portion (210) may further include an area that is not covered by the protective layer (800). For example, the first connection pattern (210T) of the 1-1 wiring pattern portion (210) may include a first portion that is connected to the first pad (210P1) of the 1-1 wiring pattern portion (210) and positioned within the first open area (OR) of the protective layer (800). In addition, the first connection pattern (210T) of the 1-1 wiring pattern portion (210) may include a second portion that is connected to the second pad (210P2) of the 1-1 wiring pattern portion (210) and positioned within the second open area of ​​the protective layer (800).

[0123] In addition, the 1-1 wiring pattern section (210) may include a plurality of 1-1 wiring patterns that are spaced apart from each other and arranged on the substrate (100) and include the first pad (210P1), the second pad (210P2) and the first connection pattern (210T) described above.

[0124] The first-second wiring pattern portion (220) may include a plurality of third pads (220P1) that are arranged within the first open area (OR) and spaced apart from each other. The plurality of third pads (220P1) of the first-second wiring pattern portion (220) may be respectively connected to different terminals of the chip. The first-second wiring pattern portion (220) may include a plurality of fourth pads (220P2) that are arranged within the second open area. The plurality of fourth pads (220P2) of the first-second wiring pattern portion (220) may be connected to an external circuit board. The first-second wiring pattern portion (220) may include a second connection pattern (220T) that connects the plurality of third pads (220P1) of the first-second wiring pattern portion (220) and the plurality of fourth pads (220P2) of the first-second wiring pattern portion (220). That is, the second connection pattern (220T) of the 1-2 wiring pattern portion (220) may include a plurality of branch lines at least one of a plurality of ends and the other ends. In addition, the plurality of branch lines of the second connection pattern (220T) provided at one end of the 1-2 wiring pattern portion (220) may be connected to a plurality of third pads (220P1) of the 1-2 wiring pattern portion (220). In addition, the plurality of branch lines of the second connection pattern (220T) provided at the other end of the 1-2 wiring pattern portion (220) may be connected to a plurality of fourth pads (220P2) of the 1-2 wiring pattern portion (220).

[0125] Additionally, the first-second wiring pattern portion (220) may include a plurality of first-second wiring patterns, each of which is spaced apart from each other and includes the third pad (220P1), the fourth pad (220P2) described above, and a second connection pattern (220T) including a plurality of branch lines.

[0126] The second wiring pattern portion (300) may have one end positioned within the first open area (OR) of the protective layer (800) and the other end positioned within the third open area of ​​the protective layer (800). For example, one end of the second wiring pattern portion (300) may be connected to the chip, and the other end of the second wiring pattern portion (300) may be connected to the display panel. That is, the second wiring pattern portion (300) may refer to a wiring pattern that electrically connects the chip and the display panel. For example, the second wiring pattern portion (300) may include a fifth pad (310P1, 320P1) positioned within the first open area (OR), a sixth pad (310P2, 320P2) positioned within the third open area, and a third connection wire (310T, 320T) connecting them.

[0127] The second wiring pattern portion (310) may include a 2-1 wiring pattern portion (310) and a 2-2 wiring pattern portion (320) depending on the location. The 2-1 wiring pattern portion (310) may be provided with a fifth pad (310P1) above the first open area (OR), and the 2-2 wiring pattern portion (320) may be provided with a fifth pad (32OP1) below the first open area (OR). In addition, the third connection wire (310T) of the 2-1 wiring pattern portion (310) may be arranged toward the second side end (110E2) of the substrate (100) above the first open area (OR) and connected to the 6th pad (310P2) of the 2-1 wiring pattern portion (310). In addition, the third connection wire (320T) of the 2-2 wiring pattern portion (320) can be arranged to avoid other wiring patterns or dummy pattern portions (DP) on the lower side of the first open area (OR) and connected to the 6th pad (320P2) of the 2-2 wiring pattern portion (320).

[0128] The third wiring pattern portion (400) may have one end positioned within the second open area of ​​the protective layer (800) and the other end positioned within the third open area of ​​the protective layer (800). For example, one end of the third wiring pattern portion (400) may be connected to an external circuit board, and the other end of the third wiring pattern portion (400) may be connected to a display panel. That is, the third wiring pattern portion (400) may refer to a wiring pattern that electrically connects between the external circuit board and the display panel. For example, the third wiring pattern portion (400) may include a seventh pad (400P1) positioned within the second open area, an eighth pad (400P2) positioned within the third open area, and a fourth connection wire (400T) connecting the seventh pad (400P1) and the eighth pad (400P2).

[0129] Additionally, the third wiring pattern section (400) may include a plurality of third wiring patterns spaced apart from each other, each including the seventh pad (400P1), the eighth pad (400P2) and the fourth connection wiring (400T) described above.

[0130] The third wiring pattern portion (400) may be a bypass wiring pattern. For example, the third wiring pattern portion (400) may be a power wiring line. Accordingly, the external circuit board and display panel may receive power through the third wiring pattern portion (400).

[0131] The line width of the third wiring pattern portion (400) may be larger than the line widths of the first and second wiring pattern portions (300, 400). This can enable a stable power supply.

[0132] The first dummy pattern portion (500) may have one end positioned in the first open area (OR) and the other end covered with a protective layer (800). For example, one end of the first dummy pattern portion (500) may be connected to a chip, and the other end may not be electrically connected to other components.

[0133] The first dummy pattern portion (500) may include a ninth pad (510P, 520P, 530P) positioned within the first open area (OR), and a fifth connecting wire (510T, 520T, 530T) connected to the ninth pad (510P, 520P, 530P).

[0134] The first dummy pattern section (500) may include a first-first dummy pattern section (510), a first-second dummy pattern section (520), and a first-third dummy pattern section (530) depending on the location.

[0135] The ninth pad (510P) of the 1-1 dummy pattern portion (510) may be located on the lower side of the first open area (OR), and the fifth connection wire (510T) of the 1-1 dummy pattern portion (510) may be connected to the ninth pad (510P) and extend in a direction toward the first side end (110E1) of the substrate (100).

[0136] The ninth pad (520P) of the first-second dummy pattern portion (520) may be located on the left side of the first open area (OR), and the fifth connection wire (520T) of the first-second dummy pattern portion (520) may be extended in a direction toward the left end of the substrate (100) while being connected to the ninth pad (520P).

[0137] The ninth pad (530P) of the 1-3 dummy pattern portion (530) may be located on the right side of the first open area (OR), and the fifth connection wire (530T) of the 1-3 dummy pattern portion (530) may be extended in a direction toward the right end of the substrate (100) while being connected to the ninth pad (530P).

[0138] The first dummy pattern section (500) described above is connected to the chip and can be used for testing a specific terminal of the chip or can have a heat dissipation function to transfer heat generated from the chip.

[0139] The second dummy pattern portion (600) may have one end positioned in the second open area, and the other end covered with a protective layer (800). For example, one end of the second dummy pattern portion (600) may be connected to an external circuit board, and the other end may not be electrically connected to other components.

[0140] The second dummy pattern portion (600) may include a tenth pad (610P) positioned within the second open area, and a sixth connection wire (610T) connected to the tenth pad (610P).

[0141] The second dummy pattern section (600) described above can be connected to an external circuit board and used for testing a specific signal line of the external circuit board or can have a heat dissipation function to transfer heat generated from the external circuit board.

[0142] The third dummy pattern portion (700) may have one end positioned in the third open area, and the other end covered with a protective layer (800). For example, one end of the third dummy pattern portion (700) may be connected to an external circuit board, and the other end may not be electrically connected to other components.

[0143] The third dummy pattern portion (700) may include an eleventh pad (710P) positioned within the second open area, and a seventh connection wire (710T) connected to the eleventh pad (710P).

[0144] The third dummy pattern section (700) described above is connected to the display panel and can be used for testing a specific signal line of the display panel or can have a heat dissipation function to transfer heat generated from the display panel.

[0145] In addition, the dummy pattern portion (DP) described above can have a reinforcing function, thereby preventing the flexible circuit board (1000) from bending. In addition, the line width and spacing of the wiring pattern portion (WP) can be made uniform by the dummy pattern portion (DP).

[0146] The protective layer (800) may be disposed on the substrate (100) and may include a plurality of open areas. For example, the protective layer (800) may include a first open area (OR). The first open area (OR) may overlap the chip mounting area (CHA) in a vertical direction.

[0147] The protective layer (800) may include a second open area and a third open area. In this case, the second open area and the third open area may be intentionally formed open areas, or alternatively, may be areas formed by not placing the protective layer (800) in the corresponding areas.

[0148] For example, the lower end of the protective layer (800) may be located further inward than the first side end (110E1) of the substrate (100). Accordingly, a second open area may be provided between the lower end of the protective layer (800) and the first side end (110E1) of the substrate (100).

[0149] Additionally, the upper end of the protective layer (800) may be positioned further inward than the second side end (110E2) of the substrate (100). Accordingly, a third open area may be provided between the upper end of the protective layer (800) and the second side end (110E2) of the substrate (100).

[0150]

[0151] Figure 2 is an enlarged plan view of the first region (R1) of Figure 1B.

[0152] Referring to FIG. 2, the first-first wiring pattern portion (210) includes a first pad (210P1) that is placed in the chip mounting area (CHA) and connected to the chip.

[0153] At this time, the 1-1 wiring pattern section (210) may include a plurality of 1-1 wiring patterns spaced apart from each other along the horizontal direction. Each of the plurality of 1-1 wiring patterns may be arranged to extend long in the first direction (D1). In addition, the plurality of 1-1 wiring patterns may be arranged to be spaced apart from each other in the second direction (D2). At this time, the plurality of 1-1 pattern patterns may have different lengths and may be arranged alternately in the first and second rows.

[0154] For example, the 1-1 wiring pattern section (210) may include a plurality of 1-1 pads (P11) spaced apart and arranged in the first direction (D1). For example, the 1-1 pads (P11) may be arranged in odd or even rows.

[0155] Additionally, the first-first wiring pattern portion (210) may include a plurality of first-second pads (P12) arranged between a plurality of first-first pads (P11). For example, the first-second pads (P12) may be arranged in a different column from the first-first pads (P11). For example, the first-second pads (P12) may be arranged in an even column or an odd column.

[0156] For example, the 1-1 pad (P11) may be placed in the 1st, 3rd, 5th, and 7th rows, and the 1-2 pad (P12) may be placed in the 2nd, 4th, and 6th rows. In other words, the 1-1 pad (P11) and the 1-2 pad (P12) may be placed alternately.

[0157] At this time, the first-first pad (P11) and the first-second pad (P12) may have different lengths. For example, the respective tips of the first-first pad (P11) and the first-second pad (P12) may be provided at different positions. For example, the tip of the first-first pad (P11) may be located further inside the substrate (100) than the end of the first-second pad (P12). The tips of the first-first pad (P11) and the first-second pad (P12) may be formed in a zigzag shape and positioned at different positions.

[0158] Accordingly, the plurality of first-first pads (P11) may not overlap with the first-second pads (P12) along the second direction (D2). In contrast, the plurality of first-second pads (P12) may overlap with the plurality of first-first pads (P11) along the second direction (D2).

[0159] At this time, the planar shape of the plurality of first-1 pads (P11) may be different from the planar shape of the plurality of first-2 pads (P12). For example, the plurality of first-1 pads (P11) may include a region in which the line width changes along the first direction (D1), which is the longitudinal direction. In contrast, the plurality of first-2 pads (P12) may not have the line width change along the first direction (D1).

[0160] For example, the plurality of first-1 pads (P11) may include a region having a line width greater than the line width of the plurality of first-2 pads (P12).

[0161] That is, the 1-1 pad (P11) may include a first coupling portion (P11-1) and a first extension portion (P11-2) extending from the first coupling portion (P11-1). The first coupling portion (P11-1) of the 1-1 pad (P11) may refer to an area coupled to a terminal of the chip. In addition, the first extension portion (P11-2) of the 1-1 pad (P11) may connect between the first coupling portion (P11-1) and the connection pattern (T1) of the 1-1 pad (P11).

[0162] The line width (W1) of the first connecting portion (P11-1) may be different from the line width (W2) of the first extension portion (P11-2). Preferably, the line width (W1) of the first connecting portion (P11-1) may be greater than the line width (W2) of the first extension portion (P11-2).

[0163] That is, the first coupling portion (P11-1) does not overlap with the first-second pad (P12) along the second direction (D1). For example, the first-second pad (P12) may not be arranged on the left and right sides of the first coupling portion (P11-1). Accordingly, the spacing between adjacent coupling portions in the area where the first coupling portion (P11-1) is arranged may correspond to the spacing between adjacent first coupling portions. Accordingly, in the embodiment, even if the line width (W1) of the first coupling portion (P11-1) is increased in the area where the first coupling portion (P11-1) is arranged, there may be room in the spacing between adjacent coupling portions.

[0164] Accordingly, the embodiment allows the line width (W1) of the first bonding portion (P11-1) to have a relatively larger line width than the line widths of the other bonding portions. Through this, the embodiment can improve the contact area between the first bonding portion (P11-1) and the contact member, thereby enabling the chip to be stably mounted on the first bonding portion (P11-1). Furthermore, since the second bonding portion (P12-1) of the first-second pad (P12) adjacent to the first bonding portion (P11-1) does not exist, the spacing between the plurality of first bonding portions (P11-1) can be maintained at a certain level or more. Accordingly, the embodiment can secure a process margin in the process of mounting the chip even if the line width (W1) of the first bonding portion (P11-1) is increased, thereby improving the product yield. Here, the process margin may mean the alignment tolerance between the first joint (P11-1) and the terminal of the chip in the process of mounting the chip.

[0165] The line width (W2) of the first extension portion (P11-2) may be smaller than the line width (W1) of the first bonding portion (P11-1). This is because the first extension portion (P11-2) is arranged to overlap the second bonding portion (P12-1) of the adjacent 1-2 pad (P12) along the second direction (D2). That is, when the line width (W2) of the first extension portion (P11-2) increases, the gap between the first extension portion (P11-2) of the 1-1 pad (P11) and the second bonding portion (P12-1) of the 1-2 pad (P12) may narrow. In this case, the alignment tolerance between the second bonding portion (P12-1) of the 1-2 pad (P12) and the terminal of the chip may decrease, which may result in a decrease in product yield.

[0166] The line width (W1) of the first bonding portion (P11-1) may have a range of 5 μm to 10 μm. For example, the line width (W1) of the first bonding portion (P11-1) may have a range of 5.5 μm to 9.5 μm. For example, the line width (W1) of the first bonding portion (P11-1) may have a range of 6 μm to 9 μm. If the line width (W1) of the first bonding portion (P11-1) is less than 5 μm, the contact area between the first bonding portion (P11-1) and the adhesive member may not be secured, and thus, it may be difficult to stably mount the chip on the first bonding portion (P11-1). In addition, if the line width (W1) of the first bonding portion (P11-1) exceeds 10 μm, the gap between adjacent first bonding portions (P11-1) may be reduced. In addition, if the spacing between adjacent first joints (P11-1) is reduced, it may be difficult to secure a process margin in the chip mounting process, and thus the product yield may decrease.

[0167] The line width (W2) of the first extension portion (P11-2) may be smaller than the line width (W1) of the first joining portion (P11-1). For example, the line width (W2) of the first extension portion (P11-2) may satisfy a range of 40% to 95% of the line width (W1) of the first joining portion (P11-1). For example, the line width (W2) of the first extension portion (P11-2) may satisfy a range of 42% to 93% of the line width (W1) of the first joining portion (P11-1). For example, the line width (W2) of the first extension portion (P11-2) may satisfy a range of 45% to 90% of the line width (W1) of the first joining portion (P11-1). At this time, if the line width (W2) of the first extension portion (P11-2) is less than 40% of the line width (W1) of the first coupling portion (P11-1), the signal transmission characteristics may deteriorate due to the difference in line widths between the first coupling portion (P11-1) and the first extension portion (P11-2). In addition, if the line width (W2) of the first coupling portion (P11-1) exceeds 95% of the line width (W1) of the first coupling portion (P11-1), the gap between the first extension portion (P11-2) and the second coupling portion (P12-1) may decrease, and thus, it may be difficult to secure a process margin in the chip mounting process.

[0168] The first-second pad (P12) may include a second joining portion (P12-1) and a second extension portion (P12-2). At this time, the first-second pad (P12) may not have a change in width along the longitudinal direction. For example, even if the first-second pad (P12) has a change in width along the longitudinal direction, the degree of change in width of the first-second pad (P12) may be less than the degree of change in width of the first-first pad (P11) in the longitudinal direction. Preferably, the line width (W3) of the second joining portion (P12-1) and the second extension portion (P12-2) of the first-second pad (P12) may be the same, but is not limited thereto.

[0169] In the embodiment, the width of the first-second pad (P12) arranged in a relatively circuit-dense area is smaller than the width of the first-first pad (P11). Through this, the embodiment can ensure sufficient process margin in the process of mounting a chip on the first-second pad (P12), thereby improving product yield.

[0170] For example, the line width (W3) of the second coupling portion (P12-1) may be smaller than the line width (W1) of the first coupling portion (P11-1). Preferably, the line width (W3) of the second coupling portion (P12-1) may satisfy a range of 40% to 95% of the line width (W1) of the first coupling portion (P11-1). For example, the line width (W3) of the second coupling portion (P12-1) may satisfy a range of 42% to 93% of the line width (W1) of the first coupling portion (P11-1). For example, the line width (W3) of the second coupling portion (P12-1) may satisfy a range of 45% to 90% of the line width (W1) of the first coupling portion (P11-1). At this time, if the line width (W3) of the second bonding portion (P12-1) is less than 40% of the line width (W1), it may be difficult to secure a contact area between the second bonding portion (P12-1) and the adhesive material, and thus, it may be difficult to stably mount the chip. In addition, if the line width (W3) of the second bonding portion (P12-1) exceeds 95% of the line width (W1) of the first bonding portion (P11-1), the gap between the second bonding portion (P12-1) and the first extension portion (P11-2) may decrease, and thus, it may be difficult to secure a process margin in the process of mounting the chip.

[0171]

[0172] Fig. 3 is an enlarged plan view of the second region (R2) of Fig. 1B, and Fig. 4 is a drawing showing a modified example of Fig. 3.

[0173] Referring to FIG. 3, the 1-1 wiring pattern portion (210) includes a second pad (210P2) arranged in the substrate connection area and connected to an external circuit board.

[0174] At this time, the 1-1 wiring pattern section (210) may include a plurality of 1-1 wiring patterns spaced apart from each other along the horizontal direction, as described in Fig. 2. Each of the plurality of 1-1 wiring patterns may be arranged to extend in the first direction (D1).

[0175] And, the plurality of first-first wiring patterns may include a second pad (210P2).

[0176] At this time, the second pad (210P2) may be alternately arranged with the second-1 pad (P21) and the second-2 pad (P22) having joints of different widths.

[0177] That is, each of the second-1 pad (P21) and the second-2 pad (P22) may include a region whose width increases. For example, the second-1 pad (P21) and the second-2 pad (P22) may include a joint (P21-1, P22-1) whose width increases in a region connected to an external circuit board.

[0178] That is, the second-1 pad (P21) may include a third coupling portion (P21-1) and a third extension portion (P21-2) extending from the third coupling portion (P21-1). The third coupling portion (P21-1) of the second-1 pad (P21) may refer to an area coupled to an external circuit board.

[0179] The line width (W4) of the third coupling portion (P21-1) may be different from the line width (W5) of the third extension portion (P21-2). Preferably, the line width (W4) of the third coupling portion (P21-1) may be greater than the line width (W5) of the third extension portion (P21-2). Furthermore, the line width (W4) of the third coupling portion (P21-1) may be greater than the line width (W1) of the first coupling portion (P11-1) and the line width (W3) of the second coupling portion (P12-1).

[0180] At this time, the third connecting portion (P21-1) is connected to pads of an external circuit board having a relatively large pitch, unlike the first connecting portion (P11-1) and the second connecting portion (P12-1). Accordingly, the pitch of the third connecting portions (P21-1) may be larger than the pitch of the first connecting portion (P11-1) and the second connecting portion (P12-1).

[0181] Accordingly, in the area where the third bonding portion (P21-1) is arranged, the fourth extension portion (P22-2) of the 2-2 pad (P22) is arranged in the neighboring area, but the pitch between them is larger than the pitch of the 1-1 pad (P11) and the 1-2 pad (P12). Accordingly, even if the line width (W4) of the third bonding portion (P21-1) increases, a process margin can be secured in the process of bonding the external circuit board. Therefore, the embodiment makes it so that the line width (W4) of the third bonding portion (P21-1) of the 2-1 pad (P21) having a relatively large pitch is larger than the line width (W5) of the third extension portion (P21-2). Through this, the embodiment can secure a contact area between the third bonding portion (P21-1) and the adhesive member, thereby enabling the external circuit board to be bonded more stably on the third bonding portion (P21-1).

[0182] Additionally, the second-second pad (P22) may include a fourth connecting portion (P22-1) and a fourth extension portion (P22-2) extending from the fourth connecting portion (P22-1). The fourth connecting portion (P22-1) of the second-second pad (P22) may refer to an area connected to an external circuit board.

[0183] The line width (W4) of the fourth connecting portion (P22-1) may be different from the line width (W5) of the fourth extension portion (P22-2). Preferably, the line width (W4) of the fourth connecting portion (P22-1) may be greater than the line width (W5) of the fourth extension portion (P22-2).

[0184] At this time, the line width of the fourth connecting portion (P22-1) may correspond to the line width of the third connecting portion (P21-1). However, the fourth connecting portion (P22-1) may not overlap with the third connecting portion (P21-1) along the second direction (D2).

[0185] That is, when the third connecting portion (P21-1) and the fourth connecting portion (P22-1) arranged adjacent to each other overlap along the second direction (D2), the gap between them may narrow. Accordingly, the process margin in the process of connecting the external circuit board may not be secured, and the product yield may decrease.

[0186] Accordingly, the embodiment is such that the second-first pad (P21) and the second-second pad (P22) of the second pad (210P2) include third coupling portions (P21-1) and fourth coupling portions (P22-1) having relatively large line widths (W4), and are arranged in a zigzag manner along the second direction. For example, the position of the third coupling portion (P21-1) may be different from the position of the fourth coupling portion (P22-1). For example, the third coupling portion (P21-1) may be positioned closer to the first side end (110E1) of the substrate (100) than the fourth coupling portion (P22-1). However, the embodiment is not limited thereto. For example, the fourth coupling portion (P22-1) may be positioned closer to the first side end (110E1) of the substrate (100) than the third coupling portion (P21-1).

[0187] Each of the ends of the second-first pad (P21) and the second-second pad (P22) may be spaced apart from the first side end (110E1) of the substrate (100). For example, each of the second-first pad (P21) and the second-second pad (P22) may be positioned further inward than the first side end (110E1) of the substrate (100). Through this, the embodiment can prevent the second-first pad (P21) and the second-second pad (P22) from being cut along a cutting line after manufacturing a flexible circuit board. Accordingly, the embodiment can solve reliability problems, such as separation of conductive pattern portions (WP, DP), that may occur during the cutting process.

[0188] Referring to FIG. 4, the ends of each of the 2-1 pad (P21) and the 2-2 pad (P22) may be connected to the first side end (110E1) of the substrate (100). For example, the ends of each of the 2-1 pad (P21) and the 2-2 pad (P22) may be positioned on the same vertical line as the first side end (110E1) of the substrate (100).

[0189] However, the ends of each of the second-first pad (P21) and the second-second pad (P22) may have a step portion (ST). For example, each of the second-first pad (P21) and the second-second pad (P22) may include a step portion (ST) whose width changes and is positioned between the third connecting portion (P21-1) or the fourth connecting portion (P22-1) and the first side end (110E1) of the substrate (100).

[0190] Preferably, each of the second-first pad (P21) and the second-second pad (P22) may include a step (ST) between the third coupling portion (P21-1) or the fourth coupling portion (P22-1) and the first side end (110E1) of the substrate (100), the step portion having a smaller width as it approaches the first side end (110E1).

[0191] Through this, the embodiment can ensure rigidity in the process of manufacturing a flexible circuit board by ensuring that each end of the 2-1 pad (P21) and the 2-2 pad (P22) is positioned on the same vertical line as the first side end (110E1) of the substrate (100). Furthermore, the embodiment can solve reliability problems that may occur in the process of cutting a flexible circuit board by ensuring that a step portion (ST) having a narrow width is provided at each end of the 2-1 pad (P21) and the 2-2 pad (P22).

[0192]

[0193] FIG. 5 is an enlarged plan view of the third area (R3) of FIG. 1B according to the first embodiment, and FIG. 6 is an enlarged plan view of the third area (R3) of FIG. 1B according to the second embodiment.

[0194] Referring to FIG. 5, the first-second wiring pattern portion (220) includes a third pad (220P1) that is placed in the chip mounting area (CHA) and connected to the chip.

[0195] At this time, the 1-2 wiring pattern section (220) may include a plurality of 1-2 wiring patterns spaced apart from each other along the horizontal direction. Each of the plurality of 1-2 wiring patterns may have a structure in which a plurality of pads are commonly connected to one connection pattern.

[0196] For example, the 1-2 wiring pattern section (220) may include a plurality of 3-1 pads (200P11) spaced apart and arranged in the first direction (D1). For example, the 3-1 pads (220P11) may be arranged in odd or even rows.

[0197] Additionally, the 1-2 wiring pattern portion (220) may include a plurality of 3-2 pads (220P12) arranged between a plurality of 3-1 pads (220P11). For example, the 3-2 pads (220P12) may be arranged in a different column from the 3-1 pads (220P11). For example, the 3-2 pads (220P12) may be arranged in an even column or an odd column.

[0198] At this time, the 3-1 pad (220P1) and the 3-2 pad (220P12) may have different lengths. For example, the ends of the 3-1 pad (P22011) and the 3-2 pad (220P12) may be provided at different positions. For example, the end of the 3-1 pad (220P11) may be located further inside the substrate (100) than the end of the 3-2 pad (220P12).

[0199] Accordingly, the plurality of third-1 pads (220P11) may not overlap with the third-2 pads (220P12) along the second direction (D2). In contrast, the plurality of third-2 pads (220P12) may overlap with the plurality of third-1 pads (220P11) along the second direction (D2).

[0200] At this time, the planar shape of the plurality of 3-1 pads (220P11) may be different from the planar shape of the plurality of 3-2 pads (220P12). For example, the plurality of 3-1 pads (220P11) may include a region in which the line width changes along the first direction (D1), which is the longitudinal direction. In contrast, the plurality of 3-2 pads (220P12) may not have the line width change along the first direction (D1).

[0201] For example, the plurality of 3-1 pads (220P11) may include an area having a line width greater than the line width of the plurality of 3-2 pads (220P12).

[0202] That is, the 3-1 pad (220P11) may include a fifth connecting portion (220P11-1) and a fifth extension portion (220P11-2) extending from the fifth connecting portion (220P11-1). The fifth connecting portion (220P11-1) of the 3-1 pad (220P11) may refer to an area connected to a terminal of the chip. In addition, the fifth extension portion (220P11-2) of the 3-1 pad (220P11) may connect between the fifth connecting portion (220P11-1) and the connecting pattern (220T1) of the 3-1 pad (220P11).

[0203] That is, the fifth connecting portion (220P11-1) does not overlap with the third-second pad (220P12) along the second direction (D1). For example, the third-second pad (220P12) may not be arranged on the left and right sides of the fifth connecting portion (220P11-1). Accordingly, the spacing between adjacent connecting portions in the area where the fifth connecting portion (220P11-1) is arranged may correspond to the spacing between adjacent third connecting portions. Accordingly, in the embodiment, even if the line width of the fifth connecting portion (220P11-1) is increased in the area where the fifth connecting portion (220P11-1) is arranged, there may be room in the spacing between adjacent connecting portions.

[0204] The line width of the fifth extension (220P11-2) may be smaller than the line width of the fifth connecting portion (220P11-1). This is because the fifth extension (220P11-2) is arranged to overlap with the sixth connecting portion (220P12-1) of the adjacent third-second pad (220P12) along the second direction (D2). That is, when the line width of the fifth extension (220P11-2) increases, the gap between the fifth extension (220P11-2) of the third-first pad (220P11) and the sixth connecting portion (220P12-1) of the third-second pad (220P12) may narrow. In this case, the alignment tolerance between the sixth joint (220P12-1) of the 3-2 pad (220P12) and the terminal of the chip may decrease, and the product yield may decrease accordingly.

[0205] The line width of the fifth connecting portion (220P11-1) may correspond to the line width (W1) of the first connecting portion (P11-1) described above. In addition, the line width of the fifth extension portion (220P11-2) may correspond to the line width of the first extension portion (P11-2).

[0206] The third-second pad (220P12) may include a sixth joining portion (220P12-1) and a sixth extension portion (220P12-2). At this time, the third-second pad (220P12) may not have a change in width along the longitudinal direction. For example, even if the third-second pad (220P12) has a change in width along the longitudinal direction, the degree of change in width of the third-second pad (220P12) may be less than the degree of change in width of the third-first pad (220P11) in the longitudinal direction. Preferably, the line width (W3) of the sixth joining portion (220P12-1) and the fourth extension portion (P12-2) of the third-second pad (220P12) may be the same, but is not limited thereto.

[0207] In the embodiment, the width of the 3-2 pad (220P12) arranged in a relatively circuit-dense area is made smaller than the width of the 3-1 pad (220P11). Through this, the embodiment can ensure sufficient process margin in the process of mounting a chip on the 3-2 pad (220P12), thereby improving product yield.

[0208] For example, the line width of the sixth connecting portion (220P12-1) may have a line width corresponding to the second connecting portion (P12-1) described above, and a detailed description thereof is omitted.

[0209] Additionally, the third-1 pad (220P11) and the third-2 pad (220P12) can be electrically connected to each other. That is, the third-1 pad (220P11) and the third-2 pad (220P12) can be connected to one second connection pattern (220T).

[0210] For example, the second connection pattern (220T) may include a plurality of branch lines, and each of the plurality of branch lines may be connected to the 3-1 pad (220P11) and the 3-2 pad (220P12).

[0211] The third pad (220P1) of the first-second wiring pattern section (220) according to another embodiment is described as follows.

[0212] Referring to FIG. 6, the 1-2 wiring pattern portion (220) may include a plurality of 3-2 pads (220P12) arranged between a plurality of 3-1 pads (220P11). For example, the 3-2 pads (220P12) may be arranged in a different column from the 3-1 pads (220P11). For example, the 3-2 pads (220P12) may be arranged in an even column or an odd column.

[0213] At this time, the third-1 pad (220P1) and the third-2 pad (220P12) may have the same length. For example, each end of the third-1 pad (P22011) and the third-2 pad (220P12) may be aligned along the second direction (D2).

[0214] Accordingly, the 3-1 pad (220P1) and the 3-2 pad (220P12) in the first embodiment are provided with different shapes. In contrast, the 3-1 pad (220P1) and the 3-2 pad (220P12) in the second embodiment may be provided with the same shape.

[0215] Each of the plurality of third-1 pads (220P11) and the plurality of third-2 pads (220P12) may include a region in which the line width changes. For example, the plurality of third-1 pads (220P11) and the plurality of third-2 pads (220P12) are connected via the second connection pattern (220T). Accordingly, the line width of the second connection pattern (220T) may be larger than the sum of the line widths of the plurality of third-1 pads (220P11) and the plurality of third-2 pads (220P12). In this case, if the difference between the widths of the plurality of third-1 pads (220P11) and the plurality of third-2 pads (220P12) and the width of the second connection pattern (220T) is too large, loss may occur during signal transmission between them, and thus, communication characteristics may deteriorate.

[0216] Accordingly, the plurality of 3-1 pads (220P11) and the plurality of 3-2 pads (220P12) may include a region whose width increases toward the second connection pattern (220T). For example, the plurality of 3-1 pads (220P11) may include a fifth coupling portion (220P11-1) and a fifth extension portion (220P11-2). The line width of the fifth coupling portion (220P11-1) may be different from the line width of the fifth extension portion (220P11-2). The line width of the fifth coupling portion (220P11-1) may be smaller than the line width of the fifth extension portion (220P11-2). For example, the fifth extension (220P11-2) may have a width greater than the width of the fifth coupling portion (220P11-1) to minimize the width difference between the second connection pattern (220T) and the fifth coupling portion (220P11-1).

[0217] Accordingly, the plurality of third-second pads (220P12) may include a sixth coupling portion (220P12-1) and a sixth extension portion (220P12-2). The line width of the sixth coupling portion (220P12-1) may be different from the line width of the sixth extension portion (220P12-2). The line width of the sixth coupling portion (220P12-1) may be smaller than the line width of the sixth extension portion (220P12-2). For example, the sixth extension portion (220P12-2) may have a width greater than the width of the sixth coupling portion (220P12-1) in order to minimize the width difference between the second connection pattern (220T) and the sixth coupling portion (220P12-1).

[0218]

[0219] Figure 7 is an enlarged plan view of the fourth region (R4) of Figure 1B.

[0220] Referring to FIG. 7, the 1-2 wiring pattern portion (220) includes a fourth pad (220P2) that is arranged in the substrate connection area and connected to an external circuit board.

[0221] At this time, the 1-2 wiring pattern section (220) includes a second connection pattern (220T), and the second connection pattern (220T) may include a branch line that branches into a plurality of lines.

[0222] In addition, the first-second wiring pattern section (220) may include a fourth pad (220P2) connected to each branch line of the second connection pattern (220T).

[0223] At this time, the 4th pad (220P2) may be alternately arranged with the 4-1 pad (220P21) and the 4-2 pad (220P22) having joints of different widths.

[0224] That is, each of the 4-1 pad (220P21) and the 4-2 pad (220P22) may include a region whose width increases. For example, the 4-1 pad (220P21) and the 4-2 pad (220P22) may include a joint (220P21-1, 220P22-1) whose width increases in a region connected to an external circuit board.

[0225] That is, the 4-1 pad (220P21) may include a seventh connecting portion (220P21-1) and a seventh extension portion (220P21-2) extending from the seventh connecting portion (220P21-1). The seventh connecting portion (220P21-1) of the 4-1 pad (220P21) may refer to an area that is connected to an external circuit board.

[0226] The 4-2 pad (220P22) may include an eighth connecting portion (220P22-1) and an eighth extension portion (220P22-2) extending from the eighth connecting portion (220P22-1). The eighth connecting portion (220P22-1) of the 4-2 pad (220P22) may refer to an area that is connected to an external circuit board.

[0227] At this time, the 4-1 pad (220P21) and the 4-2 pad (220P22) may have structures corresponding to the 2-1 pad (P21) and the 2-2 pad (P22) described in FIGS. 3 and 4, and thus, a detailed description thereof is omitted.

[0228] However, the 4-1 pad (220P21) and the 4-2 pad (220P22) may be commonly connected to one second connection pattern (220T), and differently, the 2-1 pad (P21) and the 2-2 pad (P22) may be connected to different connection patterns, respectively.

[0229]

[0230] Figure 8 is an enlarged plan view of the fifth region (R5) of Figure 1B, and Figure 9 is an enlarged plan view of the sixth region (R6) of Figure 1B.

[0231] Before the description of FIGS. 8 and 9, the second wiring pattern portion (300) includes a 2-1 wiring pattern portion (310) and a 2-2 wiring pattern portion (320). At this time, the 2-1 wiring pattern portion (310) and the 2-2 wiring pattern portion (320) may have the same structure except for the difference in the arrangement position of the 5th pad (310P1, 320P1) within the open area (OR).

[0232] The second wiring pattern portion (300) includes a fifth pad (300P1) that is arranged in the chip mounting area (CHA) and connected to the chip. Here, the fifth pad (300P1) of the second wiring pattern portion (300) may refer to the fifth pad (310P1) of the 2-1 wiring pattern portion (310), or may refer to the fifth pad (320P1) of the 2-2 wiring pattern portion (320). That is, the second wiring pattern portion (300) described below may refer to either the 2-1 wiring pattern portion (310) or the 2-2 wiring pattern portion (320).

[0233] The second wiring pattern section (300) may include a plurality of second wiring patterns spaced apart from each other along the horizontal direction. Each of the plurality of second wiring patterns may be connected to a different connection pattern (300T).

[0234] Accordingly, the fifth pad (300P1) of the second wiring pattern portion (300) may include a plurality of fifth pads spaced apart in the second direction (D2).

[0235] For example, it may include a plurality of 5-1 pads (300P11) spaced apart and arranged in the first direction (D1). For example, the 5-1 pads (300P11) may be arranged in odd or even rows.

[0236] Additionally, the second wiring pattern portion (300) may include a plurality of 5-2 pads (300P12) arranged between a plurality of 5-1 pads (300P11). For example, the 5-2 pads (300P12) may be arranged in a different column from the 5-1 pads (300P11). For example, the 5-2 pads (300P12) may be arranged in an even column or an odd column.

[0237] At this time, the 5-1 pad (300P11) and the 5-2 pad (300P12) may have different lengths. For example, the ends of the 5-1 pad (300P11) and the 5-2 pad (300P12) may be provided at different positions. For example, the end of the 5-1 pad (300P11) may be located further inside the substrate (100) than the end of the 5-2 pad (300P12).

[0238] Accordingly, the plurality of 5-1 pads (300P11) may not overlap with the 5-2 pads (300P12) along the second direction (D2). In contrast, the plurality of 5-2 pads (300P12) may overlap with the plurality of 5-1 pads (300P11) along the second direction (D2).

[0239] At this time, the planar shape of the plurality of 5-1 pads (300P11) may be different from the planar shape of the plurality of 5-2 pads (300P12). For example, the plurality of 5-1 pads (300P11) may include a region in which the line width changes along the first direction (D1), which is the longitudinal direction. In contrast, the plurality of 5-2 pads (300P12) may not have the line width change along the first direction (D1).

[0240] For example, the plurality of 5-1 pads (300P11) may include a region having a line width greater than the line width of the plurality of 5-2 pads (300P12).

[0241] That is, the 5-1 pad (300P11) may include a ninth connecting portion (300P11-1) and a ninth extension portion (300P11-2) extending from the ninth connecting portion (300P11-1). The ninth connecting portion (300P11-1) of the 5-1 pad (300P11) may refer to an area connected to a terminal of the chip. In addition, the ninth extension portion (300P11-2) of the 5-1 pad (300P11) may connect between the ninth connecting portion (300P11-1) and the connecting pattern (300T) of the 5-1 pad (300P11).

[0242] The 5-2 pad (300P12) may include a 10th connecting portion (300P12-1) and a 10th extension portion (300P12-2). At this time, the 5-2 pad (300P12) may not have a change in width along the longitudinal direction. For example, even if the 5-2 pad (300P12) has a change in width along the longitudinal direction, the degree of change in width of the 5-2 pad (300P12) may be less than the degree of change in width of the 5-1 pad (300P11) in the longitudinal direction. Preferably, the line widths of the 10th connecting portion (300P12-1) and the 4th extension portion (P12-2) of the 5-2 pad (300P12) may be the same, but are not limited thereto.

[0243] The fifth pad (300P1) of the second wiring pattern portion (300) may correspond to the structure of the first wiring pattern portion (200) illustrated in FIG. 2 or FIG. 5.

[0244] Referring to FIG. 9, the second wiring pattern portion (300) includes a sixth pad (300P2) that is positioned in the panel connection area and connected to the display panel. The sixth pad (300P2) can be connected to the fifth pad (300P1) via the third connection pattern (300T).

[0245] At this time, the sixth pad (300P2) and the third connection pattern (300T) adjacent to the sixth pad (300P2) may be arranged in a diagonal direction. For example, the sixth pad (300P2) and the third connection pattern (300T) may be arranged in a diagonal direction between the first direction (D1) and the second direction (D2).

[0246] That is, a plurality of sixth pads (300P2) are arranged on the second side of the substrate (100). At this time, the number and density of the sixth pads (300P2) may increase as the resolution of the display panel increases. Accordingly, the embodiment arranges the sixth pads (300P2) diagonally to prevent damage to the sixth pads (300P2) during a cutting process performed along a cutting line. That is, when the sixth pads (300P2) are arranged diagonally, damage to the sixth pads (300P2) during the cutting process can be minimized, and thus electrical and / or mechanical reliability can be improved.

[0247] At this time, the 6th pad (300P2) may alternately have the 6-1st pad (300P21) and the 6-2nd pad (300P22) having joints of different widths. That is, each of the 6-1st pad (300P21) and the 6-2nd pad (300P22) may include a region where the width increases. For example, the 6-1st pad (300P21) and the 6-2nd pad (300P22) may include joints (300P21-1, 300P22-1) where the width increases in a region where they are connected to an external circuit board.

[0248] That is, the 6-1 pad (300P21) may include an 11th connecting portion (300P21-1) and an 11th extension portion (300P21-2) extending from the 11th connecting portion (300P21-1). The 11th connecting portion (300P21-1) of the 6-1 pad (300P21) may refer to an area that is connected to an external circuit board.

[0249] The 6-2 pad (300P22) may include a 12th connecting portion (300P22-1) and a 12th extension portion (300P22-2) extending from the 12th connecting portion (300P22-1). The 12th connecting portion (300P22-1) of the 6-2 pad (300P22) may refer to an area that is connected to an external circuit board.

[0250] At this time, the 6-1 pad (300P21) and the 6-2 pad (300P22) may have structures corresponding to the 2-1 pad (P21) and the 2-2 pad (P22) described in FIGS. 3 and 4, and thus, a detailed description thereof is omitted.

[0251]

[0252] Figure 10 is an enlarged plan view of the seventh area (R7) of Figure 1B, and Figure 11 is an enlarged plan view of the eighth area (R8) of Figure 1B.

[0253] Referring to FIG. 10, the third wiring pattern portion (400) includes a seventh pad (400P1) that is arranged in the substrate connection area and connected to an external circuit board.

[0254] At this time, the 7th pad (400P1) may alternately be formed with the 7-1 pad (400P21) and the 7-2 pad (400P22) having joints of different widths.

[0255] That is, each of the 7-1 pad (400P21) and the 7-2 pad (400P22) may include a region whose width increases. For example, the 7-1 pad (400P21) and the 7-2 pad (400P22) may include a joint (400P21-1, 400P22-1) whose width increases in a region connected to an external circuit board.

[0256] That is, the 7-1 pad (400P21) may include a 13th connecting portion (400P21-1) and a 13th extension portion (400P21-2) extending from the 13th connecting portion (400P21-1). The 13th connecting portion (400P21-1) of the 7-1 pad (400P21) may refer to an area that is connected to an external circuit board.

[0257] The 7-2 pad (400P22) may include a 14th connecting portion (400P22-1) and a 14th extension portion (400P22-2) extending from the 14th connecting portion (400P22-1). The 14th connecting portion (400P22-1) of the 7-2 pad (400P22) may refer to an area that is connected to an external circuit board.

[0258] At this time, the 7-1 pad (400P21) and the 7-2 pad (400P22) may have structures corresponding to the 2-1 pad (P21) and the 2-2 pad (P22) described in FIGS. 3 and 4, and thus, a detailed description thereof is omitted.

[0259] Referring to FIG. 11, the third wiring pattern portion (400) includes an eighth pad (400P2) that is positioned in the panel connection area and connected to the display panel. The eighth pad (400P2) may include the seventh pad (400P1) via the connection pattern (400T).

[0260] At this time, the 8th pad (400P2) may have an 8-1 pad (400P21) and an 8-2 pad (400P22) having joints of different widths alternately arranged. That is, each of the 8-1st pad (400P21) and the 8-2nd pad (400P22) may include a region whose width increases. For example, the 8-1st pad (400P21) and the 8-2nd pad (400P22) may include joints (300P21-1, 300P22-1) whose width increases in a region connected to an external circuit board.

[0261] That is, the 8-1 pad (400P21) may include a 15th connecting portion (400P21-1) and a 15th extension portion (400P21-2) extending from the 15th connecting portion (400P21-1). The 15th connecting portion (400P21-1) of the 8-1 pad (400P21) may refer to an area that is connected to an external circuit board.

[0262] The 8-2 pad (400P22) may include a 16th connecting portion (400P22-1) and a 16th extension portion (400P22-2) extending from the 16th connecting portion (400P22-1). The 16th connecting portion (400P22-1) of the 8-2 pad (400P22) may refer to an area that is connected to an external circuit board.

[0263]

[0264] Fig. 12 is an enlarged plan view of the first dummy pattern section according to the embodiment.

[0265] Referring to FIG. 12, the first dummy pattern portion (500) includes a ninth pad (500P) and a connection pattern (500T) connected to the ninth pad (500P). The ninth pad (500P) may be exposed through an open area (OR) and connected to a terminal of the chip. The ninth pad (500P) may have a structure corresponding to the second pads corresponding to any one of FIGS. 5 and 6.

[0266] However, the connection pattern (500) of the first dummy pattern portion (500) may not extend to the end of the substrate (100). For example, the connection pattern (500) of the first dummy pattern portion (500) may not electrically connect between other components and the ninth pad (500P).

[0267] Meanwhile, the 10th pad (600P) of the second dummy pattern portion (600) has a structure corresponding to the second pad illustrated in FIG. 3 or FIG. 4, and the connection pattern (600T) may not electrically connect the other components with the 10th pad (600P).

[0268] In addition, the 11th pad (700P) of the 3rd dummy pattern portion (700) may have a structure corresponding to the pad illustrated in FIG. 9, and the connection pattern (700T) may not electrically connect the 11th pad (700P) with other components.

[0269] Meanwhile, the second dummy pattern portion (600) and the third dummy pattern portion (700) may have shapes corresponding to the 4-1 pad (220P21), the 4-2 pad (220P22), and the second connection pattern (220T) illustrated in FIG. 7. For example, the second dummy pattern portion (600) and the third dummy pattern portion (700) may include a connection pattern including a plurality of branch lines, and pads each connected to the plurality of branch lines of the connection pattern.

[0270]

[0271] Meanwhile, although not shown in the drawing, the wiring pattern portion (WP) and the dummy pattern portion (DP) may be provided on one surface and the other surface of the substrate (100), respectively. For example, the substrate (100) may include a through-via electrode penetrating the one surface and the other surface of the substrate (100), and the wiring pattern portions (WP) disposed on the one surface and the other surface of the substrate (100) may be electrically connected through the through-via electrode. At this time, the pads disposed in the open area (OR) described through FIGS. 2 to 12 may be disposed on one surface of the substrate (100), the pads disposed in the substrate connection area described through FIGS. 2 to 12 may be provided on at least one of the one surface and the other surface of the substrate (100), and the pads disposed in the panel connection area described through FIGS. 2 to 12 may be provided on at least one of the one surface and the other surface of the substrate (100).

[0272]

[0273] Fig. 13 is a cross-sectional view showing the layer structure of a conductive pattern portion according to the first embodiment, and Fig. 14 describes the layer structure of a conductive pattern portion according to the second embodiment. Specifically, Figs. 13 and 14 may show the 1-1 wiring pattern portion (210) among the wiring pattern portions (WP) of the conductive pattern portions (WP, DP). In addition, other wiring pattern portions and dummy pattern portions (DP) excluding the 1-1 wiring pattern portion (210) may also have a layer structure corresponding to the 1-1 wiring pattern portion (210) described below.

[0274] Referring to FIG. 13, the first connection pattern (210T) and the first pad (210P1) of the first-1 wiring pattern portion (210) include a buffer layer (215), a metal layer (211), and a bonding layer (213).

[0275] The buffer layer (215) may include multiple layers. Specifically, the buffer layer (215) includes a first buffer layer (215A) and a second buffer layer (215B). The first buffer layer (215A) is disposed on the substrate (100). The second buffer layer (215B) is disposed on the first buffer layer (215A).

[0276] The first buffer layer (215A) includes a material having good adhesion to the substrate (100). For example, the first buffer layer (215A) may include nickel (Ni). In addition, the second buffer layer (215B) includes a material having good adhesion to the circuit pattern. For example, the second buffer layer (215B) may include chromium (Cr).

[0277] The buffer layer (215) may have a thin film thickness in the nanometer range. For example, the buffer layer (215) may have a thickness of 20 nm or less. The adhesion between the substrate (100) and the circuit pattern is improved by the buffer layer (215).

[0278] The metal layer (211) is disposed on the buffer layer (215). Specifically, the metal layer (211) is disposed on the second buffer layer (215B). The metal layer (211) includes a metal material. For example, the metal layer (211) may include copper (Cu).

[0279] The metal layer (211) can be formed by electroplating using the buffer layer as a seed layer. That is, the metal layer (211) can be a plating layer.

[0280] The thickness of the metal layer (211) may be 5 μm to 30 μm. The bonding layer (213) is disposed on the metal layer (211). The bonding layer (213) is disposed on the side and upper surface of the metal layer (211). For example, the bonding layer (213) may be disposed to surround the metal layer (211). The bonding layer (213) includes a metal. For example, the bonding layer (213) may include tin (Sn). The bonding layer (213) is formed by a plating process. In detail, the bonding layer (213) may be a plating layer.

[0281] The thickness of the bonding layer (213) may be 0.3 μm to 0.7 μm. The tin content may increase as it extends from the lower surface of the bonding layer (213) toward the upper surface. That is, the bonding layer (213) is in contact with the metal layer (211). Therefore, the tin content increases as it extends from the lower surface of the bonding layer (213) toward the upper surface. In addition, the copper content decreases as it extends from the lower surface of the bonding layer (213) toward the upper surface.

[0282] Accordingly, pure tin may remain in a thickness range of 0.1 μm to 0.3 μm from the upper surface of the bonding layer (213). The pad portion can be easily bonded to terminals of chips, circuit boards, and display panels by the bonding layer (213). For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion is easily bonded to terminals of chips, circuit boards, and display panels.

[0283] Referring to Fig. 14, the metal layer (211) may include a first metal layer (211A) and a second metal layer (211B). The first metal layer (211A) is disposed on the buffer layer (215). The second metal layer (211B) is disposed on the first metal layer (211A). The second metal layer (211B) may be formed by electroplating using the first metal layer (211A) as a seed layer. In other words, the second metal layer (211B) may be a plating layer.

[0284] The thickness of the first metal layer (211A) may be smaller than the thickness of the second metal layer (211B).

[0285] For example, the thickness of the first metal layer (211A) may be 0.7 μm to 2 μm, and the thickness of the second metal layer (211B) may be 5 μm to 25 μm.

[0286] The first metal layer (211A) and the second metal layer (211B) may include the same metal material. For example, the first metal layer (211A) and the second metal layer (211B) may include copper (Cu).

[0287] The bonding layer (213) may include a first bonding layer (213A) and a second bonding layer (203b).

[0288] The first bonding layer (213A) is disposed on the metal layer (211). In detail, the first bonding layer (213A) is disposed on the first connection pattern (210T), the first pad (210P1), and the second pad (210P2).

[0289] The second bonding layer (203b) is disposed on the first bonding layer (213A). In detail, the second bonding layer (203b) is disposed on the first pad (210P1) and the second pad (210P2).

[0290] Accordingly, the first connection pattern (210T) includes a buffer layer (215), a metal layer (211), and a first bonding layer (213A). In addition, the first pad (210P1) and the second pad (210P2) include a buffer layer (215), a metal layer (211), a first bonding layer (213A), and a second bonding layer (203b).

[0291] The first bonding layer (213A) and the second bonding layer (203b) include metal. In detail, the first bonding layer (213A) and the second bonding layer (203b) may include tin (Sn).

[0292] The first bonding layer (213A) and the second bonding layer (203b) are arranged with different thicknesses. Specifically, the thickness of the second bonding layer (203b) is greater than the thickness of the first bonding layer (213A).

[0293] For example, the first bonding layer (213A) has a thickness of 0.02 μm to 0.06 μm. Additionally, the second bonding layer (203b) has a thickness of 0.2 μm to 0.6 μm.

[0294] Accordingly, the thickness of the first connection pattern (210T) is reduced. The flexible circuit board includes a bending area (BA) that is bent in one area. The first connection pattern (210T) is arranged on the bending area (BA). Accordingly, the thickness of the bonding layer on the first connection pattern (210T) is formed to be small. Accordingly, when the flexible circuit board is bent, cracks can be prevented from forming in the first connection pattern (210T).

[0295] The thickness of the circuit pattern may be greater than 5 μm to 25 μm. In detail, the thickness of the circuit pattern may be 6 μm to 20 μm. In detail, the thickness of the circuit pattern may be 7 μm to 15 μm.

[0296] If the circuit pattern thickness is less than 5 μm, the circuit pattern resistance may increase. If the circuit pattern thickness exceeds 25 μm, it becomes difficult to implement a fine pattern.

[0297]

[0298] Below, a flexible circuit board according to another embodiment is described.

[0299] However, a detailed description is omitted for the configuration of the following embodiments that is substantially the same as the configuration of the flexible circuit board of the previous embodiments.

[0300] FIG. 15a and FIG. 15b are plan views schematically showing a flexible circuit board according to a third embodiment, FIG. 16 is an enlarged plan view of a first region (R1) of FIG. 15b, FIG. 17a is an enlarged plan view of a first region (R1) of FIG. 15b according to a first comparative example, FIG. 17b is an enlarged plan view of a first region (R1) of FIG. 15b according to a second comparative example, FIG. 18 is an enlarged plan view of a second region (R2) of FIG. 15b according to an embodiment, FIG. 19 is an enlarged plan view of a third region (R3) of FIG. 15b according to an embodiment, FIG. 20 is an enlarged plan view of a part of a first dummy pattern part shown in FIG. 15b, FIG. 21 is an enlarged plan view of a part of a second dummy pattern part shown in FIG. 15b, and FIG. 22 is an enlarged plan view of a part of a third dummy pattern part shown in FIG. 15b. FIG. 23 is an enlarged plan view, and FIG. 23 is an enlarged plan view of the first region (R1) of FIG. 15b according to the fourth embodiment, and FIG. 24a, FIG. 24b and FIG. 25 are plan views schematically showing a flexible circuit board according to the fourth embodiment.

[0301] Referring to FIGS. 15A and 15B, a flexible circuit board (1000A) includes a substrate (1100), a conductive pattern portion (WP, DP), and a protective layer (1800). The conductive pattern portion includes a wiring pattern portion (WP) and a dummy pattern portion (DP).

[0302] The wiring pattern portion (WP) may include a first wiring pattern portion (1200), a second wiring pattern portion (1300), and a third wiring pattern portion (1400) depending on the placement location and / or function. Hereinafter, test patterns provided in the conductive pattern portion (WP, DP) will be described.

[0303] Here, FIGS. 16, 17a and 18b illustrate the first region (R1) with the protective layer (1800) removed for convenience of explanation.

[0304] Referring to FIG. 15a, FIG. 15b and FIG. 16, the first wiring pattern portion (1200) may include a first-first wiring pattern (1210) and a first-second wiring pattern (1220).

[0305] At this time, the first wiring pattern section (1200) includes a plurality of first wiring patterns spaced apart in the second horizontal direction (2D). The plurality of first wiring patterns are divided into a first-first wiring pattern (1210) and a first-second wiring pattern (1220).

[0306] As described above, the 1-1 wiring pattern (1210) may include a 1-1 inner pad (1210P1) disposed within the first open area (OR1). The 1-1 inner pad (1210P1) of the 1-1 wiring pattern (1210) may be connected to a chip. The 1-1 wiring pattern (1210) may include a 1-1 outer pad (1210P2) disposed within the second open area (OR2). In addition, the 1-1 wiring pattern (1210) may include a 1-1 wiring line (1210CP) connecting the 1-1 inner pad (1210P1) and the 1-1 outer pad (1210P2).

[0307] Additionally, the 1-2 wiring pattern (1220) may include a 1-2 inner pad (1220P1) disposed in a 1st open area (OR1), a 1-2 outer pad (1220P2) disposed in a 2nd open area (OR2), and a 1-2 wiring line (1220CP) connecting the 1-2 inner pad (1220P1) and the 1-2 outer pad (1220P2).

[0308] At this time, the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) are arranged adjacent to each other. That is, the illustrated 1-1 wiring line (1210CP) represents the wiring line arranged most adjacent to the 1-2 wiring line (1220CP) among the wiring lines of the plurality of first wiring patterns.

[0309] The first-second wiring pattern (1220) may include a first test pattern (1220TP) connected to the first-second wiring line (1220CP). The first test pattern (1220TP) may extend in a direction different from the extension direction of the first-second wiring line (1220CP). For example, the first-second wiring line (1220CP) may extend in a first horizontal direction (1D), and the first test pattern (1220TP) may extend from the first-second wiring line (1220CP) in a second horizontal direction (2D).

[0310] The first test pattern (1220TP) may be extended from the first-second wiring line (1220CP) of the first-second wiring pattern (1220), thereby enabling testing of the first-second wiring pattern (1220). For example, the first test pattern (1220TP) is provided for electrical reliability testing of the first wiring pattern portion (1200) and / or performance testing of a chip or external device connected to the first wiring pattern portion (1200).

[0311] At this time, the 1-1 wiring pattern (1210) may be arranged further inward than the 1-2 wiring pattern (1220). In addition, the 1-2 wiring pattern (1220) may be arranged further outward than the 1-1 wiring pattern (1210). For example, the substrate (1100) may be arranged closer to the third side end (1100E3) or the fourth side end (1100E4) facing in the second horizontal direction (2D).

[0312] Specifically, the first-first wiring line (1210CP) may be positioned closer to the inside of the substrate (1100) than the first-second wiring line (1220CP). Additionally, the first-second wiring line (1220CP) may be positioned closer to the outside of the substrate (1100) than the first-first wiring line (1210CP).

[0313] Through this, the embodiment can secure space for arranging the first test pattern (1220TP) without affecting the width and / or spacing of a plurality of first-first wiring patterns (1210) and first-second wiring patterns (1220).

[0314] The first-first wiring line (1210CP) and the first-second wiring line (1220CP) may have different widths. For example, the width (W1) of the first-first wiring line (1210CP) may be smaller than the width (W2) of the first-second wiring line (1220CP).

[0315] The width (W1) of the first-first wiring line (1210CP) may be 20 μm or less, 18 μm or less, or 15 μm or less. For example, the width (W1) of the first-first wiring line (1210CP) may have a range of 5 μm to 20 μm, 6 μm to 18 μm, or 6.5 μm to 15 μm. If the width (W1) of the first-first wiring line (1210CP) exceeds 20 μm, the space occupied by the first wiring pattern portion (1200) may increase, and thus the size of the flexible circuit board may increase. That is, if the width (W1) of the first-first wiring line (1210CP) exceeds 20 μm, it may be difficult to miniaturize the first wiring pattern portion (1200). In addition, if the width (W1) of the 1-1 wiring line (1210CP) is less than 5 µm, the process characteristics in the process of manufacturing the 1-1 wiring line (1210CP) may deteriorate. For example, the process characteristics in the exposure and development process of the dry film for forming the 1st wiring pattern portion (1200) may deteriorate, and as a result, an electrical open problem in the wiring line may occur due to a specific area not being exposed and developed.

[0316] The width (W2) of the 1-2 wiring line (1220CP) may be greater than the width (W1) of the 1-1 wiring line (1210CP). Through this, the embodiment can improve the test characteristics of the 1st wiring pattern portion (1200) performed using the 1st test pad (1220TP1). Furthermore, the 1-2 wiring line (1220CP) is the wiring line located at the outermost end among the wiring lines of the 1st wiring pattern portion (1200). Therefore, the 1-2 wiring line (1220CP) may not require miniaturization compared to the 1-1 wiring line (1210CP). Through this, the width (W2) of the 1-2 wiring line (1220CP) is made greater than the width (W1) of the 1-1 wiring line (1210CP). Through this, the rigidity of the flexible circuit board can be improved, and further, easy testing of the first wiring pattern portion (1200) can be performed through the first test pad (1220TP1).

[0317] The width (W2) of the 1-2 wiring line (1220CP) may range from 1.2 to 15 times, 1.5 to 13 times, or 2 to 11 times the width (W1) of the 1-1 wiring line (1210CP). If the width (W2) of the 1-2 wiring line (1220CP) is less than 1.2 times the width (W1) of the 1-1 wiring line (1210CP), it may be difficult to easily test the 1-1 wiring pattern portion (1200). In addition, if the width (W2) of the 1-2 wiring line (1220CP) is less than 1.2 times the width (W1) of the 1-1 wiring line (1210CP), the effect of improving the rigidity of the flexible circuit board may be insufficient. Additionally, if the width (W2) of the 1-2 wiring line (1220CP) exceeds 15 times the width (W1) of the 1-1 wiring line (1210CP), the size of the flexible circuit board may increase.

[0318] Here, the width of each of the first-first wiring line (1210CP) and the first-second wiring line (1220CP) may refer to the width in an area adjacent to the first test pattern (1220TP). For example, the first-first wiring line (1210CP) and the first-second wiring line (1220CP) in an area adjacent to the first test pattern (1220TP) may have the widths (W1, W2) described above. However, the widths of the first-first wiring line (1210CP) and the first-second wiring line (1220CP) may change as they move away from the first test pattern (1220TP). The first-first wiring line (1210CP) and the first-second wiring line (1220CP) may have the same width at a position spaced apart from the first test pattern (1220TP) by a certain distance.

[0319] In addition, the first-first wiring line (1210CP) and the first-second wiring line (1220CP) may be spaced apart by a certain distance (D1). The distance (D1) between the first-first wiring line (1210CP) and the first-second wiring line (1220CP) may be 20 μm or less, 18 μm or less, or 15 μm or less. For example, the distance (D1) between the first-first wiring line (1210CP) and the first-second wiring line (1220CP) may have a range of 5 μm to 20 μm, 6 μm to 18 μm, or 6.5 μm to 15 μm. When the distance (D1) between the first-first wiring line (1210CP) and the first-second wiring line (1220CP) exceeds 20 μm, the space occupied by the first wiring pattern portion (1200) increases, and thus the size of the flexible circuit board may increase. That is, if the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) exceeds 20 μm, it may be difficult to refine the 1st wiring pattern portion (1200). In addition, if the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is less than 5 μm, the process characteristics in the process of manufacturing the 1-1 wiring line (1210CP) may deteriorate. For example, the process characteristics in the exposure and development process of the dry film for forming the 1st wiring pattern portion (1200) may deteriorate, and as a result, an electrical open problem in the wiring line may occur due to a specific area not being exposed and not being developed.

[0320] In addition, the first test pattern (1220TP) includes a first test pad (1220TP1) having a width (W3) greater than a certain level. At this time, the width (W3) of the first test pad (1220TP1) can satisfy a range of 100 µm to 1200 µm, or 200 µm to 1100 µm, or 400 µm to 1000 µm.

[0321] If the width (W3) of the first test pad (1220TP1) is 100 μm or less, it may be difficult to perform a test. For example, if the width (W3) of the first test pad (1220TP1) is 100 μm or less, it may be difficult to secure a space for detecting a probe pin, which may make it difficult to perform a normal test. In addition, if the width (W3) of the first test pad (1220TP1) exceeds 1200 μm, it may be difficult to secure a space for arranging wiring patterns, which may cause an electrical short where the 1-2 wiring line (1220CP) connected to the first test pad (1220TP1) is connected to the 1-1 wiring line (1210CP).

[0322] At this time, the first test pad (1220TP1) is spaced apart from the first-second wiring line (1220CP) by a certain distance. Preferably, a first test connection line (1220TP2) may be provided between the first test pad (1220TP1) of the first-second wiring pattern (1220) and the first-second wiring line (1220CP).

[0323] The first test connection line (1220TP2) is arranged between the first test pad (1220TP1) and the first-second wiring line (1220CP), and can electrically connect the first test pad (1220TP1) and the first-second wiring line (1220CP).

[0324] At this time, the first test connection line (1220TP2) may be provided when the gap (D1) between the 1-2 wiring line (1220CP) connected to the first test pad (1220TP1) and the adjacent 1-1 wiring line (1210CP) is 20 μm or less. Alternatively, the first test connection line (1220TP2) may be provided when the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is smaller than the width (W2) of the first test pad (1220TP1).

[0325] That is, if the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is 20㎛ or less, or if the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is greater than the width (W2) of the first test pad (1220TP1), it is difficult to control the flow rate of the developer in the process of exposing and developing the dry film for forming the first wiring pattern portion (1200), and thus, overdevelopment may occur due to rapid movement of the developer. As a result, an electrical short may occur in which neighboring wiring patterns are electrically connected to each other.

[0326] At this time, the first test connection line (1220TP2) may have a certain length (L1). Here, the length (L1) of the first test connection line (1220TP2) may mean a separation distance between the first test pad (1220TP1) and the first-second wiring line (1220CP). That is, the first test pad (1220TP1) may be separated from the first-second wiring line (1220CP) by a distance corresponding to the length (L1) of the first test connection line (1220TP2).

[0327] The length (L1) of the first test connection line (1220TP2) may be smaller than the width (W3) of the first test pad (1220TP1). Preferably, the length (L1) of the first test connection line (1220TP2) may satisfy a range of 5% to 60%, 8% to 50%, or 10% to 45% of the width (W3) of the first test pad (1220TP1). If the length (L1) of the first test connection line (1220TP2) is less than 5% of the width (W3) of the first test pad (1220TP1), the distance between the first test pad (1220TP1) and the first-second wiring line (1220CP) may not be sufficiently secured. If the distance between the first test pad (1220TP1) and the first-second wiring line (1220CP) is not sufficient, it may be difficult to control the flow rate of the developing solution described below, which may cause an electrical short circuit of the wiring patterns. In addition, if the length (L1) of the first test connection line (1220TP2) exceeds 60% of the width (W3) of the first test pad (1220TP1), the space where the first test pattern (1220TP) is placed may increase, which may increase the size of the flexible circuit board.

[0328] In addition, the length (L1) of the first test connection line (1220TP2) may be greater than the interval (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP). The length (L1) of the first test connection line (1220TP2) may range from 2 to 20 times, or from 2.5 to 18 times, or from 3 to 15 times the interval (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP). For example, when the length (L1) of the first test connection line (1220TP2) is less than 2 times the interval (D1) described above, the flow rate control effect of the developer described above may be insufficient, and thus, the process characteristics in the process of exposing and developing a dry film may deteriorate. This may cause an electrical open problem or an electrical short problem in the first wiring pattern portion (1200). In addition, if the length (L1) of the first test connection line (1220TP2) exceeds 20 times the above-described interval (D1), the space in which the first test pattern (1220TP) is arranged may increase, which may increase the size of the flexible circuit board.

[0329] In addition, the first test connection line (1220TP2) may have a certain width (W4). The width (W4) of the first test connection line (1220TP2) may range from 1.2 to 15 times, 1.5 to 13 times, or 2 to 11 times the width (W1) of the 1-1 wiring line (1210CP). If the width (W4) of the first test connection line (1220TP2) is less than 1.2 times the width (W1) of the 1-1 wiring line (1210CP), it may be difficult to easily test the first wiring pattern portion (1200). In addition, if the width (W4) of the first test connection line (1220TP2) exceeds 15 times the width (W1) of the 1-1 wiring line (1210CP), the flow rate control effect of the developing solution may be insufficient.

[0330] That is, when the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is 20㎛ or less, or when the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is greater than the width (W2) of the first test pad (1220TP1), it is difficult to control the flow rate of the developer in the process of exposing and developing the dry film for forming the first wiring pattern portion (1200), and thus overdevelopment may occur due to the rapid movement of the developer. As a result, an electrical short may occur in which neighboring wiring patterns are electrically connected to each other. Therefore, the first test connection line (1220TP2) can prevent overdevelopment due to the flow rate of the developer as described above, and thus prevent reliability problems such as electrical open and / or electrical short from occurring in the process of forming wiring patterns.

[0331] Specifically, the manufacturing process of the flexible circuit board performs a process of forming an aperture pattern in an area where a first wiring pattern portion (1200) is to be formed by exposing and developing a dry film. At this time, the first test pad (1220TP1) provided in the first wiring pattern portion (1200) has a relatively large width (W4). Accordingly, during the developing process of the dry film, the flow rate of the developing solution in the area corresponding to the first test pad (1220TP1) increases, which may cause overdevelopment. Accordingly, the embodiment controls the flow rate of the developing solution by arranging the first test connection line (1220TP2) between the first test pad (1220TP1) and the first-second wiring line (1220CP). Through this, the embodiment can prevent overdevelopment of the dry film by controlling the flow rate of the developing solution. Therefore, the embodiment can prevent reliability problems such as electrical shorts from occurring.

[0332] For example, referring to FIG. 17a, in the first comparative example, the 1-2 wiring line (1220CP) and the first test pad (1220TP1) are substantially directly connected. Accordingly, the width (W4') of the first test pad (1220TP1) at the connection portion between the 1-2 wiring line (1220CP) and the first test pad (1220TP1) exceeds 70%, or exceeds 80%, or exceeds 85% of the width of the first test pad (1220TP1). In this case, it is difficult to control the flow rate of the developer during development of the dry film in the area corresponding to the first test pad (1220TP1), and thus overdevelopment (A) may occur. However, in the first comparative example, the gap (D1a) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) exceeds 20 μm. At this time, the width of the above-described over-phenomenon (A) portion is smaller than the gap (D1a) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP). Accordingly, in the first comparative example, even if over-phenomenon (A) occurred, an electrical short-circuit problem in which adjacent wiring lines were connected to each other did not occur.

[0333] Also, referring to FIG. 17b, in the second comparative example, the 1-2 wiring line (1220CP) and the first test pad (1220TP1) are substantially directly connected. Accordingly, the width (W4') of the first test pad (1220TP1) at the connection portion between the 1-2 wiring line (1220CP) and the first test pad (1220TP1) exceeds 70%, or exceeds 80%, or exceeds 85% of the width of the first test pad (1220TP1). In this case, it is difficult to control the flow rate of the developer when developing the dry film in the area corresponding to the first test pad (1220TP1), and thus overdevelopment (B) may occur. However, in the second comparative example, the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is 20 μm or less. At this time, the width of the over-development (B) portion in the second comparative example is greater than or equal to the gap (D1a) between the first-first wiring line (1210CP) and the first-second wiring line (1220CP). As a result, in the second comparative example, an electrical short occurs in which adjacent wiring lines are connected to each other as the over-development (B) occurs.

[0334] Through this, the embodiment forms a first test connection line (1220TP2) when the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is 20㎛ or less, or when the gap (D1) between the 1-1 wiring line (1210CP) and the 1-2 wiring line (1220CP) is greater than the width (W2) of the first test pad (1220TP1). Through this, in the process of exposing and developing a dry film for forming the first wiring pattern portion (1200), the flow rate of the developing solution can be easily controlled, and overdevelopment of the dry film can be prevented accordingly. Therefore, the embodiment can prevent reliability problems such as electrical open and / or electrical short from occurring in the process of forming wiring patterns.

[0335]

[0336] Additionally, referring to FIG. 15a, FIG. 15b and FIG. 18, the second wiring pattern portion (1300) may include a 2-1 wiring pattern (1310) and a 2-2 wiring pattern (1320).

[0337] At this time, the second wiring pattern section (1300) includes a plurality of second wiring patterns spaced apart in the second horizontal direction (2D). The plurality of second wiring patterns are divided into a second-first wiring pattern (1310) and a second-second wiring pattern (1320).

[0338] As described above, the 2-1 wiring pattern (1310) may include a 2-1 inner pad (1310P1) disposed within the first open area (OR1). The 2-1 inner pad (1310P1) of the 2-1 wiring pattern (1310) may be connected to a chip. The 2-1 wiring pattern (1310) may include a 2-1 outer pad (1310P2) disposed within the third open area (OR3). In addition, the 2-1 wiring pattern (1310) may include a 2-1 wiring line (1310CP) connecting the 2-1 inner pad (1310P1) and the 2-1 outer pad (1310P2).

[0339] Additionally, the 2-2 wiring pattern (1320) may include a 2-2 inner pad (1320P1) disposed in the first open area (OR1), a 2-2 outer pad (1320P2) disposed in the third open area (OR3), and a 2-2 wiring line (1320CP) connecting the 2-2 inner pad (1320P1) and the 2-2 outer pad (1320P2).

[0340] At this time, the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) are arranged adjacent to each other. That is, the illustrated 2-1 wiring line (1310CP) represents the wiring line arranged most adjacent to the 2-2 wiring line (1320CP) among the wiring lines of the plurality of second wiring patterns.

[0341] The second-second wiring pattern (1320) may include a second test pattern (1320TP) connected to the second-second wiring line (1320CP). The second test pattern (1320TP) may extend in a direction different from the extension direction of the second-second wiring line (1320CP). For example, the second-second wiring line (1320CP) may extend in a first horizontal direction (1D), and the second test pattern (1320TP) may extend from the second-second wiring line (1320CP) in a second horizontal direction (2D).

[0342] The second test pattern (1320TP) may be extended from the second-2 wiring line (1320CP) of the second-2 wiring pattern (1320), thereby enabling testing of the second-2 wiring pattern (1320). For example, the second test pattern (1320TP) is provided for an electrical reliability test of the second wiring pattern portion (1300) and / or a performance test of a chip or external device connected to the second wiring pattern portion (1300).

[0343] At this time, the 2-1 wiring pattern (1310) may be arranged further inward than the 2-2 wiring pattern (1320). In addition, the 2-2 wiring pattern (1320) may be arranged further outward than the 2-1 wiring pattern (1310). For example, the substrate (1100) may be arranged closer to the third side end (1100E3) or the fourth side end (1100E4) facing in the second horizontal direction (2D).

[0344] Specifically, the 2-1 wiring line (1310CP) may be positioned closer to the inside of the substrate (1100) than the 2-2 wiring line (1320CP). Additionally, the 2-2 wiring line (1320CP) may be positioned closer to the outside of the substrate (1100) than the 2-1 wiring line (1310CP).

[0345] Through this, the embodiment can secure space for arranging the second test pattern (1320TP) without affecting the width and / or spacing of a plurality of second-1 wiring patterns (1310) and second-2 wiring patterns (1320).

[0346] The 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) may have different widths. For example, the width (W1) of the 2-1 wiring line (1310CP) may be smaller than the width (W2) of the 2-2 wiring line (1320CP).

[0347] The width (W1) of the second-first wiring line (1310CP) may be 20 μm or less, 18 μm or less, or 15 μm or less. For example, the width (W1) of the second-first wiring line (1310CP) may have a range of 5 μm to 20 μm, 6 μm to 18 μm, or 6.5 μm to 15 μm. If the width (W1) of the second-first wiring line (1310CP) exceeds 20 μm, the space occupied by the second wiring pattern portion (1300) may increase, and thus the size of the flexible circuit board may increase. That is, if the width (W1) of the second-first wiring line (1310CP) exceeds 20 μm, it may be difficult to miniaturize the second wiring pattern portion (1300). In addition, if the width (W1) of the 2-1 wiring line (1310CP) is less than 5 ㎛, the process characteristics in the process of manufacturing the 2-1 wiring line (1310CP) may deteriorate. For example, the process characteristics in the exposure and development process of the dry film for forming the 2nd wiring pattern portion (1300) may deteriorate, and as a result, an electrical open problem in the wiring line may occur due to a specific area not being exposed and developed.

[0348] The width (W2) of the 2-2 wiring line (1320CP) may be greater than the width (W1) of the 2-1 wiring line (1310CP). Through this, the embodiment can improve the test characteristics of the 2nd wiring pattern portion (1300) performed using the 2nd test pad (1320TP1). Furthermore, the 2-2 wiring line (1320CP) is the wiring line located at the outermost end among the wiring lines of the 2nd wiring pattern portion (1300). Therefore, the 2-2 wiring line (1320CP) may not require miniaturization compared to the 2-1 wiring line (1310CP). Through this, the width (W2) of the 2-2 wiring line (1320CP) is made greater than the width (W1) of the 2-1 wiring line (1310CP). Through this, the rigidity of the flexible circuit board can be improved, and further, easy testing of the second wiring pattern portion (1300) can be performed through the second test pad (1320TP1).

[0349] The width (W2) of the 2-2 wiring line (1320CP) may range from 1.2 to 15 times, 1.5 to 13 times, or 2 to 11 times the width (W1) of the 2-1 wiring line (1310CP). If the width (W2) of the 2-2 wiring line (1320CP) is less than 1.2 times the width (W1) of the 2-1 wiring line (1310CP), it may be difficult to easily test the 2nd wiring pattern portion (1300). In addition, if the width (W2) of the 2-2 wiring line (1320CP) is less than 1.2 times the width (W1) of the 2-1 wiring line (1310CP), the effect of improving the rigidity of the flexible circuit board may be insufficient. Additionally, if the width (W2) of the 2-2 wiring line (1320CP) exceeds 15 times the width (W1) of the 2-1 wiring line (1310CP), the size of the flexible circuit board may increase.

[0350] In addition, the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) may be spaced apart by a certain distance (D1). The distance (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) may be 20 ㎛ or less, 18 ㎛ or less, or 15 ㎛ or less. For example, the distance (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) may have a range of 5 ㎛ to 20 ㎛, 6 ㎛ to 18 ㎛, or 6.5 ㎛ to 15 ㎛. If the distance (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) exceeds 20 ㎛, the space occupied by the 2nd wiring pattern portion (1300) may increase, and thus the size of the flexible circuit board may increase. That is, if the gap (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) exceeds 20㎛, it may be difficult to refine the 2nd wiring pattern portion (1300). In addition, if the gap (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) is less than 5㎛, the process characteristics in the process of manufacturing the 2-1 wiring line (1310CP) may deteriorate. For example, the process characteristics in the exposure and development process of the dry film for forming the 2nd wiring pattern portion (1300) may deteriorate, and as a result, an electrical open problem in the wiring line may occur due to a specific area not being exposed and not being developed.

[0351] Additionally, the second test pattern (1320TP) includes a second test pad (1320TP1) having a width (W3) greater than a certain level. At this time, the width (W3) of the second test pad (1320TP1) can satisfy a range of 100 µm to 1200 µm, or 200 µm to 1100 µm, or 400 µm to 1000 µm.

[0352] If the width (W3) of the second test pad (1320TP1) is 100 μm or less, it may be difficult to perform a test. For example, if the width (W3) of the second test pad (1320TP1) is 100 μm or less, it may be difficult to secure a space for detecting a probe pin, which may make it difficult to perform a normal test. In addition, if the width (W3) of the second test pad (1320TP1) exceeds 1200 μm, it may be difficult to secure a space for arranging wiring patterns, which may cause an electrical short where the 2-2 wiring line (1320CP) connected to the 2-2 test pad (1320TP1) is connected to the 2-1 wiring line (1310CP).

[0353] At this time, the second test pad (1320TP1) is spaced apart from the 2-2 wiring line (1320CP) by a certain distance. Preferably, a second test connection line (1320TP2) may be provided between the 2-2 wiring pattern (1320) second test pad (1320TP1) and the 2-2 wiring line (1320CP).

[0354] The second test connection line (1320TP2) is arranged between the second test pad (1320TP1) and the 2-2 wiring line (1320CP), and can electrically connect the second test pad (1320TP1) and the 2-2 wiring line (1320CP).

[0355] At this time, the second test connection line (1320TP2) may be provided when the gap (D1) between the 2-2 wiring line (1320CP) to which the 2nd test pad (1320TP1) is connected and the adjacent 2-1 wiring line (1310CP) is 20㎛ or less. Alternatively, the second test connection line (1320TP2) may be provided when the gap (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) is smaller than the width (W2) of the 2nd test pad (1320TP1).

[0356] That is, if the gap (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) is 20㎛ or less, or if the gap (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) is greater than the width (W2) of the second test pad (1320TP1), it is difficult to control the flow rate of the developer in the process of exposing and developing the dry film for forming the second wiring pattern portion (1300), and thus, overdevelopment may occur due to rapid movement of the developer. As a result, an electrical short may occur in which neighboring wiring patterns are electrically connected to each other.

[0357] At this time, the second test connection line (1320TP2) may have a certain length (L1). Here, the length (L1) of the second test connection line (1320TP2) may refer to a separation distance between the second test pad (1320TP1) and the 2-2 wiring line (1320CP). That is, the second test pad (1320TP1) may be separated from the 2-2 wiring line (1320CP) by a distance corresponding to the length (L1) of the second test connection line (1320TP2).

[0358] The length (L1) of the second test connection line (1320TP2) may be smaller than the width (W3) of the second test pad (1320TP1). Preferably, the length (L1) of the second test connection line (1320TP2) may satisfy a range of 5% to 60%, 8% to 50%, or 10% to 45% of the width (W3) of the second test pad (1320TP1). If the length (L1) of the second test connection line (1320TP2) is less than 5% of the width (W3) of the second test pad (1320TP1), the distance between the second test pad (1320TP1) and the second-2 wiring line (1320CP) may not be sufficiently secured. If the distance between the second test pad (1320TP1) and the second-second wiring line (1320CP) is not sufficient, it may be difficult to control the flow rate of the developing solution described below, which may cause an electrical short circuit of the wiring patterns. In addition, if the length (L1) of the second test connection line (1320TP2) exceeds 60% of the width (W3) of the second test pad (1320TP1), the space where the second test pattern (1320TP) is arranged may increase, which may increase the size of the flexible circuit board.

[0359] In addition, the length (L1) of the second test connection line (1320TP2) may be greater than the interval (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP). The length (L1) of the second test connection line (1320TP2) may range from 2 to 20 times, or from 2.5 to 18 times, or from 3 to 15 times the interval (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP). For example, when the length (L1) of the second test connection line (1320TP2) is less than 2 times the interval (D1) described above, the flow rate control effect of the developer described above may be insufficient, and thus, the process characteristics in the process of exposing and developing a dry film may deteriorate. This may cause an electrical open problem or an electrical short problem in the second wiring pattern portion (1300). In addition, if the length (L1) of the second test connection line (1320TP2) exceeds 20 times the above-described spacing (D1), the space where the second test pattern (1320TP) is arranged may increase, which may increase the size of the flexible circuit board.

[0360] In addition, the second test connection line (1320TP2) may have a certain width (W4). The width (W4) of the second test connection line (1320TP2) may range from 1.2 to 15 times, 1.5 to 13 times, or 2 to 11 times the width (W1) of the 2-1 wiring line (1310CP). If the width (W4) of the second test connection line (1320TP2) is less than 1.2 times the width (W1) of the 2-1 wiring line (1310CP), it may be difficult to easily test the second wiring pattern portion (1300). In addition, if the width (W4) of the second test connection line (1320TP2) exceeds 15 times the width (W1) of the 2-1 wiring line (1310CP), the flow rate control effect of the developing solution may be insufficient.

[0361] That is, when the gap (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) is 20㎛ or less, or when the gap (D1) between the 2-1 wiring line (1310CP) and the 2-2 wiring line (1320CP) is greater than the width (W2) of the second test pad (1320TP1), it is difficult to control the flow rate of the developer in the process of exposing and developing the dry film for forming the second wiring pattern portion (1300), and thus overdevelopment may occur due to the rapid movement of the developer. As a result, an electrical short may occur in which adjacent wiring patterns are electrically connected to each other. Therefore, the second test connection line (1320TP2) can prevent overdevelopment due to the flow rate of the developer as described above, and thus prevent reliability problems such as electrical open and / or electrical short from occurring in the process of forming wiring patterns.

[0362] Specifically, the manufacturing process of the flexible circuit board performs a process of forming an aperture pattern in an area where a second wiring pattern portion (1300) is to be formed by exposing and developing a dry film. At this time, the second test pad (1320TP1) provided in the second wiring pattern portion (1300) has a relatively large width (W4). Accordingly, during the developing process of the dry film, the flow rate of the developing solution in the area corresponding to the second test pad (1320TP1) becomes fast, which may cause overdevelopment. Accordingly, the embodiment controls the flow rate of the developing solution by arranging the second test connection line (1320TP2) between the second test pad (1320TP1) and the 2-2 wiring line (1320CP). Through this, the embodiment can prevent overdevelopment of the dry film by controlling the flow rate of the developing solution. Therefore, the embodiment can prevent reliability problems such as electrical shorts from occurring.

[0363]

[0364] Referring to FIGS. 15a, 15b, and 19, the basic structure of the test pattern provided in the third wiring pattern section (1400) may correspond to the structure of the test pattern provided in the first wiring pattern section (1200) and the second wiring pattern section (1300) described in FIGS. 16 and 18. Accordingly, the test pattern of the third wiring pattern section (1300) will be briefly described.

[0365] The third wiring pattern section (1400) may include a third-first wiring pattern (1410) and a third-second wiring pattern (1420).

[0366] At this time, the third wiring pattern section (1400) includes a plurality of third wiring patterns spaced apart in the second horizontal direction (2D). The plurality of third wiring patterns are divided into a third-first wiring pattern (1410) and a third-second wiring pattern (1420).

[0367] As described above, the 3-1 wiring pattern (1410) may include a 3-1 outer pad (1410P1) disposed within the 2nd open area (OR2). The 3-1 wiring pattern (1410) may include a 3-2 outer pad (1410P2) disposed within the 3rd open area (OR3). In addition, the 3-1 wiring pattern (1410) may include a 3-1 wiring line (1410CP) connecting the 3-1 outer pad (1410P1) and the 3-2 outer pad (1410P2).

[0368] Additionally, the 3-2 wiring pattern (1420) may include a 3-3 outer pad (1420P1) positioned in the 2nd open area (OR2), a 3-4 outer pad (1420P2) positioned in the 3rd open area (OR3), and a 3-2 wiring line (1420CP) connecting the 3-3 outer pad (1420P1) and the 3-4 outer pad (1420P2).

[0369] At this time, the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) are arranged adjacent to each other. That is, the illustrated 3-1 wiring line (1410CP) represents the wiring line arranged most adjacent to the 3-2 wiring line (1420CP) among the wiring lines of the plurality of 3rd wiring patterns.

[0370] The third-second wiring pattern (1420) may include a third test pattern (1420TP) connected to the third-second wiring line (1420CP). The third test pattern (1420TP) may extend in a direction different from the extension direction of the third-second wiring line (1420CP). For example, the third-second wiring line (1420CP) may extend in a first horizontal direction (1D), and the third test pattern (1420TP) may extend from the third-second wiring line (1420CP) in a second horizontal direction (2D).

[0371] The third test pattern (1420TP) may be extended from the third-second wiring line (1420CP) of the third-second wiring pattern (1420), thereby enabling testing of the third-second wiring pattern (1420). For example, the third test pattern (1420TP) is provided for an electrical reliability test of the third wiring pattern portion (1400) and / or a performance test of a chip or external device connected to the third wiring pattern portion (1400).

[0372] At this time, the 3-1 wiring pattern (1410) may be arranged further inward than the 3-2 wiring pattern (1420). Additionally, the 3-2 wiring pattern (1420) may be arranged further outward than the 3-1 wiring pattern (1410). For example, the substrate (1100) may be arranged closer to the third side end (1100E3) or the fourth side end (1100E4) facing in the second horizontal direction (2D).

[0373] Specifically, the 3-1 wiring line (1410CP) may be positioned closer to the inside of the substrate (1100) than the 3-2 wiring line (1420CP). Additionally, the 3-2 wiring line (1420CP) may be positioned closer to the outside of the substrate (1100) than the 3-1 wiring line (1410CP).

[0374] Through this, the embodiment can secure space for arranging the third test pattern (1420TP) without affecting the width and / or spacing of the plurality of 3-1 wiring patterns (1410) and 3-2 wiring patterns (1420).

[0375] The 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) may have different widths. For example, the width of the 3-1 wiring line (1410CP) may be smaller than the width of the 3-2 wiring line (1420CP).

[0376] The width of the 3-2 wiring line (1420CP) may be greater than the width of the 3-1 wiring line (1410CP). Through this, the embodiment can improve the test characteristics of the 3rd wiring pattern portion (1400) performed using the 3rd test pad (1420TP1). In addition, by making the width of the 3-2 wiring line (1420CP) greater than the width of the 3-1 wiring line (1410CP), the rigidity of the flexible circuit board can be improved, and further, easy testing of the 3rd wiring pattern portion (1400) can be performed through the 3rd test pad (1420TP1).

[0377] The width of the 3-2 wiring line (1420CP) may range from 1.2 to 15 times, 1.5 to 13 times, or 2 to 11 times the width of the 3-1 wiring line (1410CP). If the width of the 3-2 wiring line (1420CP) is less than 1.2 times the width of the 3-1 wiring line (1410CP), it may be difficult to easily test the 3rd wiring pattern portion (1400). In addition, if the width of the 3-2 wiring line (1420CP) is less than 1.2 times the width of the 3-1 wiring line (1410CP), the effect of improving the rigidity of the flexible circuit board may be minimal. In addition, if the width of the 3-2 wiring line (1420CP) exceeds 15 times the width of the 3-1 wiring line (1410CP), the size of the flexible circuit board may increase.

[0378] In addition, the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) may be spaced apart from each other by a certain distance. The distance between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) may be 20 ㎛ or less, 18 ㎛ or less, or 15 ㎛ or less. For example, the distance between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) may have a range of 5 ㎛ to 20 ㎛, 6 ㎛ to 18 ㎛, or 6.5 ㎛ to 15 ㎛. If the distance between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) exceeds 20 ㎛, the space occupied by the 3rd wiring pattern portion (1400) may increase, and thus the size of the flexible circuit board may increase. That is, if the gap between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) exceeds 20㎛, it may be difficult to refine the 3rd wiring pattern portion (1400). In addition, if the gap between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) is less than 5㎛, the process characteristics in the process of manufacturing the 3-1 wiring line (1410CP) may deteriorate. For example, the process characteristics in the exposure and development process of the dry film for forming the 3rd wiring pattern portion (1400) may deteriorate, and as a result, an electrical open problem in the wiring line may occur due to a specific area not being exposed and not being developed.

[0379] Additionally, the third test pattern (1420TP) includes a third test pad (1420TP1) having a width greater than a certain level. At this time, the width of the third test pad (1420TP1) can satisfy a range of 100 µm to 1200 µm, or 200 µm to 1100 µm, or 400 µm to 1000 µm.

[0380] At this time, the third test pad (1420TP1) is spaced apart from the third-second wiring line (1420CP) by a certain distance. Preferably, a third test connection line (1420TP2) may be provided between the third test pad (1420TP1) of the third-second wiring pattern (1420) and the third-second wiring line (1420CP).

[0381] The third test connection line (1420TP2) is arranged between the third test pad (1420TP1) and the third-2 wiring line (1420CP), and can electrically connect the third test pad (1420TP1) and the third-2 wiring line (1420CP).

[0382] At this time, the third test connection line (1420TP2) may be provided when the gap between the 3-2 wiring line (1420CP) connected to the 3rd test pad (1420TP1) and the adjacent 3-1 wiring line (1410CP) is 20㎛ or less. Alternatively, the third test connection line (1420TP2) may be provided when the gap between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) is smaller than the width of the 3rd test pad (1420TP1).

[0383] That is, if the gap between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) is 20㎛ or less, or if the gap between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) is greater than the width of the 3rd test pad (1420TP1), it is difficult to control the flow rate of the developer in the process of exposing and developing the dry film to form the 3rd wiring pattern portion (1400), and thus, overdevelopment may occur due to the rapid movement of the developer. As a result, an electrical short may occur in which neighboring wiring patterns are electrically connected to each other.

[0384] At this time, the third test connection line (1420TP2) may have a certain length. Here, the length of the third test connection line (1420TP2) may mean the separation distance between the third test pad (1420TP1) and the third-second wiring line (1420CP). That is, the third test pad (1420TP1) may be separated from the third-second wiring line (1420CP) by a distance corresponding to the length of the third test connection line (1420TP2).

[0385] The length of the third test connection line (1420TP2) may be shorter than the width of the third test pad (1420TP1). Preferably, the length of the third test connection line (1420TP2) may satisfy a range of 5% to 60%, 8% to 50%, or 10% to 45% of the width of the third test pad (1420TP1). If the length of the third test connection line (1420TP2) is less than 5% of the width of the third test pad (1420TP1), the distance between the third test pad (1420TP1) and the 3-2 wiring line (1420CP) may not be sufficiently secured. If the distance between the third test pad (1420TP1) and the 3-2 wiring line (1420CP) is not sufficiently secured, it may be difficult to control the flow rate of the developing solution, which may cause an electrical short in the wiring patterns. Additionally, if the length of the third test connection line (1420TP2) exceeds 60% of the width of the third test pad (1420TP1), the space where the third test pattern (1420TP) is placed may increase, which may increase the size of the flexible circuit board.

[0386] In addition, the length of the third test connection line (1420TP2) may be greater than the interval between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP). The length of the third test connection line (1420TP2) may range from 2 to 20 times, or from 2.5 to 18 times, or from 3 to 15 times the interval between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP). For example, when the length of the third test connection line (1420TP2) is less than 2 times the interval described above, the flow rate control effect of the developer described above may be insufficient, and thus the process characteristics in the process of exposing and developing the dry film may deteriorate. As a result, an electrical open problem or an electrical short problem of the third wiring pattern portion (1400) may occur. Additionally, if the length of the third test connection line (1420TP2) exceeds 20 times the above-described interval, the space in which the third test pattern (1420TP) is placed may increase, which may increase the size of the flexible circuit board.

[0387] In addition, the third test connection line (1420TP2) may have a certain width. The width of the third test connection line (1420TP2) may range from 1.2 to 15 times, 1.5 to 13 times, or 2 to 11 times the width of the third-1 wiring line (1410CP). If the width of the third test connection line (1420TP2) is less than 1.2 times the width of the third-1 wiring line (1410CP), it may be difficult to easily test the third wiring pattern portion (1400). In addition, if the width of the third test connection line (1420TP2) exceeds 15 times the width of the third-1 wiring line (1410CP), the flow rate control effect of the developing solution may be insufficient.

[0388] That is, if the gap between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) is 20㎛ or less, or if the gap between the 3-1 wiring line (1410CP) and the 3-2 wiring line (1420CP) is greater than the width of the 3rd test pad (1420TP1), it is difficult to control the flow rate of the developer in the process of exposing and developing the dry film for forming the 3rd wiring pattern portion (1400), and thus overdevelopment may occur due to the rapid movement of the developer. This may cause an electrical short in which adjacent wiring patterns are electrically connected to each other. Therefore, the 3rd test connection line (1420TP2) can prevent overdevelopment due to the flow rate of the developer as described above, and thus prevent reliability problems such as electrical open and / or electrical short from occurring in the process of forming wiring patterns.

[0389] Specifically, the manufacturing process of the flexible circuit board performs a process of forming an aperture pattern in an area where a third wiring pattern portion (1400) is to be formed by exposing and developing a dry film. At this time, the third test pad (1420TP1) provided in the third wiring pattern portion (1400) has a relatively large width. Accordingly, during the developing process of the dry film, the flow rate of the developing solution in the area corresponding to the third test pad (1420TP1) becomes fast, which may cause overdevelopment. Accordingly, the embodiment controls the flow rate of the developing solution by arranging the third test connection line (1420TP2) between the third test pad (1420TP1) and the 3-2 wiring line (1420CP). Through this, the embodiment can prevent overdevelopment of the dry film by controlling the flow rate of the developing solution. Therefore, the embodiment can prevent reliability problems such as electrical shorts from occurring.

[0390]

[0391] Referring to FIGS. 15a, 15b and 20, the first dummy pattern portion (1500) is connected to the chip and can be used for testing a specific terminal of the chip or can have a heat dissipation function to transfer heat generated from the chip.

[0392] For example, the first dummy pattern unit (1500) may include a first dummy pattern (1510) and a first dummy pattern (1520). The first dummy pattern (1510) may refer to a dummy pattern that performs only a dummy function. In addition, the first dummy pattern (1520) may refer to a dummy pattern that performs a test function while performing the dummy function.

[0393] The first-second dummy pattern (1520) may include a first-second dummy pad (1520P1) positioned within the first open area (OR1) and a first-second dummy wiring line (1520CP) connected from the first-second dummy pad (1520P1). In addition, the first-second dummy pattern (1520) may include a first dummy test pattern (1520TP) connected to the first-second dummy wiring line (1520CP).

[0394] The first dummy test pattern (1520TP) can be directly connected to one end of the first-second dummy wiring line (1520CP).

[0395] Specifically, one end of the first dummy test pattern (1520TP) may be directly connected to the first-second dummy wiring line (1520CP), and the other end of the first dummy test pattern (1520TP) may be directly connected to the first-second dummy pad (1520P1).

[0396] The first dummy test pattern (1520TP) may mean a first dummy test pad directly connected to the first-second dummy wiring line (1520CP).

[0397] The first dummy test pad constituting the first dummy test pattern (1520TP) is directly connected to the first-second dummy wiring line (1520CP), and can be used to test the performance of a chip placed on the first-second dummy pad (1520P1). For example, the first dummy test pattern (1520TP) can be used to test the performance of a chip after the chip is mounted on the first-second dummy pad (1520P1).

[0398] The wiring patterns of the wiring pattern portion may not be arranged in the adjacent area of ​​the first-second dummy pattern (1520). For example, the first-second dummy pattern (1520) may be arranged in an area where dummy patterns are concentrated. Accordingly, the first dummy test pattern (1520TP) may include only test pads without test connection lines.

[0399]

[0400] Referring to FIGS. 15a, 15b and 21, the second dummy pattern portion (1600) is connected to a display panel or an external circuit board, and can be used for testing a specific terminal of the display panel or the external circuit board, or can have a heat dissipation function to transfer heat generated from the display panel or the external circuit board.

[0401] For example, the second dummy pattern unit (1600) may include a second-first dummy pattern (1610) and a second-second dummy pattern (1620). The second-first dummy pattern (1610) may refer to a dummy pattern that performs only a dummy function. In addition, the second-second dummy pattern (1620) may refer to a dummy pattern that performs a test function while performing the dummy function.

[0402] The second-second dummy pattern (1620) may include a second-second dummy pad (1620P1) positioned within the second open area (OR2) and a second-second dummy wiring line (1620CP) connected from the second-second dummy pad (1620P1). In addition, the second-second dummy pattern (1620) may include a second dummy test pattern (1620TP) connected to the second-second dummy wiring line (1620CP).

[0403] The second dummy test pattern (1620TP) can be directly connected to one end of the second-2 dummy wiring line (1620CP).

[0404] Specifically, one end of the second dummy test pattern (1620TP) may be directly connected to the 2-2 dummy wiring line (1620CP), and the other end of the second dummy test pattern (1620TP) may be directly connected to the 2-2 dummy pad (1620P1).

[0405] The second dummy test pattern (1620TP) may mean a second dummy test pad directly connected to the 2-2 dummy wiring line (1620CP).

[0406] The second dummy test pad constituting the second dummy test pattern (1620TP) is directly connected to the second-2 dummy wiring line (1620CP), and can be used to test the performance of a display panel or an external circuit board placed on the second-2 dummy pad (1620P1). For example, the second dummy test pattern (1620TP) can be used to test the performance of a display panel or an external circuit board after the display panel or the external circuit board is mounted on the second-2 dummy pad (1620P1).

[0407] The wiring patterns of the wiring pattern portion may not be arranged in the adjacent area of ​​the second dummy pattern (1620). For example, the second dummy pattern (1620) may be arranged in an area where dummy patterns are concentrated. Accordingly, the second dummy test pattern (1620TP) may include only test pads without test connection lines.

[0408]

[0409] Referring to FIGS. 15a, 15b and 22, the third dummy pattern portion (1700) is connected to a display panel or an external circuit board, and can be used for testing a specific terminal of the display panel or the external circuit board, or can have a heat dissipation function to transfer heat generated from the display panel or the external circuit board.

[0410] For example, the third dummy pattern unit (1700) may include a third-first dummy pattern (1710) and a third-second dummy pattern (1720). The third-first dummy pattern (1710) may refer to a dummy pattern that performs only a dummy function. In addition, the third-second dummy pattern (1720) may refer to a dummy pattern that performs a test function while performing the dummy function.

[0411] The third-second dummy pattern (1720) may include a third-second dummy pad (1720P1) positioned within the third open area (OR3) and a third-second dummy wiring line (1720CP) connected from the third-second dummy pad (1720P1). In addition, the third-second dummy pattern (1720) may include a third dummy test pattern (1720TP) connected to the third-second dummy wiring line (1720CP).

[0412] The third dummy test pattern (1720TP) can be directly connected to one end of the third-2 dummy wiring line (1720CP).

[0413] Specifically, one end of the third dummy test pattern (1720TP) may be directly connected to the third-2 dummy wiring line (1720CP), and the other end of the third dummy test pattern (1720TP) may be directly connected to the third-2 dummy pad (1720P1).

[0414] The third dummy test pattern (1720TP) may refer to a third dummy test pad directly connected to the third-2 dummy wiring line (1720CP).

[0415] The third dummy test pad constituting the third dummy test pattern (1720TP) is directly connected to the third-second dummy wiring line (1720CP), and can be used to test the performance of a display panel or an external circuit board placed on the third-second dummy pad (1720P1). For example, the third dummy test pattern (1720TP) can be used to test the performance of a display panel or an external circuit board after the display panel or the external circuit board is mounted on the third-second dummy pad (1720P1).

[0416] The wiring patterns of the wiring pattern portion may not be arranged in the adjacent area of ​​the 3-2 dummy pattern (1720). For example, the 3-2 dummy pattern (1720) may be arranged in an area where dummy patterns are concentrated. Accordingly, the 3rd dummy test pattern (1720TP) may include only test pads without test connection lines.

[0417]

[0418] Referring to FIG. 23, the first wiring pattern section (1200) may include a first-first wiring pattern (1210) and a first-second wiring pattern (1220).

[0419] The first-first wiring pattern (1210) may include a first-first inner pad (1210P1), a first-first outer pad (1210P2), and a first-first wiring line (1210CP). In addition, the first-second wiring pattern (1220) may include a first-second inner pad (1220P1), a first-second outer pad (1220P2), and a first-second wiring line (1220CP).

[0420] The first-second wiring pattern (1220) may include a first test pattern (1220TP) connected to the first-second wiring line (1220CP).

[0421] The first test pattern (1220TP) includes a first test pad (1220TP1) having a width greater than a certain level. At this time, the first test pad (1220TP1) is spaced apart from the first-second wiring line (1220CP) by a certain distance. Preferably, a first test connection line (1220TP2) may be provided between the first test pad (1220TP1) of the first-second wiring pattern (1220) and the first-second wiring line (1220CP).

[0422] The first test connection line (1220TP2) is arranged between the first test pad (1220TP1) and the first-second wiring line (1220CP), and can electrically connect the first test pad (1220TP1) and the first-second wiring line (1220CP).

[0423] The first test connection line (1220TP2) includes a first part (1220TP3) connected to the first-second wiring line (1220CP) and a second part (1220TP4) connected to the first test pad (1220TP1).

[0424] The first part (1220TP3) and the second part (1220TP4) of the first test connection line (1220TP2) may have a shape to minimize stress occurring at the portion connected to the first-second wiring line (1220CP) and the first test pad (1220TP1).

[0425] That is, the side surfaces of the first portion (1220TP3) and the second portion (1220TP4) of the first test connection line (1220TP2) may have curved surfaces having specific curvatures depending on the extension direction. For example, the width of the first portion (1220TP3) of the first test connection line (1220TP2) may decrease toward the second portion (1220TP4). Additionally, the width of the second portion (1220TP4) of the first test connection line (1220TP2) may decrease toward the second portion (220TP3).

[0426] Through this, the embodiment can minimize stress concentration in the first part (1220TP3) and the second part (1220TP4) of the first test connection line (1220TP2).

[0427]

[0428] Meanwhile, in the above description, each of the first wiring pattern portion (1200), the second wiring pattern portion (1300), the third wiring pattern portion (1400), the first dummy pattern portion (1500), the second dummy pattern portion (1600), and the third dummy pattern portion (1700) is provided with a test pattern, but this is not limited thereto. At least one of the test patterns described above may be omitted.

[0429] That is, the test pattern described above refers to a pattern placed in the effective area (AA) of the substrate (1100). That is, the test pattern described below refers to a pattern that is placed in the effective area (AA) of the substrate (1100) and remains on the substrate (1100) even after the flexible circuit board (1000A) is finally manufactured.

[0430] At this time, the test pattern may be provided for the wiring pattern that requires testing. For example, if testing is required for the first wiring pattern section (1200) and testing is unnecessary for the second wiring pattern section (1300), the first wiring pattern section (1200) may include a test pattern, and the second wiring pattern section (1300) may not include a test pattern.

[0431] Additionally, the test pattern may be provided in a wiring pattern portion where normal testing is difficult on the inner pad and / or outer pad.

[0432] For example, the line width and spacing of the wiring patterns of the wiring pattern portion (WP) are becoming finer, and accordingly, the width of the inner pad and / or the outer pad is also becoming smaller. At this time, the above-described test is performed by probing the inner pad and / or the outer pad. However, as described above, due to the miniaturization of the inner pad and / or the outer pad, the width of the inner pad and / or the outer pad that can normally probing the probe pin may not be secured. Accordingly, the embodiment may provide a test pattern in the wiring pattern portion where normal testing is difficult on the inner pad and / or the outer pad.

[0433] For example, as display panels become more high-performance, the number of terminals increases, and the number of outer pads connected to the display panel on flexible circuit boards increases, leading to a decrease in line width. In this case, it may be difficult to properly probe the outer pads connected to the display panel with a probe pin. Therefore, embodiments may include a test pattern provided on the wiring pattern portion connected to the display panel.

[0434]

[0435] The embodiment forms a test pattern on at least one of the wiring lines of the conductive pattern portion. The test pattern may be covered with a protective layer. Accordingly, the embodiment can enable probing of a probe pin for testing using the test pattern after manufacturing the flexible circuit board.

[0436] Accordingly, the embodiment can test the electrical reliability of the conductive pattern portion even after the flexible circuit board is manufactured or after the chip and / or display panel and the external circuit board are connected, and further can test the performance of the chip, the display panel, and the external circuit board.

[0437] Therefore, the embodiment can improve the electrical reliability of a flexible circuit board. This allows the embodiment to enable the flexible circuit board and the COF module including the flexible circuit board to operate more stably. Consequently, product reliability can be improved.

[0438] Additionally, the conductive pattern portion includes a wiring pattern portion and a dummy pattern portion. Furthermore, test patterns may be provided not only in the wiring pattern portion but also in the dummy pattern portion. Therefore, the embodiment can more easily test the performance of chips, display panels, and external circuit boards.

[0439] Additionally, the embodiment can arrange the wiring pattern equipped with the test pattern among each wiring pattern to be positioned further outward than the other wiring patterns. Accordingly, the embodiment can arrange the test pattern without affecting the line width and / or spacing of the wiring patterns. Therefore, the embodiment can further improve product reliability.

[0440] Additionally, the wiring lines connected to the test pattern are wider than the other wiring lines. This facilitates easier testing. Furthermore, the rigidity of the flexible circuit board can be improved. Therefore, the embodiment can improve the electrical reliability of the flexible circuit board. Consequently, the embodiment can enable the flexible circuit board and the COF module including it to operate more stably. Consequently, product reliability can be improved.

[0441] Furthermore, the test pattern includes a test pad connected to a wiring line and a test connection line positioned between the test pad and the wiring line. The test connection line may have a width smaller than the test pad and may connect the test pad and the wiring line. Therefore, the embodiment can further improve the electrical reliability of the flexible circuit board.

[0442] Specifically, in a process of exposing and developing a dry film for forming a wiring pattern portion, it is difficult to control the flow rate of the developer in the area where the test pad is placed, and thus, overdevelopment may occur due to rapid movement of the developer. This may result in an electrical short circuit in which adjacent wiring patterns are electrically connected to each other. Therefore, the embodiment places a test connection line between the test pad and the wiring line. The test connection line can prevent overdevelopment due to the flow rate of the developer, and thus prevent reliability problems such as electrical open and / or electrical short circuit from occurring in the process of forming wiring patterns.

[0443]

[0444] Below, a flexible circuit board according to another embodiment is described.

[0445] Preferably, it may be a cross-sectional flexible circuit board having a structure in which a wiring pattern portion (WP), a dummy pattern portion (DP), and a protective layer (1800) are arranged only on the first side (1S) of the previous substrate (1100).

[0446] In contrast, the following embodiment may be a double-sided flexible circuit board having a structure in which a wiring pattern portion (WP), a dummy pattern portion (DP), and a protective layer (1800) are arranged on each of the first side (1S) and the second side (2S) of the substrate (1100).

[0447] Referring to FIGS. 24a, 24b and 25, the flexible circuit board may include a substrate (1100), a wiring pattern portion (WP), a dummy pattern portion (DP) and a protective layer (1800).

[0448] In addition, the wiring pattern portion (WP), the dummy pattern portion (DP) and the protective layer (1800) may be provided on the first side (1S) of the substrate (1100) and the second side (2S) opposite to the first side (1S), respectively.

[0449] That is, the flexible circuit board may be a double-sided flexible circuit board in which a wiring pattern portion (WP) and a dummy pattern portion (DP) are respectively arranged on the first side (1S) and the second side (2S) of the substrate (1100).

[0450] Accordingly, each of the wiring pattern portion (WP) and the dummy pattern portion (DP) may include an upper wiring pattern portion and an upper dummy pattern portion arranged on the first surface (1S) of the substrate (1100). In addition, the wiring pattern portion (WP) and the dummy pattern portion (DP) may include a lower wiring pattern portion and a lower dummy pattern portion arranged on the second surface (2S) of the substrate (1100).

[0451] Additionally, the protective layer (1800) may include an upper protective layer (1800U) disposed on a first surface (1S) of the substrate (1100) and a lower protective layer (1800L) disposed on a second surface (2S) of the substrate (1100).

[0452] That is, among the wiring pattern portions (WP) illustrated in FIGS. 15a and 15b, the second wiring pattern portion (1300) and the third wiring pattern portion (1400) may include only the upper wiring pattern portion arranged only on the first surface (1S) of the substrate (1100), and the first wiring pattern portion (1200) may include the upper wiring pattern portion and the lower wiring pattern portion arranged respectively on the first surface (1S) and the second surface (2S) of the substrate (1100).

[0453] At this time, FIGS. 24a, 24b, and 25 may be enlarged views of the upper wiring pattern and the lower wiring pattern of the first wiring pattern portion (1200) arranged on the first surface (1S) and the second surface (2S) of the substrate (1100). In addition, the first wiring pattern portion (1200) described below may be equally applied to the 1-1 wiring pattern (1210) and the 1-2 wiring pattern (1220) described in the previous embodiment.

[0454] Referring to FIG. 24a, the upper wiring of the first wiring pattern portion (1200) arranged on the first surface (1S) of the substrate (1100) may include a first via (V1) arranged in the chip mounting area (CHA) and penetrating the substrate (1100).

[0455] The upper wiring may include a first upper wiring (1201) including a pad directly connected to the first via (V1).

[0456] Additionally, the upper wiring of the first wiring pattern portion (1200) may include a second upper wiring (1203) including a connecting wiring extending toward one end of the first surface (1S) of the pad and substrate (1100) in the chip mounting area (CHA). A second via (V2) may be provided at an end of the second upper wiring (1203).

[0457] Also, referring to FIG. 24b, the lower wiring of the first wiring pattern portion (1200) is arranged on the second surface (2S) of the substrate (1100). The lower wiring of the second surface (2S) may include a first lower wiring (1302) connected to the first upper wiring (1201) through a first via (V1). In addition, the lower wiring of the second surface (2S) may include a second lower wiring (1304) connected to the second upper wiring (1202) through a second via (V2).

[0458] And, referring to FIG. 25, a lower protective layer (1800L) may be arranged on the second surface (2S) of the substrate (1100). And, the lower protective layer (1800L) includes a second open area (OR2), and thus, a part of the first lower wiring (1302) and a part of the second lower wiring (1304) may be exposed. A part of the first lower wiring (1302) and a part of the second lower wiring (1304) exposed through the second open area (OR2) of the lower protective layer (1800L) may function as an external circuit board connection pad connected to an external circuit board. At this time, when the open area is provided in the lower protective layer (1800L), any one of the first to third open areas (OR1, OR2, OR3) described in the previous embodiment may be omitted in the upper protective layer (1800U). For example, in the previous embodiment, the first to third open areas (OR1, OR2, OR3) were all provided in the upper protective layer (1800U). In contrast, in another embodiment, among the first to third open areas (OR1, OR2, OR3), the first and third open areas (OR1 OR3) may be provided in the upper protective layer (1800U), and the second open area (OR2) may be provided in the lower protective layer (1800L).

[0459] In addition, at least one of the plurality of wiring patterns of the first wiring pattern portion (1200) having the above-described structure may be provided with a first test pattern (1220TP). At this time, the first test pattern (1220TP) may be arranged on the first surface (1S) of the substrate (1100) and may be connected to the upper wiring through this. Alternatively, the first test pattern (1220TP) may be arranged on the second surface (2S) of the substrate (1100) and may be connected to the lower wiring through this.

[0460]

[0461] FIGS. 26 and 27 are drawings for explaining the connection of a COF module and other members according to an embodiment.

[0462] Referring to FIGS. 26 and 27, one end of the COF module (2000) is connected to the display panel (4000), and the other end is connected to the circuit board (3000).

[0463] Referring to Fig. 26, the display panel (4000) and the circuit board (3000) are disposed on one surface of the COF module (2000). That is, in the flexible circuit board according to the first embodiment, the display panel (4000) and the circuit board (3000) are disposed on the same surface of the COF module (2000).

[0464] Referring to FIG. 27, the display panel (4000) and the circuit board (3000) are disposed on different surfaces of the COF module (2000). That is, in the flexible circuit board according to the second embodiment, the display panel (4000) and the circuit board (3000) are disposed on different surfaces of the COF module (2000).

[0465] Since the COF module (2000) includes a flexible substrate, it has a rigid shape and a bent shape between the display panel (3000) and the circuit board (4000). That is, the COF module (2000) may include a bending area (BA).

[0466] The COF module (2000) connects the display panel (4000) and the circuit board (3000), which are arranged opposite each other, in a curved manner. Therefore, the thickness of the electronic device is reduced. Furthermore, the design freedom of the electronic device is enhanced. Furthermore, the COF module (2000) prevents wires from breaking even when in a curved configuration. Consequently, the reliability of the electronic device is enhanced.

[0467] Since the above COF module is flexible, it can be used in various electronic devices.

[0468] FIGS. 28 to 30 are drawings of electronic devices including flexible circuit boards according to embodiments.

[0469] For example, referring to FIG. 28, the COF module can be applied to a flexible touch window. Accordingly, a touch device device including the COF module can be a flexible touch device. Accordingly, the user can bend or fold it by hand. Such a flexible touch window can be applied to a wearable touch, etc.

[0470] Referring to Fig. 29, the COF module can be applied to various wearable touch devices including curved displays. Accordingly, an electronic device including the COF module can be slimmed down or made lighter.

[0471] Referring to Fig. 30, the COF module can be used in various electronic devices having a display portion, such as a TV, monitor, or laptop. In this case, the COF module can also be used in an electronic device having a curved display portion.

[0472]

[0473] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0474] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. Description; A first wiring pattern portion arranged on the above substrate; and A protective layer is disposed on the first wiring pattern portion and includes an open area, The first wiring pattern portion includes a first-first wiring pattern portion including a plurality of first pads arranged within the open area, The plurality of first pads include 1-1 pads and 1-2 pads that are alternately arranged, The leading edge of the above 1-1 pad and the leading edge of the above 1-2 pad are not aligned on the same line, The above 1-1 pad includes a first connecting portion adjacent to the tip of the 1-1 pad, and a first extension portion extending from the first connecting portion, A flexible circuit board, wherein the width of the first connecting portion is greater than the width of the first extension portion.

2. In paragraph 1, The above 1-2 pad includes a second connecting portion adjacent to the tip of the 1-2 pad, and a second extension portion extending from the second connecting portion, The first connecting portion does not overlap with the second connecting portion and the second extension portion along the separation direction of the first-1 pad and the first-2 pad, A flexible circuit board, wherein the second connecting portion overlaps the first extension portion along the separation direction.

3. In paragraph 2, A flexible circuit board, wherein the width of the second joint is smaller than the width of the first joint.

4. In paragraph 2, A flexible circuit board, wherein the width of the second connecting portion corresponds to the width of the first extension portion and the width of the second extension portion.

5. In paragraph 1, The above 1-1 wiring pattern part, A plurality of second pads disposed adjacent to the first side of the substrate and not covered by the protective layer; and a plurality of first connection patterns connecting the plurality of first pads and the plurality of second pads, The plurality of second pads include a second-1 pad connected to the first-1 pad and a second-2 pad connected to the first-2 pad, The above 2-1 pad includes a third connecting portion and a third extension portion having a width smaller than the width of the third connecting portion, The above 2-2 pad includes a fourth connecting portion and a fourth extension portion having a width smaller than the width of the fourth connecting portion, A flexible circuit board, wherein the 2-1 pad and the 2-2 pad are alternately arranged so that the 4th bonding portion is located between the 3rd bonding portions of two adjacent 2-1 pads.

6. In paragraph 1, The above first wiring pattern portion, A plurality of third pads arranged within the open area, a plurality of fourth pads arranged adjacent to the first side of the substrate, and a second connection pattern connecting the plurality of third pads and the plurality of fourth pads and including a plurality of branch lines, A flexible circuit board, wherein the second connection pattern connects between the plurality of third pads and the plurality of fourth pads through the plurality of branch lines.

7. In paragraph 6, The plurality of third pads include third-1 pads and third-2 pads that are arranged alternately, The leading edge of the above 3-1 pad and the leading edge of the above 3-2 pad are not aligned on the same line, A flexible circuit board, wherein the third-first pad includes a fifth connecting portion adjacent to a tip of the third-first pad, and a fifth extension portion extending from the fifth connecting portion and having a width smaller than a width of the fifth connecting portion.

8. In paragraph 6, The tips of the plurality of third pads are aligned on the same line, A flexible circuit board, wherein the plurality of third pads include a region whose width increases from the tip of each of the plurality of third pads toward the second connection pattern.

9. In paragraph 1, Further comprising a second wiring pattern portion arranged on the above description, A flexible circuit board, wherein the second wiring pattern portion includes a plurality of fifth pads arranged in the open area, a plurality of sixth pads arranged adjacent to the second side end of the substrate and not covered by the protective layer, and a third connection pattern connecting the plurality of fifth pads and the plurality of sixth pads.

10. In paragraph 9, The plurality of fifth pads include a fifth-first pad and a fifth-second pad that are alternately arranged, The leading edge of the above 5-1 pad and the leading edge of the above 5-2 pad are not aligned on the same line, A flexible circuit board, wherein the 5-1 pad includes a ninth connecting portion adjacent to a tip of the 5-1 pad, and a ninth extension portion extending from the ninth connecting portion and having a width smaller than a width of the ninth connecting portion.

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