Array substrate, display panel, and display device
By setting a shield at the via location of the high-resolution display panel, the problem of etching solution corroding metal lines and active patterns is solved, thereby improving the display quality and transmittance of the display panel.
Patent Information
- Application Number
- PCT/CN2024/098240
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2026-02-05
AI Technical Summary
During the etching process, high-resolution display panels may experience problems such as bright spots and bright/dark lines due to poor via coverage, which can cause etching solution to enter the gaps and corrode metal lines and active patterns.
A shield is provided at the via location. By increasing the shield to cover the edge of the via, the etching solution is prevented from entering and corroding the metal lines and active patterns. The shield, made of transparent conductive material, does not affect the transmittance of the display panel.
It effectively avoids the corrosion of metal lines and active patterns by etching solution, improves the display quality of display panel, avoids defects such as bright spots and bright/dark lines, and maintains high transmittance.
Smart Images
Figure CN2024098240_05022026_PF_FP_ABST
Abstract
Description
Array substrate, display panel and display device Technical Field
[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology
[0002] High-resolution (Pixels Per Inch, PPI) display technology has become an important research direction in the field of display technology in recent years. With the widespread use of electronic devices and the rapid development of network applications, people's demands for image clarity and precision are constantly increasing, placing higher demands on display technology. High-resolution display products offer a superior immersive display experience and have wide applications in near-eye display products.
[0003] Summary of the Invention
[0004] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:
[0005] Substrate;
[0006] A first active layer, located on one side of the substrate, includes: a plurality of first active patterns located in the pixel area; the first active pattern includes: a first part, a second part connected to one end of the first part, and a third part connected to the other end of the first part;
[0007] A first insulating layer, located on the side of the first active layer opposite to the substrate, has a plurality of first vias;
[0008] A first metal layer, located on the side of the first insulating layer opposite to the first active layer, includes: a plurality of first metal lines; the first metal lines are electrically connected to the second part through the first via;
[0009] The first conductive layer, located on the side of the first metal layer away from the first insulating layer, includes: a plurality of conductive portions and a plurality of first shielding portions located in the pixel area, wherein the orthographic projection of the conductive portions on the substrate does not overlap with the orthographic projection of the first shielding portions on the substrate; the conductive portions are electrically connected to the third portion; and the orthographic projection of the first shielding portions on the substrate covers the orthographic projection of the first via on the substrate.
[0010] In one possible implementation, the width of the first shielding portion perpendicular to the extension direction of the first metal line is greater than the width of the first via perpendicular to the extension direction of the first metal line.
[0011] In one possible implementation, the width of the first blocking portion perpendicular to the extension direction of the first metal line is greater than the width of the second portion perpendicular to the extension direction of the first metal line.
[0012] In one possible implementation, at the first via location, the first metal line includes: a first metal portion, a second metal portion, and a third metal portion; the first metal portion covers the bottom of the first via; the second metal portion is located on one side of the first metal portion perpendicular to the extension direction of the first metal line and extends along the sidewall of the first via; the third metal portion is located on the other side of the first metal portion perpendicular to the extension direction of the first metal line and extends along the sidewall of the first via.
[0013] In one possible implementation, in the direction from the substrate to the first conductive layer, at least one of the second metal portion and the third metal portion gradually decreases in thickness in the direction perpendicular to the extension of the first metal line.
[0014] In one possible implementation, the maximum thickness of the second metal portion in the direction perpendicular to the substrate is the same as the maximum thickness of the third metal portion in the direction perpendicular to the substrate; and the maximum length of the second metal portion in the direction perpendicular to the extension of the first metal line is equal to the maximum length of the third metal portion in the direction perpendicular to the extension of the first metal line.
[0015] In one possible implementation, the second metal portion covers only one sidewall of the first via; the third metal portion covers only the other sidewall of the first via.
[0016] In one possible implementation, the second metal portion covers the entire sidewall of the first via located on one side of the first metal line, and covers the portion of the first insulating layer on the side facing away from the substrate; the third metal portion covers the entire sidewall of the first via located on the other side of the first metal line, and covers the portion of the first insulating layer on the side facing away from the substrate.
[0017] In one possible implementation, the maximum thickness of the second metal portion in the direction perpendicular to the substrate is less than the maximum thickness of the third metal portion in the direction perpendicular to the substrate; and the maximum length of the second metal portion in the direction perpendicular to the extension of the first metal line is less than the maximum length of the third metal portion in the direction perpendicular to the extension of the first metal line.
[0018] In one possible implementation, the first via includes: a first sidewall and a second sidewall; wherein the first sidewall and the second sidewall are located on both sides of the first metal portion;
[0019] The second metal portion covers a portion of the first sidewall; the third metal portion covers a portion of the second sidewall; and the area of the second metal portion covering the first sidewall is smaller than the area of the third metal portion covering the second sidewall.
[0020] In one possible implementation, the first via includes: a first sidewall and a second sidewall; wherein the first sidewall and the second sidewall are located on both sides of the first metal portion along a direction perpendicular to the extension of the first metal line;
[0021] The second metal portion covers a portion of the first sidewall; the third metal portion covers the entire second sidewall and a portion of the surface of the first insulating layer surrounding the second sidewall that faces away from the substrate.
[0022] In one possible implementation, a second insulating layer is provided between the first conductive layer and the first metal layer; the second insulating layer includes: a first insulating portion and a second insulating portion located around the first insulating portion; the orthographic projection of the first insulating portion on the substrate overlaps with the orthographic projection of the first via on the substrate.
[0023] In one possible implementation, the first insulating part and the second insulating part are integrally connected.
[0024] In one possible implementation, the second insulating portion on at least one side perpendicular to the extension direction of the first metal wire has a first gap with the first insulating portion.
[0025] In one possible implementation, the first gap and the orthographic projection of the second metal portion onto the substrate are located on the same side as the orthographic projection of the first metal portion onto the substrate.
[0026] In one possible implementation, at the location of the first via, the first gap extends from the surface of the second insulating layer on the side opposite to the substrate to the bottom of the first via.
[0027] In one possible implementation, at the location of the first via, the first gap extends from the surface of the second insulating layer on the side opposite to the substrate to the first metal line.
[0028] In one possible implementation, the first shielding portion covers the first insulating portion, covers a portion of the second insulating portion surrounding the first insulating portion, and fills at least a portion of the first gap.
[0029] In one possible implementation, the first insulating portion has a first recessed portion at a position corresponding to the first metal portion that is recessed toward the substrate side, and a first protruding portion at a position corresponding to the second metal portion and the third metal portion that is protruding toward the side away from the substrate.
[0030] In one possible implementation, the distance between the first protrusion and the substrate is greater than the distance between the second insulating portion and the substrate.
[0031] In one possible implementation, the first blocking portion has a second recess at a position corresponding to the first recess and a second protrusion at a position corresponding to the first protrusion.
[0032] In one possible implementation, the linewidth of the first metal line is smaller than the width of the first via perpendicular to the extension direction of the first metal line.
[0033] In one possible implementation, the minimum distance in a first direction between the orthographic projection of the outer edge of the first shielding portion onto the substrate and the orthographic projection of the outer edge of the first via onto the substrate is greater than 0.52 μm.
[0034] In one possible implementation, the array substrate further includes: a second conductive layer located on the side of the first conductive layer opposite to the first metal layer; the second conductive layer includes: a plurality of first electrodes located in the pixel region;
[0035] The first electrode is electrically connected to the third part through the conductive part.
[0036] In one possible implementation, the array substrate further includes: a second metal layer located between the first active layer and the first metal layer, and a third metal layer located on the side of the first active layer facing the substrate;
[0037] The second metal layer includes: a plurality of second metal lines extending along a first direction; the third metal layer includes: a plurality of shielding patterns; the orthographic projection of the shielding patterns on the substrate covers the orthographic projection of the first via on the substrate.
[0038] In one possible implementation, the orthographic projection of the shading pattern onto the substrate covers the orthographic projection of the first shading portion onto the substrate.
[0039] In one possible implementation, the first metal wire extends along a second direction;
[0040] The first part includes: a first sub-part extending along the second direction, and a second sub-part connected to the first sub-part and extending along the third direction; the second part is connected to the end of the second sub-part away from the first sub-part, and the third part is connected to the end of the first sub-part away from the second sub-part.
[0041] In one possible implementation, the first metal wire includes: a first sub-metal portion and a second sub-metal portion arranged alternately along the second direction; the first sub-metal portion and the second sub-metal portion extend in different directions.
[0042] The orthographic projection of the second sub-metal portion onto the substrate overlaps with the orthographic projection of the first via onto the substrate; the extension direction of the first portion is the same as the extension direction of the first sub-metal portion.
[0043] In one possible implementation, the array substrate further includes a third signal line and a fourth signal line located in the peripheral region; the third signal line is on the same layer as the first metal line; a third insulating layer is provided between the fourth signal line and the third signal line, and the third insulating layer has a plurality of second vias; the third signal line is electrically connected through the second vias.
[0044] The first conductive layer further includes: a plurality of second shielding portions; the orthographic projection of the second shielding portions on the substrate covers the orthographic projection of the second via on the substrate.
[0045] In one possible implementation, the array substrate further includes: a second active layer located on the side of the first active layer facing the substrate, a driving source, a driving drain, and a driving gate located on the side of the second active layer away from the substrate.
[0046] The material of the first active layer includes: metal oxide; the material of the second active layer includes: low-temperature polycrystalline silicon.
[0047] This disclosure also provides a display panel, which includes the array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate.
[0048] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description
[0049] Figure 1 is one of the top views of the array substrate provided in the embodiments of this disclosure;
[0050] Figure 2A is a second top view of the array substrate provided in the embodiment of this disclosure;
[0051] Figure 2B is a schematic diagram of the single film layer of the third metal layer in Figure 2A;
[0052] Figure 2C is a schematic diagram of the first active layer in Figure 2A;
[0053] Figure 2D is a schematic diagram of a single film layer of the second metal layer in Figure 2A;
[0054] Figure 2E is a schematic diagram of the single film layer of the first metal layer in Figure 2A;
[0055] Figure 2F is a schematic diagram of a single film layer of the first conductive layer in Figure 2A;
[0056] Figure 2G is a schematic diagram of a single film layer of the second conductive layer in Figure 2A;
[0057] Figure 2H is a schematic diagram of the cross section along the dashed line f in Figure 2A;
[0058] Figure 2I is a third top view of the array substrate provided in the embodiment of this disclosure;
[0059] Figure 3A is a schematic diagram of the array substrate after the third conductive layer is superimposed on Figure 2A;
[0060] Figure 3B is a schematic diagram of a single film layer of the third conductive layer in Figure 3A;
[0061] Figure 4A is one of the actual morphological diagrams corresponding to the dashed line width S1 in Figure 2H;
[0062] Figure 4B is a schematic diagram showing the extension of the second gap J2 to the bottom of the first through hole K1;
[0063] Figure 4C is a schematic diagram of Figure 4A after the first shielding part D11 is covered;
[0064] Figure 4D is the second schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;
[0065] Figure 4E is the third schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;
[0066] Figure 4F is the fourth schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;
[0067] Figure 5A is the fifth schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;
[0068] Figure 5B is a schematic diagram of Figure 5A after the first shielding part D11 is covered;
[0069] Figure 5C is the sixth schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;
[0070] Figure 5D is the seventh schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;
[0071] Figure 5E is a schematic diagram after Figure 5D covers the first shielding part;
[0072] Figure 6A is the eighth schematic diagram of the actual morphology corresponding to the dashed line width S1 in Figure 2H;
[0073] Figure 6B is a schematic diagram of Figure 6A after the first shielding part D11 is covered;
[0074] Figure 7 is a third top view of the array substrate provided in the embodiment of this disclosure;
[0075] Figure 8 is one of the cross-sectional schematic diagrams of the array substrate provided in the embodiments of this disclosure;
[0076] Figure 9 is a second cross-sectional schematic diagram of the array substrate provided in the embodiments of this disclosure. Detailed Implementation
[0077] Different forms may be used to implement this disclosure. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited solely to the content described in the following embodiments. Without conflict, the embodiments and features described in these embodiments can be arbitrarily combined with each other.
[0078] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values shown in the drawings.
[0079] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure can include two or more quantities.
[0080] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.
[0081] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.
[0082] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.
[0083] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0084] Furthermore, the gate of a transistor can be referred to as the control electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.
[0085] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.
[0086] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.
[0087] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."
[0088] In this specification, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this specification, "roughly the same" can mean that the values differ by no more than 10%.
[0089] In high PPI display panels, the active pattern is typically partially connected to the pixel electrode via an adapter electrode, while the other part of the active pattern is connected to the data line via vias. Due to the smaller linewidth and aperture of high PPI display panels, the insulation layer covering the vias may have poor coverage. For example, gaps may exist around the vias. When etching to form the adapter electrode, the etching liquid may enter the gaps, corroding the data line inside the via, or even corroding the oxide active pattern connected to the data line, resulting in bright spots, dark lines, and other related display defects on the display panel.
[0090] In view of the above, this disclosure provides an array substrate, as shown in Figures 1 and 2A-2H. Figure 1 is one of the top views of the array substrate provided in this disclosure; Figure 2A is another top view of the array substrate provided in this disclosure; Figure 2B is a single-film schematic diagram of the third metal layer in Figure 2A; Figure 2C is a single-film schematic diagram of the first active layer in Figure 2A; Figure 2D is a single-film schematic diagram of the second metal layer in Figure 2A; Figure 2E is a single-film schematic diagram of the first metal layer in Figure 2A; Figure 2F is a single-film schematic diagram of the first conductive layer in Figure 2A; Figure 2G is a single-film schematic diagram of the second conductive layer in Figure 2A; and Figure 2H is a cross-sectional schematic diagram along the dashed line f in Figure 2A. The substrate has a pixel region AA and a peripheral region BB located around the pixel region AA, including:
[0091] Substrate 1;
[0092] The first active layer 2, located on one side of the substrate 1, includes: a plurality of first active patterns 20 located in the pixel region AA; the first active pattern 20 includes: a first part 21, a second part 22 connected to one end of the first part 21, and a third part 23 connected to the other end of the first part 21; optionally, as shown in FIG2C, the first part 21 includes: a first sub-part 211 extending along the second direction Y, and a second sub-part 212 connected to the first sub-part 211 and extending along the third direction Z; the second part 22 is connected to the end of the second sub-part 212 away from the first sub-part 211, and the third part 23 is connected to the end of the first sub-part 211 away from the second sub-part 212;
[0093] The first insulating layer 3 is located on the side of the first active layer 2 away from the substrate 1 and has a plurality of first vias K1;
[0094] The first metal layer M1, located on the side of the first insulating layer 3 opposite to the first active layer 2, includes: multiple first metal lines M10; the first metal lines M10 are electrically connected to the second part 22 through a first via K1; optionally, the first metal lines M10 can be data lines, and the first metal layer M1 can be the layer where the data lines are located; specifically, the pixel area AA can have multiple first transistors, and the second part 22 can serve as the first electrode of the first transistor at the position where it overlaps with the first metal lines M10; the second part 22 can be turned on at the position where it overlaps with the first metal lines M11, realizing the electrical connection between the first transistor and the data lines;
[0095] The first conductive layer D1, located on the side of the first metal layer M1 opposite to the first insulating layer 3, includes: multiple conductive portions D10 and multiple first shielding portions D11 located in the pixel area AA. The orthographic projections of the conductive portions D10 onto the substrate 1 and the orthographic projections of the first shielding portions D11 onto the substrate 1 do not overlap. The conductive portions D10 are electrically connected to the third portion 23. Optionally, as shown in Figures 2A and 2H, the conductive portions D10 can be electrically connected to the third portion 23 through the third via K3. The conductive portions D10 can further be electrically connected to the first electrode D20 through the fourth via K4. The first electrode D20 can be a pixel electrode. The orthographic projection of the first shielding portions D11 onto the substrate 1 covers the orthographic projection of the first via K1 onto the substrate 1. Specifically, the first conductive layer D1 can be a transparent conductive layer, and the conductive portions D10 can serve as the second electrode of the first transistor, connecting the first active pattern 20 and the first electrode D20. Specifically, the orthographic projection shape of the conductive portions D10 onto the substrate 1 can be rectangular.
[0096] In this embodiment, the first conductive layer D1 includes a plurality of conductive portions D10 and a plurality of first shielding portions D11. The orthographic projection of the first shielding portion D11 onto the substrate 1 covers the orthographic projection of the first via K1 onto the substrate 1. By increasing the shielding of the first via K1 by the first shielding portion D11, the etching solution for etching the conductive portion D10 is effectively prevented from entering the first via K1 through the gap at the edge of the hole and corroding the first metal line M10 and the first active pattern 20, thereby causing defects such as bright spots and bright / dark lines. Moreover, since the first shielding portion D11 is normally connected to the conductive portion D10, and the conductive portion D10 is usually made of transparent material, which is transparent in the visible light wavelength range, the use of the first shielding portion D11 does not affect the transmittance of the entire display panel.
[0097] In related technologies, on high-resolution LTPO structure display panels, the first metal line M10 needs to be extremely fine, as shown in Figure 1. The linewidth a4 of the first metal line M10 is smaller than the size a2 of the first via K1. Therefore, the film layer above the first via K1 has poor coverage, resulting in broken voids. For example, as shown in Figure 4A, a first gap J1 appears at the location of the second insulating layer 4 at the position of the first via K1. The conductive portion D10 above the second insulating layer 4 uses a transparent material (e.g., indium tin oxide), and is generally etched using a wet etching method. Since the etching solution is acidic, when the second insulating layer 4 has poor coverage, causing a first gap J1 at the location of the first via K1, the etching solution can enter the first via K1 through the first gap J1, thereby corroding the first metal line M10. (Optionally, the first metal line M10 may include multiple sub-metal layers stacked together, for example...) The structure may include a first sub-metal layer M01, a second sub-metal layer M02, and a third sub-metal layer M03 stacked sequentially. The first sub-metal layer M01 may be made of titanium or molybdenum, the second sub-metal layer M02 may be made of aluminum, and the third sub-metal layer M03 may be made of titanium or molybdenum. Optionally, the first metal line M10 may be a single layer of metal or an alloy. For example, if it is a single layer of metal, the first metal line M10 may be made of molybdenum; if it is an alloy, the first metal line M10 may be made of WMo alloy. The first active pattern 20 below the first metal line M10 can lead to high resistance in the first metal line M10, and may even result in breakage. Furthermore, due to the chemical reaction between the acidic etching liquid and the first active pattern 20 of the oxide (e.g., indium gallium zinc oxide), for example, Zn may be deposited, causing a negative bias in the electrical characteristics of the oxide transistor, resulting in bright spots and other related electrical defects. In this embodiment of the present disclosure, referring to FIG4C, by covering the location of the first via K1 with the first shielding part D11, the first shielding part D11 shields the location of the first via K1, effectively preventing the etching solution from entering the hole of the first via K1 through the gap at the edge of the hole, thereby preventing the etching solution from corroding the first metal line M10 and / or the first active pattern 20, and thus improving the defects such as bright spots and bright and dark lines caused by the corrosion of the first metal line M10 and / or the first active pattern 20.
[0098] In one possible implementation, referring to FIG1, the minimum distance a5 between the orthographic projection of the outer edge of the first shielding portion D11 onto the substrate 1 and the orthographic projection of the outer edge of the first via K1 onto the substrate 1 in the direction perpendicular to the extension of the first metal line M10 is greater than 0.52 μm.
[0099] In one possible implementation, the first shielding portion D11 is generally designed as a cube or a circle. To ensure complete shielding, the size and alignment deviation of the first shielding portion D11 need to be considered. In this embodiment, the minimum distance a5 between the orthographic projection of the outer edge of the first shielding portion D11 onto the substrate 1 and the orthographic projection of the outer edge of the first via K1 onto the substrate 1 in the first direction X is greater than 0.52 μm. This ensures effective shielding of the first via K1 by the first shielding portion D11 within the range considering the influence of alignment deviation. Taking the size of the first via K1 CDC = 1.5 μm as an example, the first error tolerance value CDA in the first direction X is 0.6 μm, the second error tolerance value CDB in the second direction Y is 0.6 μm, and the alignment deviation is OVL = 0.3 μm. Then, the required size of the shielding on one side is... Therefore, the required size of the first shielding part D11 is CD = CDC + 2 * CD1 = 2.54 μm.
[0100] In one possible implementation, referring to FIG1, the width a1 of the first blocking portion D11 in the direction perpendicular to the extension of the first metal line M10 is greater than the width a2 of the first via K1 in the direction perpendicular to the extension of the first metal line M10. This ensures that the first blocking portion D11 fully covers the first via K1.
[0101] In one possible implementation, referring to FIG1, the width a1 of the first blocking portion D11 in the direction perpendicular to the extension of the first metal line M10 is greater than the width a3 of the second portion 22 in the direction perpendicular to the extension of the first metal line M10.
[0102] In one possible implementation, referring to Figures 4A-4C, where Figure 4A is one of the actual topographical diagrams corresponding to the dashed line width S1 of Figure 2H, Figure 2H is one of the schematic diagrams of the array substrate, Figure 4B is a schematic diagram of the second gap J2 extending to the bottom of the first via K1, and Figure 4C is a schematic diagram of Figure 4A after covering the first shielding portion D11. At the location of the first via K1, the first metal line M10 includes: a first metal portion M11, a second metal portion M12, and a third metal portion M13; the first metal portion M11 covers the bottom of the first via K1; the second metal portion M12 is located on one side of the first metal portion M11 perpendicular to the extension direction of the first metal line M10 and extends along the sidewall of the first via K1; the third metal portion M13 is located on the other side of the first metal portion M11 perpendicular to the extension direction of the first metal line M10 and extends along the sidewall of the first via K1.
[0103] In one possible implementation, referring to FIG4A, in the direction from the substrate 1 to the first conductive layer D1, at least one of the second metal portion M12 and the third metal portion M13 gradually decreases in thickness c1 perpendicular to the extension direction of the first metal line M10 (for example, if the first metal line M10 extends along the first direction X, then the extension direction perpendicular to the first metal line M10 is also the direction perpendicular to the first direction X). That is, as shown in FIG4A, from bottom to top, the thickness c1 of the second metal portion M12 gradually decreases along the extension direction perpendicular to the first metal line M10, forming a sharp angle.
[0104] In one possible implementation, referring to FIG4A, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 is the same as the maximum thickness d12 of the third metal portion M13 in the direction perpendicular to the substrate 1; and the maximum length d13 of the second metal portion M12 in the direction perpendicular to the extension of the first metal line M10 is equal to the maximum length d14 of the third metal portion M13 in the direction perpendicular to the extension of the first metal line M10.
[0105] In one possible implementation, referring to FIG4A, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 is greater than the maximum depth d20 of the first via K1 in the direction perpendicular to the substrate 1. In another possible implementation, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 may be equal to the maximum depth d20 of the first via K1 in the direction perpendicular to the substrate 1. In yet another possible implementation, the maximum thickness d11 of the second metal portion M12 in the direction perpendicular to the substrate 1 is less than the maximum depth d20 of the first via K1 in the direction perpendicular to the substrate 1.
[0106] In one possible implementation, referring to FIG4A, the second metal portion M12 covers only one sidewall of the first via K1; the third metal portion M13 covers only the other sidewall of the first via K1. For example, as shown in FIG4A, the second metal portion M12 covers only the left sidewall of the first via K1; the third metal portion M13 covers only the right sidewall of the first via K1. That is, as shown in FIG4A, the second metal portion M12 will not rise to the upper surface of the left side of the first insulating layer 3 of the first via K1; the third metal portion M13 will not rise to the upper surface of the right side of the first insulating layer 3 of the first via K1.
[0107] In one possible implementation, referring to FIG6A, the second metal portion M12 covers the entire sidewall of the first via K1 located on one side of the first metal line M10, and covers the portion of the first insulating layer 3 on the side facing away from the substrate 1; the third metal portion M13 covers the entire sidewall of the first via K1 located on the other side of the first metal line M10, and covers the portion of the first insulating layer 3 on the side facing away from the substrate 1. Specifically, referring to FIG6A, the first via K1 includes: a first sidewall K11 and a second sidewall K12; wherein, the first sidewall K11 and the second sidewall K12 are respectively located on both sides of the first metal portion M11 perpendicular to the extending direction of the first metal line M10; referring to FIG6A, the second metal portion M12 covers the entire first sidewall K11, and covers the portion of the first insulating layer 3 on the side facing away from the substrate 1 around the first sidewall K11; the third metal portion M13 covers the entire second sidewall K12, and covers the portion of the first insulating layer 3 on the side facing away from the substrate 1.
[0108] In one possible implementation, as shown in FIG6A, the line width of the first metal line M10 in the first direction X can be greater than the width of the first via K1 in the first direction X. In this way, by making the line width of the first metal line M10 at the position of the first via K1 wider (the first metal line M10 can still be made thinner at the position outside the first via K1), the second insulating layer 4 can be prevented from breaking at the position of the first via K1, thereby preventing the etching solution from corroding the first metal line M10 and / or the first active pattern 20 along the broken gap.
[0109] In one possible implementation, due to actual manufacturing process reasons, the relative positions of the first metal line M10 and the first via K1 may be offset, causing the climbing height of the first metal line M10 to be different on different sides of the first via K1. For example, referring to Figures 4E and 5A, the maximum heights of the second metal parts M12 and the third metal parts M13 on both sides of the first metal part M11 in the direction perpendicular to the substrate 1 may be different, and their maximum lengths in the direction perpendicular to the extension of the first metal line M10 may also be different. For example, as shown in Figures 4E and 5A, the maximum thickness d11 of the second metal part M12 in the direction perpendicular to the substrate 1 is less than the maximum thickness d12 of the third metal part M13 in the direction perpendicular to the substrate 1; and the maximum length d13 of the second metal part M12 in the direction perpendicular to the extension of the first metal line M10 is less than the maximum length d14 of the third metal part M13 in the direction perpendicular to the extension of the first metal line M10.
[0110] In one possible implementation, referring to FIG4E, the first via K1 includes: a first sidewall K11 and a second sidewall K12; wherein the first sidewall K11 and the second sidewall K12 are respectively located on both sides of the first metal portion M11; the second metal portion M12 covers a portion of the first sidewall K11; the third metal portion M13 covers a portion of the second sidewall K12; and the area of the second metal portion M12 covering the first sidewall K11 is smaller than the area of the third metal portion M13 covering the second sidewall K12. That is, although the relative position of the first metal line M10 and the first via K1 may be offset, neither the second metal portion M12 nor the third metal portion M13 has yet climbed to the upper surface of the portion of the first insulating layer 3 surrounding the first via K1.
[0111] In one possible implementation, referring to FIG5A, the first via K1 includes: a first sidewall K11 and a second sidewall K12; wherein the first sidewall K11 and the second sidewall K12 are respectively located on both sides of the first metal portion M11; the second metal portion M12 covers a portion of the first sidewall K11; the third metal portion M13 covers the entire second sidewall K12 and covers a portion of the surface of the first insulating layer surrounding the second sidewall K12 facing away from the substrate 1. That is, the relative position of the first metal line M10 and the first via K1 may be offset, and the third metal portion M13 rises to a portion of the upper surface of the first insulating layer 3 surrounding the first via K1.
[0112] In one possible implementation, referring to Figures 2H and 4A-4E, a second insulating layer 4 is provided between the first conductive layer D1 and the first metal layer M1; the second insulating layer 4 includes: a first insulating portion 41, and a second insulating portion 42 located around the first insulating portion 41; the orthographic projection of the first insulating portion 41 onto the substrate 1 overlaps with the orthographic projection of the first via K1 onto the substrate 1; optionally, the portion of the second insulating layer 4 at the position corresponding to the first via K1 can be used as the first insulating portion 41, and the portion other than the first insulating portion 41 can be used as the second insulating portion 42.
[0113] In one possible implementation, referring to Figures 4A-4C, at least one side of the second insulating portion 42 perpendicular to the extension direction of the first metal wire M10 has a first gap J1 between it and the first insulating portion 41. In one possible implementation, referring to Figure 4B, both sides of the second insulating portion 42 perpendicular to the extension direction of the first metal wire M10 have a first gap J1 between it and the first insulating portion 41. In one possible implementation, referring to Figure 5D, one side of the second insulating portion 42 perpendicular to the extension direction of the first metal wire M10 has a first gap J1 between it and the first insulating portion 41. That is, due to the extremely fineness of the first metal wire M10, the coverage of the second insulating layer 4 at the location of the first via K1 may be poor, which may result in a first gap J1 between the first insulating portion 41 and the second insulating portion 42.
[0114] In one possible implementation, referring to FIG5D, the orthographic projections of the first gap J1 and the second metal portion M12 onto the substrate 1 are located on the same side as the orthographic projection of the first metal portion M11 onto the substrate 1. For example, as shown in FIG5D, the orthographic projections of the first gap J1 and the second metal portion M12 onto the substrate 1 are located to the left of the orthographic projection of the first metal portion M11 onto the substrate 1. That is, when the relative position of the first metal line M10 and the first via K1 is offset, the first gap J1 can be located on the opposite side of the offset direction. For example, as shown in FIG5D, if the first metal line M10 is offset to the right relative to the center of the first via K1, a first gap J1 will be generated between the second insulating portion 42 and the first insulating portion 41 on the left side of the first via K1.
[0115] In one possible implementation, referring to FIG4A, at the location of the first via K1, the first gap J1 extends from the surface of the second insulating layer 4 away from the substrate 1 to the first metal line M10.
[0116] In one possible implementation, referring to FIG4B, at the location of the first via K1, the first gap J1 extends from the surface of the second insulating layer 4 on the side opposite to the substrate 1 to the bottom of the first via K1. That is, there is also a gap between the first metal line M10 and the sidewall of the first via K1.
[0117] In one possible implementation, referring to FIG4C, the first blocking portion D11 covers the first insulating portion 41, covers a portion of the second insulating portion 42 surrounding the first insulating portion 41, and fills at least a portion of the first gap J1. In one possible implementation, the first blocking portion D11 fills the entire first gap J1; in another possible implementation, the first blocking portion D11 may also be a portion that fills the first gap J1.
[0118] In one possible implementation, as shown in Figures 4D, 5A-5B, and 6A-6B, there may be no first gap J1 between the first insulating part 41 and the second insulating part 42. That is, the first insulating part 41 and the second insulating part 42 are integrally connected, and the first insulating layer 4 is a continuous structure at the first through hole K1 and its periphery.
[0119] In one possible implementation, as shown in Figures 4F, 5D, and 5E, Figure 5E is a schematic diagram of Figure 5D after the first shielding portion is covered. The first insulating portion 41 and the second insulating portion 42 may also have a first gap J1 on only one side.
[0120] In one possible implementation, as shown in Figures 4C, 5B, and 6B, the first shielding portion D11 covers the first insulating portion 41 and covers a portion of the second insulating portion 42 surrounding the first insulating portion 41.
[0121] In one possible implementation, referring to FIG5B, the first metal line M10 may include multiple sub-metal layers stacked together. For example, it may include a first sub-metal layer M01, a second sub-metal layer M02, and a third sub-metal layer M03 stacked sequentially. The first sub-metal layer M01 may be made of titanium or molybdenum, the second sub-metal layer M02 may be made of aluminum, and the third sub-metal layer M03 may be made of titanium or molybdenum. At the edge of the first metal line M10, the second sub-metal layer M02 is recessed relative to the first sub-metal layer M01 and / or the third sub-metal layer M03, that is, there is an over-etching of aluminum. In another possible implementation, referring to FIG5C, at the edge of the first metal line M10, the second sub-metal layer M02 is approximately flush with the first sub-metal layer M01 and / or the third sub-metal layer M03, that is, there may be no over-etching of aluminum.
[0122] In one possible implementation, referring to FIG4A, the first insulating portion 41 has a first recessed portion 410 recessed towards the substrate 1 at a position corresponding to the first metal portion M11, and a first protruding portion 420 protruding away from the substrate 1 at a position corresponding to the second metal portion M12 and the third metal portion M13.
[0123] In one possible implementation, as shown in FIG4A, the maximum distance between the first protrusion 420 and the substrate 1 is greater than the maximum distance between the second insulating portion 42 and the substrate 1.
[0124] In one possible implementation, referring to FIG4C, the first blocking portion D11 has a second recessed portion D111 at a position corresponding to the first recessed portion 410, and a second protruding portion D112 at a position corresponding to the first protruding portion 420.
[0125] In one possible embodiment, as shown in Figures 2A and 2H, the array substrate further includes: a second conductive layer D2 located on the side of the first conductive layer D1 opposite to the first metal layer M1; the second conductive layer D2 includes: a plurality of first electrodes D20 located in the pixel area AA; the first electrodes D20 are electrically connected to the third part 23 through conductive portions D10; in one possible embodiment, the material of the conductive portion D10 and the material of the first electrodes D20 may be the same.
[0126] In one possible implementation, the first electrode D20 is a pixel electrode, and the second conductive layer D2 can be the layer containing the pixel electrode. In one possible implementation, the second conductive layer D2 can be a pixel electrode layer; in one possible implementation, the second conductive layer D2 can be a transparent electrode layer; in one possible implementation, the material of the second conductive layer D2 can include a metal oxide. For example, one or a combination of indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), and indium-doped cadmium oxide.
[0127] In one possible implementation, referring to FIG2I, the array substrate further includes: a second metal layer M2 located between the first active layer 2 and the first metal layer M1, and a third metal layer M3 located on the side of the first active layer 2 facing the substrate 1; the second metal layer M2 includes: a plurality of second metal lines M20 extending along the first direction X; the third metal layer M3 includes: a plurality of shielding patterns M33; the orthographic projection of the shielding pattern M33 onto the substrate 1 covers the orthographic projection of the first via K1 onto the substrate 1. In this embodiment of the present disclosure, the array substrate further includes a plurality of shielding patterns M33, which can achieve light shielding at the location of the first via K1.
[0128] In one possible implementation, as shown in FIG2A, the orthographic projection of the shading pattern M33 onto the substrate 1 covers the orthographic projection of the first shading portion D11 onto the substrate 1.
[0129] In one possible implementation, the second metal line M20 can be a gate line.
[0130] In one possible implementation, referring to Figures 2A and 2H, the third metal layer M3 further includes a third metal line M30 extending along the first direction X; the orthographic projection of the third metal line M30 onto the substrate 1 covers the orthographic projection of the second metal line M20 onto the substrate 1. Optionally, the orthographic projection of the third metal line M30 onto the substrate 1 covers the portion of the orthographic projection of the first active pattern 20 onto the substrate 1, thereby preventing external light from illuminating the channel region of the first active pattern 20 and affecting the transistor characteristics.
[0131] In one possible implementation, the orthographic projection shape of the first shielding portion D11 onto the substrate 1 is rectangular, circular, elliptical, triangular, trapezoidal, pentagonal, hexagonal, or octagonal.
[0132] In one possible implementation, the orthographic projection shape of the occlusion pattern M33 onto the substrate 1 is rectangular, circular, elliptical, triangular, trapezoidal, pentagonal, hexagonal, or octagonal.
[0133] In one possible implementation, the orthographic projection shape of the first blocking portion D11 onto the substrate 1 can be similar to the orthographic projection shape of the blocking pattern M33 onto the substrate 1, for example, both being rectangular; or for example, both being circular.
[0134] In one possible implementation, referring to FIG2A, the first metal line M10 extends along the second direction Y. That is, the first metal line M10 is a straight line extending along the second direction Y.
[0135] In one possible implementation, referring to FIG7, the first metal line M10 includes: a first sub-metal portion M1a and a second sub-metal portion M1b alternately arranged along the second direction Y; the first sub-metal portion M1a and the second sub-metal portion M1b have different extending directions; the orthographic projection of the second sub-metal portion M1b onto the substrate 1 overlaps with the orthographic projection of the first via K1 onto the substrate 1; the extending direction of the first portion 21 is the same as the extending direction of the first sub-metal portion M1a. That is, the first metal line M10 can also be a zigzag shape. When the first metal line M10 is a zigzag shape, the extending direction of the first portion 21 can be the same as the extending direction of the first sub-metal portion M1a.
[0136] In one possible implementation, referring to FIG8, the array substrate further includes a third signal line M13 and a fourth signal line M14 located in the peripheral region BB; the third signal line M13 is on the same layer as the first metal line M10; a third insulating layer is provided between the fourth signal line M14 and the third signal line M13, and the third insulating layer has a plurality of second vias K2; the third signal line M13 is electrically connected through the second vias K2; the first conductive layer D1 further includes a plurality of second shielding portions D12; the orthographic projection of the second shielding portion D12 on the substrate 1 covers the orthographic projection of the second vias K2 on the substrate. In this embodiment of the present disclosure, for the third signal line M13 in the peripheral region BB that is on the same layer as the first metal line M10, when it is connected to the fourth signal line M14 in the slit through the second vias K2, a second shielding portion D12 can also be provided at the location of the second vias K2 to prevent the etching solution from corroding the third signal line M13 through the periphery of the second vias K2, thus preventing the third signal line M13 from malfunctioning.
[0137] In one possible implementation, referring to Figures 3A-3B and Figure 8, the array substrate further includes: a third conductive layer D3 located on the side of the second conductive layer D2 facing away from the substrate 1, and a fourth metal layer M4 located on the side of the third conductive layer D3 facing away from the substrate 1; wherein, the third conductive layer D3 can be a common electrode layer, and the fourth metal layer M4 can be in direct contact with the third conductive layer D3 to reduce the resistance of the third conductive layer D3; wherein, the fourth metal layer M4 can include: a plurality of light-shielding patterns M40, the plurality of light-shielding patterns M40 can include a first light-shielding pattern extending along a first direction X, and a second light-shielding pattern extending along a second direction Y, wherein, the orthographic projection of the first light-shielding pattern on the substrate 1 can overlap with the orthographic projection of the second metal line M20 on the substrate 1, and the orthographic projection of the second light-shielding pattern on the substrate 1 can overlap with the orthographic projection of the first metal line M10 on the substrate 1.
[0138] In one possible implementation, referring to FIG8, the array substrate further includes: a buffer layer 11 located on one side of the substrate 1, a first gate insulating layer 12 located on the side of the buffer layer 11 away from the substrate 1, a first interlayer dielectric layer 13 located on the side of the first gate insulating layer 12 away from the buffer layer 11, a second gate insulating layer 31 located on the side of the first interlayer dielectric layer 13 away from the first gate insulating layer 12, a second interlayer dielectric layer 32 located on the side of the second gate insulating layer 31 away from the first interlayer dielectric layer 13, a third interlayer dielectric layer 14 located on the side of the second interlayer dielectric layer 32 away from the second gate insulating layer 31, a planarization layer 15 located on the side of the third interlayer dielectric layer 14 away from the second interlayer dielectric layer 32, and a passivation layer 16 located on the side of the planarization layer 15 away from the third interlayer dielectric layer 14.
[0139] The first insulating layer 3 may include a second gate insulating layer 31 and a second interlayer dielectric layer 32; the second insulating layer 4 may include a third interlayer dielectric layer 14.
[0140] In one possible implementation, referring to FIG9, the first electrode D20 may include a first sub-electrode D21 and a second sub-electrode D22; the first sub-electrode D21 is partially located at the bottom of the first via K1, partially located on the sidewall of the fourth via K4, and partially extended to the surface of the planarization layer 15 away from the substrate 1; the second sub-electrode D22 is located on the side of the first sub-electrode D21 away from the substrate 1, and is in direct contact with the portion of the first sub-electrode D21 that extends to the surface of the planarization layer 15 away from the substrate 1.
[0141] In one possible implementation, referring to FIG9, the array substrate further includes a filling portion 62 filling the fourth via K4 to achieve planarization at the first electrode D20.
[0142] In one possible implementation, as shown in FIG8 or FIG9, the array substrate further includes a first spacer 18 located on the side of the second conductive layer D2 facing away from the substrate 1.
[0143] In one possible implementation, referring to Figures 8 or 9, the array substrate further includes a color filter layer located on the side of the second conductive layer D2 facing the substrate 1; the color filter layer includes a plurality of color resists 17, for example, it may include a red color resist, a green color resist, and a blue color resist. In this embodiment of the present disclosure, the array substrate further includes a color filter layer to avoid color crosstalk between different sub-pixels, which can be applied to display products with a PPI of 1500 or higher.
[0144] In one possible implementation, the array substrate may not have a color filter layer. Instead, a fourth metal layer M4 can be used to improve cross-color between different sub-pixels, thereby reducing the level of cross-color without increasing the black matrix.
[0145] In one possible implementation, referring to FIG8, the array substrate further includes: a second active layer 5 located on the side of the first active layer 2 facing the substrate 1, a driving source drain 61 and a driving drain 62 located on the side of the second active layer 5 facing away from the substrate 1, and a driving gate 7. In one possible implementation, referring to FIG8, the driving source drain 61 and the driving drain 62 can be in the same layer and with the same material as the first metal trace M10, and the driving gate 7 can be in the same layer and with the same material as the third metal layer M3.
[0146] In one possible implementation, referring to FIG8, the array substrate further includes, in the peripheral region BB: a first driving electrode M31, a second driving electrode M16, a third driving electrode D32, a fourth driving electrode M17, and a fifth driving electrode D31, wherein the first driving electrode M31 and the second driving electrode M16 can be electrically connected through the second driving electrode M16, and the fourth driving electrode M17 and the fifth driving electrode D31 are electrically connected. Specifically, the first driving electrode M31 can serve as a first signal line, and the fourth driving electrode M17 can serve as a second signal line. The first signal line may include a signal line electrically connected to the gate driving circuit, and / or a signal line electrically connected to a multiplexer; the second signal line may include a signal line electrically connected to the gate driving circuit, and / or a signal line electrically connected to a multiplexer. The first signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light emission control line. The second signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light emission control line.
[0147] In one possible implementation, referring to Figure 8, the material of the first active layer 2 includes metal oxide; the material of the second active layer 5 includes low-temperature polycrystalline silicon. In this embodiment, the array substrate uses LTPO (Low Temperature Polycrystalline Oxide) technology to integrate both LTPS (Low Temperature Poly-Silicon) and Oxide TFTs (Thin Film Transistors), enabling AR and VR products to have high resolution (e.g., above 1000 PPI), high aperture ratio, and high transmittance.
[0148] In one possible implementation, the material of the first active layer 2 includes a metal oxide semiconductor material. The metal oxide semiconductor material may include any one or more of the following: amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxides (RE-OS), wherein the rare earth element-doped metal oxide may include lanthanide-doped metal oxides (Ln-OS). The crystallization state of the active layer material can be amorphous, partially crystalline, or polycrystalline. In this embodiment, the material of the first active layer 2 is a rare earth element-doped metal oxide. Even when exposed to light, the first active layer 2 can maintain stable performance, thus eliminating the need for a light-shielding layer in the pixel light-transmitting area and further improving the aperture ratio of the display panel. In this embodiment, the first active layer 2 of the display area transistor can be an oxide active layer; that is, thin-film transistors with oxide active layers have advantages such as low leakage current.
[0149] Based on the same inventive concept, this disclosure also provides a display panel, which includes an array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate.
[0150] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.
[0151] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0152] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.
Claims
1. An array substrate having a pixel region and a peripheral region located at a periphery of the pixel region, wherein, The application relates to a substrate, a first active layer, a first insulating layer, a first metal layer, and a first conductive layer. The first active layer is located on one side of the substrate and comprises a plurality of first active patterns in the pixel region; each first active pattern comprises a first part, a second part connected to one end of the first part, and a third part connected to the other end of the first part. The first insulating layer is located on the side of the first active layer away from the substrate and has a plurality of first vias. The first metal layer is located on the side of the first insulating layer away from the first active layer and comprises a plurality of first metal lines; the first metal lines are electrically connected to the second parts through the first vias. The first conductive layer is located on the side of the first metal layer away from the first insulating layer and comprises a plurality of conductive parts in the pixel region and a plurality of first shielding parts; the conductive parts do not overlap with the first shielding parts in the projection of the substrate; the conductive parts are electrically connected to the third parts; the first shielding parts cover the first vias in the projection of the substrate. The width of the first shielding part in the direction perpendicular to the extension direction of the first metal lines is greater than the width of the first via in the direction perpendicular to the extension direction of the first metal lines.
2. The array substrate of claim 1, wherein, The width of the first shielding part in the direction perpendicular to the extension direction of the first metal lines is greater than the width of the second part in the direction perpendicular to the extension direction of the first metal lines.
3. The array substrate of claim 2, wherein, The first metal line at the position of the first via comprises a first metal part, a second metal part, and a third metal part; the first metal part covers the bottom of the first via; the second metal part is located on the side of the first metal part in the direction perpendicular to the extension direction of the first metal line and extends along the sidewall of the first via; and the third metal part is located on the other side of the first metal part in the direction perpendicular to the extension direction of the first metal line and extends along the sidewall of the first via.
4. The array substrate of claim 2 or 3, wherein, In the direction from the substrate to the first conductive layer, the thickness of at least one of the second metal part and the third metal part in the direction perpendicular to the extension direction of the first metal line gradually decreases.
5. The array substrate of claim 4, wherein, The maximum thickness of the second metal part in the direction perpendicular to the substrate is the same as the maximum thickness of the third metal part in the direction perpendicular to the substrate; and the maximum length of the second metal part in the direction perpendicular to the extension direction of the first metal line is equal to the maximum length of the third metal part in the direction perpendicular to the extension direction of the first metal line.
6. The array substrate of claim 4 or 5, wherein, The second metal part only covers the sidewall on one side of the first via; and the third metal part only covers the sidewall on the other side of the first via.
7. The array substrate of claim 6, wherein, The second metal part covers all the sidewalls of the first via on one side of the first metal line and covers part of the surface of the first insulating layer away from the substrate; and the third metal part covers all the sidewalls of the first via on the other side of the first metal line and covers part of the surface of the first insulating layer away from the substrate.
8. The array substrate of claim 6, wherein, 9. The array substrate of claim 4 or 5, wherein, The maximum thickness of the second metal portion in a direction perpendicular to the substrate is less than the maximum thickness of the third metal portion in a direction perpendicular to the substrate; and the maximum length of the second metal portion in a direction perpendicular to the extending direction of the first metal line is less than the maximum length of the third metal portion in a direction perpendicular to the extending direction of the first metal line.
10. The array substrate of claim 9, wherein, The first via includes a first sidewall and a second sidewall, wherein the first sidewall and the second sidewall are respectively located on two sides of the first metal portion. The second metal portion covers a portion of the first sidewall, and the third metal portion covers a portion of the second sidewall.
11. The array substrate of claim 9, wherein, The first via includes a first sidewall and a second sidewall, wherein the first sidewall and the second sidewall are respectively located on two sides of the first metal portion in a direction perpendicular to the extending direction of the first metal line. The second metal portion covers a portion of the first sidewall, and the third metal portion covers a portion of the second sidewall.
12. The array substrate of any of claims 4-11, wherein, The first conductive layer and the first metal layer have a second insulating layer therebetween; the second insulating layer includes a first insulating portion and a second insulating portion located at the periphery of the first insulating portion; the orthographic projection of the first insulating portion on the substrate overlaps the orthographic projection of the first via on the substrate.
13. The array substrate of claim 12, wherein, The first insulating portion and the second insulating portion are in an integral connection structure.
14. The array substrate of claim 12, wherein, At least one side of the second insulating portion in a direction perpendicular to the extending direction of the first metal line has a first gap with the first insulating portion.
15. The array substrate of claim 14, wherein, The orthographic projection of the first gap and the second metal portion on the substrate is located on the same side of the orthographic projection of the first metal portion on the substrate.
16. The array substrate of claim 14 or 15, wherein, At the position of the first via, the first gap extends from the surface of the second insulating layer away from the substrate to the bottom of the first via.
17. The array substrate of claim 14 or 15, wherein, At the position of the first via, the first gap extends from the surface of the second insulating layer away from the substrate to the first metal line.
18. The array substrate of any one of claims 14-17, wherein, The first shielding portion covers the first insulating portion, covers a portion of the second insulating portion at the periphery of the first insulating portion, and fills at least a portion of the first gap.
19. The array substrate of any one of claims 12-18, wherein, The first insulating portion has a first recessed portion recessed toward the substrate at a position corresponding to the first metal portion, and has a first protruding portion protruding away from the substrate at positions corresponding to the second metal portion and the third metal portion.
20. The array substrate of claim 19, wherein, The distance between the first protruding portion and the substrate is greater than the distance between the second insulating portion and the substrate.
21. The array substrate of claim 19 or 20, wherein, The first shielding portion has a second recessed portion at a position corresponding to the first recessed portion, and has a second protruding portion at a position corresponding to the first protruding portion.
22. The array substrate of any of claims 1-7, 8-21, wherein, The line width of the first metal line is less than the width of the first via in a direction perpendicular to the extending direction of the first metal line.
23. The array substrate of any of claims 1-22, wherein, The minimum distance between the outer edge of the first shielding portion and the outer edge of the first via in the first direction in the orthographic projection of the substrate is greater than 0.52 μm.
24. The array substrate of any one of claims 1-23, wherein, The array substrate further comprises a second conductive layer on the side of the first conductive layer away from the first metal layer; the second conductive layer comprises a plurality of first electrodes in the pixel region; The first electrode is electrically connected to the third portion through the conductive portion.
25. The array substrate of any one of claims 1-24, wherein, The array substrate further comprises a second metal layer between the first active layer and the first metal layer, and a third metal layer on the side of the first active layer facing the substrate; The second metal layer comprises a plurality of second metal lines extending in a first direction; the third metal layer comprises a plurality of shielding patterns; the shielding patterns in the orthographic projection of the substrate cover the first via in the orthographic projection of the substrate.
26. The array substrate of claim 25, wherein, The shielding patterns in the orthographic projection of the substrate cover the first shielding portion in the orthographic projection of the substrate.
27. The array substrate of any of claims 1-26, wherein, The first metal lines extend in a second direction; The first portion comprises a first sub-portion extending in the second direction, and a second sub-portion connected to the first sub-portion and extending in a third direction; the second portion is connected to one end of the second sub-portion away from the first sub-portion, and the third portion is connected to one end of the first sub-portion away from the second sub-portion. The first metal lines comprise first sub-metal portions and second sub-metal portions arranged alternately in the second direction; the first sub-metal portions and the second sub-metal portions extend in different directions; 28. The array substrate of any of claims 1-27, wherein, The second sub-metal portions in the orthographic projection of the substrate overlap the first via in the orthographic projection of the substrate; the first portion extends in the same direction as the first sub-metal portions. The array substrate further comprises a third signal line and a fourth signal line in the peripheral region; the third signal line is in the same layer as the first metal lines; the fourth signal line has a third insulating layer between the third signal line; the third insulating layer has a plurality of second vias; 29. The array substrate of any of claims 1-28, wherein, The third signal line is electrically connected through the second vias; The first conductive layer further comprises a plurality of second shielding portions; The second shielding portions in the orthographic projection of the substrate cover the second vias in the orthographic projection of the substrate. The array substrate further comprises a second active layer on the side of the first active layer facing the substrate, a driving source electrode on the side of the second active layer away from the substrate, a driving drain electrode, and a driving gate electrode; 30. The array substrate of any of claims 1-29, wherein, The material of the first active layer comprises metal oxide; the material of the second active layer comprises low-temperature polysilicon. The array substrate as claimed in any one of claims 1-30, further comprising a counter substrate arranged opposite to the array substrate.
31. A display panel, wherein, The display panel as claimed in claim 31.
32. A display device comprising: