Display panel and display device

Abstract

The present application discloses a display panel and a display device. A first active layer comprises switch active portions and drive active portions arranged in pixel regions; each data line comprises a first line segment and a second line segment connected to the first line segment and bent towards the drive active portion in a protruding manner; a first end of a corresponding switch active portion is close to the first line segment, and a second end of the switch active portion extends toward the second line segment; and a first electrode is connected between the second line segment and the second end of the switch active portion.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] An active-matrix organic light emitting diode (AMOLED) display panel has advantages of wide color gamut range and low energy consumption, and has been applied more and more widely in recent years.

[0003] The AMOLED display panel includes an array substrate, and a plurality of thin film transistors arranged in an array are arranged on the array substrate. The source-drain electrode of the thin film transistor is connected with a semiconductor layer, and the signal transmission from the source electrode to the drain electrode is realized through the conduction of the channel of the semiconductor layer.

[0004] At present, the source-drain electrode is connected with the semiconductor layer through a via hole, and the distribution of the via hole between the source-drain electrode and the semiconductor layer greatly affects the electrical property of the thin film transistor. For example, when the distribution of the via hole between the source-drain electrode and the semiconductor layer is uneven, the dehydrogenation effect of the insulating layer in the array substrate is poor, and then the threshold voltage of the thin film transistor is offset, resulting in bright spots or dark spots in the display panel. SUMMARY

[0005] The display panel and the display device provided by the embodiments of the present application can improve the distribution uniformity of the contact hole between the switching active part and the first electrode, and then improve the dehydrogenation effect of the film layer in the display panel, improve the electrical stability of the thin film transistor in the pixel area driving circuit, and improve the display uniformity of the display panel.

[0006] The display panel provided by the embodiments of the present application includes a plurality of pixel areas and a pixel driving circuit arranged in each pixel area; the pixel driving circuit includes a switching transistor and a driving transistor connected with each other, the switching transistor includes a switching active part, and the driving transistor includes a driving active part.

[0007] The display panel further includes:

[0008] A first active layer includes the switching active part and the driving active part arranged in the pixel area;

[0009] A first conductive layer is arranged on one side of the first active layer and includes a first electrode and a second electrode;

[0010] A second conductive layer is arranged on the side of the first conductive layer away from the first active layer and includes a data line extending along the length direction of the first side edge of the pixel area.

[0011] The data line comprises a first segment arranged close to the first side edge and a second segment connected to the first segment and bending out towards the direction close to the driving active part, the first end of the switch active part is arranged close to the first segment and connected to the second electrode, the second end of the switch active part extends towards the direction close to the second segment, and the first electrode is connected between the second segment and the second end of the switch active part.

[0012] According to the above purpose of the present application, the embodiment of the present application further provides a display device, which comprises a display panel, the display panel comprises a plurality of pixel areas and pixel driving circuits arranged in each of the pixel areas; the pixel driving circuit comprises a switch transistor and a driving transistor connected to each other, the switch transistor comprises a switch active part, and the driving transistor comprises a driving active part;

[0013] The display panel further comprises:

[0014] a first active layer comprising the switch active part and the driving active part arranged in the pixel area;

[0015] a first conductive layer arranged on one side of the first active layer and comprising a first electrode and a second electrode;

[0016] a second conductive layer arranged on the side of the first conductive layer away from the first active layer and comprising a data line extending along the length direction of the first side edge of the pixel area;

[0017] The data line comprises a first segment arranged close to the first side edge and a second segment connected to the first segment and bending out towards the direction close to the driving active part, the first end of the switch active part is arranged close to the first segment and connected to the second electrode, the second end of the switch active part extends towards the direction close to the second segment, and the first electrode is connected between the second segment and the second end of the switch active part. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a schematic structural diagram of a semiconductor layer provided in an embodiment;

[0019] FIG. 2 is a schematic structural diagram of a first active layer provided in an embodiment of the present application;

[0020] FIG. 3 is a schematic structural diagram of a first conductive layer provided in an embodiment of the present application;

[0021] FIG. 4 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0022] FIG. 5 is a schematic view of a planar distribution structure of a pixel driving circuit according to an embodiment of the present application;

[0023] FIG. 6 is a schematic view of a structure of a display panel according to an embodiment of the present application;

[0024] FIG. 7 is a schematic view of another planar distribution structure of a pixel driving circuit according to an embodiment of the present application;

[0025] FIG. 8 is a schematic view of a structure of a light shielding layer according to an embodiment of the present application;

[0026] FIG. 9 is a schematic view of a structure of a first gate layer according to an embodiment of the present application;

[0027] FIG. 10 is a schematic view of a structure of a second gate layer according to an embodiment of the present application;

[0028] FIG. 11 is a schematic view of a structure of a second active layer according to an embodiment of the present application;

[0029] FIG. 12 is a schematic view of a structure of a third gate layer according to an embodiment of the present application;

[0030] FIG. 13 is a schematic view of a structure of a second conductive layer according to an embodiment of the present application;

[0031] FIG. 14 is a schematic view of a structure of a display device according to an embodiment of the present application. Embodiments of the present application

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0033] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the components and arrangements of the specific examples are described in the following. Of course, they are only examples and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to the numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, and it does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides various specific examples of processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0034] Please refer to FIG. 1, the display panel includes a plurality of pixel driving circuits 1, and a plurality of thin film transistors are distributed in the pixel driving circuit 1, wherein the active layers of at least part of the thin film transistors are located in the same layer, that is, in a semiconductor layer 2; the pixel driving circuit 1 includes a switching transistor, the switching transistor includes a switching active part 3, and the switching active part 3 is arranged in a vertical straight line; further, the switching active part 3 needs to be connected with a source or a drain in a different layer, and then a contact hole 4 needs to be opened above the switching active part 3, so that the source or the drain can be connected with the switching active part 3 through the contact hole 4; in the process of the display panel, after the contact hole 4 is opened, the display panel also needs to be subjected to a high-temperature process, so as to perform dehydrogenation treatment on the film layers such as the insulating layer in the display panel, reduce the hydrogen content in the film layers in the display panel, and reduce the probability of threshold voltage shift of the thin film transistor due to hydrogen diffusion; however, since the two adjacent pixel driving circuits 1 are arranged in axial symmetry, and then the two switching active parts 3 in the two adjacent pixel driving circuits 1 are adjacent and close to each other; resulting in uneven distribution of the contact holes 4, some positions have high density, and some positions have low density, thereby affecting the dehydrogenation effect of the display panel in the high-temperature process, which is not conducive to the reduction of the hydrogen content in the film layers of the display panel, and the electrical stability of the thin film transistor is affected, and then the threshold voltage of the thin film transistor is easily shifted, resulting in bright spots or dark spots in the display panel.

[0035] Please refer to FIG. 2, FIG. 3, FIG. 4 and FIG. 5, the embodiment of the present application provides a display panel, the display panel includes a plurality of pixel regions 100 and pixel driving circuits 1000 arranged in each pixel region 100; the pixel driving circuit 1000 includes a switching transistor T02 and a driving transistor T01, the switching transistor T02 includes a switching active part 11, and the driving transistor T01 includes a driving active part 12.

[0036] The display panel further includes a first active layer 10, a first conductive layer 20 and a second conductive layer 80; the first active layer 10 includes the switching active part 11 and the driving active part 12 arranged in the pixel region 100; the first conductive layer 20 is arranged on one side of the first active layer 10 and includes a first electrode 201 and a second electrode 202; the second conductive layer 80 is arranged on the side of the first conductive layer 20 away from the first active layer 10 and includes a data line 81 extending along the length direction of the first side edge 101 of the pixel region 100.

[0037] The data line 82 includes a first line segment 811 arranged close to the first side 101 and a second line segment 812 connected to the first line segment 811 and protruding and bending towards the direction close to the driving active part 12. The first end of the switching active part 11 is arranged close to the first line segment 811 and connected to the first electrode 201. The second end of the switching active part 11 extends towards the direction close to the second line segment 812. The first electrode 201 is connected between the second line segment 812 and the second end of the switching active part 11.

[0038] In the application process, the second end of the switching active part 11 is arranged close to the pixel area 100, which can improve the uniformity of the contact hole between the first electrode 201 and the switching active part 11, and is beneficial to improve the dehydrogenation effect of the film layer in the display panel, reduce the hydrogen content of the film layer in the display panel, improve the electrical stability of the thin film transistor in the pixel driving circuit 1000, and improve the display uniformity of the display panel.

[0039] In an embodiment of the present application, the switching active part includes a first switching connection part, a second switching connection part, and a switching channel part connected between the first switching connection part and the second switching connection part. One end of the second switching connection part is arranged close to the first line segment. The other end of the second switching connection part extends towards the direction close to the second line segment and is connected to the switching channel part. The first switching connection part is connected to one end of the switching channel part away from the second switching connection part.

[0040] The first electrode is connected between the first switching connection part and the second line segment.

[0041] In an embodiment of the present application, the driving transistor includes a driving active part. The driving active part includes a first driving connection part, a second driving connection part, and a driving channel part connected between the first driving connection part and the second driving connection part.

[0042] The first driving connection part is connected to the second switching connection part close to the first line segment. The driving channel part is located on the side of the first driving connection part away from the first side. The first switching connection part and the driving channel part are arranged at least partially overlapped in the first direction. The first direction is the length direction of the first side.

[0043] In an embodiment of the present application, the driving channel part includes a first sub-part, and a second sub-part and a third sub-part connected to the opposite ends of the first sub-part. The second sub-part and the third sub-part are both located on the same side of the first sub-part in the first direction. The second sub-part is connected to the first driving connection part.

[0044] The first switch connection portion is at least partially overlapped with the first sub-portion and / or the second sub-portion along the first direction.

[0045] In an embodiment of the present application, the pixel driving circuit further comprises a first light emitting control transistor, the switch transistor, the driving transistor and the first light emitting control transistor are connected to a first node, the first light emitting control transistor comprises a first light emitting control active portion.

[0046] The first active layer comprises the first light emitting control active portion, the first light emitting control active portion is arranged close to the first line segment and connected to the second switch connection portion and the first driving connection portion, and the first switch connection portion is located on a side of the first light emitting control active portion close to the driving active portion.

[0047] In an embodiment of the present application, the first line segment and the second line segment are arranged staggered or partially overlapped along the first direction, the distance between the second line segment and the first switch connection portion along a second direction is smaller than the distance between the first line segment and the first switch connection portion along the second direction, and the second direction is perpendicular to the first direction.

[0048] In an embodiment of the present application, a plurality of pixel driving circuits in a plurality of pixel regions are arranged in an array along the first direction and the second direction, and two adjacent pixel driving circuits along the second direction are arranged in axial symmetry.

[0049] In an embodiment of the present application, the switch channel portion is connected to the first switch connection portion and extends along the first direction, and at least part of the second switch connection portion extends to the first side along the second direction.

[0050] In an embodiment of the present application, the pixel driving circuit further comprises a light emitting device, a compensation transistor, a first reset transistor, a second light emitting control transistor, a second reset transistor, a third reset transistor, a first capacitor and a second capacitor.

[0051] The drain of the switch transistor, the source of the drive transistor, the drain of the first light-emitting control transistor, and the drain of the third reset transistor are connected to the first node, the source of the second light-emitting control transistor, the drain of the drive transistor, and the source of the compensation transistor are connected to the second node, the gate of the drive transistor, the drain of the first reset transistor, and the drain of the compensation transistor are connected to the third node, the drain of the second reset transistor, the drain of the second light-emitting control transistor, and the light-emitting device are connected to the fourth node, the first capacitor is connected between the third node and the source of the first light-emitting control transistor, and the second capacitor is connected between the third node and the gate of the switch transistor.

[0052] In an embodiment of the present application, the display panel further comprises a second active layer disposed between the first active layer and the second conductive layer, the material of the first active layer comprises polysilicon, and the material of the second active layer comprises metal oxide.

[0053] The first active layer further comprises an active part of the second light-emitting control transistor, an active part of the reset transistor, and an active part of the second reset transistor.

[0054] The second active layer comprises an active part of the compensation transistor and an active part of the first reset transistor.

[0055] In an embodiment of the present application, the pixel region further comprises a second side edge disposed opposite to the first side edge, and the minimum distance between the first switch connection part and the second side edge is greater than the minimum distance between the second switch connection part and the first side edge.

[0056] Further, please continue to combine FIG. 1, FIG. 2, and FIG. 3, the display panel provided in the embodiments of the present application comprises a plurality of pixel regions 100, and the plurality of pixel regions 100 are arranged in an array along a first direction X1 and a second direction X2, and the first direction X1 and the second direction X2 intersect, further, the first direction X1 and the second direction X2 can be perpendicular.

[0057] In an embodiment, each pixel region 100 is provided with a pixel driving circuit 1000 as shown in FIG. 4, the pixel driving circuit 1000 comprises a light-emitting device, a drive transistor T01, a switch transistor T02, a compensation transistor T03, a first reset transistor T04, a first light-emitting control transistor T05, a second light-emitting control transistor T06, a second reset transistor T07, a third reset transistor T08, a first capacitor Cst, and a second capacitor Cboost.

[0058] The drain of the drive transistor T01 is connected to the second node B, the gate of the drive transistor T01 is connected to the second node Q, and the source of the drive transistor T01 is connected to the first node A.

[0059] The source of the first switch transistor T02 is connected to the data signal Data, the gate of the first switch transistor T02 is connected to the first scan signal Pscan, and the drain of the first switch transistor T02 is connected to the first node A.

[0060] The first pole of the compensation transistor T03 is connected to the second node B, the gate of the compensation transistor T03 is connected to the second scan signal NscanT3, and the drain of the compensation transistor T03 is connected to the third node Q.

[0061] The source of the first reset transistor T04 is connected to the first reset signal Vi_G, the gate of the first reset transistor T04 is connected to the third scan signal NscanT4, and the drain of the first reset transistor T04 is connected to the third node Q.

[0062] The source of the first emission control transistor T05 is connected to the first power signal VDD, the gate of the first emission control transistor T05 is connected to the emission control signal EM, and the drain of the first emission control transistor T05 is connected to the first node A.

[0063] The source of the second emission control transistor T06 is connected to the second node B, the gate of the second emission control transistor T06 is connected to the emission control signal EM, and the drain of the second emission control transistor T06 is connected to the fourth node C.

[0064] The source of the second reset transistor T07 is connected to the second reset signal Vi_ANo, the gate of the second reset transistor T07 is connected to the fourth scan signal Pscan2, and the drain of the second reset transistor T07 is connected to the fourth node C.

[0065] The source of the third reset transistor T08 is connected to the third reset signal Vi, the gate of the third reset transistor T08 is connected to the fourth scan signal Pscan2, and the drain of the reset transistor T08 is connected to the first node A.

[0066] The first pole of the light emitting device is connected to the fourth node C, and the second pole of the light emitting device is connected to the second power signal VSS.

[0067] The first capacitor Cst is connected between the third node Q and the first node A, and the second capacitor Cboost is connected between the third node Q and the first scan signal Pscan.

[0068] Further, referring to FIG. 6, the display panel provided by the embodiment of the present application includes a substrate 90 and a thin film transistor array layer disposed on the substrate 90, and the thin film transistor devices in the pixel driving circuit 1000 described in the above embodiment are all disposed in the thin film transistor array layer.

[0069] In one embodiment, the display panel includes, in sequence, a barrier layer 91, a buffer layer 92, a first gate insulating layer 93, a second gate insulating layer 94, a first interlayer dielectric layer 95, a third gate insulating layer 96, a second interlayer dielectric layer 97, a first planarization layer 98, and a second planarization layer 99 disposed on the substrate 90, and the thin film transistor devices in the pixel driving circuit 1000 described in the above embodiment can all be covered by the insulating film layers.

[0070] The display panel includes, in sequence, a first active layer 10 disposed on the buffer layer 92 and covered by the first gate insulating layer 93, a first gate layer 40 disposed on the first gate insulating layer 93 and covered by the second gate insulating layer 94, a second gate layer 50 disposed on the second gate insulating layer 94 and covered by the first interlayer dielectric layer 95, a second active layer 60 disposed on the first interlayer dielectric layer 95 and covered by the third gate insulating layer 96, a third gate layer 70 disposed on the third gate insulating layer 96 and covered by the second interlayer dielectric layer 97, a first conductive layer 20 disposed on the second interlayer dielectric layer 97 and covered by the first planarization layer 98, and a second conductive layer 80 disposed on the first planarization layer 98 and covered by the second planarization layer 99.

[0071] In an embodiment, as shown in FIG. 6, the first type of transistor T1 and the second type of transistor T2 are taken as examples for illustration; the display panel includes the light shielding layer 30 disposed in the barrier layer 91, and the light shielding layer 30 can be located below the first type of transistor T1 to shield light for the first type of transistor T1, thereby improving the electrical stability of the first type of transistor T1. The material of the first active layer 10 includes a polysilicon material, such as a Poly Si material, and the material of the second active layer 60 includes a metal oxide material, such as an IGZO material, that is, the first type of transistor T1 can be a transistor in the pixel driving circuit 1000 that uses a polysilicon material to prepare the active layer, and the first type of transistor T1 can include the switching transistor T02, the driving transistor T01, the first light emitting control transistor T05, the second light emitting control transistor T06, the second reset transistor T07, and the reset transistor T08. The second type of transistor T2 can be a transistor in the pixel driving circuit 1000 that uses a metal oxide material to prepare the active layer, and the second type of transistor T2 can include the compensation transistor T03 and the first reset transistor T04. Therefore, the active layers of the switching transistor T02, the driving transistor T01, the first light emitting control transistor T05, the second light emitting control transistor T06, the second reset transistor T07, and the reset transistor T08 can be located in the same layer, that is, in the first active layer 10, and the active layers of the compensation transistor T03 and the first reset transistor T04 can be located in the same layer, that is, in the second active layer 60.

[0072] Further, the device film layers of each thin film transistor in the pixel driving circuit 1000 provided by the embodiments of the present application will be specifically described with reference to FIGS. 2 to 13.

[0073] As shown in FIG. 8, the light shielding layer 30 in the display panel includes the light shielding portion 31, and the light shielding portion 31 can be located below the active portion of the driving transistor T01.

[0074] As shown in FIG. 2, the first active layer 10 in the display panel includes the switching active portion 11, the driving active portion 12, the first light emitting control active portion 13, the second light emitting control active portion 14, the second reset active portion 15, and the third reset active portion 16, and at least the driving active portion 12 is located above the light shielding portion 31.

[0075] It can be understood that the switching active portion 11 is the active portion of the switching transistor T02, the driving active portion 12 is the active portion of the driving transistor T01, the first light emitting control active portion 13 is the active portion of the first light emitting control transistor T05, the second light emitting control active portion 14 is the active portion of the second light emitting control transistor T06, the second reset active portion 15 is the active portion of the second reset transistor T07, and the third reset active portion 16 is the active portion of the third reset transistor T08.

[0076] In the embodiment of the present application, the pixel region 100 includes a first side edge 101 and a second side edge 102 arranged oppositely, the switch active part 11 includes a first switch connecting part 111, a second switch connecting part 112, and a switch channel part 113 connected between the first switch connecting part 111 and the second switch connecting part 112; one end of the second switch connecting part 112 is arranged close to the first side edge 101, the other end of the second switch connecting part 112 extends along the first side edge 101 in a direction close to the center of the pixel region 100 and is connected to the switch channel part 113, the first switch connecting part 111 is connected to one end of the switch channel part 113 away from the second switch connecting part 112, and the source or drain of the switch transistor T02 is connected to the first switch connecting part 111 through a via hole.

[0077] Therefore, in the embodiment of the present application, the first switch connecting part 111 of the switch active part 11 is arranged close to the center of the pixel region 100, and compared with the structure shown in FIG. 1, the distance between the via holes above the first switch connecting part 111 in two adjacent pixel regions 100 can be increased, that is, the distribution uniformity of the via holes above the first switch connecting part 111 is improved, which is more conducive to improving the dehydrogenation effect of the film layer in the display panel, reducing the hydrogen content of the film layer in the display panel, improving the electrical stability of the thin film transistor in the pixel driving circuit 1000, and improving the display uniformity of the display panel.

[0078] In an embodiment, two adjacent pixel driving circuits 1000 along the second direction X2 are arranged in axial symmetry.

[0079] In an embodiment, the first side edge 101 is parallel to the first direction X1.

[0080] In an embodiment, the switch channel part 113 is connected to the first switch connecting part 111 and extends along the first direction X1, and part of the second switch connecting part 112 extends along the second direction X2 and extends to the first side edge 101.

[0081] The driving active part 12 includes a first driving connecting part 121, a second driving connecting part 122, and a driving channel part 123 connected between the first driving connecting part 121 and the second driving connecting part 122, the first driving connecting part 121 is connected to the second switch connecting part 112 extending to the first side edge 101, the driving channel part 123 is located on the side of the first driving connecting part 121 away from the first side edge 101, and the second driving connecting part 122 is located on the side of the driving channel part 123 away from the first driving connecting part 121.

[0082] In an embodiment, the driving channel portion 123 is located in the middle region of the pixel region 100, and the first switch connecting portion 111 is at least partially overlapped with the driving channel portion 123 along the first direction X1, and the first switch connecting portion 111 is also located in the middle region of the pixel region 100 in the embodiment, so as to further improve the uniformity of the distribution of the via above the first switch connecting portion 111.

[0083] In an embodiment, the driving channel portion 123 includes a first sub-portion 1231, and a second sub-portion 1232 and a third sub-portion 1233 connected to opposite ends of the first sub-portion 1231, and the second sub-portion 1232 and the third sub-portion 1233 are both located on the same side of the first sub-portion 1231 along the first direction X1, wherein the second sub-portion 1232 is connected to the first driving connecting portion 121, and the third sub-portion 1233 is connected to the second driving connecting portion 122, and the driving channel portion 123 is arranged in a "U" shape.

[0084] Further, the first switch connecting portion 111 is at least partially overlapped with the first sub-portion 1231 and / or the second sub-portion 1232 along the first direction X1, so as to avoid the length of the second switch connecting portion 112 in the switch active portion 11 along the second direction X2 being too long to cause the impedance to be too large.

[0085] In an embodiment, the minimum distance between the first switch connecting portion 111 and the second side edge 102 is greater than the minimum distance between the second switch connecting portion 112 and the first side edge 101, so as to avoid the first switch connecting portion 111 extending to the second side edge 102, which causes the uniformity of the distribution of the via above the first switch connecting portion 111 to be unable to be improved.

[0086] In addition, one end of the first light-emitting control active portion 13 is connected to the second switch connecting portion 112 and the first driving connecting portion 121, and the other end of the first light-emitting control active portion 13 is connected to the first light-emitting control active portion 13 in the adjacent and axisymmetric other pixel driving circuit 1000; further, the first light-emitting active portion 13 is located close to the first side edge 101, and the first switch connecting portion 111 is located on the side of the first light-emitting control active portion 13 close to the center of the pixel region 100.

[0087] One end of the second light-emitting control active portion 14 is connected to the second driving connecting portion 122, and the other end of the second light-emitting control active portion 14 is connected to the second reset active portion 15, and the third reset active portion 16 is located between the second reset active portion 15 and the first side edge 101.

[0088] Please refer to FIG. 2, FIG. 4 and FIG. 9, FIG. 9 shows the first gate layer 40 in the display panel, the first gate layer 40 includes the first reset signal line 41, the first scan signal line 42, the driving gate 43 of the driving transistor T01, the light emitting control signal line 44 and the fourth scan signal line 45.

[0089] The first reset signal line 41 is used for transmitting the first reset signal Vi_G, and the first reset signal line 41 is connected with the first reset transistor T04.

[0090] The first scan signal line 42 is used for transmitting the first scan signal Pscan, and is multiplexed as the switch gate of the switch transistor T02, the position of the first scan signal line 42 overlapping with the switch channel 113 is the switch gate.

[0091] The light emitting control signal line 44 is used for transmitting the light emitting control signal EM, and the light emitting control signal line 44 is respectively overlapped with the first light emitting control active part 13 and the second light emitting control active part 14, the part of the first light emitting control active part 13 overlapping with the light emitting control signal line 44 is the channel of the first light emitting control active part 13, and the part of the second light emitting control active part 14 overlapping with the light emitting control signal line 44 is the channel of the second light emitting control active part 14.

[0092] The fourth scan signal line 45 is used for transmitting the fourth scan signal Pscan2, and the fourth scan signal line 45 is respectively overlapped with the second reset active part 15 and the third reset active part 16, the part of the second reset active part 15 overlapping with the fourth scan signal line 45 is the channel of the second reset active part 15, and the part of the third reset active part 16 overlapping with the fourth scan signal line 45 is the channel of the third reset active part 16.

[0093] Please refer to FIG. 2, FIG. 4 and FIG. 10, FIG. 10 shows the second gate layer 50 in the display panel, the second gate layer 50 includes the third scan signal line 51, the second scan signal line 52 and the first electrode plate 54.

[0094] The third scan signal line 51 is used for transmitting the third scan signal NscanT4, and the third scan signal line 51 is also multiplexed as the gate of the first reset transistor T04; the second scan signal line 52 is used for transmitting the second scan signal NscanT3, and the second scan signal line 52 is also multiplexed as the gate of the compensation transistor T03; the first electrode plate 54 can be used for constituting the storage capacitor Cst.

[0095] Please refer to FIG. 2, FIG. 4, FIG. 10 and FIG. 11, FIG. 11 is a second active layer 60 in the display panel, the second active layer 60 includes a first reset active part 61, a compensation active part 62 and a second electrode plate 63, the first reset active part 61 is an active part of a first reset transistor T04, and the compensation active part 62 is an active part of a compensation transistor T03.

[0096] The first reset active part 61 is arranged in overlap with the third scan signal line 51, and the part of the first reset active part 61 overlapping with the third scan signal line 51 is a channel of the first reset active part 61; the compensation active part 62 is arranged in overlap with the second scan signal line 52, and the part of the compensation active part 62 overlapping with the second scan signal line 52 is a channel of the compensation active part 62; and the second electrode plate 63 overlaps with the first scan signal line 42 to form a second capacitor Cboost.

[0097] Please refer to FIG. 2, FIG. 4 and FIG. 12, FIG. 12 is a third gate layer 70 in the display panel, the third gate layer 70 includes a first top gate line 71, a second top gate line 72 and a third reset signal line 73.

[0098] The first top gate line 71 is used for transmitting a third scan signal NscanT4, and the first top gate line 71 is arranged in overlap with the first reset active part 61, and the first top gate line 71 is also multiplexed as a top gate of the first reset transistor T04, so that the first reset transistor T04 is a double-gate thin film transistor having two gates formed by the third scan signal line 51 and the first top gate line 71.

[0099] The second top gate line 72 is used for transmitting a second scan signal NscanT3, and the second top gate line 72 is arranged in overlap with the compensation active part 62, and the second top gate line 72 is also multiplexed as a top gate of the compensation transistor T03, so that the compensation transistor T03 is a double-gate thin film transistor having two gates formed by the second scan signal line 52 and the second top gate line 72.

[0100] The third reset signal line 73 is used for transmitting a third reset signal Vi and is connected with the third reset transistor T08.

[0101] Please refer to FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 7, FIG. 9, FIG. 10 and FIG. 11, FIG. 3 is a first conductive layer 20 in the display panel, the first conductive layer 20 includes a first electrode 201, a second electrode 202, a third electrode 203, a fourth electrode 204, a fifth electrode 205, a sixth electrode 206, a seventh electrode 207, an eighth electrode 208, a ninth electrode 209, a tenth electrode 210, an eleventh electrode 211 and a second reset signal line 21.

[0102] The first electrode 201 is connected with the first switch connection part 111 through a first connection node 901, and the first electrode 201 can be used as a source electrode of the switch transistor T02.

[0103] The second electrode 202 is connected with the second switch connection part 112, the first drive connection part 121 and the first light emitting control active part 13 through a first node A, and the second electrode 202 can be used as a drain electrode of the switch transistor T02, a source electrode of the drive transistor T01 and a drain electrode of the first light emitting control transistor T05, i.e. the drain electrode of the switch transistor T02, the source electrode of the drive transistor T01 and the drain electrode of the first light emitting control transistor T05 jointly constitute the second electrode 202.

[0104] The third electrode 203 is connected with the third reset active part 16 through a second connection node 902, and the third electrode 203 can be used as a drain electrode of the reset transistor T08. The second electrode 202 is connected with the third electrode 203 to realize that the drain electrode of the switch transistor T02, the drain electrode of the first light emitting control transistor T05 and the source electrode of the drive transistor T01 are all connected with the drain electrode of the reset transistor T08.

[0105] The fourth electrode 204 is connected with the third reset active part 16 through a third connection node 903, and the fourth electrode 204 can be used as a source electrode of the third reset transistor T08. The fourth electrode 204 is also connected with the third reset signal line 73 through a fourth connection node 904 to input the third reset signal Vi to the source electrode of the reset transistor T08.

[0106] The fifth electrode 205 is connected with the first reset active part 61 through a fifth connection node 905, and the fifth electrode 205 is connected with the first reset signal line 41 through a sixth connection node 906. The fifth electrode 205 can be used as a source electrode of the first reset transistor T04 to input the first reset signal Vi_G to the source electrode of the first reset transistor T04.

[0107] The sixth electrode 206 is connected with the first reset active part 61 through a seventh connection node 907, and the sixth electrode 206 can be used as a drain electrode of the first reset transistor T04. In addition, the sixth electrode 206 is also connected with the compensation active part 62 through the seventh connection node 907, and the sixth electrode 206 can also be used as a drain electrode of the compensation transistor T03, i.e. the drain electrode of the first reset transistor T04 and the drain electrode of the compensation transistor T03 jointly constitute the sixth electrode 206.

[0108] The seventh electrode 207 is connected with the driving gate 43 through the third node Q, and the seventh electrode 207 is connected with the driving gate 43 through the via hole 53 on the first electrode plate 54, and the seventh electrode 207 is connected with the sixth electrode 206, so as to realize that the driving gate 43 of the driving transistor T01 is connected with the drain of the first reset transistor T04 and the drain of the compensation transistor T03.

[0109] The eighth electrode 208 is connected with the compensation active part 62 through the eighth connection node 908, and the eighth electrode 208 can be used as the source of the compensation transistor T03.

[0110] The ninth electrode 209 is connected with the second driving connection part 122 through the second node B, and the ninth electrode 209 can be used as the drain of the driving transistor T01, further, the ninth electrode 209 is connected with the eighth electrode 208, so as to realize that the drain of the driving transistor T01 is connected with the source of the compensation transistor T03; further, the ninth electrode 209 is also connected with the second light-emitting control active part 14 through the second node B, and the ninth electrode 209 can also be used as the source of the second light-emitting control active part 14, that is, the drain of the driving transistor T01 and the source of the second light-emitting control active part 14 jointly constitute the ninth electrode 209.

[0111] The tenth electrode 210 is connected with the second light-emitting control active part 14 and the second reset active part 15 through the third node C, and the tenth electrode 210 can be used as the drain of the second light-emitting control transistor T06 and the drain of the second reset transistor T07, that is, the drain of the second light-emitting control transistor T06 and the drain of the second reset transistor T07 jointly constitute the tenth electrode 210.

[0112] The eleventh electrode 211 is connected with the second reset active part 15 through the ninth connection node 909, and the eleventh electrode 211 can be used as the source of the second reset transistor T07.

[0113] The second reset signal line 21 is used for transmitting the second reset signal Vi_ANo, and the second reset signal line 21 is used for being connected with the eleventh electrode 211, so as to input the second reset signal Vi_ANo to the source of the second reset transistor T07.

[0114] Please combine FIG. 2, FIG. 3, FIG. 4 and FIG. 13, FIG. 13 is a second conductive layer 80 in the display panel, the second conductive layer 80 includes a data line 81, an auxiliary reset signal line 82, a third electrode plate 83 and a switching electrode 84.

[0115] The data line 81 extends along the first direction X1 and is arranged along the second direction X2, and the data line 81 is also connected with the first electrode 201 through the first connection node 901, so as to realize that the data line 81 inputs the data signal to the source of the switching transistor T02.

[0116] In an embodiment, the data line 81 is arranged close to the first side edge 101 of the pixel area 100, and the first electrode 201 is connected between the data line 81 and the first switch connecting part 111.

[0117] In an embodiment, the data line 81 comprises a first line segment 811 and a second line segment 812 connected to each other, the first line segment 811 is arranged close to the first side edge 101, the second line segment 812 is connected to the first line segment 811 and bends outwards towards the direction close to the driving active part 12; and the driving active part 12 is located on the side of the data line 81 close to the inside of the pixel area 100, thus the second line segment 812 bends outwards towards the direction close to the middle area of the pixel area 100; one end of the second switch connecting part 112 is arranged close to the first line segment 811, the other end of the second switch connecting part 112 extends towards the direction close to the second line segment 812 and is connected to the switch channel part 113, the first switch connecting part 111 is connected to the end of the switch channel part 113 away from the second switch connecting part 112; and the first electrode 201 is connected between the first switch connecting part 111 and the second line segment 812.

[0118] In an embodiment, the first line segment 811 and the second line segment 812 are arranged staggered or partially overlapped along the first direction X1, the distance between the second line segment 812 and the first switch connecting part 111 along the second direction X2 is smaller than the distance between the first line segment 811 and the first switch connecting part 111 along the second direction X2, and the first electrode 201 is connected to the second line segment 812; that is, due to the offset of the first switch connecting part 111 towards the center of the pixel area 100 in the embodiment, the connection point of the first electrode 201 and the first switch connecting part 111 is also offset towards the center of the pixel area 100, thus the partial line segments of the data line 81, such as the second line segment 812, are arranged offset towards the center of the pixel area 100 in the embodiment, which is more conducive to the connection between the data line 81 and the first electrode 201 and the first switch connecting part 111.

[0119] The auxiliary reset signal line 82 extends along the first direction X1, and the auxiliary reset signal line 82 is connected to the third reset signal line 73 through the fourth connection node 904, so that the multiple third reset signal lines 73 extending along the second direction X2 can also be connected through the auxiliary reset signal line 82 extending along the first direction X1, so that the multiple third reset signal lines 73 are connected in parallel, so as to reduce the impedance of the multiple third reset signal lines 73, improve the signal transmission uniformity of the third reset signal line 73, and improve the display uniformity of the display panel.

[0120] In an embodiment, the auxiliary reset signal lines 82 are located between two adjacent data lines 81, and the number of auxiliary reset signal lines 82 is multiple, and a mesh structure is formed between the multiple auxiliary reset signal lines 82 and the multiple third reset signal lines 73, so as to further reduce the impedance of the multiple third reset signal lines 73, further improve the signal transmission uniformity in the third reset signal lines 73, and further improve the display uniformity of the display panel.

[0121] The third electrode plate 83 overlaps the first electrode plate 54, and the third electrode plate 83, the driving gate 43, and the first electrode plate 54 form a storage capacitor Cst.

[0122] As described above, in the embodiment, the first switch connection part 111 of the switch active part 11 is arranged close to the center of the pixel area 100, and compared with the structure shown in FIG. 1, the distance between the via holes above the first switch connection part 111 in two adjacent pixel areas 100 is increased, that is, the distribution uniformity of the via holes above the first switch connection part 111 is improved, which is more conducive to improving the dehydrogenation effect of the film layer in the display panel, reducing the hydrogen content of the film layer in the display panel, improving the electrical stability of the thin film transistor in the pixel driving circuit 1000, improving the threshold voltage offset phenomenon of the thin film transistor in the pixel driving circuit 1000, and improving the display uniformity of the display panel.

[0123] In addition, the embodiment of the present application also provides a manufacturing method of the display panel, which refers to FIG. 6, and the manufacturing method comprises the following steps.

[0124] A substrate 90 is provided.

[0125] In an embodiment, the substrate 90 can be a glass substrate, and the glass substrate can be pre-baked after being cleaned.

[0126] A plurality of sub-layers are sequentially deposited on the substrate 90, the material of the plurality of sub-layers can be one or more of a-Si, SiN, SiO, and polyimide, and the material of the sub-layer farthest from the substrate 90 side of the plurality of sub-layers is an inorganic material, so as to form a barrier layer 91.

[0127] Then, a first metal layer is formed on the barrier layer 91, and the first metal layer is subjected to a patterning process to obtain the light shielding layer 30, and the material of the first metal layer can include one or more of Mo, Al, Cu, and Ti, and the first metal layer can be a single-layer metal film or a multi-layer metal film.

[0128] Then, a buffer layer 92 is deposited on the barrier layer 91 to cover the light shielding layer 30, and the material of the buffer layer 92 can include one or more of SiO and SiN, and the buffer layer 92 can be a single-layer thin film or a multi-layer thin film.

[0129] Then, a first semiconductor layer is deposited on the buffer layer 92, and a material of the first semiconductor layer includes a-Si.

[0130] The first semiconductor layer is subjected to rapid thermal annealing or laser crystallization to convert the a-Si into Poly-Si, and then the first semiconductor layer is subjected to a photo-lithography and etching process to be patterned.

[0131] Then, the first semiconductor layer is subjected to ion doping to form channel doping, and the doping ion can be B ion.

[0132] Then, a first gate insulating layer 93 is formed to cover the first semiconductor layer, and a material of the first gate insulating layer 93 includes one or more of SiO and SiN, and the first gate insulating layer 93 can be a single layer thin film or a multi-layer thin film.

[0133] A second metal layer is formed on the first gate insulating layer 93, and the second metal layer is subjected to a photo-lithography and etching process to obtain the first gate layer 40, and a material of the second metal layer can include one or more of Mo, Al, Cu, and Ti, and the second metal layer can be a single layer metal film or a multi-layer metal film.

[0134] The first semiconductor layer is subjected to ion implantation by a self-alignment process to form a P+ doped region to form the first active layer 10, and the implantation ion can be B ion.

[0135] Then, a second gate insulating layer 94 is deposited to cover the first gate layer 40, and a material of the second gate insulating layer 94 includes one or more of SiO and SiN, and the second gate insulating layer 94 can be a single layer thin film or a multi-layer thin film.

[0136] A third metal layer is formed on the second gate insulating layer 94, and the third metal layer is subjected to a photo-lithography and etching process to obtain the second gate layer 50, and a material of the third metal layer can include one or more of Mo, Al, Cu, and Ti, and the third metal layer can be a single layer metal film or a multi-layer metal film.

[0137] A first interlayer dielectric layer 95 is formed to cover the second gate layer 50, and a material of the first interlayer dielectric layer 95 includes one or more of SiO and SiN, and the first interlayer dielectric layer 95 can be a single layer thin film or a multi-layer thin film.

[0138] A second semiconductor layer is deposited on the first interlayer dielectric layer 95, and the second semiconductor layer is subjected to a photo-lithography and etching process to be patterned, and a material of the second semiconductor layer can include IGZO, IGTO, ITZO, or IGZTO.

[0139] Then, a third gate insulating layer 96 is formed to cover the second active layer 60, and the material of the third gate insulating layer 96 includes one or more of SiO and SiN, and the third gate insulating layer 96 can be a single thin film or a multi-layer thin film.

[0140] A fourth metal layer is formed on the third gate insulating layer 96, and the fourth metal layer is patterned to obtain a third gate layer 70, and the material of the fourth metal layer can include one or more of Mo, Al, Cu and Ti, and the fourth metal layer can be a single metal film or a multi-layer metal film.

[0141] Then, the second semiconductor layer is ion implanted by using a self-alignment process to form an N+ doped region, and then the second active layer 60 is formed, and the implanted ions can be B ions.

[0142] A second interlayer dielectric layer 97 is formed to cover the third gate layer 70, and the material of the second interlayer dielectric layer 97 includes one or more of SiO and SiN, and the second interlayer dielectric layer 97 can be a single thin film or a multi-layer thin film.

[0143] Then, a contact hole is formed by using a photolithography process, and the contact hole can expose part of the upper surface of the first active layer 10 and part of the upper surface of the second active layer 60.

[0144] Then, a fifth metal layer is formed, and the fifth metal layer is patterned to form a first conductive layer 20, and the material of the fifth metal layer can include one or more of Mo, Al, Cu and Ti, and the fifth metal layer can be a single metal film or a multi-layer metal film.

[0145] A first planar layer 98 is formed to cover the first conductive layer 20, and the material of the first planar layer 98 includes an organic photoresist material.

[0146] Then, a sixth metal layer is formed on the first planar layer 98, and the sixth metal layer is patterned to form a second conductive layer 80, and the material of the sixth metal layer can include one or more of Mo, Al, Cu and Ti, and the sixth metal layer can be a single metal film or a multi-layer metal film.

[0147] A second planar layer 99 is formed to cover the second conductive layer 80, and the material of the second planar layer 99 can include an organic photoresist material.

[0148] Then, an anode, a pixel definition layer, an organic light-emitting layer, a spacer column and a packaging layer are sequentially formed on the second planar layer 99 to obtain a display panel as described in the above embodiment.

[0149] In addition, referring to FIG. 14, the display device 900 according to an embodiment of the present application includes the display panel 9000 according to the above-described embodiment.

[0150] In summary, by arranging the first switch connecting portion 111 of the switch active portion 11 at a position close to the center of the pixel region 100, and further compared with the structure shown in FIG. 1, the distance of the via above the first switch connecting portion 111 in two adjacent pixel regions 100 can be increased, i.e. the distribution uniformity of the via above the first switch connecting portion 111 is improved, which is more conducive to improving the dehydrogenation effect of the film layer in the display panel, reducing the hydrogen content of the film layer in the display panel, improving the electrical stability of the thin film transistor in the pixel driving circuit 1000, improving the threshold voltage shift phenomenon of the thin film transistor in the pixel driving circuit 1000, and improving the display uniformity of the display panel.

[0151] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0152] The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising a plurality of pixel regions, and a pixel driving circuit arranged in each of the pixel regions; the pixel driving circuit comprises a switching transistor and a driving transistor connected in series, the switching transistor comprises a switching active part, and the driving transistor comprises a driving active part; the display panel further comprises: a first active layer comprising the switching active part and the driving active part arranged in the pixel region; a first conductive layer arranged on one side of the first active layer and comprising a first electrode and a second electrode; a second conductive layer arranged on a side of the first conductive layer away from the first active layer and comprising a data line extending along the length direction of a first side of the pixel region; wherein the data line comprises a first segment arranged close to the first side and a second segment connected to the first segment and bent outwards towards the driving active part, a first end of the switching active part is arranged close to the first segment and connected to the second electrode, a second end of the switching active part extends towards the second segment, and the first electrode is connected between the second segment and the second end of the switching active part.

2. The display panel of claim 1, wherein, the switching active part comprises a first switching connecting part, a second switching connecting part, and a switching channel part connected between the first switching connecting part and the second switching connecting part, one end of the second switching connecting part is arranged close to the first segment, the other end of the second switching connecting part extends towards the second segment and is connected to the switching channel part, and the first switching connecting part is connected to one end of the switching channel part away from the second switching connecting part; wherein the first electrode is connected between the first switching connecting part and the second segment.

3. The display panel of claim 2, wherein, the driving transistor comprises a driving active part, the driving active part comprises a first driving connecting part, a second driving connecting part, and a driving channel part connected between the first driving connecting part and the second driving connecting part; wherein the first driving connecting part is connected to the second switching connecting part close to the first segment, the driving channel part is located on a side of the first driving connecting part away from the first side, the first switching connecting part and the driving channel part are at least partially overlapped in a first direction, and the first direction is the length direction of the first side.

4. The display panel of claim 3, wherein, the driving channel part comprises a first sub-part, and a second sub-part and a third sub-part connected to opposite ends of the first sub-part, and the second sub-part and the third sub-part are both located on the same side of the first sub-part in the first direction, and the second sub-part is connected to the first driving connecting part; wherein the first switching connecting part and the first sub-part and / or the second sub-part are at least partially overlapped in the first direction.

5. The display panel of claim 3, wherein, the pixel driving circuit further comprises a first light-emitting control transistor, the switching transistor, the driving transistor, and the first light-emitting control transistor are all connected to a first node, and the first light-emitting control transistor comprises a first light-emitting control active part. The first active layer comprises the first light-emitting control active part, the first light-emitting control active part is arranged close to the first line segment and is connected with the second switch connection part and the first drive connection part, and the first switch connection part is located on one side of the first light-emitting control active part close to the drive active part.

6. The display panel of claim 3, wherein, The first line segment and the second line segment are arranged staggered or partially overlapped along the first direction, the distance between the second line segment and the first switch connection part along the second direction is smaller than the distance between the first line segment and the first switch connection part along the second direction, and the second direction is perpendicular to the first direction.

7. The display panel of claim 6, wherein, The pixel driving circuits in the plurality of pixel regions are arranged in an array along the first direction and the second direction, and two adjacent pixel driving circuits along the second direction are arranged in axial symmetry.

8. The display panel of claim 6, wherein, The switch channel part is connected with the first switch connection part and extends along the first direction, and at least part of the second switch connection part extends to the first side edge along the second direction.

9. The display panel of claim 3, wherein, The pixel driving circuit further comprises a light-emitting device, a compensation transistor, a first reset transistor, a second light-emitting control transistor, a second reset transistor, a third reset transistor, a first capacitor, and a second capacitor. The drain of the switch transistor, the source of the drive transistor, the drain of the first light-emitting control transistor, and the drain of the third reset transistor are all connected to the first node, the source of the second light-emitting control transistor, the drain of the drive transistor, and the source of the compensation transistor are all connected to the second node, the gate of the drive transistor, the drain of the first reset transistor, and the drain of the compensation transistor are all connected to the third node, the drain of the second reset transistor, the drain of the second light-emitting control transistor, and the light-emitting device are all connected to the fourth node, the first capacitor is connected between the third node and the source of the first light-emitting control transistor, and the second capacitor is connected between the third node and the gate of the switch transistor.

10. The display panel of claim 9, wherein, The display panel further comprises a second active layer arranged between the first active layer and the second conductive layer, the material of the first active layer comprises polycrystalline silicon, and the material of the second active layer comprises metal oxide. The first active layer further comprises an active part of the second light-emitting control transistor, an active part of the reset transistor, and an active part of the second reset transistor. The second active layer comprises an active part of the compensation transistor and an active part of the first reset transistor.

11. The display panel of claim 2, wherein, The pixel region further comprises a second side edge arranged opposite to the first side edge, and the minimum distance between the first switch connection part and the second side edge is greater than the minimum distance between the second switch connection part and the first side edge.

12. A display device comprising a display panel including a plurality of pixel regions, and a pixel drive circuit provided in each of the pixel regions. The pixel driving circuit comprises a switch transistor and a drive transistor connected with each other, the switch transistor comprises a switch active part, and the drive transistor comprises a drive active part. The display panel further comprises: a first active layer comprising the switch active part and the drive active part arranged in the pixel region. The first conductive layer is arranged on one side of the first active layer and includes a first electrode and a second electrode. The second conductive layer is arranged on the side of the first conductive layer away from the first active layer and includes a data line extending along the length direction of the first side edge of the pixel region. The data line includes a first segment arranged close to the first side edge and a second segment connected to the first segment and protruding in a direction close to the driving active part, the first end of the switching active part is arranged close to the first segment and connected to the second electrode, the second end of the switching active part extends in a direction close to the second segment, and the first electrode is connected between the second segment and the second end of the switching active part.

13. The display device of claim 12, wherein, The switching active part includes a first switching connecting part, a second switching connecting part, and a switching channel part connected between the first switching connecting part and the second switching connecting part, one end of the second switching connecting part is arranged close to the first segment, the other end of the second switching connecting part extends in a direction close to the second segment and is connected to the switching channel part, and the first switching connecting part is connected to one end of the switching channel part away from the second switching connecting part. The first electrode is connected between the first switching connecting part and the second segment.

14. The display device of claim 13, wherein, The driving transistor includes a driving active part, the driving active part includes a first driving connecting part, a second driving connecting part, and a driving channel part connected between the first driving connecting part and the second driving connecting part. The first driving connecting part is connected to the second switching connecting part close to the first segment, the driving channel part is located on the side of the first driving connecting part away from the first side edge, the first switching connecting part and the driving channel part are arranged at least partially overlapped in a first direction, and the first direction is the length direction of the first side edge.

15. The display device of claim 14, wherein, The driving channel part includes a first sub-part and a second sub-part and a third sub-part connected to opposite ends of the first sub-part, and the second sub-part and the third sub-part are located on the same side of the first sub-part in the first direction, and the second sub-part is connected to the first driving connecting part. The first switching connecting part and the first sub-part and / or the second sub-part are arranged at least partially overlapped in the first direction.

16. The display device of claim 14, wherein, The pixel driving circuit further includes a first light-emitting control transistor, the switching transistor, the driving transistor, and the first light-emitting control transistor are connected to a first node, and the first light-emitting control transistor includes a first light-emitting control active part. The first active layer includes the first light-emitting control active part, the first light-emitting control active part is arranged close to the first segment and connected to the second switching connecting part and the first driving connecting part, and the first switching connecting part is located on the side of the first light-emitting control active part close to the driving active part.

17. The display device of claim 14, wherein, The first line segment and the second line segment are staggered or partially overlapped along the first direction, the second line segment is spaced apart from the first switch connection portion along a second direction, and the spacing between the second line segment and the first switch connection portion along the second direction is less than the spacing between the first line segment and the first switch connection portion along the second direction, the second direction being perpendicular to the first direction.

18. The display device of claim 17, wherein, The pixel driving circuits in the plurality of pixel regions are arranged in an array along the first direction and the second direction, and two adjacent pixel driving circuits along the second direction are arranged in axial symmetry.

19. The display device of claim 17, wherein, The switch channel portion is connected to the first switch connection portion and extends along the first direction, and at least part of the second switch connection portion extends to the first side along the second direction.

20. The display device of claim 14, wherein, The pixel driving circuit further comprises a light emitting device, a compensation transistor, a first reset transistor, a second light emitting control transistor, a second reset transistor, a third reset transistor, a first capacitor, and a second capacitor. The drain of the switch transistor, the source of the driving transistor, the drain of the first light emitting control transistor, and the drain of the third reset transistor are all connected to the first node, the source of the second light emitting control transistor, the drain of the driving transistor, and the source of the compensation transistor are all connected to the second node, the gate of the driving transistor, the drain of the first reset transistor, and the drain of the compensation transistor are all connected to the third node, the drain of the second reset transistor, the drain of the second light emitting control transistor, and the light emitting device are all connected to the fourth node, the first capacitor is connected between the third node and the source of the first light emitting control transistor, and the second capacitor is connected between the third node and the gate of the switch transistor.

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