Vertical copolymer organic semiconductor device having floating field plate and manufacturing method therefor

Abstract

The present invention provides a vertical copolymer organic semiconductor device having a floating field plate, comprising a substrate, a drain metal electrode, an organic semiconductor layer, a gate dielectric layer, a floating metal field plate, a gate metal electrode and a source metal electrode. A recess is formed at the center of the top of the organic semiconductor layer, and the gate dielectric layer is deposited in the recess; a coaxial recess is formed at the center of the top of the gate dielectric layer, and the gate metal electrode is embedded in the recess; the annular drain metal electrode and the annular source metal electrode are coaxially arranged on the surface of the substrate and the surface of the organic semiconductor layer; the organic semiconductor layer located between the gate metal electrode and the drain metal electrode is formed as a longitudinal drift region; and the floating metal field plate is embedded in the gate dielectric layer, and the longitudinal length of the floating metal field plate can be selected according to voltage withstand requirements. The present invention can increase the width of a depletion layer, weaken the peak value of an electric field, and regulate a breakdown electric field in a drift region, thereby improving the overall voltage withstand performance of devices.

Description

Vertical structure copolymer organic semiconductor device with floating field plate and preparation method thereof TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor device manufacturing, and relates to a vertical structure copolymer organic semiconductor device with a floating field plate and a preparation method thereof. BACKGROUND

[0002] In recent years, organic semiconductor-based electronic devices have attracted widespread attention due to their low cost, flexibility, transparency, large-area preparation capability, and environmental protection characteristics. These advantages enable organic semiconductors to be widely used in the fields of health care, flexible displays, flexible logic and storage devices, sensors, etc. In the power field, copolymer organic semiconductor material-based power devices are expected to promote the development of power integrated circuits and power modules. Power devices need to work in a high-voltage and large-current environment for a long time, so the voltage withstand performance and current transmission performance of the device are crucial. Compared with traditional inorganic devices, copolymer organic power devices still have problems such as small working current, insufficient load driving capability, and low switching speed. To solve these problems, it is necessary to reduce the channel length of the device. Due to the limitations of copolymer organic semiconductor materials and dielectric materials, high-precision control of lateral copolymer organic devices using photolithography technology requires a relatively complex preparation process and very precise instruments and equipment. At the same time, as the channel length and drift region length are reduced to the nanometer level, the channel electric field aggregation effect may also occur, thereby reducing the voltage withstand performance of the device.

[0003] For example, the prior patent document CN116761479A provided by the research group of the present application provides a preparation method of a longitudinal copolymer organic device with a vertical gate slot structure. By vertically arranging the length of the organic semiconductor layer between the gate and the drain, i.e., the channel length, the device channel length can be controlled by controlling only a single parameter such as the concentration of the organic semiconductor solution, the acceleration and speed of the spin coater, etc., without the need for a high-precision photolithography machine. nm-level channels can be manufactured, and the control accuracy can reach ±2nm. SUMMARY

[0004] On the basis of the prior achievements of the research group, in order to further improve the voltage withstand performance of the longitudinal copolymer organic device, the present application provides a vertical structure copolymer organic semiconductor device with a floating field plate. Not only can the device channel be stably controlled to the nanometer level by a simple solution spin coating process, but also the channel cross-sectional area can be increased, thereby improving the charge transport efficiency and enabling excellent on-state performance. The longitudinal drift region of the prepared device is voltage-resistant, and the field plate can further widen the depletion layer, effectively adjust the peak electric field distribution, avoid premature breakdown of the device, and significantly improve the voltage withstand performance of the device.

[0005] The purpose of the present application is achieved by the following technology:

[0006] In the first aspect, the present application provides a vertical structure copolymer organic semiconductor device with floating field plate, comprising a substrate, an organic semiconductor layer, a gate dielectric layer, a floating metal field plate, a drain metal electrode, a gate metal electrode and a source metal electrode; the organic semiconductor layer is located on the substrate, and the preparation material of the organic semiconductor layer is copolymer; the bottom of the organic semiconductor layer is embedded with an annular drain metal electrode; the gate dielectric layer is coaxially inserted into the center of the organic semiconductor layer with the drain metal electrode, and a top recess coaxial with the gate dielectric layer is formed in the top center of the gate dielectric layer, and a cylindrical gate metal electrode is embedded in the top recess; a metal floating field plate is embedded in the inside of the gate dielectric layer and below the gate metal electrode, and the gate metal electrode is not in contact with the metal floating field plate; the top surfaces of the organic semiconductor layer, the gate dielectric layer and the gate metal electrode are located in the same horizontal plane; the source metal electrode is annular and coaxially arranged with the gate metal electrode on the top surface of the organic semiconductor layer outside the gate dielectric layer; the outer diameter and the inner diameter of the drain metal electrode and the source metal electrode are equal, and the inner diameters of the source metal electrode and the drain metal electrode are not less than the outer diameter of the gate dielectric layer;

[0007] The vertical and annular organic semiconductor layer between the drain metal electrode and the gate metal electrode forms a drift region; by controlling the vertical spacing between the drain metal electrode and the gate metal electrode, the vertical length of the drift region can be controlled; as the vertical length of the drift region increases, the voltage resistance performance of the vertical structure copolymer organic semiconductor device with floating field plate gradually improves; by etching a recess in the semiconductor layer, depositing gate dielectric layer material in the recess, evaporating field plate metal and then depositing gate dielectric layer material again, the field plate metal becomes a buried layer, thereby achieving the purpose of preparing a floating metal field plate; by controlling the depth of the recess in the gate dielectric layer, as well as the rate and time of evaporating metal, the relative position of the floating metal field plate relative to the whole device and its longitudinal length can be adjusted;

[0008] Preferably, the preparation material of the organic semiconductor layer is any one of P3HT, DPPT-TT, N2200 and pentacene;

[0009] Preferably, the material of the gate dielectric layer is any one of the insulating materials SiO2, Si3N4 and Al2O3;

[0010] Preferably, the materials of the gate metal electrode, the source metal electrode, the drain metal electrode and the floating metal field plate are any one of gold, aluminum, copper and nickel metal materials;

[0011] Preferably, the substrate is made of any one of glass, flexible plastic, bulk silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide and germanium silicon material.

[0012] In the second aspect, the application provides a preparation method of the vertical structure copolymer organic semiconductor device with floating field plate, as shown in Fig. 2, the preparation method comprises the following steps: cleaning the substrate, evaporating the drain metal electrode, spin-coating the organic semiconductor layer, etching the columnar groove on the top of the organic semiconductor layer, depositing the gate dielectric layer on the surface of the columnar groove to form the first gate dielectric groove, evaporating the metal field plate on the bottom of the gate dielectric groove to form the floating field plate, depositing the gate dielectric layer on the surface of the floating field plate to form the new gate dielectric groove, which is referred to as the second gate dielectric groove, evaporating the gate electrode in the second gate dielectric groove, and forming the drift region in the vertical organic semiconductor layer between the gate electrode and the drain electrode, and evaporating the annular source electrode on the top of the organic semiconductor layer outside the periphery of the annular gate dielectric layer.

[0013] The application provides a preferred preparation method of the vertical structure copolymer organic semiconductor device with floating field plate, wherein:

[0014] The step of evaporating the drain metal electrode comprises the following steps: evaporating the annular drain metal electrode on the cleaned substrate by using the electron beam thermal evaporation instrument, evaporating 5 nm of Ni as the metal adhesive at the evaporation rate of 0.1 A / s for 500 s, and then evaporating 40 nm of Au at the evaporation rate of 0.3 A / s for 1333 s to form the drain electrode.

[0015] The step of spin-coating the organic semiconductor layer comprises the following steps: spin-coating the 1,2-dichlorobenzene (DCB) solution of 10 mg / ml of DPPT-TT on the surface of the substrate and the drain electrode to form the semiconductor layer, spin-coating for 3 times, and the rotation speed of the DPPT-TT solution in each spin-coating is configured as follows: the initial speed of spin-coating is 0 rpm, the acceleration is 200 rpm / s, and the speed is accelerated to 500 rpm, and the acceleration and uniform speed time in this stage lasts for 10 s; then the acceleration is 250 rpm / s, and the speed is accelerated to 700 rpm, and the acceleration and uniform speed time in this stage lasts for 60 s; then the acceleration is-300 rpm / s, and the speed is decelerated to 0 rpm, and the deceleration and stop time in this stage lasts for 5 s; after the first two spin-coatings, the semiconductor layer is annealed at 80℃ for 2 min, annealed at 150℃ for 2 min, and cooled at room temperature for 1 min, and after the last spin-coating, the semiconductor layer is annealed at 80℃ for 5 min, and annealed at 150℃ for 1 h, and the thickness of the completed semiconductor layer is 700 nm.

[0016] The step of etching a columnar groove on the top of the organic semiconductor layer comprises: etching a coaxial columnar groove on the top of the organic semiconductor layer by using a plasma etching machine, the etching rate is 1.7 nm / s, and the etching is performed for 353 s, so that the groove depth is 600 nm, and the outer diameter of the columnar groove is preferably not greater than the inner diameter of the drain metal;

[0017] The step of depositing a gate dielectric layer on the surface of the columnar groove to form a gate dielectric groove comprises: depositing 100 nm thick SiO2 as the gate dielectric layer in the columnar groove by using a normal temperature PECVD device, the growth rate is 0.6 nm / s, and the growth time is 167 s;

[0018] The step of evaporating a metal field plate on the bottom of the gate dielectric groove comprises: evaporating Cu as the metal field plate in the gate dielectric groove by using an electron beam thermal evaporation instrument, the evaporation rate is 0.8 A / s, the evaporation time is 1250 s, and the obtained metal field plate has a longitudinal length of 100 nm;

[0019] The step of depositing a gate dielectric layer on the surface of the floating field plate again comprises: depositing 100 nm thick SiO2 as the gate dielectric layer on the surface of the floating field plate by using a normal temperature PECVD device, the growth rate is 0.6 nm / s, and the growth time is 167 s, so that the gate dielectric layer is wrapped outside the metal field plate to form the floating field plate;

[0020] The step of evaporating a gate electrode in the second gate dielectric groove comprises: evaporating 300 nm of Cu to form the gate electrode in the second gate dielectric groove by using an electron beam thermal evaporation instrument, the evaporation rate is 1 A / s, the evaporation time is 3000 s, and the vertical organic semiconductor layer between the gate electrode and the drain electrode is formed as a drift region;

[0021] The step of evaporating a ring-shaped source electrode on the top of the organic semiconductor layer at the outer periphery of the annular gate dielectric layer comprises: evaporating 40 nm of Au to form the source electrode on the top surface of the organic semiconductor layer at the outer periphery of the gate dielectric layer by using an electron beam thermal evaporation instrument, the evaporation rate is 0.3 A / s, and the evaporation time is 1333 s, so that the source electrode metal is ring-shaped and coaxial with the drain metal.

[0022] The present application has the following beneficial effects:

[0023] 1、The vertical structure copolymer organic semiconductor device with a floating field plate provided by the first aspect of the present application adopts a longitudinal vertical structure, the film thickness can be stably controlled to the nanometer level by using a simple and low-cost spin coating process, and the anisotropy of part of the organic copolymer is fully utilized, the material properties of the transverse device and the longitudinal device prepared on this basis are different, the charge has higher mobility and lower collision ionization coefficient when being transmitted in the longitudinal direction, so that the charge transmission efficiency of the device is improved, and the breakdown voltage is also improved.

[0024] 2、The organic semiconductor layer in the application is prepared by normal temperature spin coating process, the preparation process is simple, the thickness of the organic semiconductor layer can be stably controlled by changing the solution concentration of the organic solution, the spin coating speed of the spin coater, the acceleration and the spin coating time, then the groove is formed by etching with an etching machine such as ICP-RIE etching machine, the stable film is formed by PECVD deposition of gate dielectric, so that the control of the channel length and the drift region length is realized.

[0025] 3、The floating metal field plate in the application is embedded in the gate dielectric layer, which can significantly improve the width of the device depletion layer, reasonably control the electric field distribution of the drift region, weaken the sharp peak electric field, and greatly improve the voltage withstanding performance of the device.

[0026] 4、The floating metal field plate in the application is prepared by electron beam thermal evaporation deposition or magnetron sputtering, the manufacturing process is simple, and the longitudinal length of the floating field plate can be adjusted by controlling the evaporation rate and time, and the relative position of the floating field plate can be adjusted by controlling the depth of the groove in the gate dielectric layer, so that the electric field distribution of the drift region can be more accurately adjusted. BRIEF DESCRIPTION OF DRAWINGS

[0027] Fig. 1 is a semi-sectional view of a vertical structure copolymer organic semiconductor device with a floating field plate according to the application;

[0028] Fig. 2 is a preparation flow chart of a vertical structure copolymer organic semiconductor device with a floating field plate according to the application;

[0029] Fig. 3 is a semi-sectional view of a vertical structure copolymer organic semiconductor device according to the comparative example 1 of the application;

[0030] Fig. 4 is a semi-sectional view of a vertical structure copolymer organic semiconductor device with a floating field plate according to the embodiment 2 of the application;

[0031] Fig. 5 is a semi-sectional view of a vertical structure copolymer organic semiconductor device with a floating field plate according to the embodiment 3 of the application;

[0032] Fig. 6 shows the breakdown characteristic curve of the vertical structure copolymer organic semiconductor device prepared according to the comparative example and the embodiment of the application;

[0033] Fig. 7 shows the output characteristic curve of the vertical structure copolymer organic semiconductor device with a floating field plate prepared according to the embodiment 1 of the application;

[0034] Fig. 8 shows the output characteristic curve of the vertical structure copolymer organic semiconductor device prepared according to the comparative example 1 of the application;

[0035] Fig. 9 shows the output characteristic curve of the vertical structure copolymer organic semiconductor device with a floating field plate prepared according to the embodiment 2 of the application;

[0036] Figure 10 shows the output characteristic curve of the vertical structure copolymer organic semiconductor device with floating metal field plate prepared in Example 3 of the present application;

[0037] Wherein, 1-source metal, 2-organic semiconductor layer, 3-gate metal, 4-gate dielectric layer, 5-floating metal field plate, 6-drain metal, 7-substrate. DETAILED DESCRIPTION

[0038] The present application is described in detail below with reference to the accompanying drawings and specific examples, but the present application is not limited to only these examples. The present application encompasses any alternative, modification, equivalent method and scheme made within the spirit and scope of the present application. In order for the public to have a thorough understanding of the present application, specific details are described in detail in the following examples of the present application, and the present application can be fully understood without the description of these details by those skilled in the art.

[0039] In the description of the present application, it should be understood that the terms "left side", "right side", "upper part", "lower part" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and "first", "second" and the like do not represent the importance of the parts, and therefore cannot be understood as a limitation on the present application. The specific dimensions used in the present embodiment are only for the purpose of illustrating the technical scheme and do not limit the protection scope of the present application.

[0040] The sources of raw materials and reagents used in Examples 1-3 and Comparative Example 1 are as follows: 1-2 dichlorobenzene solvent (DCB) from Sigma Aldrich Company, and DPPT-TT from Shenzhen Ruixun Optoelectronic Material Technology Co., Ltd.

[0041] Example 1

[0042] The present embodiment provides a vertical structure copolymer organic semiconductor device with floating metal field plate, referring to Figure 1, the manufacturing process is shown in Figure 2, including the following steps:

[0043] Step S1, clean the substrate, use 0.5mm thick acrylic glass substrate produced by Corning Company in the United States, ultrasonic in deionized water for 5min, then ultrasonic in alcohol for 5min, cycle cleaning three times, dry with nitrogen, and place on a heating table at 100℃ for post-baking;

[0044] Step S2, evaporating the drain electrode, evaporating the annular drain electrode metal electrode on the cleaned substrate by using the electron beam thermal evaporation instrument, evaporating Ni (5 nm) as the metal adhesive first, the evaporation rate is 0.1 A / s, the evaporation time is 500 s, then evaporating Au (40 nm) with the evaporation rate of 0.3 A / s, the evaporation time is 1333 s, forming the drain electrode;

[0045] Step S3, spin-coating the organic semiconductor layer, spin-coating the 1,2-dichlorobenzene (DCB) solution of 10 mg / ml DPPT-TT on the substrate and the surface of the drain electrode to form the semiconductor layer, a total of 3 times of spin-coating, the rotation speed of the DPPT-TT solution in each spin-coating is configured as follows: the initial speed of spin-coating is 0 rpm, accelerating to 500 rpm at the acceleration of 200 rpm / s, the acceleration and uniform speed time in this stage lasts for 10 s in total; then accelerating to 700 rpm at the acceleration of 250 rpm / s, the acceleration and uniform speed time in this stage lasts for 60 s in total; then decelerating to 0 rpm at the acceleration of-300 rpm / s, the deceleration and stop time in this stage lasts for 5 s in total; after the first two spin-coatings, annealing at 80°C for 2 min, annealing at 150°C for 2 min, and cooling at room temperature for 1 min, after the last spin-coating, annealing at 80°C for 5 min, and annealing at 150°C for 1 h, the thickness of the completed semiconductor layer is 700 nm;

[0046] Step S4, etching the columnar groove, etching a coaxial columnar groove on the top of the organic semiconductor layer by using the plasma etching machine, the etching rate is 1.7 nm / s, a total of 353 s of etching is performed, the groove depth is 600 nm, and the diameter of the columnar groove is preferably less than the inner diameter of the drain metal;

[0047] Step S5, depositing the gate dielectric layer, depositing 100 nm thick SiO2 as the gate dielectric layer in the columnar groove formed in step S4 by using the normal temperature PECVD device, the growth rate is 0.6 nm / s, and the growth time is 167 s.

[0048] Step S6, evaporating the metal field plate, evaporating Cu as the metal field plate in the gate dielectric groove formed in step S5 by using the electron beam thermal evaporation instrument, the evaporation rate is 0.8 A / s, and the evaporation time is 1250 s, the obtained metal field plate has a longitudinal length of 100 nm.

[0049] Step S7, depositing the gate dielectric layer again, depositing 100 nm thick SiO2 as the gate dielectric layer on the surface of the floating field plate formed in step S6 by using the normal temperature PECVD device, the growth rate is 0.6 nm / s, and the growth time is 167 s, so that the gate dielectric layer wraps the outside of the metal field plate, forming the floating field plate;

[0050] Step S8, evaporating the gate electrode, evaporating 300nm Cu in the gate dielectric groove formed in step S7 by using electron beam thermal evaporation instrument, the evaporation rate is 1A / s, the evaporation time is 3000s, the vertical organic semiconductor layer between the gate electrode and the drain electrode is formed as a drift region;

[0051] Step S9, evaporating the source electrode, evaporating Au(40nm) on the top surface of the organic semiconductor layer outside the gate dielectric layer by using electron beam thermal evaporation instrument to form the source electrode, the evaporation rate is 0.3A / s, the evaporation time is 1333s, the source electrode metal is annular and coaxial with the drain electrode metal.

[0052] Comparative Example 1: Vertical structure copolymer organic semiconductor device without field plate

[0053] Referring to FIG. 3, the comparative example 1 provides a vertical structure copolymer organic semiconductor device, which is different from the example 1 only in that there is no step of evaporating a metal field plate and re-depositing a gate dielectric layer in the comparative example 1, and specifically, the preparation process of the comparative example 1 comprises:

[0054] Step S1, cleaning the substrate, using 0.5mm thick acrylic glass substrate produced by Corning Company of the United States, ultrasonic cleaning with deionized water for 5min and then ultrasonic cleaning with alcohol for 5min, three times of cyclic cleaning, blowing dry with nitrogen, and placing on a heating table at 100℃ for drying;

[0055] Step S2, evaporating the drain electrode, evaporating annular drain electrode metal electrode on the cleaned substrate by using electron beam thermal evaporation instrument, first evaporating Ni(5nm) as a metal adhesive, the evaporation rate is 0.1A / s, the evaporation time is 500s, then evaporating Au(40nm), the evaporation rate is 0.3A / s, the evaporation time is 1333s, forming the drain electrode;

[0056] Step S3, spin-coating the organic semiconductor layer, using 10mg / ml DPPT-TT 1,2-dichlorobenzene(DCB) solution to spin-coat on the substrate and the surface of the drain electrode to form the semiconductor layer, a total of 3 times of spin-coating, the rotation speed of the DPPT-TT solution is configured as follows: the initial speed of spin-coating is 0rpm, accelerating to 500rpm at an acceleration of 200rpm / s, the acceleration and uniform speed time in this stage lasts for a total of 10s; then accelerating to 700rpm at an acceleration of 250rpm / s, the acceleration and uniform speed time in this stage lasts for a total of 60s; then decelerating to 0rpm at a deceleration of -300rpm / s, the deceleration and stopping time in this stage lasts for a total of 5s; after the first two times of spin-coating, annealing at 80℃ for 2min, annealing at 150℃ for 2min, and cooling at room temperature for 1min, after the last time of spin-coating, annealing at 80℃ for 5min, and annealing at 150℃ for 1h, the thickness of the completed semiconductor layer is 700nm;

[0057] Step S4, etching a columnar groove, using a plasma etching machine to etch a coaxial columnar groove on the top of the organic semiconductor layer, the etching rate is 1.7 nm / s, etching for 353 s, the groove depth is 600 nm, and the diameter of the columnar groove is preferably less than the inner diameter of the drain metal;

[0058] Step S5, depositing a gate dielectric layer, using a normal temperature PECVD device to deposit a 600 nm thick SiO2 as a gate dielectric layer in the columnar groove formed in step S4, the growth rate is 0.6 nm / s, and the growth time is 1000 s.

[0059] Step S6, etching a gate dielectric layer groove, using a plasma etching machine to etch a coaxial columnar groove in the gate dielectric layer formed in step S5, the etching rate is 0.64 nm / s, etching for 469 s, the groove depth is 300 nm;

[0060] Step S7, evaporating a gate, using an electron beam thermal evaporation instrument to evaporate 300 nm of Cu to form a gate in the gate dielectric groove formed in step S6, the evaporation rate is 1 A / s, the evaporation time is 3000 s, and the vertical organic semiconductor layer between the gate and the drain forms a drift region;

[0061] Step S8, evaporating a source, using an electron beam thermal evaporation instrument to evaporate Au (40 nm) on the top surface of the organic semiconductor layer outside the gate dielectric layer to form a source, the evaporation rate is 0.3 A / s, the evaporation time is 1333 s, the source metal is annular and coaxial with the drain metal;

[0062] The differences between Examples 2 and 3 and Example 1 are that the relative positions of the floating field plates of the devices prepared in Example 2 are different, the thicknesses and relative positions of the floating field plates of Example 3 are different, and in order to maintain the length of the metal field plate of the device prepared in Example 2 and Example 2 consistent with the length of the metal field plate evaporated in Example 1, and to facilitate precise control of the relative position and thickness of the metal field plate in Example 2 and Example 3, the first gate dielectric groove in Example 2 is formed by filling the gate insulating material first and then etching to form a first gate dielectric groove with the same wall thickness as in Example 1, and correspondingly, the second gate dielectric groove in Example 2 is also formed by filling the gate insulating material first and then etching to form a second gate dielectric groove with the same wall thickness as in Example 1, to ensure that the size and morphology of the subsequent gate are consistent with Example 1.

[0063] Example 2

[0064] This embodiment 2 provides a vertical structure copolymer organic semiconductor device with a floating field plate, referring to FIG. 4, the difference from Example 1 is only that the relative position of the floating field plate is different;

[0065] Step S1, cleaning the substrate, using 0.5mm thick acrylic glass substrate produced by Corning, Inc., ultrasonic cleaning with deionized water for 5min and then ultrasonic cleaning with alcohol for 5min, three times, dried with nitrogen and placed on a heating table at 100℃ for drying;

[0066] Step S2, evaporation of the drain, on the cleaned substrate, using an electron beam thermal evaporation instrument to evaporate a ring-shaped drain metal electrode, first evaporate Ni (5nm) as an adhesive, evaporation rate 0.1A / s, evaporation time 500s, then evaporate Au (40nm) evaporation rate 0.3A / s, evaporation time 1333s, to form the drain;

[0067] Step S3, spin coating the organic semiconductor layer, using 10mg / ml of DPPT-TT in 1,2-dichlorobenzene (DCB) solution to spin coat the substrate and the drain surface to form a semiconductor layer, a total of 3 times, the rotation speed of DPPT-TT solution spin coating is configured as follows: the initial speed of spin coating is 0rpm, accelerated to 500rpm at an acceleration of 200rpm / s, the acceleration and uniform speed time of this stage lasts for 10s; then accelerated to 700rpm at an acceleration of 250rpm / s, the acceleration and uniform speed time of this stage lasts for 60s; then decelerated to 0rpm at an acceleration of -300rpm / s, the deceleration and stop time of this stage lasts for 5s; after the first two spin coatings, annealing at 80℃ for 2min, annealing at 150℃ for 2min, and cooling at room temperature for 1min, after the last spin coating, annealing at 80℃ for 5min, and annealing at 150℃ for 1h, the thickness of the completed semiconductor layer is 700nm;

[0068] Step S4, etching a cylindrical groove, using a plasma etching machine to etch a coaxial cylindrical groove on the top of the organic semiconductor layer, etching rate 1.7nm / s, a total of 353s, the groove depth is 600nm, and the cylindrical groove diameter is equal to the inner diameter of the drain metal;

[0069] Step S5, depositing a gate dielectric layer, using a room temperature PECVD device to deposit a 600nm thick SiO2 as a gate dielectric layer in the cylindrical groove formed in step S4, growth rate 0.6nm / s, growth time 1000s;

[0070] Step S6, etching a groove in the gate dielectric layer, using a plasma etching machine to etch a coaxial cylindrical groove in the cylindrical groove formed in step S5, etching rate 0.64nm / s, a total of 703s, the groove depth is 450nm;

[0071] Step S7, evaporating metal field plate, evaporating Cu as metal field plate in the gate dielectric groove formed in step S6 by using electron beam thermal evaporating instrument, the evaporation rate is 0.8 A / s, the evaporation time is 1250 s, the length of the metal field plate is 100 nm.

[0072] Step S8, depositing gate dielectric layer again, depositing 350 nm thick SiO2 as gate dielectric layer on the surface of the floating field plate formed in step S7 by using normal temperature PECVD equipment, the growth rate is 0.6 nm / s, the growth time is 583 s, so that the gate dielectric layer is wrapped outside the metal field plate to form the floating field plate.

[0073] Step S9, etching gate dielectric layer groove, etching a coaxial cylindrical groove in the insulating layer formed in step S8 by using plasma etching machine, the etching rate is 0.64 nm / s, the total etching time is 469 s, and the groove depth is 300 nm.

[0074] Step S10, evaporating gate, evaporating 300 nm Cu as gate in the gate dielectric groove formed in step S9 by using electron beam thermal evaporating instrument, the evaporation rate is 1 A / s, the evaporation time is 3000 s, and the vertical organic semiconductor layer between the gate and the drain forms a drift region.

[0075] Step S11, evaporating source, evaporating Au (40 nm) as source on the top surface of the organic semiconductor layer outside the gate dielectric layer by using electron beam thermal evaporating instrument, the evaporation rate is 0.3 A / s, the evaporation time is 1333 s, the source metal is annular and coaxial with the drain metal.

[0076] Example 3

[0077] This embodiment 3 provides a vertical structure copolymer organic semiconductor device with floating field plate, referring to FIG. 6, the steps S1-S5 and steps S9-S11 in embodiment 2 are the same, the difference is only in steps S6-S8, the specific steps S6-S8 are as follows:

[0078] Step S6, etching gate dielectric layer groove, etching a coaxial cylindrical groove in the cylindrical groove formed in step S5 by using plasma etching machine, the etching rate is 0.64 nm / s, the total etching time is 859 s, and the groove depth is 550 nm.

[0079] Step S7, evaporating metal field plate, evaporating Cu as metal field plate in the gate dielectric groove formed in step S6 by using electron beam thermal evaporating instrument, the evaporation rate is 1 A / s, the evaporation time is 2000 s, and the length of the metal field plate is 200 nm.

[0080] Step S8, the gate dielectric layer is deposited again, the surface of the floating field plate formed in step S7 is deposited with 350nm thick SiO2 as the gate dielectric layer using the normal temperature PECVD equipment, the growth rate is 0.6nm / s, the growth time is 583s, so that the gate dielectric layer is wrapped outside the metal field plate to form the floating field plate;

[0081] FIGS. 6-10 are breakdown characteristic curves and output characteristic curves of the vertical structure copolymer organic semiconductor devices of the comparative examples and the examples prepared at room temperature using the Keysight B1505A test analyzer, the Taiwan Yiyeh CG-196 high temperature low probe station using the conventional slide test method.

[0082] FIG. 6 is the breakdown characteristic curves of several devices, from which it can be seen that the breakdown voltage of the vertical structure copolymer organic semiconductor devices with floating field plates in examples 1-3 is improved to varying degrees compared to the devices without field plate structure, for example, the breakdown voltage of the device prepared in example 1 is 460V, which is 35% higher than 340V in comparative example 1, the setting of the floating field plate improves the electric field aggregation phenomenon of the device under the condition of maintaining the working current, significantly improves the voltage resistance performance of the device, and when the longitudinal length and relative position of the field plate change in different examples, the voltage resistance performance of the device also changes, the relative position and thickness setting of the metal field plate in example 1 is higher than that in comparative example 1, and the voltage resistance performance of the device is higher. FIG. 7 is the output characteristic curve of example 1, compared with the traditional horizontal copolymer organic semiconductor device, the working current of the vertical structure device is larger, which is due to the fact that this structure greatly reduces the channel length; FIGS. 8, 9 and 10 are output characteristic curves of comparative example 1, example 2 and example 3, respectively, and the working current of examples 1-3 is basically unchanged compared with comparative example 1, it can be seen that the examples improve the voltage resistance while maintaining good forward conduction characteristics.

Claims

1. A vertical structure copolymer organic semiconductor device with floating air-plate, characterized in that, The vertical structure copolymer organic semiconductor device comprises a substrate, an organic semiconductor layer, a gate dielectric layer, a floating metal field plate, a drain metal electrode, a gate metal electrode and a source metal electrode; the organic semiconductor layer is located on the substrate, and the preparation material of the organic semiconductor layer is a copolymer; the organic semiconductor layer is embedded with an annular drain metal electrode at the bottom; the gate dielectric layer is coaxially inserted into the center of the organic semiconductor layer with the drain metal electrode, and a top recess is formed in the center of the top of the gate dielectric layer coaxially with the gate dielectric layer, and a cylindrical gate metal electrode is embedded in the top recess; a metal floating field plate is embedded in the inside of the gate dielectric layer and below the gate metal electrode, and the gate metal electrode is not in contact with the metal floating field plate; the top surfaces of the organic semiconductor layer, the gate dielectric layer and the gate metal electrode are located on the same horizontal plane; the source metal electrode is annular and coaxially arranged with the gate metal electrode on the top surface of the organic semiconductor layer outside the gate dielectric layer; the outer diameter and the inner diameter of the drain metal electrode and the source metal electrode are equal, and the inner diameters of the source metal electrode and the drain metal electrode are not less than the outer diameter of the gate dielectric layer; the vertical and annular organic semiconductor layer between the drain metal electrode and the gate metal electrode forms a drift region.

2. The vertical structure copolymer organic semiconductor device with floating field plate according to claim 1, wherein, The preparation material copolymer of the organic semiconductor layer is any one of P3HT, DPPT-TT, N2200 and pentacene.

3. The vertical structure copolymer organic semiconductor device with floating air- space field plate according to claim 1, wherein: The material of the gate dielectric layer is any one of insulating materials SiO2, Si3N4 and Al2O3.

4. The vertical structure copolymer organic semiconductor device with floating field plate according to claim 1, wherein, The materials of the gate metal electrode, the source metal electrode, the drain metal electrode and the floating metal field plate are any one of gold, aluminum, copper and nickel metal materials.

5. The vertical structure copolymer organic semiconductor device with floating field plate according to claim 1, wherein, The substrate is any one of glass, flexible plastic, bulk silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide and germanium silicon materials.

6. The method of producing a vertical structure copolymer organic semiconductor device having a floating field plate according to any one of claims 1 to 5, characterized by, The preparation method comprises the following steps: after cleaning the substrate, evaporating the drain metal electrode, then spin-coating the organic semiconductor layer, etching a cylindrical groove on the top of the organic semiconductor layer, and depositing the gate dielectric layer on the surface of the cylindrical groove to form a first gate dielectric recess; evaporating a metal field plate on the bottom of the gate dielectric recess to form a floating field plate, and again depositing the gate dielectric layer on the surface of the floating field plate to form a new gate dielectric recess, which is referred to as a second gate dielectric recess, evaporating the gate electrode in the second gate dielectric recess, and the vertical organic semiconductor layer between the gate electrode and the drain electrode forming a drift region, and evaporating the annular source electrode on the top of the organic semiconductor layer outside the annular gate dielectric layer.

7. The preparation method according to claim 6, wherein the step of evaporating the drain metal electrode comprises: evaporating an annular drain metal electrode on the cleaned substrate by using an electron beam thermal evaporation instrument, evaporating 5 nm of Ni as a metal adhesive first, the evaporation rate being 0.1 A / s, and the evaporation time being 500 s, and then evaporating 40 nm of Au, the evaporation rate being 0.3 A / s, and the evaporation time being 1333 s, to form the drain electrode; The step of spin-coating the organic semiconductor layer includes: spin-coating 1,2-dichlorobenzene (DCB) solution of 10 mg / ml DPPT-TT onto the substrate and the surface of the drain to form a semiconductor layer, a total of 3 times, and the rotation speed of each spin-coating of the DPPT-TT solution is configured as: an initial speed of spin-coating is 0 rpm, an acceleration to 500 rpm is 200 rpm / s, the acceleration and uniform speed time of this stage lasts for 10 s in total, then an acceleration to 700 rpm is 250 rpm / s, the acceleration and uniform speed time of this stage lasts for 60 s in total, then a deceleration to 0 rpm is-300 rpm / s, the deceleration and stop time of this stage lasts for 5 s in total, after the first two spin-coatings, annealing at 80°C for 2 min, annealing at 150°C for 2 min, and cooling at room temperature for 1 min, after the last spin-coating, annealing at 80°C for 5 min, and annealing at 150°C for 1 h, the thickness of the completed semiconductor layer is 700 nm; The step of etching a columnar groove on the top of the organic semiconductor layer includes: etching a coaxial columnar groove on the top of the organic semiconductor layer by using a plasma etching machine, an etching rate is 1.7 nm / s, a total etching time is 353 s, a groove depth is 600 nm, and an outer diameter of the columnar groove is preferably not greater than an inner diameter of the drain metal; The step of depositing a gate dielectric layer on the surface of the columnar groove to form a gate dielectric groove includes: depositing 100 nm thick SiO2 as the gate dielectric layer in the columnar groove by using a normal-temperature PECVD device, a growth rate is 0.6 nm / s, and a growth time is 167 s; The step of evaporating a metal field plate at the bottom of the gate dielectric groove includes: evaporating Cu as the metal field plate in the gate dielectric groove by using an electron beam thermal evaporator, an evaporation rate is 0.8 A / s, an evaporation time is 1250 s, and a longitudinal length of the metal field plate is 100 nm; The step of depositing a gate dielectric layer on the surface of the floating field plate again includes: depositing 100 nm thick SiO2 as the gate dielectric layer on the surface of the floating field plate by using a normal-temperature PECVD device, a growth rate is 0.6 nm / s, and a growth time is 167 s, so that the gate dielectric layer is wrapped outside the metal field plate to form the floating field plate; The step of evaporating a gate in the second gate dielectric groove includes: evaporating 300 nm Cu to form the gate in the second gate dielectric groove by using an electron beam thermal evaporator, an evaporation rate is 1 A / s, an evaporation time is 3000 s, and the vertical organic semiconductor layer between the gate and the drain is formed as a drift region; The step of evaporating a ring-shaped source on the top of the organic semiconductor layer at the outer periphery of the ring-shaped gate dielectric layer includes: evaporating 40 nm Au to form the source on the top surface of the organic semiconductor layer at the outer periphery of the gate dielectric layer by using an electron beam thermal evaporator, an evaporation rate is 0.3 A / s, an evaporation time is 1333 s, and the source metal is ring-shaped and coaxial with the drain metal.

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