Driving circuit and driving method therefor, and display panel, display module and electronic device

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a driving circuit and a driving method therefor, and a display panel, a display module and an electronic device. The driving circuit comprises first shift registers and third shift registers, which are under partition control, and a second shift register, which is added at a partition position. A signal outputted by the second shift register only serves as a starting signal of a first-stage third shift register, and is not outputted as a scan signal. Even if the signal outputted by the second shift register is different from a signal outputted by a last-stage first shift register, the display is not affected. After a second gate starting signal is shaped and shifted by the second shift register and the first-stage third shift register, a signal outputted by the first-stage third shift register is restored to normal. In this way, when an electronic device having a partition display function performs full-screen display, the brightness difference between display rows at a partition position is significantly reduced, thereby ameliorating the problem of bright lines or dark lines appearing in a display picture.

Description

Driving circuit and driving method thereof, display panel, display module and electronic device

[0001] The present application claims priority from the Chinese patent application No. 202410727049.0 filed on June 5, 2024, and entitled "Driving circuit and driving method thereof, display panel, display module and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, in particular to a driving circuit and driving method thereof, a display panel, a display module and an electronic device. BACKGROUND

[0003] With the diversification of the form and use scene of electronic devices, the size of display panels is gradually expanding. The larger the display panel is, the more the display power consumption increases, which affects the overall endurance of the electronic device. Therefore, the demand for low power consumption of the display panel has become a new design improvement point in the display field.

[0004] At present, the technical personnel in the field proposes that the display panel has the function of partition display, and reduces the display panel by partition refreshing. However, the partition display will cause display abnormality at the partition position, which affects the display effect. SUMMARY

[0005] The embodiments of the present application provide a driving circuit and driving method thereof, a display panel, a display module and an electronic device, which are used to improve the problem of display abnormality at the partition position.

[0006] In order to achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a driving circuit, which can be a gate driver on array (GOA) or an emission circuit on array (EOA). The driving circuit includes a plurality of cascaded first shift registers, a second shift register, and a plurality of cascaded third shift registers. An input terminal of a first stage of the first shift registers is configured to receive a first gate start signal, and an input terminal of an Nth stage of the first shift registers is coupled to an output terminal of an (N-1)th stage of the first shift registers. An output terminal of each stage of the first shift registers is further configured to output a scan signal. N is an integer greater than 1. The second shift register and the plurality of cascaded third shift registers are provided. An input terminal of the second shift register is configured to receive a second gate start signal. An input terminal of a first stage of the third shift registers is coupled to an output terminal of the second shift register, and an input terminal of an Mth stage of the third shift registers is coupled to an output terminal of an (M-1)th stage of the third shift registers. An output terminal of each stage of the third shift registers is further configured to output a scan signal. M is an integer greater than 1.

[0008] The driving circuit provided by the present application increases a second shift register as a redundant shift register at a partition position of the driving circuit. The signal output by the output terminal of the second shift register is only transmitted to the input terminal of the first stage of the third shift registers in the next row, and the signal output by the output terminal of the second shift register is not output as a scan signal. Although the signal output by the output terminal of the second shift register is still different from the signal output by the output terminal of the last stage of the first shift registers, the signal output by the output terminal of the second shift register does not control the display of the effective display area. Therefore, the signal output by the output terminal of the second shift register does not affect the display of the effective display area. After the second gate start signal is shaped and shifted by the second shift register and the first stage of the third shift registers, the signal output by the output terminal of the first stage of the third shift registers returns to normal. The signal output by the output terminal of the first stage of the third shift registers is the same as the signal output by the output terminal of the last stage of the first shift registers, and the display brightness of the display row controlled by the first stage of the third shift registers is the same as the display brightness of the display row controlled by other shift registers. Therefore, the brightness difference between the display rows at the partition position of the electronic device with the partition display function is significantly reduced when the electronic device displays in full screen, and the problem of bright lines or dark lines appearing in the display image is improved.

[0009] In a possible implementation, the driving circuit further includes a fourth shift register and a plurality of cascaded fifth shift registers; an input terminal of the fourth shift register is configured to receive the third gate start signal; an input terminal of a first fifth shift register is coupled with an output terminal of the fourth shift register, and an input terminal of a Pth fifth shift register is coupled with an output terminal of a (P-1)th fifth shift register; an output terminal of each fifth shift register is further configured to output a scanning signal; and P is an integer greater than 1. In this structure, the display of the display panel can be divided into three regions, and the display of the three regions can be independently controlled.

[0010] In a possible implementation, the second shift register has the same structure as the third shift register. In this way, the design of the driving circuit can be simplified.

[0011] In a possible implementation, the first shift register is further coupled with a power voltage terminal, and the second shift register and the third shift register are also coupled with the power voltage terminal. In this way, the design of the driving circuit can be simplified.

[0012] In a possible implementation, the first shift register is further coupled with a clock signal terminal, and the second shift register and the third shift register are also coupled with the clock signal terminal. In this way, the design of the driving circuit can be simplified.

[0013] In a possible implementation, the first gate start signal is an on signal, and the second gate start signal is an off signal. In this way, one region of the display panel can display a picture, and one region of the display panel can not display a picture.

[0014] In a possible implementation, the first gate start signal is an off signal, and the second gate start signal is an on signal. In this way, one region of the display panel can display a picture, and one region of the display panel can not display a picture.

[0015] In a possible implementation, the first gate start signal and the second gate start signal are both on signals. In this way, the display panel can display a picture in full screen.

[0016] In a possible implementation, the first gate start signal and the second gate start signal are both off signals. In this way, the display panel can not display a picture in full screen.

[0017] According to a second aspect of the embodiment of the present application, a display panel is provided, which includes a driving circuit and a plurality of pixel circuits arranged in an array; the driving circuit includes the driving circuit according to any one of the first aspect; an output terminal of a last stage of the first shift register in the driving circuit is coupled with an (X-1)th row of pixel circuits, and an output terminal of a first stage of the third shift register is coupled with an Xth row of pixel circuits; and X is an integer greater than 1.

[0018] The display panel provided in the second aspect of the embodiments has the same advantages as the driving circuit provided in the first aspect, which will not be repeated here.

[0019] In a possible implementation, the output terminal of the fifth shift register in the first stage of the driving circuit is coupled with the pixel circuit in the Yth row, Y being an integer greater than X. Such a display panel can realize three-zone display.

[0020] In a possible implementation, the output terminal of the first shift register in the last stage is further coupled with the pixel circuit in the X-2th row, and the output terminal of the third shift register in the first stage is further coupled with the pixel circuit in the X+1th row; X being an integer greater than 2. In such a display panel, a shift register in one stage can control the driving of multiple rows of pixel circuits, meeting different use requirements.

[0021] In a possible implementation, the output terminal of the fifth shift register in the first stage is further coupled with the pixel circuit in the Y+1th row, Y being an integer greater than X+1. In such a display panel, a shift register in one stage can control the driving of multiple rows of pixel circuits, meeting different use requirements.

[0022] In a possible implementation, the display panel includes multiple driving circuits. The second shift register is arranged in each of the multiple driving circuits, which can further optimize the display effect of the display panel.

[0023] In the third aspect of the embodiments, a display module is provided. The display module includes a display panel and a display driver. The display panel includes the display panel in the second aspect. The display driver is configured to provide the first gate start signal and the second gate start signal for the driving circuit in the display panel.

[0024] In a possible implementation, the multiple driving circuits include a first driving circuit and a second driving circuit located at different sides of the display panel. The display driver includes a first sub-display driver and a second sub-display driver. The first sub-display driver is configured to provide the first gate start signal and the second gate start signal for the first driving circuit. The second sub-display driver is configured to provide the first gate start signal and the second gate start signal for the second driving circuit. The multiple driving circuits are respectively controlled by the multiple display drivers, which can solve the problem of insufficient ports of the display driver.

[0025] In the fourth aspect of the embodiments, an electronic device is provided. The electronic device includes a display module and a driving controller. The driving controller is coupled with the display module. The display module includes the display module in the third aspect.

[0026] In a fifth aspect, the embodiment of the present application provides a driving method of the driving circuit, the driving circuit comprising a plurality of cascaded first shift registers, a second shift register and a plurality of cascaded third shift registers. The driving method comprises: a first stage of the first shift registers receiving a first gate start signal, an Nth stage of the first shift registers receiving a signal output by an (N-1)th stage of the first shift registers; each stage of the first shift registers outputting a scanning signal; N is an integer greater than 1; the second shift register receiving a second gate start signal; a first stage of the third shift registers receiving a signal output by the second shift register, an Mth stage of the third shift registers receiving a signal output by an (M-1)th stage of the third shift registers; each stage of the third shift registers outputting a scanning signal; and M is an integer greater than 1.

[0027] The driving method of the driving circuit provided in the fifth aspect has the same beneficial effects as the driving circuit provided in the first aspect, which will not be repeated here.

[0028] In a possible implementation, the first gate start signal is an on signal, and the second gate start signal is an off signal. In this way, one area of the display panel can display a picture, and one area of the display panel can not display a picture.

[0029] In a possible implementation, the first gate start signal is an off signal, and the second gate start signal is an on signal. In this way, one area of the display panel can display a picture, and one area of the display panel can not display a picture.

[0030] In a possible implementation, the first gate start signal and the second gate start signal are both on signals. In this way, the display panel can display a picture in full screen.

[0031] In a possible implementation, the first gate start signal and the second gate start signal are both off signals. In this way, the display panel can not display a picture.

[0032] In a possible implementation, the driving circuit further comprises a fourth shift register and a plurality of cascaded fifth shift registers. The driving method further comprises: the fourth shift register receiving a third gate start signal; a first stage of the fifth shift registers receiving a signal output by the fourth shift register, a Pth stage of the fifth shift registers receiving a signal output by a (P-1)th stage of the fifth shift registers; each stage of the fifth shift registers outputting a scanning signal; and P is an integer greater than 1. In the case where the display panel is divided into a plurality of areas, the plurality of areas can be independently driven. BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1 is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0034] FIG. 2A is a topological structure schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0035] FIG. 2B is an architecture diagram of a driving circuit according to an embodiment of the present application;

[0036] FIG. 3A is a structural diagram of a display panel according to an embodiment of the present application;

[0037] FIG. 3B is a structural diagram of a display panel according to an embodiment of the present application;

[0038] FIG. 3C is a driving timing diagram of an EOA according to an embodiment of the present application;

[0039] FIG. 3D is a display effect diagram of a display panel according to an embodiment of the present application;

[0040] FIG. 4 is an architecture diagram of a driving circuit according to an embodiment of the present application;

[0041] FIG. 5 is a driving timing diagram of a driving circuit according to an embodiment of the present application;

[0042] FIG. 6 is an architecture diagram of a driving circuit according to an embodiment of the present application;

[0043] FIGS. 7A-7D are diagrams of a display screen and a driving circuit timing according to an embodiment of the present application;

[0044] FIGS. 8A-9C are diagrams of a display panel according to an embodiment of the present application;

[0045] FIG. 10A is a structural diagram of a display panel according to an embodiment of the present application;

[0046] FIG. 10B is a structural diagram of a display panel according to an embodiment of the present application;

[0047] FIG. 11 is a structural diagram of a display panel according to an embodiment of the present application;

[0048] FIG. 12 is a structural diagram of a display panel according to an embodiment of the present application;

[0049] FIG. 13 is a structural diagram of a display module according to an embodiment of the present application;

[0050] FIG. 14 is a structural diagram of a display module according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0052] Hereinafter, the terms "second", "first", and the like are used only for the convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "second", "first", and the like can be explicitly or implicitly included one or more of the features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0053] In addition, in the embodiments of the present application, the orientation terms such as "upper", "lower", "left", "right" and the like can include but not limited to the orientation defined by the relative placement of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the placement of the components in the drawings.

[0054] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate medium. In addition, the term "coupling" can be direct electrical connection, or indirect electrical connection through intermediate medium. The term "contact" can be direct contact, or indirect contact through intermediate medium.

[0055] In the embodiments of the present application, "and / or" describes the association relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, wherein A and B can be singular or plural. The character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0056] The embodiments of the present application provide an electronic device, which can be, for example, a folding electronic device. The electronic device can be, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial electronic product. The consumer electronic product can be, for example, a mobile phone, a pad, a notebook computer, an electronic reader, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, a drone, etc. The home electronic product can be, for example, a smart door lock, a television, a refrigerator, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), etc. The vehicle-mounted electronic product can be, for example, a vehicle-mounted navigator, a vehicle-mounted DVD, etc. The financial electronic product can be, for example, an ATM machine, a self-service electronic device, etc.

[0057] The embodiments of the present application do not make special limitation to the specific form of the electronic device, and the following embodiments are exemplarily described by taking a mobile phone as an example.

[0058] FIG. 1 is a structural schematic diagram of an electronic device according to an embodiment of the present application.

[0059] As shown in FIG. 1, the electronic device 1 includes a display module and a driving controller 30. In FIG. 1, a terminal 1 is exemplarily taken as a straight-screen mobile phone, and the present application only exemplifies one kind.

[0060] The driving controller 30 is coupled with the display module, and the driving controller 30 receives an image signal RGB and a control signal CTRL. The driving controller 30 outputs an image data signal DATA matching the interface specification of the display module according to the image signal RGB. The driving controller 30 also outputs a data control signal DCS. The driving controller 30, for example, includes a system on chip (SOC).

[0061] The display module, for example, includes a display panel 10 and a display driver 20. The display driver 20, for example, is coupled with the driving controller 30, receives the signal output by the driving controller 30, and provides a display signal for the display panel 10.

[0062] For example, the display driver 20 receives the data control signal DCS and the image data signal DATA from the driving controller 30. The display driver 20 converts the image data signal DATA into a data signal, and outputs the data signal to a plurality of data signal lines DL1-DLm. The data signal is an analog voltage corresponding to the gray level value of the image data signal DATA. The display driver 20 is also used to output a scanning control signal SCS (such as a clock signal CLK, a gate start signal STV, a reset signal RST, etc.) required for display to the display panel 10. The display driver 20, for example, includes a display driver integrated circuit (DDIC).

[0063] In a possible embodiment, the display panel 10 is a liquid crystal display (LCD). Based on this, the electronic device 1 further includes a back light unit (BLU) located at the back of the liquid crystal display panel. The back light unit can provide a light source for the liquid crystal display panel, so that each sub pixel in the liquid crystal display panel can emit light to realize image display.

[0064] In another possible embodiment, the display panel 10 is a self-luminous display module such as an organic light emitting diode (OLED) display module, an active-matrix organic light-emitting diode (AMOLED) display module, a mini organic light-emitting diode (Mini-OLED) display module, a micro light-emitting diode (Micro-LED) display module, a micro organic light-emitting diode (Micro-OLED) display module, a quantum dot light emitting diodes (QLED) display module, or the like. In this case, the display panel 10 can be a rigid display panel, or the display panel 10 can be a flexible display panel.

[0065] For any of the display panels 10 described above, the display panel 10 includes an active area (AA) and a non-display area (BB) located at a periphery of the active area AA. The active area AA is configured to display an image, and includes a plurality of sub-pixels (SPs). Each sub-pixel includes a pixel circuit 11 configured to receive a data signal provided by a display driver 20.

[0066] In this application, the pixel circuits 11 are described by way of example in a matrix form. Pixel circuits 11 arranged in a row along a horizontal direction X are referred to as pixel circuits 11 in the same row, and pixel circuits 11 arranged in a row along a vertical direction Y are referred to as pixel circuits 11 in the same column.

[0067] In some embodiments, the pixel circuit 11 generally includes a driving circuit including a plurality of transistors and a light emitting unit. The driving circuit is configured to generate a driving current to drive the light emitting unit to emit light, thereby realizing light emission of the pixel circuit 11.

[0068] In some embodiments, the electronic device 1 further includes a middle frame. The display panel 10 is disposed on the middle frame and is carried by the middle frame.

[0069] With the diversification of the form and use scenarios of the electronic device 1, the size of the display panel 10 is gradually expanding, and the larger the display panel 10 means that the display power consumption is relatively increased, which affects the overall endurance of the electronic device 1. Therefore, the demand for low-power display panel 10 has become a new design improvement point in the display field. For example, using the "picture-in-picture" function on a mobile phone product, a video is suspended on the upper position of the display panel 10, and the lower position is static reading. Or, for example, using "parallel horizon" on a tablet product, during application use, the left part is mostly static, and the right part dynamically changes with browsing sliding.

[0070] In order to make the same display panel 10 simultaneously support high refresh rate (such as 120Hz) and low refresh rate (such as 1Hz) functions, and smooth switching between high refresh rate and low refresh rate on any row of the display panel 10, the high mobility of low temperature poly-silicon thin-film transistor (LTPS TFT) and the low leakage characteristics of indium gallium zinc oxide thin-film transistor (IGZO TFT) can be comprehensively utilized in the pixel circuit of the display panel 10, and relevant circuit design is performed. To achieve both high refresh rate smoothness and low refresh rate power saving. The combination of LTPS TFT and IGZO TFT (or referred to as low temperature poly crystalline oxide (LTPO) technology) is used as the driving circuit of the pixel circuit 11, which can simultaneously realize high refresh rate, low refresh rate and seamless switching between different refresh rates, meet the dynamic frame change demand, and has wide application prospect in OLED display panel.

[0071] FIG. 2A is a topological structure schematic diagram of a pixel circuit provided by an embodiment of the present application.

[0072] In some embodiments, as shown in FIG. 2A, the pixel circuit 11 includes a first node initialization circuit 111, a write and threshold compensation circuit 112, a light-emitting control circuit 113, and a light-emitting unit 114. The pixel circuit 11 shown in FIG. 2A is only an example and is not limited in any way.

[0073] In the embodiments of the present application, the first power voltage terminal ELVDD is taken as a high-level power voltage terminal, and the second power voltage terminal ELVSS is taken as a low-level power voltage terminal, but this is not limited.

[0074] In some embodiments, referring to FIG. 2A, the first node initialization circuit 111 includes a fourth transistor M4 and a third transistor M3, the write and threshold compensation circuit 112 includes a second transistor M2, a first transistor M1, the third transistor M3, a storage capacitor Cst, and the light emitting control circuit 113 includes a fifth transistor M5 and a sixth transistor M6. The first transistor M1 is a driving transistor, and the rest of the transistors are switching transistors. The third transistor M3 is shared by the first node initialization circuit 111 and the write and threshold compensation circuit 112. The light emitting unit 114 is, for example, an OLED.

[0075] In the following description, the control electrode of a transistor can be, for example, the gate electrode of the transistor, and the first electrode and the second electrode of the transistor are the source electrode and the drain electrode of the transistor, respectively. Here, it is noted that the following description will not be explained.

[0076] The control electrode of the fourth transistor M4 is coupled to an initialization scan signal terminal SC, the first electrode of the fourth transistor M4 is coupled to an initialization voltage terminal Vinit, and the second electrode of the fourth transistor M4 is coupled to a fourth node N4.

[0077] The control electrode of the third transistor M3 is coupled to a compensation scan signal terminal SB, the first electrode of the third transistor M3 is coupled to the fourth node N4, and the second electrode of the third transistor M3 is coupled to a node N.

[0078] The control electrode of the second transistor M2 is coupled to a write scan signal terminal SX, the first electrode of the second transistor M2 is coupled to a data voltage terminal Vdata, and the second electrode of the second transistor M2 is coupled to a third node N3.

[0079] The control electrode of the first transistor M1 is coupled to the node N, the first electrode of the first transistor M1 is coupled to the third node N3, and the second electrode of the first transistor M1 is coupled to a second node N2. The second node N2 is also coupled to the fourth node N4.

[0080] One end of the storage capacitor Cst is coupled to the node N, and the other end of the storage capacitor Cst is coupled to a first power voltage terminal ELVDD.

[0081] The control electrode of the fifth transistor M5 is coupled to a light emitting control signal terminal EM, the first electrode of the fifth transistor M5 is coupled to the first power voltage terminal ELVDD, and the second electrode of the fifth transistor M5 is coupled to the third node N3.

[0082] The control electrode of the sixth transistor M6 is coupled to the light emitting control signal terminal EM, the first electrode of the sixth transistor M6 is coupled to the second node N2, and the second electrode of the sixth transistor M6 is coupled to the anode of the light emitting unit 114. The cathode of the light emitting unit 114 is coupled to a second power voltage terminal ELVSS.

[0083] For example, in the pixel circuit 11, the third transistor M3 and the fourth transistor M4 are IGZO TFTs, and are N-type transistors, which are turned on under the control of a high-level signal. The third transistor M3 and the fourth transistor M4 can also be other types of transistors, which are not limited in the embodiments of the present application. The first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are LTPS TFTs, and are P-type transistors, which are turned on under the control of a low-level signal.

[0084] The initialization scan signal terminal SC of the pixel circuit 11 is coupled with the initialization scan signal line SCL, the compensation scan signal terminal SB of the pixel circuit 11 is coupled with the compensation scan signal line SBL, the write scan signal terminal SX of the pixel circuit 11 is coupled with the write scan signal line SXL, the light-emitting control signal terminal EM of the pixel circuit 11 is coupled with the light-emitting control scan signal line EML, and the data voltage terminal Vdata of the pixel circuit 11 is coupled with the data signal line DL. The voltages of the initialization voltage terminal Vinit, the first power voltage terminal ELVDD, and the second power voltage terminal ELVSS can be provided by a voltage generator in the electronic device.

[0085] For example, the compensation scan signal line SBL in the scan signal line is taken as an example, and in FIG. 1, one row of pixel circuits 11 coupled with the same compensation scan signal line SBL is taken as an example for illustration, and the same row of pixel circuits 11 can also be coupled with multiple compensation scan signal lines SBL. For example, the pixel circuits 11 in the left half of the row are coupled with one compensation scan signal line SBL, and the pixel circuits 11 in the right half of the row are coupled with another compensation scan signal line SBL. Similarly, in FIG. 1, the same column of pixel circuits 11 coupled with the same data signal line DL is taken as an example for illustration, and the same column of pixel circuits 11 can also be coupled with multiple data signal lines DL. For example, the pixel circuits 11 in the upper half of the column are coupled with one data signal line DL, and the pixel circuits 11 in the lower half of the column are coupled with another data signal line DL.

[0086] The driving circuit 12 receives a scan control signal SCS from the driving controller 30. The driving circuit 12 can output scan signals to scan signal lines in response to the scan control signal SCS. The scan signal lines include, for example, initialization scan signal lines SCL1-SCLn, compensation scan signal lines SBL1-SBLn, write scan signal lines SXL1-SXLn, and light-emitting control scan signal lines EML1-EMLn. The driving circuit 12 can output initialization scan signals to the initialization scan signal lines SCL1-SCLn, output compensation scan signals to the compensation scan signal lines SBL1-SBLn, output write scan signals to the write scan signal lines SXL1-SXLn, and output light-emitting control signals to the light-emitting control scan signal lines EML1-EMLn in response to the scan control signal SCS.

[0087] For example, the driving circuit 12 can be a gate driver on array (GOA) and / or an emission circuit on array (EOA). The EOA is configured to output an emission control signal to an emission control scan signal line EML1-EMLn, and the GOA is configured to output an initialization scan signal to an initialization scan signal line SCL1-SCLn, output a compensation scan signal to a compensation scan signal line SBL1-SBLn, or output a write scan signal to a write scan signal line SXL1-SXLn.

[0088] FIG. 2B is an architecture diagram of a driving circuit provided in an embodiment of the present application.

[0089] Regarding the structure of the GOA or the EOA, in some embodiments, as shown in FIG. 2B, the driving circuit 12 includes at least two cascaded stages of shift registers RS1-RSn.

[0090] The signal input end STVI of the first stage of shift registers RS1 is configured to receive a gate start vertical (STV) signal. Except for the first stage of shift registers RS1, the signal input end STVI of each stage of shift registers RS(m) is coupled to the output end GO of the previous stage of shift registers RS(m-1). Except for the last stage of shift registers, the reset signal end RST of each stage of shift registers RS(m) is coupled to the output end GO of the next stage of shift registers RS(m+1). The reset signal end RST of the last stage of shift registers RSn receives the STV signal.

[0091] When the STV signal is an enable signal, the first stage of shift registers RS1 of the driving circuit 12 starts to work, and then the multiple stages of shift registers start to work in sequence.

[0092] For example, the output end GO of each stage of shift registers RS(m) can be coupled to one compensation scan signal line SBL, or the output end GO of each stage of shift registers RS(m) can be coupled to multiple (for example, 4, 5, 6, 8, 10, etc.) compensation scan signal lines SBL, which is not limited in the embodiments of the present application.

[0093] With the diversification of the form and use scenarios of the electronic device 1, the size of the display panel 10 is gradually expanding, and the larger the display panel 10 means the relatively increased display power consumption, which affects the overall endurance of the electronic device 1. Therefore, the demand for low power consumption of the display panel 10 has become a new design improvement point in the display field.

[0094] Currently, those skilled in the art propose to enable the display panel to have the function of partition display, and to reduce the power consumption of the electronic device 1 by partition refreshing of the display panel. Partition display can save the power consumption of the electronic device 1 in scenarios such as outer folding screen, multi-folding screen or other partition display application scenarios.

[0095] In some embodiments, in order to realize partition display, the EOA in the display panel 10 is divided into two or more blocks, different STV signals are used to drive different EOA to work, and then the display of different areas of the display panel 10 is controlled.

[0096] FIG. 3A is a structural schematic diagram of a display panel provided by an embodiment of the present application.

[0097] As shown in FIG. 3A, the active display area AA of the display panel 10 includes a first partition and a second partition, and the EOA in the display panel 10 includes a first light-emitting driving sub-circuit EOA1 and a second light-emitting driving sub-circuit EOA2. The first light-emitting driving sub-circuit EOA1 includes a plurality of cascaded first shift registers RS1, and the first stage first shift register RS1 receives a first gate start signal STV1. The second light-emitting driving sub-circuit EOA2 includes a plurality of cascaded second shift registers RS2, and the first stage second shift register RS2 receives a second gate start signal STV2. That is, the first light-emitting driving sub-circuit EOA1 is controlled by the first gate start signal STV1 and is used to provide a scanning signal to the pixel circuit 11 in the first partition. The second light-emitting driving sub-circuit EOA2 is controlled by the second gate start signal STV2 and is used to provide a scanning signal to the pixel circuit 11 in the second partition. The first light-emitting driving sub-circuit EOA1 and the second light-emitting driving sub-circuit EOA2 can be independently driven.

[0098] The first light-emitting driving sub-circuit EOA1 and the second light-emitting driving sub-circuit EOA2 independently output signals, and the EOA can drive the first partition and the second partition in the active display area AA separately. The first light-emitting driving sub-circuit EOA1 can be used to drive the first partition to display an image, and the second light-emitting driving sub-circuit EOA2 can be used to drive the second partition to not display an image. The first light-emitting driving sub-circuit EOA1 can also be used to drive the first partition to not display an image, and the second light-emitting driving sub-circuit EOA2 can be used to drive the second partition to display an image. The first light-emitting driving sub-circuit EOA1 can also be used to drive the first partition to not display an image, and the second light-emitting driving sub-circuit EOA2 can be used to drive the second partition to not display an image. The first light-emitting driving sub-circuit EOA1 can also be used to drive the first partition to display an image, and the second light-emitting driving sub-circuit EOA2 can be used to drive the second partition to display an image. A plurality of display scenarios can be switched at will.

[0099] By making the EOA in the display panel 10 have the function of sub-area driving, the power consumption of the electronic device 1 can be saved in the outer folding screen, the multi-folding screen or other scenarios of realizing sub-area display application. However, with the upgrading of the current pixel circuit 11 architecture, the number of GOA signals controlling the operation of the pixel circuit 11 increases, and the number of GOAs is significantly more than the number of EOAs. The above scheme can only save the power consumption of the EOA, and cannot save the power consumption of the GOA, so the power consumption saving degree of the display panel 10 is very limited.

[0100] FIG. 3B is a structural schematic diagram of a display panel provided by an embodiment of the present application.

[0101] In some embodiments, as shown in FIG. 3B, the GOA in the display panel 10 includes a first gate driving sub-circuit GOA1 and a second gate driving sub-circuit GOA2. The first gate driving sub-circuit GOA1 includes a plurality of cascaded third shift registers RS3, and the input end of the first stage third shift register RS3 is used to receive a third gate start signal STV3. The second gate driving sub-circuit GOA2 includes a plurality of cascaded fourth shift registers RS4, and the input end of the first stage fourth shift register RS4 is used to receive a fourth gate start signal STV4. The first gate driving sub-circuit GOA1 is used to provide a scanning signal to the pixel circuit 11 of the first sub-area, and the second gate driving sub-circuit GOA2 is used to provide a scanning signal to the pixel circuit 11 of the second sub-area. The first gate driving sub-circuit GOA1 and the second gate driving sub-circuit GOA2 can be independently driven.

[0102] FIG. 3C is a driving timing diagram of an EOA provided by an embodiment of the present application.

[0103] Taking the driving of the EOA as an example, as shown in FIG. 3C, the first shift register RS1 is located in the first row to the X-1 row, and the other rows from the X row are the second shift register RS2. The first shift register RS1 in the X-1 row is the first sub-area for all rows above, which is controlled by the first gate start signal STV1 and is level-shifted by the first shift register RS1. While the second shift register RS2 in the X row is the second sub-area for all rows below, which is controlled by the second gate start signal STV2 and is level-shifted by the second shift register RS2. Each stage of the first shift register RS1 and each stage of the second shift register RS2 normally receives signals of the first clock signal end CLK1 and the second clock signal end CLK2.

[0104] The signal at the output terminal GO of the first shift register RS1 in the first sub-region of the X-2th row is inputted to the input terminal STVI of the first shift register RS1 in the X-1th row. The signal at the input terminal STVI of the second shift register RS2 in the Xth row in the second sub-region is provided by the second gate start signal STV2, and the signal at the input terminal STVI of the second shift register RS2 in the X+1th row is provided by the output terminal GO of the second shift register RS2 in the Xth row.

[0105] Therefore, the signal at the output terminal GO of the second shift register RS2 in the Xth row is different from the signal at the output terminal GO of the first shift register RS1 in the X-1th row.

[0106] The signal at the input terminal STVI of the second shift register RS2 in the X+1th row is provided by the output terminal GO of the second shift register RS2 in the Xth row, and the signal at the output terminal GO of the second shift register RS2 in the X+1th row is restored to normal through the two-stage second shift register RS2.

[0107] Similarly, in the driving process of the GOA, the signal at the output terminal GO of the fourth shift register RS4 in the Xth row is different from the signal at the output terminal GO of the third shift register RS3 in the X-1th row due to the difference between the fourth gate start signal STV4 and the signal provided by the output terminal GO of the third shift register RS3 in the X-1th row.

[0108] FIG. 3D is a schematic diagram of a display effect of a display panel according to an embodiment of the present application.

[0109] Therefore, as shown in FIGS. 3A and 3D, in the full-screen display, the pixel rows controlled by the second shift register RS2 receiving the second gate start signal STV2 and the fourth shift register RS4 receiving the fourth gate start signal STV4 present a dark line or a bright line in the partial brightness gray scale scene. If each second shift register RS2 and fourth shift register RS4 controls one row of pixel circuits 11, one dark line or bright line appears. If each second shift register RS2 and fourth shift register RS4 controls multiple rows of pixel circuits 11, multiple dark lines or bright lines appear.

[0110] That is, the display of the first sub-region of the display panel 10 is controlled to be started by the first gate start signal STV1 and the third gate start signal STV3, and the display of the second sub-region is controlled to be started by the second gate start signal STV2 and the fourth gate start signal STV4, instead of the stage transmission signal. The gate start signals used in the adjacent rows in the boundary region are different, one of which is the signal stage transmission as the input signal STVI from the output of the first shift register RS1 in the previous stage, and the other is from the second gate start signal STV2 and the fourth gate start signal STV4. Due to the difference between the second gate start signal STV2 and the fourth gate start signal STV4 and the stage transmission signal, the waveforms of the scanning signals output by the adjacent rows in the boundary region are different, and the output differences include but are not limited to high and low levels, rise and fall times, signal steps, etc., thereby causing the differences between the brightness of the display rows, resulting in display abnormalities in the effective display area AA, which is manifested as dark lines or bright lines.

[0111] Therefore, the display panel 10 shown in FIG. 3D has the sub-region display function, but there is a problem that the brightness of the display rows at the sub-region position is different when full-screen display.

[0112] Based on this, the embodiment of the present application provides a new driving circuit for improving the problem of the difference in the brightness of the display rows.

[0113] FIG. 4 is an architecture diagram of a driving circuit provided by an embodiment of the present application.

[0114] The embodiment of the present application provides a driving circuit 12, which can be GOA or EOA. As shown in FIG. 4, the driving circuit 12 is EOA, and the driving circuit 12 includes a first light-emitting driving sub-circuit EOA1 and a second light-emitting driving sub-circuit EOA2. When the driving circuit 12 is GOA, the driving circuit 12 includes a first gate driving sub-circuit GOA1 and a second array substrate gate driving circuit GOA2.

[0115] The driving circuit 12 includes a plurality of cascaded first shift registers RS1. The input end STVI of the first stage first shift register RS1 is coupled to receive the first gate start signal STV1, and the input end STVI of the Nth stage first shift register RS1 is coupled to the output end STVI of the (N-1)th stage first shift register RS1.

[0116] The driving circuit 12 further includes a second shift register RS2 and a plurality of third shift registers RS3 connected in cascade. An input terminal STVI of the second shift register RS2 is configured to receive a second gate start signal STV2, an input terminal STVI of a first stage of the third shift registers RS3 is coupled to an output terminal GO of the second shift register RS2, and an input terminal GO of an Mth stage of the third shift registers RS3 is coupled to an output terminal GO of an (M-1) th stage of the third shift registers RS3.

[0117] wherein N and M are both integers greater than 1. That is, starting from a second stage of the first shift registers RS1, an input terminal STVI of each stage of the first shift registers RS1 is configured to receive a signal output by an output terminal GO of a previous stage of the first shift registers RS1. Starting from a second stage of the third shift registers RS3, an input terminal STVI of each stage of the third shift registers RS3 is configured to receive a signal output by an output terminal GO of a previous stage of the third shift registers RS3.

[0118] On this basis, in the embodiment of the present application, an output terminal GO of each stage of the first shift registers RS1 is configured to output a scanning signal to the active display area AA, and an output terminal GO of each stage of the third shift registers RS3 is configured to output a scanning signal to the active display area AA.

[0119] However, the output terminal GO of the second shift register RS2 does not output a scanning signal, but only outputs a cascade signal to an input terminal STVI of the third shift register RS3 connected in cascade therewith. The second shift register RS2 can thus be understood as a dummy shift register, which has no effect on the display effect of the active display area AA.

[0120] In the embodiment of the present application, the driving circuit 12 can include one stage of the second shift register RS2, or a plurality of stages of the second shift register RS2 connected in cascade, and the embodiment of the present application does not limit this. In the case where the driving circuit 12 includes a plurality of stages of the second shift register RS2, an output terminal GO of a last stage of the second shift register RS2 is coupled to an input terminal STVI of a first stage of the third shift registers RS3.

[0121] In addition, the type of the driving circuit 12 and the number of the first shift registers RS1 and the third shift registers RS3 depend on the number and structure of the pixel circuits 11 in the active display area AA, and the embodiment of the present application does not limit this in detail.

[0122] FIG. 5 is a driving timing diagram of a driving circuit according to an embodiment of the present application.

[0123] The first shift register RS1 of the line X-1 is the first partition, controlled by the first gate start signal STV1, and the signal is transferred by the first shift register RS1. The second shift register RS2 of the line X is the second partition, and the second shift register RS2 does not output the scanning signal, so the second shift register RS2 does not occupy the line number, and the line X is the third shift register RS3. The second partition is controlled by the second gate start signal STV2, and the signal is transferred by the second shift register RS2 to the third shift register RS3.

[0124] The signal output by the first shift register RS1 of the line X-2 in the first partition as the signal of the input end STVI of the first shift register RS1 of the line X-1. In the second partition, one level of the second shift register RS2 is added as a redundant shift register, and the signal of the input end STVI of the second shift register RS2 is the second gate start signal STV2, and the signal of the input end STVI of the third shift register RS3 of the line X is provided by the output end GO of the second shift register RS2.

[0125] The first gate start signal STV1 and the second gate start signal STV2 are gate start signals provided by different ports of the display driver 20.

[0126] For example, in the same frame, the first gate start signal STV1 is an on signal, and the second gate start signal STV2 is an off signal.

[0127] Alternatively, for example, in the same frame, the first gate start signal STV1 is an off signal, and the second gate start signal STV2 is an on signal.

[0128] Alternatively, for example, in the same frame, the first gate start signal STV1 and the second gate start signal STV2 are both on signals.

[0129] Alternatively, for example, in the same frame, the first gate start signal STV1 and the second gate start signal STV2 are both off signals.

[0130] Although the second gate start signal STV2 is different from the output signal of the output terminal GO of the first shift register RS1 of the X-1th row, the output signal of the output terminal GO of the second shift register RS2 is different from the output signal of the output terminal GO of the first shift register RS1 of the X-1th row. However, the second shift register RS2 does not actually control the display of the effective display area AA, and the output signal of the output terminal GO of the second shift register RS2 is only used as the signal of the input terminal STVI of the third shift register RS3 of the Xth row to control the start of the third shift register RS3 of the Xth row. After the shaping and shifting of the second shift register RS2 and the third shift register RS3 of the Xth row, the output signal of the output terminal GO of the third shift register RS3 of the Xth row returns to normal, and the display brightness is the same as that of other rows, which does not affect the display of the Xth row of pixels. The final effect does not show a dark line or a bright line in the Xth row of pixels.

[0131] The driving circuit 12 provided by the embodiment of the present application adds the second shift register RS2 as a redundant shift register at the partition position of the driving circuit 12. The output signal of the output terminal GO of the second shift register RS2 is only transmitted to the input terminal STVI of the first third shift register RS3 of the next row, and the output signal of the output terminal GO of the second shift register RS2 is not output as a scanning signal. Although the output signal of the output terminal GO of the second shift register RS2 is different from the output signal of the output terminal GO of the last first shift register RS1, the output signal of the output terminal GO of the second shift register RS2 does not control the display of the effective display area AA. Therefore, the output signal of the output terminal GO of the second shift register RS2 does not affect the display of the effective display area AA. After the shaping and shifting of the second shift register RS2 and the first third shift register RS3, the output signal of the output terminal GO of the first third shift register RS3 returns to normal. The output signal of the output terminal GO of the first third shift register RS3 is the same as the output signal of the output terminal GO of the last first shift register RS1, and the display brightness of the display row controlled by the first third shift register RS3 is the same as the display brightness of the display row controlled by other shift registers. Therefore, when the electronic device 1 with the partition display function displays in full screen, the brightness difference between the display rows at the partition position is significantly reduced, and the problem of bright lines or dark lines in the display image is improved.

[0132] In some embodiments, the structure of the second shift register RS2 is the same as that of the third shift register RS3. In this way, the design of the driving circuit 12 can be simplified.

[0133] In some embodiments, the first shift register RS1 and the third shift register RS3 have the same structure. This can simplify the design of the driving circuit 12.

[0134] The embodiments of the present application do not limit the structure of the first shift register RS1, the second shift register RS2 and the third shift register RS3, and the structure of the shift register in the related art is applicable to the embodiments of the present application.

[0135] In some embodiments, the first shift register RS1 is also coupled with a high-voltage of gate driver (VGH) voltage terminal, and the second shift register RS2 and the third shift register RS3 are also coupled with the high-voltage of gate driver (VGH) voltage terminal. This can simplify the design of the driving circuit 12.

[0136] Of course, the first shift register RS1, the second shift register RS2 and the third shift register RS3 can also be coupled with different high-voltage of gate driver (VGH) voltage terminals, respectively.

[0137] In some embodiments, the first shift register RS1 is also coupled with a low-voltage of gate driver (VGL) voltage terminal, and the second shift register RS2 and the third shift register RS3 are also coupled with the low-voltage of gate driver (VGL) voltage terminal. This can simplify the design of the driving circuit 12.

[0138] Of course, the first shift register RS1, the second shift register RS2 and the third shift register RS3 can also be coupled with different low-voltage of gate driver (VGL) voltage terminals, respectively.

[0139] In some embodiments, the first shift register RS1 is also coupled with a first clock signal terminal CLK1, and the second shift register RS2 and the third shift register RS3 are also coupled with the first clock signal terminal CLK1. This can simplify the design of the driving circuit 12.

[0140] Of course, the first shift register RS1, the second shift register RS2 and the third shift register RS3 can also be coupled with different first clock signal terminals CLK1, respectively.

[0141] In some embodiments, the first shift register RS1 is also coupled with a second clock signal terminal CLK2, and the second shift register RS2 and the third shift register RS3 are also coupled with the second clock signal terminal CLK2. This can simplify the design of the driving circuit 12.

[0142] Of course, the first shift register RS1, the second shift register RS2 and the third shift register RS3 can also be coupled with different second clock signal terminals CLK2, respectively.

[0143] Fig. 6 is an architecture diagram of a driving circuit provided in an embodiment of the present application.

[0144] In some embodiments, as shown in Fig. 6, the driving circuit 12 further comprises a third light-emitting driving sub-circuit EOA3 or a third gate driving sub-circuit GOA3. The driving circuit 12 further comprises a fourth shift register RS4 and a plurality of cascaded fifth shift registers RS5.

[0145] The input end STVI of the fourth shift register RS4 is configured to receive the third gate start signal STV3, the input end STVI of the first-stage fifth shift register RS5 is coupled with the output end GO of the fourth shift register RS4, and the input end STVI of the P-th stage fifth shift register RS5 is coupled with the output end GO of the (P-1)-th stage fifth shift register RS5.

[0146] P is an integer greater than 1, that is, the input end STVI of each fifth shift register RS5 starting from the second-stage fifth shift register RS5 receives the signal output by the output end GO of the previous-stage fifth shift register RS5.

[0147] On this basis, in the embodiment of the present application, the output end GO of each fifth shift register RS5 is configured to output a scanning signal to the active display area AA to control the display of the active display area AA.

[0148] However, the output end GO of the fourth shift register RS4 does not output a scanning signal, but only outputs a cascaded signal to the input end STVI of the first-stage fifth shift register RS5 coupled therewith. Then, the fourth shift register RS4 can be understood as a dummy shift register, which has no effect on the display effect of the active display area AA.

[0149] In the first sub-area, the signal received by the input end STVI of the first-stage first shift register RS1 is the first gate start signal STV1, and the signals of the input ends STVI of the remaining-stage first shift registers RS1 are provided by the output end GO of the previous-stage first shift register RS1.

[0150] In the second sub-area, one second shift register RS2 is added as a dummy shift register, the signal of the input end STVI of the second shift register RS2 is the second gate start signal STV2, the signal of the input end STVI of the first-stage third shift register RS3 is provided by the output end GO of the second shift register RS2, and the signals of the input ends STVI of the remaining-stage third shift registers RS3 are provided by the output end GO of the previous-stage third shift register RS3.

[0151] In the third sub-region, a fourth shift register RS4 is added as a redundant shift register, the signal of the input end STVI of the fourth shift register RS4 is the third gate start signal STV3, the signal of the input end STVI of the first fifth shift register RS5 is provided by the output end GO of the fourth shift register RS4, and the signal of the input end STVI of the rest of the fifth shift register RS5 is provided by the output end GO of the fifth shift register RS5 of the previous stage.

[0152] In this structure, the display of the display panel 10 can be divided into three regions, and the display of the three regions can be independently controlled. Of course, more sub-drive circuits can be divided in the driving circuit 12 in the embodiment of the application, and the above-mentioned structures of two and three sub-regions are only a schematic and are not limited in any way.

[0153] Of course, when the display panel 10 is divided into two or more sub-regions, the pixel circuits in the adjacent two sub-regions can be controlled by one sub-drive circuit. That is, not every sub-region needs to correspond to one sub-drive circuit independently, and the adjacent two sub-regions can not be independently driven.

[0154] The embodiment of the application further provides a driving method of the driving circuit 12, and the driving method comprises the following steps:

[0155] The first shift register RS1 of the first stage receives the first gate start signal STV1, and the first shift register RS1 of the Nth stage receives the signal output by the first shift register RS1 of the (N-1)th stage. Each first shift register RS1 outputs a scanning signal, and according to different display scenes, the scanning signal output by the first shift register RS1 can be a scanning start signal or a scanning stop signal.

[0156] The second shift register RS2 receives the second gate start signal STV, the first third shift register RS3 receives the signal output by the second shift register RS2, and the Mth third shift register RS3 receives the signal output by the (M-1)th third shift register RS3. Each third shift register RS3 outputs a scanning signal, and according to different display scenes, the scanning signal output by the third shift register RS3 can be a scanning start signal or a scanning stop signal.

[0157] FIGS. 7A-7D are schematic diagrams of the correspondence between a display screen and the timing of a driving circuit according to an embodiment of the application.

[0158] For example, as shown in FIG. 7A, the pixel row display screen is controlled by the first shift register RS1, and the pixel row does not display a screen and is controlled by the third shift register RS3. The first gate start signal STV1 is a start signal, and the first shift register RS1 outputs a scanning start signal. The second gate start signal STV2 is a stop signal, and the third shift register RS3 outputs a scanning stop signal.

[0159] Alternatively, as shown in FIG. 7B, the pixel row controlled by the first shift register RS1 does not display the picture, and the pixel row controlled by the third shift register RS3 displays the picture. The first gate start signal STV1 is the off signal, and the first shift register RS1 outputs the scanning off signal. The second gate start signal STV2 is the on signal, and the third shift register RS3 outputs the scanning on signal.

[0160] Alternatively, as shown in FIG. 7C, the pixel row controlled by the first shift register RS1 displays the picture, and the pixel row controlled by the third shift register RS3 displays the picture. The first gate start signal STV1 is the on signal, and the first shift register RS1 outputs the scanning on signal. The second gate start signal STV2 is the on signal, and the third shift register RS3 outputs the scanning on signal.

[0161] Alternatively, as shown in FIG. 7D, the pixel row controlled by the first shift register RS1 does not display the picture, and the pixel row controlled by the third shift register RS3 does not display the picture. The first gate start signal STV1 is the off signal, and the first shift register RS1 outputs the scanning off signal. The second gate start signal STV2 is the off signal, and the third shift register RS3 outputs the scanning off signal.

[0162] In some embodiments, the driving circuit 12 further includes a fourth shift register RS4 and a plurality of cascaded fifth shift registers RS5. The driving method of the driving circuit 12 further includes:

[0163] The fourth shift register RS4 receives the third gate start signal STV, the first fifth shift register RS5 receives the signal output by the fourth shift register RS4, the Pth fifth shift register RS5 receives the signal output by the (P-1)th fifth shift register RS5, and each fifth shift register RS5 outputs a scanning signal.

[0164] Then, on the basis of the display pictures shown in FIGS. 7A-7D, the pixel row controlled by the fifth shift register RS5 does not display the picture, the third gate start signal STV is the off signal, and the fifth shift register RS5 outputs the scanning off signal. The pixel row controlled by the fifth shift register RS5 displays the picture, the third gate start signal STV is the on signal, and the fifth shift register RS5 outputs the scanning on signal.

[0165] FIGS. 8A-9C are schematic diagrams of a display panel according to an embodiment of the present application.

[0166] The embodiment of the present application does not limit the mode of the display panel 10 when implementing the above-mentioned partition display effect, and for example, the display panel 10 is a display panel with an outer folding function.

[0167] In the first state, the display panel 10 can realize the display effects shown in FIG. 7A, FIG. 7B and FIG. 7D. For example, as shown in FIG. 8A, the display panel 10 is an outer folding display panel, and the display panel 10 is in a folded state (or a hovering state). Alternatively, as shown in FIG. 8B, the display panel 10 is in an inner folding hovering state. Alternatively, as shown in FIG. 9A, the display panel 10 is a three-fold display panel in an "S" shape or a "G" shape, and the display panel 10 is in a half-folded state. Alternatively, as shown in FIG. 9B, the display panel 10 is a three-fold display panel in a "G" shape, and the display panel 10 is in a folded state. In these cases, the display panel 10 can realize the display effects shown in FIG. 7A, FIG. 7B and FIG. 7D.

[0168] In the second state, the display panel 10 in any structure is in an unfolded state, and the display panel 10 can realize the display effects shown in FIG. 7C and FIG. 7D.

[0169] In the third state, as shown in FIG. 9C, the display panel 10 is a three-fold display panel in an "S" shape, and the display panel 10 is in a folded state, and the display panel 10 can realize the display effects shown in FIG. 7A and FIG. 7D.

[0170] FIG. 10A and FIG. 10B are structural schematic diagrams of a display panel provided in an embodiment of the present application.

[0171] The embodiment of the present application further provides a display panel 10, as shown in FIG. 10A, the display panel 10 includes a driving circuit 12 and a plurality of pixel circuits 11 arranged in an array, and the driving circuit 12 includes any one of the above driving circuits 12.

[0172] In some embodiments, as shown in FIG. 10A, each stage of the shift register in the display panel 10 is coupled with a row of pixel circuits 11.

[0173] For example, the display panel 10 is divided into two areas, the output end GO of the last stage of the first shift register RS1 in the driving circuit 12 is coupled with the X-1th row of pixel circuits 11, and the output end GO of the first stage of the third shift register RS3 is coupled with the Xth row of pixel circuits 11. X is an integer greater than 1.

[0174] For example, a plurality of first shift registers RS1 are coupled with the 1st row to the X-1th row of pixel circuits 11, and a plurality of third shift registers RS3 are coupled with the Xth row to the last row of pixel circuits 11.

[0175] Alternatively, for example, the display panel 10 is divided into three areas, the output terminal GO of the last stage of the first shift register RS1 in the driving circuit 12 is coupled with the pixel circuit 11 of the X-1th row, the output terminal GO of the first stage of the third shift register RS3 is coupled with the pixel circuit 11 of the Xth row, the output terminal GO of the last stage of the third shift register RS3 is coupled with the pixel circuit 11 of the Y-1th row, and the output terminal GO of the first stage of the fifth shift register RS5 is coupled with the pixel circuit 11 of the Yth row. X is an integer greater than 1, and Y is an integer greater than X.

[0176] For example, a plurality of first shift registers RS1 are coupled with the pixel circuits 11 of the 1st to X-1th rows, a plurality of third shift registers RS3 are coupled with the pixel circuits 11 of the Xth to Y-1th rows, and a plurality of fifth shift registers RS5 are coupled with the pixel circuits 11 of the Yth to the last row.

[0177] In some other embodiments, as shown in FIG. 10B, each stage of the shift register is coupled with a plurality of rows of pixel circuits 11 in the display panel 10. For example, each stage of the shift register is coupled with two rows of pixel circuits 11.

[0178] Alternatively, for example, the display panel 10 is divided into three areas, the output terminal GO of the last stage of the first shift register RS1 in the driving circuit 12 is coupled with the pixel circuit 11 of the X-1th row, the output terminal GO of the first stage of the third shift register RS3 is coupled with the pixel circuit 11 of the Xth row, the output terminal GO of the last stage of the third shift register RS3 is coupled with the pixel circuit 11 of the Y-1th row, and the output terminal GO of the first stage of the fifth shift register RS5 is coupled with the pixel circuit 11 of the Yth row. X is an integer greater than 1, and Y is an integer greater than X.

[0179] Alternatively, for example, the display panel 10 is divided into three areas, the output terminal GO of the last stage of the first shift register RS1 in the driving circuit 12 is coupled with the pixel circuit 11 of the X-1th row, the output terminal GO of the first stage of the third shift register RS3 is coupled with the pixel circuit 11 of the Xth row, the output terminal GO of the last stage of the third shift register RS3 is coupled with the pixel circuit 11 of the Y-1th row, and the output terminal GO of the first stage of the fifth shift register RS5 is coupled with the pixel circuit 11 of the Yth row. X is an integer greater than 1, and Y is an integer greater than X.

[0180] In some embodiments, the display panel 10 includes a plurality of driving circuits 12.

[0181] FIGS. 11 and 12 are structural schematic diagrams of a display panel according to embodiments of the present application.

[0182] In some embodiments, as shown in FIG. 11, the display panel 10 includes a first driving circuit 121 and a second driving circuit 122. The first driving circuit 121 and the second driving circuit 122 can be used to provide a scan signal to the same kind of port of the pixel circuit 11, or the first driving circuit 121 and the second driving circuit 122 can be used to provide a scan signal to different kinds of ports of the pixel circuit 11.

[0183] For example, as shown in FIG. 11, the first driving circuit 121 and the second driving circuit 122 are located on the same side of the display panel 10.

[0184] Alternatively, for example, as shown in FIG. 12, the first driving circuit 121 and the second driving circuit 122 are located on different sides of the display panel 10. For example, the first driving circuit 121 and the second driving circuit 122 are located on opposite sides of the display panel 10.

[0185] For example, the first driving circuit 121 and the second driving circuit 122 are EOA for outputting light-emitting control signals to light-emitting control scanning signal lines EML1-EMLn, GOA for outputting initialization scanning signals to initialization scanning signal lines SCL1-SCLn, GOA for outputting compensation scanning signals to compensation scanning signal lines SBL1-SBLn, or GOA for outputting write scanning signals to write scanning signal lines SXL1-SXLn.

[0186] The number of driving circuits 12 included in the display panel 10 is related to the structure of the pixel circuit 11, and one or more of the plurality of driving circuits 12 included in the display panel 10 can be the structure of the driving circuit 12 provided in the embodiments of the present application.

[0187] The plurality of driving circuits 12 in the display panel 10 can be further optimized according to the structure of the driving circuit 12 described above. Moreover, the plurality of driving circuits 12 in the display panel 10 can all adopt the design with the partition driving function described above, and compared with only the EOA having the partition driving function, the display panel 10 provided in the embodiments of the present application can reduce power consumption.

[0188] When the display panel 10 provided in the embodiments of the present application is applied to the display module provided in the embodiments of the present application, the display driver 20 in the display module is configured to provide the first gate start signal STV1 and the second gate start signal STV2 to the driving circuit 12 to realize partition control on the display panel 10.

[0189] FIGS. 13 and 14 are structural schematic diagrams of a display module provided in the embodiments of the present application.

[0190] In some embodiments, as shown in FIG. 13, the display module includes a display driver 20, the display driver 20 is configured to provide the first gate start signal STV1 and the second gate start signal STV2 to the first driving circuit 121, and the display driver 20 is further configured to provide the first gate start signal STV1 and the second gate start signal STV2 to the second driving circuit 122.

[0191] In some embodiments, as shown in FIG. 14, the display driver 20 includes a first sub-display driver 21 and a second sub-display driver 22. The first sub-display driver 21 is configured to provide the first gate start signal STV1 and the second gate start signal STV2 for the first driving circuit 121. The second sub-display driver 22 is configured to provide the first gate start signal STV1 and the second gate start signal STV2 for the second driving circuit 122.

[0192] One side of the display panel 10 can include a plurality of first driving circuits 121, and the other side of the display panel 10 can also include a plurality of second driving circuits 122. In FIG. 14, only one first driving circuit 121 and one second driving circuit 122 are shown for illustration.

[0193] The display module provided by the embodiments of the present application can be applied to the electronic device 1 provided by the embodiments of the present application. The electronic device 1 can be a folding electronic device, for example. For example, the electronic device 1 is an outer folding electronic device. Alternatively, the electronic device 1 is a multi-folding electronic device. Alternatively, the electronic device 1 is a non-folding electronic device, but the electronic device 1 has a local display scenario.

[0194] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A drive circuit characterized by comprising: The driving circuit comprises: a plurality of cascaded first shift registers; an input terminal of a first stage of the first shift registers is configured to receive a first gate start signal, an input terminal of an Nth stage of the first shift registers is coupled with an output terminal of an (N-1)th stage of the first shift registers; an output terminal of each stage of the first shift registers is further configured to output a scanning signal; N is an integer greater than 1; a second shift register and a plurality of cascaded third shift registers; an input terminal of the second shift register is configured to receive a second gate start signal; an input terminal of a first stage of the third shift registers is coupled with an output terminal of the second shift register, an input terminal of an Mth stage of the third shift registers is coupled with an output terminal of an (M-1)th stage of the third shift registers; an output terminal of each stage of the third shift registers is further configured to output a scanning signal; M is an integer greater than 1.

2. The drive circuit according to claim 1, characterized by The driving circuit further comprises a fourth shift register and a plurality of cascaded fifth shift registers; an input terminal of the fourth shift register is configured to receive a third gate start signal; an input terminal of a first stage of the fifth shift registers is coupled with an output terminal of the fourth shift register, an input terminal of a Pth stage of the fifth shift registers is coupled with an output terminal of a (P-1)th stage of the fifth shift registers; an output terminal of each stage of the fifth shift registers is further configured to output a scanning signal; P is an integer greater than 1.

3. The drive circuit according to claim 1 or 2, characterized in that, The second shift register has the same structure as the third shift register.

4. The driving circuit according to any one of claims 1-3, wherein the first shift registers are further coupled with a power voltage terminal, and the second shift registers and the third shift registers are also coupled with the power voltage terminal; or the first shift registers are further coupled with a clock signal terminal, and the second shift registers and the third shift registers are also coupled with the clock signal terminal.

5. The driving circuit according to any one of claims 1-4, wherein the first gate start signal is an on signal, and the second gate start signal is an off signal; or the first gate start signal is an off signal, and the second gate start signal is an on signal; or the first gate start signal and the second gate start signal are both on signals or off signals. The display panel comprises a driving circuit and a plurality of pixel circuits arranged in an array; the driving circuit comprises the driving circuit according to any one of claims 1-5; an output terminal of a last stage of the first shift registers in the driving circuit is coupled with an (X-1)th row of the pixel circuits, and an output terminal of a first stage of the third shift registers is coupled with an Xth row of the pixel circuits; X is an integer greater than 1. an output terminal of a first stage of the fifth shift registers in the driving circuit is coupled with a Yth row of the pixel circuits, and Y is an integer greater than X.

6. A display panel, characterized by, an output terminal of a last stage of the first shift registers is further coupled with an (X-2)th row of the pixel circuits, and an output terminal of a first stage of the third shift registers is further coupled with an (X+1)th row of the pixel circuits; X is an integer greater than 2. ​ 7. The display panel of claim 6, wherein, ​ 8. The display panel of claim 6 or 7, wherein, ​ 9. The display panel of claim 8, wherein, An output terminal of a first stage of the fifth shift register is further coupled with a pixel circuit of Y+1th row, Y is an integer greater than X+1.

10. The display panel according to any one of claims 6-9, characterized in that, The display panel comprises a plurality of the driving circuits.

11. A display module, characterized by The display module comprises a display panel and a display driver, the display panel comprises the display panel of any one of claims 6-10; the display driver is configured to provide the first gate start signal and the second gate start signal for the driving circuit in the display panel.

12. The display module of claim 11, wherein, The plurality of the driving circuits comprises a first driving circuit and a second driving circuit located at different sides of the display panel; the display driver comprises a first sub-display driver and a second sub-display driver, the first sub-display driver is configured to provide the first gate start signal and the second gate start signal for the first driving circuit, and the second sub-display driver is configured to provide the first gate start signal and the second gate start signal for the second driving circuit.

13. An electronic device, comprising: The electronic device comprises a display module and a driving controller, the driving controller is coupled with the display module, and the display module comprises the display module of claim 11 or 12.

14. A driving method of a driving circuit, characterized by, The driving circuit comprises a plurality of cascaded first shift registers, a second shift register, and a plurality of cascaded third shift registers. The driving method comprises: The first stage of the first shift register receives a first gate start signal, and the Nth stage of the first shift register receives a signal output by the N-1th stage of the first shift register; each stage of the first shift register outputs a scanning signal; N is an integer greater than 1. The second shift register receives a second gate start signal; the first stage of the third shift register receives a signal output by the second shift register, and the Mth stage of the third shift register receives a signal output by the M-1th stage of the third shift register; each stage of the third shift register outputs a scanning signal; M is an integer greater than 1.

15. The driving method of claim 14, wherein: The first gate start signal is an open signal, and the second gate start signal is a cut-off signal. Alternatively, The first gate start signal is a cut-off signal, and the second gate start signal is an open signal. Alternatively, The first gate start signal and the second gate start signal are both open signals or cut-off signals.

16. The driving method according to claim 14 or 15, wherein The driving circuit further comprises a fourth shift register and a plurality of cascaded fifth shift registers. The driving method further comprises: The fourth shift register receives a third gate start signal; the first stage of the fifth shift register receives a signal output by the fourth shift register, and the Pth stage of the fifth shift register receives a signal output by the P-1th stage of the fifth shift register; each stage of the fifth shift register outputs a scanning signal; P is an integer greater than 1.

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