Driver circuit for controlling a PFC cell, control circuit and power factor correction circuit

Abstract

The invention relates to a driver circuit for controlling a PFC cell, said driver circuit having a half-bridge with two half-bridge switches, which are connected via a connection point, and a star point switch, which connects the connection point to a star point of the PFC cell. The driver circuit has: a setpoint control signal input via which signals in the form of respective setpoint control signals for respectively controlling the two half-bridge switches and the star point switch can be input into the driver circuit; an actual control signal output via which signals originating from the setpoint control signal input can be output by the driver circuit in the form of respective actual control signals for respectively controlling the two half-bridge switches and the star point switch, said actual control signal output being designed to output, from the driver circuit, a first signal for controlling one half-bridge switch, a second signal for controlling the other half-bridge switch, and a third signal for controlling the star point switch; a half-bridge driver which is designed to control the two half-bridge switches via the actual control signal output in such a way that only one of the half-bridge switches is controlled by the first or second signal in the HIGH state; and a first logic circuit which has at least three inputs and one output and is designed to control the star point switch via the actual control signal output in that a signal obtained exclusively by a logical linking process using logic gates is only output at the logic circuit output for outputting the third signal [in the HIGH state]*** if the respective signals for controlling the half-bridge circuit are in the LOW state at the first and second half-bridge circuit inputs and the signal for controlling the star point switch is in the HIGH state at the third star point switch input. The invention further relates to a control circuit and to a power factor correction circuit having such a driver circuit.

Description

[0001] Description

[0002] Driver circuit for controlling a PFC cell, control circuit and power factor correction circuit

[0003] The invention relates to a driver circuit for controlling a cell of a power factor correction circuit, hereinafter referred to as PFC or PFC circuit (PFC = "Power Factor Correction"), wherein the cell of the PFC circuit, hereinafter referred to as PFC cell, comprises a half-bridge with two half-bridge switches connected via a junction point and a star point switch that connects the junction point to a star point of the PFC cell. The invention further relates to a control circuit with such a driver circuit and a setpoint control signal source connected to a setpoint control signal input of the driver circuit. In addition, the invention relates to a power factor correction circuit with one or more PFC cells and with one or more such driver circuits.

[0004] Such a power factor correction circuit belonging to the state of the art, comprising a driver circuit and a conventional PFC cell connected thereto, is known, for example, from DE 10 2021 206 853 B3.

[0005] Half-bridge circuits are typically used, among other things, to direct or convert a DC voltage into an AC voltage. Such half-bridge circuits usually consist of two transistors connected in series, with a DC voltage applied to this series connection. The driver circuit, in this case specifically a half-bridge driver circuit, must therefore not only ensure the generation of the desired AC voltage but also prevent both transistors from being switched on simultaneously, thus avoiding a bridge short circuit.

[0006] In the prior art, corresponding driver circuits for half-bridges with two transistors in various configurations are widely known. However, to control a PFC cell with such a half-bridge circuit and three controllable switches in the form of three transistors, three signals are required: two signals to control the half-bridge or the transistors forming the series connection of the half-bridge (hereinafter also referred to as half-bridge switches), and one signal to control the switch in the form of a transistor (hereinafter also referred to as a star point switch), which connects the star point of the cell to the junction of the transistors of the half-bridge and has a decisive influence on the output voltage level or the power factor correction. In this context, it is also known in the prior art to generate switching control signals using suitable hardware, e.g.,Conventional half-bridge drivers with appropriate protection circuitry are used to monitor the system to prevent short circuits, e.g., in the half-bridge, due to faulty control, parasitic coupling to the control circuit, etc. Furthermore, it is known from the prior art that when controlling a PFC cell with three controllable switches, it is not only necessary to ensure that the half-bridge does not create a bridge short circuit, but also to prevent a high current from the discharge / charge processes of one of the PFC cell's capacitors, which can occur when one of the half-bridge switches and the star point switch are simultaneously switched on.

[0007] Figure 2 shows a schematic representation of a PFC cell, illustrating several possible short-circuit paths where a short circuit can occur due to faulty control signals. As can be seen in Figure 2, faulty control can lead to short circuits in paths A, B, and C within the PFC cell. For example, a short circuit can occur in path A if both half-bridge switches SH and SL are faultily switched on or closed simultaneously, i.e., driven by actual control signals in the HIGH or ON state (HIGH level or ON level). Therefore, without protection, a short-circuit current can flow through both half-bridge switches SH and SL and both capacitors C1 and C2 of the PFC cell. Depending on the current magnitude and pulse duration, the short-circuit current can destroy these components.Furthermore, a short circuit can occur, for example, in path B shown, if the lower half-bridge switch SL and the neutral switch SS are incorrectly connected simultaneously. In this case, a short-circuit current can flow through the neutral switch SS, the lower capacitor C2, and the lower half-bridge switch SL without any protective function. Therefore, in this case too, with a sufficient current magnitude and pulse duration, the lower half-bridge switch SL, the neutral switch SS, or the lower capacitor C2 can be destroyed. The same applies analogously to path C shown if the upper half-bridge switch SH and the neutral switch SS are incorrectly connected simultaneously.In this case, a short-circuit current can flow through the neutral switch SS, the upper capacitor C1, and the upper half-bridge switch SH without any protective function during a fault. Therefore, in this analogous scenario, with a sufficient current magnitude and pulse duration, the destruction of, for example, the upper half-bridge switch SH, the neutral switch SS, or the upper capacitor C1 can occur. Since such short circuits occurring during a fault, if of sufficient duration, destroy the components located in the respective short-circuit path, it is proposed, according to the state of the art, to implement suitable hardware measures to prevent said short circuits.

[0008] According to the prior art document DE 10 2021 206 853 B3, a driver circuit can be reliably locked using suitable hardware. This is achieved by cascading or connecting two suitable hardware circuits in series, such as two half-bridge drivers, and setting a dead time adapted to the selected three switching elements. While the use of multiple half-bridge drivers or half-bridge driver circuits and their cascading increases safety against short circuits, this also results in higher costs for implementing this driver circuit design.

[0009] The invention is therefore based on the objective of further developing the generic driver circuits, control circuits, and power factor correction circuits for controlling PFC cells in such a way that they can be implemented with a simple and preferably cost-effective design. A preferred objective of the invention is to implement such a driver circuit which includes a protection mechanism against short circuits when controlling the respective switches. This objective is achieved by the features of the independent claims. Advantageous embodiments and further developments of the invention are described in the dependent claims.

[0010] The driver circuit according to the invention is configured to control a PFC cell, which has a half-bridge with two half-bridge switches connected via a connection point and a star point switch that connects the connection point to a star point of the PFC cell. The driver circuit according to the invention comprises:

[0011] - a target control signal input, via which signals in the form of respective target control signals for the respective control of the two half-bridge switches and the star point switch can be input into the driver circuit,

[0012] - an actual control signal output, via which signals originating from the target control signal input can be output by the driver circuit in the form of respective actual control signals for the respective control of the two half-bridge switches and the star point switch, wherein the actual control signal output is configured to output a first signal for controlling one of the half-bridge switches, a second signal for controlling the other half-bridge switch and a third signal for controlling the star point switch from the driver circuit,

[0013] - a half-bridge driver configured to control the two half-bridge switches via the actual control signal output in such a way that only one of the half-bridge switches is controlled with the first or second signal in a HIGH state, so that the controlled half-bridge switch is switched on or closed, and

[0014] - a first logic circuit, which has at least three inputs and one output and is configured to control the star point switch via the actual control signal output, preferably directly with a signal in the HIGH state, by outputting a signal obtained exclusively by logical operation using logic gates to their output for the output of the third signal in the HIGH state only if the star point switch is switched on or closed when the respective signals for controlling the half-bridge switches at their first and second inputs are in the LOW state and the signal for controlling the star point switch at their third input is in the HIGH state.

[0015] According to the invention, a simple and cost-effective protection mechanism is thus implemented using a logic circuit formed by logic gates. This mechanism prevents the star point switch from being driven with a HIGH signal if the input of the logic circuit contains a signal for driving one of the half-bridge switches, or if both signals for driving the two half-bridge switches are HIGH. Therefore, the solution according to the invention eliminates the need for multiple half-bridge driver circuits with programmed microprocessors or ASICs. Instead, a logic circuit, preferably implemented using hard-wired logic gates, can be used to drive the star point switch. Due to the protection mechanism formed by the logic gates, the switch is only driven with a HIGH signal when the respective signals for the two half-bridge switches are LOW.Hardwired logic gates can be, for example, logic gates that are formed exclusively by circuit elements such as transistors for simple logic operations, without using an arithmetic unit or a processor with memory, etc.

[0016] According to the invention, the driver circuit uses only a half-bridge driver, which can control the two half-bridge switches and thus outputs two signals in the form of respective actual control signals for the respective control of the two half-bridge switches. The half-bridge driver can, for example, be implemented by an ASIC or a programmed microprocessor. In contrast, the actual control signal for controlling the star point switch is output exclusively via the logic gates of the first logic circuit. Thus, a reliable hardware interlock of three switch control signals, or the three target control signals, is ultimately achieved using the pure logic gate circuit and the half-bridge driver.The first logic circuit is thus preferably formed by a discrete analog circuit, which logically links the three target control signals together; preferably using only a NOR logic gate, while the half-bridge drive is preceded by a NOR logic gate and two AN / D logic gates to reliably perform the interlocking function. Due to the use of the logic gates, a protection mechanism is provided in which only one switch, i.e., one of the half-bridge switches or the star point switch, is reliably and cost-effectively activated, regardless of how many target control signals are active, i.e., in the HIGH state. According to the invention, reliable protection against short circuits is thus provided, independent of faulty control. The half-bridge switches and the star point switch are preferably implemented using semiconductor switches.The half-bridge switches are each implemented, for example, as a MOSFET or IGBT. The star point switch can be implemented as a transistor without an inverse diode, i.e., as a bidirectionally blocking transistor, or as a series connection of anti-series transistor elements that incorporate inverse diodes to form a bidirectional transistor device that constitutes the star point switch. If the star point switch is implemented as a transistor device with two transistor elements, and the transistor elements incorporate inverse diodes, then the forward directions of the transistor elements are opposite to each other.

[0017] The driver circuit according to the invention can advantageously be further developed such that the first logic circuit has

[0018] - a first NOR gate with two inputs and one output, wherein the first NOR gate is configured to logically combine signals input to its two inputs via the target control signal input to control the two half-bridge switches and to output a combined signal at its output, and

[0019] - a first AND gate with two inputs and one output, wherein the first AND gate is configured to logically combine a signal for controlling the star point switch at one input of the target control signal input and the linked signal of the NOR gate at the other input of the target control signal input, and to output a linked signal as a third signal, in particular with a HIGH state, via the actual control signal output when the linked signal of the NOR gate has a HIGH state and the signal for controlling the star point switch, in particular the target control signal for the star point switch, has a HIGH state.

[0020] Furthermore, the driver circuit according to the invention can be implemented in such a way that a second logic circuit is connected upstream of the half-bridge driver, which has a second AND gate and a third AND gate as well as a second NOR gate connected upstream of the second and third AND gates, wherein

[0021] - the second NOR gate preceding the second and third AND gates has two inputs and one output and is configured to logically combine signals, in particular target control signals, exclusively entered at its two inputs via the setpoint control signal input for controlling the star point switch and to output a combined signal to the second and third AND gates at its output,

[0022] - the second AND gate has two inputs and one output and is configured to logically combine a signal, in particular a target control signal, at one of its inputs via the target control signal input to control one half-bridge switch and at its other input to logically combine the linked signal of the upstream second NOR gate and output a linked signal at its output to control one half-bridge switch to the half-bridge driver,

[0023] - the third AND gate has two inputs and one output and is configured to receive a signal, in particular a target control signal, at one of its inputs via the target control signal input to control the other half-bridge switch, and to logically combine the linked signal of the upstream second NOR gate at its other input, and to output a linked signal to the half-bridge driver at its output to control the other half-bridge switch.

[0024] Furthermore, the driver circuit according to the invention can be implemented in such a way that

[0025] - the second AND gate is configured, at whose output a first signal with a HIGH state is to be output to the half-bridge driver to control one of the half-bridge switches, when at one of its inputs the combined signal of the second NOR gate has a HIGH state and at its other input the signal for controlling one of the half-bridge switches, in particular the desired control signal of one of the half-bridge switches, has a HIGH state, and / or

[0026] - the third AND gate is set up, at whose output a second signal with a HIGH state is to be output to the half-bridge driver to control the other half-bridge switch, when at one of its inputs the combined signal of the second NOR gate has a HIGH state and at its other input the signal to control the other half-bridge switch, in particular the desired control signal of the other half-bridge switch, has a HIGH state.

[0027] Furthermore, the driver circuit according to the invention can be configured such that the half-bridge driver is configured to control one of the half-bridge switches via the actual control signal output when the first signal for controlling one of the half-bridge switches is in the HIGH state and the second signal for controlling the other of the half-bridge switches is in the LOW state, and / or that the half-bridge driver is configured to control the other of the half-bridge switches via the actual control signal output when the first signal for controlling one of the half-bridge switches is in the LOW state and the second signal for controlling the other of the half-bridge switches is in the HIGH state.

[0028] In other words, the half-bridge driver outputs a signal via the actual control signal output as the first or second signal only if both signals input to the half-bridge driver for controlling the two half-bridge switches are not in a HIGH state. However, if the second NOR gate does not output a HIGH signal, then the second and third AND gates will also not output a HIGH signal to the half-bridge driver.

[0029] Furthermore, the driver circuit according to the invention can be designed such that the half-bridge driver has two inputs and two outputs and is configured to control the half-bridge switches via the actual control signal output, by connecting the two outputs to the two half-bridge switches via the actual control signal output and by outputting signals at the two outputs as first or second signals with the state HIGH only if both signals input via the two inputs do not have a state HIGH at the two inputs.

[0030] The control circuit according to the invention comprises at least one driver circuit according to the invention and a setpoint control signal source which is connected to the setpoint control signal input and is configured to output or supply setpoint control signals for the two half-bridge switches as well as for the star point switch.

[0031] This results in the same or similar properties and advantages described in connection with the driver circuit according to the invention, which is why, to avoid repetition, reference is made to the preceding explanations in connection with the driver circuit according to the invention.

[0032] The control circuit according to the invention can advantageously be further developed in such a way that the control circuit has several driver circuits and is set up to control several PFC cells via the respective driver circuits.

[0033] Accordingly, a control circuit according to the invention can be provided, comprising the driver circuit or several driver circuits. The control circuit is further equipped with a setpoint control signal source. This setpoint control signal source, in particular its (multi-stage) output, is connected to the (multi-stage) setpoint control signal input. The setpoint control signal source is configured to output setpoint control signals intended for the two half-bridge switches and the star point switch. The at least one driver circuit, and thus the control circuit, can have at least one actual control signal output, which is configured to output actual control signals intended for the half-bridge switches and the star point switch.The control circuit can be configured to output signals at the actual control signal output that are designed according to a predetermined target output voltage of the PFC cell and / or according to a target phase angle of an alternating current (relative to an alternating voltage waveform) and / or according to a target power factor of the PFC cell.

[0034] The driver circuit thus features a setpoint control signal input for setpoint control signals. This input is configured for three individual control signals that can be input into the driver circuit, for example, from the setpoint control signal source, which can be in the form of a PFC controller. The setpoint control signal source can be an ASIC or a microprocessor with appropriate programming.

[0035] The single- or multi-phase power factor correction circuit according to the invention comprises one or more PFC cells and one or more driver circuits according to the invention, wherein each PFC cell has a half-bridge with two half-bridge switches connected via a connection point and a star point switch, as well as a working inductor that connects the connection point to a first AC voltage input, wherein a second AC voltage input is connected to the star point formed by a junction between two capacitors connected in series, wherein the series connection of the capacitors is connected in parallel to the half-bridge and the ends of the half-bridges form two DC voltage outputs of the power factor correction circuit.This results in the same or similar properties and advantages described in connection with the driver circuit according to the invention, which is why, to avoid repetition, reference is made to the preceding explanations in connection with the driver circuit according to the invention.

[0036] The single-phase or multi-phase power factor correction circuit can thus have one or more PFC cells, the number of which corresponds to the number of phases in the circuit. The power factor correction circuit can also have one or more driver circuits. Each PFC cell has its own corresponding driver circuit. Each PFC cell comprises a half-bridge. The half-bridge consists of two half-bridge switches connected (in series) via a junction. Each PFC cell has a neutral switch. In particular, each PFC cell has a load inductor. This inductor connects the junction (of the half-bridge) to a first AC voltage input of the PFC cell.

[0037] In a single-phase configuration, a second AC input is connected to the neutral point of the PFC cell. The neutral point is formed by the junction of two capacitors connected in series. These capacitors can be referred to as DC link capacitors. The capacitors are connected in parallel to the half-bridge. In other words, the series connection of the two capacitors is connected in parallel to the half-bridge, i.e., the series connection of the two half-bridge switches. The ends of the half-bridges form two DC outputs, which are designed to be connected, for example, to a vehicle electrical system or a high-voltage battery.

[0038] In a multi-phase power factor correction circuit, several PFC cells are provided, each with a half-bridge. With a multi-phase AC input, each phase L1, L2, L3 of this input is connected via its own operating inductor to the junction point of the half-bridge of the respective PFC cell. If there are multiple PFC cells in a power factor correction circuit, their neutral points can be connected to each other to form a common neutral point for the multi-phase power factor correction circuit. This common neutral point can be connected to a neutral conductor terminal of the multi-phase AC input, particularly in a switchable manner.

[0039] A vehicle-side AC charging device may be provided, comprising at least one of the driver or control circuits described herein, and preferably also comprising the power factor correction circuit described herein. An externally accessible vehicle charging port (also commonly referred to as a "plug-in socket" or "charging socket") may be provided, which is connected to the at least one PFC cell, preferably via the AC input. A vehicle-side high-voltage traction battery may be connected directly or indirectly to the half-bridges in order to charge it via the at least one PFC cell.

[0040] A preferred embodiment of the invention is explained below by way of example with reference to the figure.

[0041] It shows:

[0042] Figure 1 shows a schematic representation of a single-phase power factor correction circuit according to the invention, comprising a driver circuit according to the invention and a PFC cell connected thereto.

[0043] As can be seen in Figure 1, a single-phase power factor correction (PFC) circuit according to the invention is shown in a very schematic way, i.e., in the form of an exemplary circuit. Some components of the power factor correction circuit according to the invention are identical to those of the power factor correction circuit according to the aforementioned DE 10 2021 206 853 B3, including the setpoint control signal source C, the half-bridge driver T, and the PFC cell PZ, which will be explained in more detail below. Although these components will be discussed again below, reference is also made to the corresponding disclosure in DE 10 2021 206 853 B3, which is incorporated herein by reference.

[0044] In the illustrated case, the power factor correction (PFC) circuit comprises exactly one driver circuit TS and exactly one connected PFC cell PZ. The driver circuit TS controls the PFC cell PZ, which—as is known from the prior art—is constructed in a conventional manner. Accordingly, the PFC cell PZ comprises a half-bridge with two transistor half-bridge switches SH and SL connected via a junction VP, and a transistor star switch SS that connects junction VP to a star point SP of the PFC cell PZ. Furthermore, the PFC cell PZ has a load inductance L that connects junction VP to a first AC input IN1, while a second AC input IN2 is connected to the star point SP, which is formed by a junction between two capacitors C1 and C2 connected in series.The series circuit of capacitors C1 and C2 is connected in parallel to the half-bridge SH, SL, and two DC voltage outputs V+, V- of the power factor correction circuit PFC are formed at the ends of the half-bridge.

[0045] The half-bridge performs the rectification function, with the neutral switch SS (especially in conjunction with the load inductor L) used to adjust the power factor or voltage conversion (or output voltage level). The load inductor L, together with the half-bridge, can also influence the voltage conversion (or output voltage level) of the PFC cell PZ.

[0046] The driver circuit TS has a target control signal input Sl, an actual control signal output IO, a first logic circuit LS1, a second logic circuit LS2 and a half-bridge driver T.

[0047] The target control signal input Sl forms an interface to a target control signal source C that can be connected to it.

[0048] The setpoint control signal source C outputs the setpoint control signals HS, LS, and PS to the driver circuit TS via the setpoint control signal input Sl of the driver circuit TS. These three signals are intended for, or assigned to, the three switches of the PFC cell PZ, i.e., the two half-bridge switches SH and SL, and the star point switch SS. The setpoint control signal HS is intended for the first half-bridge switch SH, also commonly referred to as the "high-side switch," and the setpoint control signal LS is intended for the second half-bridge switch SL, also commonly referred to as the "low-side switch." Finally, the setpoint control signal PS is intended for the star point switch SS.

[0049] The half-bridge switches SH, SL and the star point switch SS are to be controlled according to these target control signals HS, LS, PS, whereby the driver circuit TS ensures that in the event of faulty target control signals, which is the case, for example, when more than one target control signal simultaneously has the state ON or HIGH (ON or HIGH level), the three switches, namely the half-bridge switches SH, SL and the star point switch SS, are not controlled with the faulty control signals.

[0050] The driver circuit TS, together with the connected target control signal source C, forms a control circuit. After appropriate signal processing within the driver circuit TS, the processed target control signals HS, LS, SS can be output via the actual control signal output IO. Specifically, the target control signals originating from the target control signal input Sl can be output via the actual control signal output IO as the respective actual control signals Hl, LI, PI for controlling the two half-bridge switches SH and SL, as well as the star point switch SS, by the driver circuit TS.In particular, the actual control signal output IO is set up to output the actual control signal Hl as a first signal for controlling one of the half-bridge switches SH, the actual control signal LI as a second signal for controlling the other half-bridge switch SL, and the actual control signal PI as a third signal for controlling the star point switch SS from the driver circuit TS.

[0051] The first logic circuit LS1, the second logic circuit LS2, and the half-bridge driver T are connected between the target control signal input Sl and the actual control signal output IO and perform the signal processing. The first logic circuit LS1 comprises three inputs (signal inputs) and one output (signal output) and is configured to control the star-point switch SS via the actual control signal output IO. The first logic circuit LS1 accomplishes this by outputting a signal in the form of the actual control signal PI with a HIGH state at the output for the third signal only when the respective signals for controlling the half-bridge switches SH and SL at their first and second inputs are LOW, i.e., the target control signals HS and LS are LOW, and the signal for controlling the star-point switch SS at its third input is HIGH, i.e., the target control signal PS is HIGH.

[0052] For this purpose, the first logic circuit has a first NOR gate NOR1 and a first AND gate AND1. The first NOR gate NOR1 has two inputs and one output, and is configured to logically combine signals input to its two inputs via the target control signal input Sl to control the two half-bridge switches SH and SL, i.e., to logically combine the target control signals HS and LS, and to output a combined signal VK1.

[0053] The first AND gate, AND1, has two inputs and one output. It is configured to take the target control signal input, Sl, and at one input, logically combine a signal for controlling the star switch, SS, with the logically combined signal, VK1, of the first NOR gate, NOR1, at the other input. At its output, a third, logically combined signal, HIGH, is output via the actual control signal output, IO. Specifically, the actual control signal, PI, is HIGH when the logically combined signal, VK1, at the input of the first NOR gate and the signal for controlling the star switch, SS (the target control signal, PS), are HIGH. For example, the output of the first AND gate, AND1, is connected to a control input of this star switch, SS, such as its gate.

[0054] Furthermore, the second logic circuit LS2 is connected upstream of the half-bridge driver T and comprises a second NOR gate NOR2, a second AND gate AND2, and a third AND gate AND3, with the second NOR gate NOR2 being connected upstream of the second and third AND gates AND2 and AND3. The second NOR gate NOR2, which is connected upstream of the second and third AND gates AND2 and AND3, comprises two inputs and one output and is configured to logically combine signals input to the target control signal input Sl at its two inputs for controlling the star point switch SS, i.e., to logically combine only two parallel target control signals PS, and to output a combined signal VK2 at its output, which is then also output to one input each of the second and third AND gates AND2 and AND3.The second AND gate AND2 has two inputs and one output and is configured to logically combine a signal for controlling one half-bridge switch SH, i.e. the target control signal HS, via the target control signal input Sl at one of its inputs, and at its other input the linked signal VK2 of the upstream second NOR gate NOR2, and to output a linked signal for controlling one half-bridge switch SH to the half-bridge driver T at its output.

[0055] The third AND gate AND3 has two inputs and one output and is configured to logically combine a signal to control the other half-bridge switch SL, i.e. the target control signal LS, via the target control signal input Sl at one of its inputs, and at its other input the combined signal of the upstream second NOR gate NOR2, and to output a combined signal to control the other half-bridge switch SL to the half-bridge driver T at its output.

[0056] In particular, the second AND gate, AND2, is configured to output a first HIGH signal to the half-bridge driver T to control one half-bridge switch SH, provided that the combined signal VK2 of the second NOR gate, NOR2, is HIGH at one input of the driver T, and the signal for controlling one half-bridge switch SH (i.e., the desired control signal HS) is HIGH at the other input of the driver T. The third AND gate, AN D3, is configured analogously to the second AND gate, AND2, to output a second HIGH signal to the half-bridge driver T to control the other half-bridge switch SL, provided that the combined signal VK2 of the second NOR gate, NOR2, is HIGH at one input of the driver T, and the signal for controlling the other half-bridge switch SL (i.e., the desired control signal LS) is HIGH at the other input of the driver T.

[0057] The half-bridge driver T is configured to control the two half-bridge switches SH and SL via the actual control signal output IO. Accordingly, the half-bridge driver T controls one half-bridge switch SH via the actual control signal output IO when the first signal for controlling one half-bridge switch SH is HIGH and the second signal for controlling the other half-bridge switch SL is LOW. Conversely, the half-bridge driver T controls the other half-bridge switch SL via the actual control signal output IO when the first signal for controlling one half-bridge switch SH is LOW and the second signal for controlling the other half-bridge switch SL is HIGH.Thus, the half-bridge driver T comprises two inputs and two outputs and is configured to control the half-bridge switches SH, SL via the actual control signal output IO, by connecting the two outputs to the two half-bridge switches SH, SL via the actual control signal output IO and by only outputting signals at the two outputs as first or second signals with the state HIGH if not both signals input via the two inputs have a state HIGH at the two inputs.

[0058] The driver circuit TS, together with the upstream target control signal source C, forms a control circuit configured to output the target control signals HS, LS, SS for the two half-bridge switches SH, SL, and for the neutral switch SS. The driver circuit TS has an actual control signal output IO, which is configured to output the actual control signals H1, LI, PI to the half-bridge switches SH, SL, and the neutral switch SS of the PFC cell connected to the actual control signal output IO. Among other functions, the driver circuit prevents a half-bridge short circuit through SH, SL, and prevents excessive inrush current that can flow through the neutral switch SS to capacitors C1, C2 when either half-bridge switch SH or SL is closed. The same applies to discharge current originating from capacitor C1 or C2.

[0059] In an alternative embodiment, the control circuit may comprise several such driver circuits TS and be configured to control multiple PFC cells via the respective driver circuits TS. In the context of a multi-phase power factor correction circuit, this includes several of the illustrated driver circuits TS and also several PFC cells PZ.

[0060] In a multi-phase power factor correction circuit, the multiple star points of the PFC cells PZ are connected to each other and, if necessary, to a neutral conductor connection. The multiple AC phase connections resulting from a multi-phase application are individually connected to the connection points VP. Each AC phase connection is connected to a connection point VP of an individual PFC cell.

[0061] The features of the invention disclosed in the foregoing description, in the drawings and in the claims may be essential for the realization of the invention, either individually or in any combination.

Claims

Patent claims 1. Driver circuit (TS) for controlling a power factor correction circuit cell, PFC cell, (PZ), comprising a half-bridge with two half-bridge switches (SH, SL) connected via a connection point (VP) and a star point switch (SS) connecting the connection point (VP) to a star point (SP) of the PFC cell, wherein the driver circuit (TS) comprises - a target control signal input (Sl), via which signals in the form of respective target control signals (HS, LS, PS) can be input into the driver circuit (TS) for the respective control of the two half-bridge switches (SH, SL) and the star point switch (SS), - an actual control signal output (IO) via which signals originating from the target control signal input (Sl) in the form of respective actual control signals (Hl, LI, PI) can be output by the driver circuit (TS) for the respective control of the two half-bridge switches (SH, SL) and the star point switch (SS), wherein the actual control signals (Hl, LI, PI) comprise a first signal (Hl), a second signal (LI) and a third signal (PI) and the actual control signal output (IO) is configured to output the first signal for controlling one (SH) of the half-bridge switches (SH, SL), the second signal for controlling the other (SL) of the half-bridge switches (SH, SL) and the third signal (PI) for controlling the star point switch (SS) from the driver circuit (TS), - a half-bridge driver (T) configured to control the two half-bridge switches (SH, SL) via the actual control signal output (IO) such that only one of the half-bridge switches (SH, SL) is driven with the first (Hl) or second signal (LI) in the HIGH state, and - a first logic circuit (LS1) which has at least a first input, second input and third input and an output and is configured to control the star point switch (SS) via the actual control signal output (IO) by outputting a signal obtained exclusively by logical operation using logic gates to their output for the output of the third signal (PI) with a HIGH state only if the target control signal (HS) for controlling one half-bridge switch (SH) at the first input and the target control signal (LS) for controlling the other half-bridge switch (SL) at the second input are each in the LOW state and the target control signal (PS) for controlling the star point switch (SS) at the third input is in the HIGH state.

2. Driver circuit (TS) according to claim 1, wherein the first logic circuit (LS1) comprises - a first NOR gate (NOR1 ) with two inputs and one output, wherein the first NOR gate (NOR1 ) is configured to logically combine the target control signals (HS, LS) input via the target control signal input (Sl) at its two inputs to control the two half-bridge switches (SH, SL) and to output a combined signal (VK1 ) at its output, and - a first AND gate (AND1 ) with two inputs and one output, wherein the first AND gate (AND1 ) is configured to logically combine the target control signal (PS) for controlling the star point switch (SS) at one input of the target control signal (Sl) and the linked signal (VK1 ) of the first NOR gate (NOR) at its other input, and to output a linked signal as the third signal with a HIGH state via the actual control signal output (IO) when the linked signal of the first NOR gate (NOR1 ) has a HIGH state and the target control signal (PS) for controlling the star point switch (SS) has a HIGH state.

3. Driver circuit (TS) according to claim 1 or 2, wherein a second logic circuit (LS2) is connected upstream of the half-bridge driver (T), comprising a second AND gate (AND2) and a third AND gate (AND3) as well as a second NOR gate (NOR2) connected upstream of the second and third AND gates, wherein - the second NOR gate (NOR2) preceding the second and third AND gates (AND2, AND3) has two inputs and one output and is configured to logically combine the target control signal (PS) input exclusively at its two inputs for controlling the star point switch (SS) via the target control signal input (Sl) and to output a combined signal (VK2) to the second and third AND gates (AND2, AND3) at its output, - the second AND gate (AND2) has two inputs and one output and is configured to logically combine the target control signal (HS) signal for controlling one half-bridge switch (SH) at one input of the target control signal input (Sl) and the linked signal (VK2) of the upstream second NOR gate (NOR2) at its other input, and to output a linked signal for controlling one half-bridge switch (SH) to the half-bridge driver (T) at its output, - the third AND gate (AND3) has two inputs and one output and is configured to logically combine the target control signal (LS) for controlling the other half-bridge switch (SL) at one input of the target control signal input (Sl) and the linked signal (VK2) of the upstream second NOR gate (NOR2) at its other input, and to output a linked signal to the half-bridge driver (T) for controlling the other half-bridge switch (SL).

4. Driver circuit (TS) according to claim 3, wherein - the second AND gate (AND2) is configured, at whose output a first signal with a HIGH state is to be output to the half-bridge driver (T) to control one half-bridge switch (SH), when at one of its inputs the combined signal (VK2) of the second NOR gate (NOR2) has a HIGH state and at its other input the desired control signal (HS) for controlling one half-bridge switch (SH) has a HIGH state, and / or - the third AND gate (AND3) is set up, at whose output a second signal with a HIGH state is to be output to the half-bridge driver (T) to control the other half-bridge switch (SL), when at one of its inputs the combined signal (VK2) of the second NOR gate (NOR2) has a HIGH state and at its other input the desired control signal (LS) to control the other half-bridge switch (SL) has a HIGH state.

5. Driver circuit (TS) according to one of claims 1 to 4, wherein - the half-bridge driver (T) is configured to control one half-bridge switch (SH) via the actual control signal output (IO) when the first signal to control one half-bridge switch (SH) is HIGH and the second signal to control the other half-bridge switch (SL) is LOW, and / or - the half-bridge driver (T) is configured to control the other half-bridge switch (SL) via the actual control signal output (IO) when the first signal to control one half-bridge switch (SH) is in the LOW state and the second signal to control the other half-bridge switch (SL) is in the HIGH state.

6. Driver circuit (TS) according to any one of claims 1 to 5, wherein the half-bridge driver (T) has two inputs and two outputs and is configured to control the half-bridge switches (SH, SL) via the actual control signal output (IO) by connecting the two outputs via the The actual control signal output (IO) is connected to the two half-bridge switches (SH, SL) and signals at the two outputs are only output as first or second signals with the state HIGH if not both signals input via the two inputs have a state HIGH at the two inputs.

7. Control circuit with at least one driver circuit (TS) according to one of the preceding claims and a setpoint control signal source (C) which is connected to the setpoint control signal input (Sl) of the driver circuit (TS) and is configured to output setpoint control signals (HS, LS, SS) for the two half-bridge switches (SH, SL) and for the star point switch (SS).

8. Control circuit according to claim 7, wherein the control circuit has several driver circuits (TS) and is configured to control several PFC cells via the respective driver circuits (TS).

9. A single- or multi-phase power factor correction circuit (PFC) comprising one or more PFC cells (PZ) and one or more driver circuits (TS) according to any one of claims 1-6, wherein each PFC cell (PZ) comprises a half-bridge with two half-bridge switches (SH, SL) connected via a junction point (VP) and a star point switch (SS), and a working inductor (L) connecting the junction point (VP) to a first AC voltage input (IN1), wherein a second AC voltage input (IN2) is connected to the star point (SP) formed by a junction between two capacitors (C1, C2) connected in series, wherein the series connection of the capacitors (C1, C2) is connected in parallel to the half-bridge (SH, SL) and the ends of the half-bridge form two DC voltage outputs (V+, V-) of the power factor correction circuit (PFC).

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