Gate drive device

Abstract

This gate drive device drives a gate drive-type semiconductor element connected in series by upper and lower arms. The gate drive device includes: a gate-on circuit connected between the gate of the semiconductor element and the gate positive power supply; a gate-off circuit connected between the gate and the gate negative power supply; a switching element that is connected between the gate and the gate negative power supply and that is turned on when the gate-on circuit provided to the semiconductor element on the opposing arm side is turned on; and a Zener diode connected in series to the switching element.

Description

Gate Driver

[0001] The present invention relates to a gate driver.

[0002] A power conversion device for driving a three-phase AC motor is provided with six switching elements for three-phase upper and lower arms, each of which is provided with a gate drive circuit. The upper and lower arm switching elements are turned on and off by gate drive signals from the gate drive circuit, thereby generating three-phase AC current for driving the motor. For example, the device described in Patent Document 1 uses SiC semiconductor elements for the switching elements.

[0003] Patent Document 1 discloses a configuration in which a switching element that functions as a Miller clamp circuit is connected in parallel between the gate and source of a switching element (synchronous rectification switching element), and a diode and a capacitor are connected in parallel to the source terminal of the switching element. When the switching element of the opposing arm is on, the addition of a Zener diode and a capacitor increases the negative bias voltage value, thereby preventing false firing, reducing gate surges, and reducing reverse conduction losses during dead time.

[0004] Japanese Patent Application Publication No. 2020-068630

[0005] However, when a SiC semiconductor element is used as a switching element, there is a problem that a recovery surge voltage is large due to the recovery characteristics of a parasitic diode, which causes problems such as a decrease in EMC (Electromagnetic Compatibility) performance and an increase in switching loss.

[0006] A gate drive device according to an aspect of the present invention is a gate drive device that drives gate-driven semiconductor elements connected in series in upper and lower arms, and includes a gate-on circuit connected between the gate of the semiconductor element and a gate positive power supply, a gate-off circuit connected between the gate and a gate negative power supply, a switching element connected between the gate and the gate negative power supply and turned on when the gate-on circuit provided for the semiconductor element on the opposite arm is turned on, and a Zener diode connected in series to the switching element.

[0007] According to the present invention, it is possible to reduce the recovery surge voltage.

[0008] Fig. 1 shows a schematic configuration of an inverter device for driving a motor. Fig. 2 shows a circuit configuration for one phase of an upper and lower arm of a three-phase switching arm. Fig. 3 shows an example of gate charge characteristics of a MOSFET used in a semiconductor element. Fig. 4 is a diagram explaining circuit operation during upper arm turn-on operation. Fig. 5 is a timing chart of the operation shown in Fig. 4. Fig. 6 shows a first modification. Fig. 7 shows a second modification.

[0009] Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, identical or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the content described below merely shows one example of an embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0010] FIG. 1 is a diagram showing an example of a power conversion device, illustrating the schematic configuration of an inverter device 1 that drives a motor 2. A high-voltage battery 3 is connected to the inverter device 1 via a contactor 4 that can be connected and disconnected. The inverter device 1 includes a three-phase switching arm 10, a driver circuit 20, a motor controller 30, and the like. The motor controller 30 operates on power from a constant-voltage (12 V) DC power supply 5. A voltage smoothing capacitor 40 smoothes the applied voltage that fluctuates during power conversion. The motor 2 is provided with a rotation sensor 50 for detecting motor rotation. The output current of the inverter device 1 is detected by a current sensor 60. The input voltage of the inverter device 1 is detected by a voltage sensor 70.

[0011] Motor controller 30 receives motor driving commands, such as torque and rotation commands, from a higher-level controller (not shown). Motor controller 30 inputs a PWM signal to driver circuit 20 according to the input command and detection information from rotation sensor 50, current sensor 60, and voltage sensor 70. Driver circuit 20 controls the switching of three-phase switching arm 10 according to the input PWM signal. This converts DC voltage from battery 3 into AC voltage for driving motor 2, thereby controlling the torque and rotation speed of motor 2.

[0012] 2 is a diagram showing the circuit configuration for one phase of the upper and lower arms of the three-phase switching arm 10. In this embodiment, in order to improve the efficiency of the inverter device 1, SiC (silicon carbide) semiconductor elements (e.g., MOSFETs) are used as the switching elements of the three-phase switching arm 10. The driver circuit 20 is provided with an upper arm drive circuit 20a for the upper arm semiconductor element 100a and a lower arm drive circuit 20b for the lower arm semiconductor element 100b.

[0013] The GDIC (gate driver integrated circuit) 200 provided in the upper arm driver circuit 20a and the lower arm driver circuit 20b includes a switching element S1H connected to a gate positive power supply VCC2 and switching elements S1L and S2 connected to a gate negative power supply VEE. A turn-on gate resistor Rgon is connected to the output terminal OUT1H of the switching element S1H. The switching element S1H and the turn-on gate resistor Rgon form a gate-on circuit. A turn-off gate resistor Rgoff is connected to the output terminal OUT1L of the switching element S1L. The switching element S1L and the turn-off gate resistor Rgoff form a gate-off circuit.

[0014] The output terminal OUT2 of the switching element S2 for the Miller clamp function (hereinafter referred to as the Miller clamp function switching element) built into the upper-arm GDIC 200 is connected to the gate terminal of the semiconductor element 100a via a parallel circuit of a Zener diode ZD1 and a resistor R1. Similarly, the output terminal OUT2 of the switching element S2 for the Miller clamp function built into the lower-arm GDIC 200 is connected to the gate terminal of the semiconductor element 100b via a parallel circuit of a Zener diode ZD2 and a resistor R2.

[0015] 3 is a diagram showing an example of the gate charge characteristics (electrical characteristics) of the MOSFET used in the semiconductor elements 100a and 100b. The MOSFET has parasitic capacitances, namely, gate-drain capacitance Cgd, gate-source capacitance Cgs, and drain-source capacitance Cds. The period from time t0 to time t2 is the period during which the gate-source capacitance Cgs is charged, the gate-source voltage Vgs rises, and the gate-source voltage Vplt is reached. When the gate-source voltage Vgs exceeds the gate threshold voltage Vth at time t1, the drain-source current Ids begins to flow.

[0016] The period from time t2 to time t3 is called the mirror period, during which the gate-drain capacitance Cgd is charged by the gate current, and the gate-source voltage Vgs does not increase. During the mirror period, the gate-source voltage Vgs is maintained at the mirror plateau voltage Vplt. As the source potential increases, the drain-source voltage Vds decreases, and the mirror period ends when the drain-source voltage Vds has completely decreased (t=t3). When the mirror period ends, the gate-source capacitance Cgs and the gate-drain capacitance Cgd are charged until the gate-source voltage Vgs reaches its final value.

[0017] FIG. 4 illustrates circuit operation when the upper arm is turned on. The circuit operation when the lower arm is turned on is the same as that of the upper arm, so a detailed description of the operation is omitted. When the upper arm semiconductor element 100a is turned on, a recovery current Irr and a recovery voltage Vrr are generated between the drain and source terminals of the lower arm semiconductor element 100b. At this time, a current Irss = CrSS × dVrr / dt, which depends on the rate of change of the recovery voltage Vrr (dVrr / dt) and the feedback parasitic capacitance CrSS (= Cgd) of the semiconductor element 100b, is generated and flows into the turn-off side gate resistor Rgoff and resistor R2 of the lower arm drive circuit (GDIC 200b). As a result, the gate-source voltage Vgs_L of the semiconductor element 100b rises to Vgs_L = Irss × (Rgoff × R2) / (Rgoff + R2).

[0018] Because the Zener diode ZD2 is connected in parallel to the resistor R2, the voltage across the parallel circuit is the Zener voltage Vz2 of the Zener diode ZD2. That is, the gate-source voltage Vgs_L of the semiconductor element 100b is clamped to the Zener voltage Vz2. In this embodiment, the Zener voltage Vz2 of the Zener diode ZD2 is set to a voltage at which the semiconductor element 100b of the lower arm does not turn on, i.e., a voltage less than the gate threshold voltage Vth in FIG. 3. In this case, it is preferable to set the Zener voltage Vz2 close to the gate threshold voltage Vth. The Zener voltage Vz1 of the Zener diode ZD1 provided on the upper arm side is set in the same manner.

[0019] 5 is a timing chart of the operation shown in FIG. 4. In FIG. 5, waveform (A) shows the signal waveform at the output terminal OUT1H of the upper arm driver circuit (GDIC 200a). Waveforms (B), (C), and (D) show the gate-source voltage Vgs_H, drain-source voltage Vds, and drain-source current Ids of the upper arm semiconductor element 100a, respectively. Waveforms (E), (F), and (G) show the recovery current Irr, recovery voltage Vrr, and gate-source voltage Vgs_L of the lower arm semiconductor element 100b, respectively.

[0020] At time t0, when the signal at the output terminal OUT1H of the GDIC 200a of the upper arm drive circuit 20a changes from low to high, the gate-source voltage Vgs_H of the upper arm semiconductor element 100a begins to rise. At time t1, when the gate-source voltage Vgs_H of the upper arm semiconductor element 100a exceeds the gate threshold voltage Vth, the semiconductor element 100a begins to turn on, and the drain-source voltage Vds begins to decrease. A recovery voltage Vrr that fluctuates between times t3 and t4 is generated on the lower arm.

[0021] In waveform (F), the solid line indicates the recovery voltage Vrr in this embodiment. Meanwhile, the recovery voltage Vrr indicated by dashed line L1 indicates the recovery voltage in a conventional configuration in which the gate-source voltage Vgs_L is maintained at the Lo level to suppress gate surges. The amplitude of the oscillation component of the recovery voltage Vrr depends on the output capacitance Coss of the semiconductor device 100b and is proportional to 1 / √(Coss). In SiC semiconductor devices, the output capacitance Coss is gate voltage dependent; when a negative voltage is applied between the gate and source, the output capacitance Coss decreases, and when a positive voltage is applied, the output capacitance Coss increases. The dashed line L2 in waveform (G) indicates the gate-source voltage Vgs_L in a conventional configuration. When the gate-source voltage Vgs_L is as indicated by dashed line L2, the recovery voltage Vrr becomes as indicated by dashed line L1 in waveform (F).

[0022] In contrast, in this embodiment, a parallel circuit of the Zener diode ZD2 and resistor R2 is provided between the gate terminal of the semiconductor element 100b and the output terminal OUT2 of the Miller clamp function switching element S2 (see FIGS. 2 and 4). Therefore, the gate-source voltage Vgs_L rises during the period from time t3 to time t4, as shown in waveform (G). When the recovery voltage Vrr, shown by the solid line in waveform (F), is generated, a current Irss = Crss × dVrr / dt flows into the parallel circuit of the Zener diode ZD2 and resistor R2 (see FIG. 4). Then, as shown by the solid line in waveform (G), the gate-source voltage Vgs_L is clamped to the Zener voltage Vz2.

[0023] As described above, the Zener voltage Vz2 is set to be less than the gate threshold voltage Vth. Therefore, during the period from time t3 to t4, the gate-source voltage Vgs_L rises to the Zener voltage Vz2, thereby preventing false ignition and suppressing the recovery surge voltage. As a result, the EMC performance can be improved and the turn-on loss can be reduced.

[0024] The value of the resistor R2 connected in parallel with the Zener diode ZD2 is set, for example, as follows: In FIG. 4, if the Zener diode ZD2 is not present, the gate-source voltage Vgs_L is Vgs_L = Irss × (Rgoff × R2) / (Rgoff + R2), and the voltage value changes according to the change in current Irss over time. The resistor R2 can be set so that this voltage waveform does not fall below the Zener voltage Vz2. By setting the resistor R2 in this manner, the gate-source voltage Vgs_L during the period t3 to t4 is maintained at a constant value (= Vz2), as shown by the solid line in the waveform (G). The value of the resistor R1 on the upper arm side is set in the same way as the resistor R2.

[0025] In addition, if the value of Vgs_L = Irss × (Rgoff × R2) / (Rgoff + R2) is a value that sufficiently suppresses the recovery surge voltage and does not cause false ignition of the semiconductor element 100b, it is also possible to omit the Zener diode ZD2 for clamping the gate-source voltage Vgs_L.

[0026] (Variation 1) FIG. 6 is a diagram illustrating Variation 1 of the above-described embodiment. In Variation 1, only Zener diode ZD2 is provided between the gate terminal of semiconductor element 100b and output terminal OUT2 of Miller clamp function switching element S2. The Zener voltage Vz of Zener diode ZD2 is set to be less than the gate threshold voltage Vth of semiconductor element 100b, as in the case of FIG. 2. Note that Zener diode ZD1 is also provided in a similar configuration on the upper arm side. The other configurations are the same as the circuit configuration shown in FIG. 2.

[0027] In Modification 1, when both the output terminals OUT1L and OUT2 of the lower-arm switching elements S1L and S2 are at the potential of the gate negative power supply VEE, the Zener diode ZD2 is connected in parallel to the turn-off side gate resistor Rgoff. The current Irss generated when the upper arm is turned on flows into the turn-off side gate resistor Rgoff, and when the condition Irss × Rgoff > Vz2 is met, the current Irss also flows into the Zener diode ZD2. Therefore, the same effect of reducing the recovery surge voltage as in the circuit configurations shown in FIGS. 2 and 4 can be obtained.

[0028] The circuit configuration in Figure 6 does not use the Miller clamp function. In such a case, even if the resistors R1 and R2 are not provided as shown in Figure 6, the value of the gate-source voltage Vgs_L when the current Irss is generated can be clamped to the Zener voltage Vz2. As a result, the recovery surge voltage when the arm turns on can be reduced.

[0029] (Variation 2) FIG. 7 illustrates a second variation of the embodiment described above. In this variation, the GDIC 200 incorporates a Miller clamp function switching element S2 and a self-turn-on function switching element S3. The output terminal OUT2 of the Miller clamp function switching element S2 is connected to the gate terminals of the semiconductor elements (100a, 100b). The output terminal OUT3 of the upper arm self-turn-on function switching element S3 is connected to the gate terminal of the semiconductor element 100a via a parallel circuit consisting of a Zener diode ZD1 and a resistor R1. Similarly, the output terminal OUT3 of the lower arm self-turn-on function switching element S3 is connected to the gate terminal of the semiconductor element 100b via a parallel circuit consisting of a Zener diode ZD2 and a resistor R2. The remaining configuration is the same as the circuit configuration shown in FIG. 2.

[0030] In the second modification, when the pair of arms are turned on, the Miller clamp function switching element S2 is turned off and the self-turn-on function switching element S3 is turned on. As a result, when the pair of arms are turned on, the current Irss flows into the output terminals OUT1L and OUT3, and as in the above-described embodiment (see FIGS. 2 and 4), the gate-source voltages of the semiconductor elements (100a and 100b) are clamped to the Zener voltages of the Zener diodes (ZD1 and ZD2). Therefore, as in the above-described embodiment, the recovery surge voltage when the pair of arms are turned on can be reduced.

[0031] 2 and 4, for example, the combined gate resistance when semiconductor element 100a is turned off is the combined resistance of the turn-off side gate resistance Rgoff and resistor R1. Similarly, the combined gate resistance when semiconductor element 100b is turned off is the combined resistance of the turn-off side gate resistance Rgoff and resistor R2. Therefore, the turn-off time from when a turn-off command is input to GDIC 200 until the drain-source current Ids decreases to the turn-off current value (the current value at which semiconductor elements (100a, 100b) are turned off) is longer than in the conventional case where only the turn-off side gate resistance Rgoff is used for turn-off. As a result, the software dead time must be set longer than in the conventional case. This longer dead time period increases loss due to reverse conduction current during the dead time period.

[0032] In the second modification, a parallel circuit of Zener diode ZD1 and resistor R1 is provided at output terminal OUT3 of self-turn-on switching element S3, enabling the Miller clamp function to operate. Furthermore, by turning on Miller clamp switching element S2 at turn-off, the combined gate resistance is set to zero ohms, i.e., by maintaining low impedance between the gate and source, the turn-off time can be shortened. Therefore, there is no need to set a large software dead time as in the configuration of FIG. 2, and an increase in loss due to reverse conduction current can be prevented.

[0033] In the above-described embodiment and modified examples, a configuration has been described in which a Miller clamp function and a self-turn-on function are built into the GDIC 200. However, a configuration may also be adopted in which a switching element for the Miller clamp function or the self-turn-on function is provided as an external circuit of the GDIC 200, and a parallel circuit of Zener diodes (ZD1, ZD2) and resistors (R1, R2) is arranged between the switching element and the gate terminal of the semiconductor element (100a, 100b).

[0034] According to the embodiment and modified examples of the present invention described above, the following advantageous effects are achieved.

[0035] (1) As shown in FIG. 6, in a driver circuit (gate driver) 20 that drives gate-driven semiconductor elements 100a, 100b connected in series in upper and lower arms, for example, the lower arm driver circuit 20b includes a gate-on circuit (switching element S1H and turn-on side gate resistor Rgon) connected between the gate of the semiconductor element 100b and a gate positive power supply VCC2, a gate-off circuit (switching element S1L and turn-off side gate resistor Rgoff) connected between the gate and a gate negative power supply VEE, a switching element S2 that is connected between the gate and the gate negative power supply VEE and is turned on when the gate-on circuit (switching element S1H and turn-on side gate resistor Rgon) provided for the semiconductor element 100a on the opposite arm side (upper arm side) is turned on, and a Zener diode ZD2 connected in series to the switching element S2.

[0036] When the switching element S2 is turned on, the Zener diode ZD2 is connected in parallel to the turn-off gate resistor Rgoff. Therefore, the gate-source voltage Vgs_L when the current Irss is generated can be clamped to the Zener voltage Vz2, reducing the recovery surge voltage when the arm is turned on. As a result, it is possible to suppress the degradation of EMC (Electromagnetic Compatibility) performance and the increase in switching loss caused by the recovery surge voltage.

[0037] (2) In the above (1), as shown in Fig. 3 etc., the Zener voltages (Vz1, Vz2) of the Zener diodes (ZD1, ZD2) are set to be less than the gate threshold voltage Vth at which the semiconductor elements (100a, 100b) are turned on. This makes it possible to prevent false ignition and reduce the recovery surge voltage.

[0038] (3) In the above (2), as shown in FIGS. 2 and 4, a resistor R2 (R1) is further provided connected in parallel to the Zener diode ZD2 (ZD1). In FIG. 4, when a current Irss flows into the turn-off side gate resistor Rgoff and resistor R2 of the lower-arm drive circuit 20b, the gate-source voltage Vgs_L of the semiconductor element 100b rises to Vgs_L = Irss × (Rgoff × R2) / (Rgoff + R2). When the gate-source voltage Vgs_L exceeds the Zener voltage Vz2 of the Zener diode ZD2, the current Irss flows through the Zener diode ZD2, and the gate-source voltage Vgs_L is clamped to the Zener voltage Vz2. As a result, the recovery surge voltage can be reduced more than in the past.

[0039] (4) In the above (3), as shown in Fig. 7, a Miller clamp circuit is further provided that maintains a low impedance between the gate and source of the semiconductor elements (100a, 100b) when the semiconductor elements (100a, 100b) are turned off. For example, in the upper arm drive circuit 20a and the lower arm drive circuit 20b in Fig. 7, the Miller clamp function switching element S2 connected to the gate terminal of the semiconductor elements (100a, 100b) corresponds to the Miller clamp circuit.

[0040] In the example shown in Figure 7, the combined gate resistance during turn-off is the combined resistance of the turn-off side gate resistor Rgoff and resistor R1 or R2. Therefore, the turn-off time of the semiconductor elements (100a, 100b) is longer than in the conventional case where only the turn-off side gate resistor Rgoff is used for turn-off. However, by turning on the Miller clamp function switching element S2 during turn-off to maintain a low impedance between the gate and source, the turn-off time can be shortened. As a result, an increase in loss due to reverse conduction current can be prevented.

[0041] (5) In the above (1), the gate-driven semiconductor elements 100a and 100b connected in series by the upper and lower arms shown in Fig. 2 are SiC semiconductor elements, and the driver circuit 20, which is a gate drive device, drives the SiC semiconductor elements. Although the recovery surge voltage of SiC semiconductor elements is larger than that of Si semiconductor elements, etc., the recovery surge voltage can be reduced by using the driver circuit 20 described above.

[0042] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these, as long as the features of the invention are not impaired. Other embodiments that can be conceived within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0043] 1... inverter device, 2... motor, 3... battery, 10... three-phase switching arm, 20... driver circuit, 20a... upper arm drive circuit, 20b... lower arm drive circuit, 100a, 100b... semiconductor element, 200, 200a, 200b... GDIC, VCC2... gate positive power supply, VEE... gate negative power supply, Rgoff... turn-off side gate resistor, Rgon... turn-on side gate resistor, S1H, S1L, S2, S3... switching element, ZD1, ZD2... Zener diode

Claims

1. A gate drive device for driving gate-driven semiconductor elements connected in series in upper and lower arms, comprising: a gate-on circuit connected between the gate of the semiconductor element and a gate positive power supply; a gate-off circuit connected between the gate and a gate negative power supply; a switching element connected between the gate and the gate negative power supply and turned on when the gate-on circuit provided for the semiconductor element on the opposite arm is turned on; and a Zener diode connected in series to the switching element.

2. A gate driver according to claim 1, wherein the Zener voltage of the Zener diode is set to be lower than the gate threshold voltage at which the semiconductor element is turned on.

3. The gate driver according to claim 2, further comprising a resistor connected in parallel to said Zener diode.

4. A gate driver according to claim 3, further comprising a Miller clamp circuit that maintains a low impedance between the gate and source of the semiconductor element when the semiconductor element is turned off.

5. A gate drive device according to claim 1, wherein the gate drive type semiconductor elements connected in series by upper and lower arms are SiC semiconductor elements, and the gate drive device drives the SiC semiconductor elements.

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