Semiconductor device

Abstract

This semiconductor device comprises: a first chip; a second chip that is layered on the first chip so as to have an electrical connection with the first chip; a pad to which a first voltage is supplied; a first logic circuit that is provided on the first chip and operates on the basis of the first voltage from the pad; a regulator circuit that is provided either on the first chip or on the second chip and outputs a second voltage by adjusting the first voltage from the pad; and a second logic circuit that is provided on the second chip and operates on the basis of the second voltage from the regulator circuit.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] For example, Japanese Patent Application Laid-Open No. 2003-124222 discloses a technique for supplying power to an imaging device in a divided manner in order to reduce image noise.

[0003] JP 2023-53806 A

[0004] A semiconductor device used in an imaging device or the like may have multiple circuits that operate on different power supply voltages. If multiple power supply voltages corresponding to the multiple circuits are supplied from outside the semiconductor device, the number of pads increases according to the number of power supply voltages, which in turn increases the size of the device due to factors such as an increase in the semiconductor chip area.

[0005] One aspect of the present disclosure is to prevent the device from becoming large.

[0006] A semiconductor device according to one aspect of the present disclosure includes a first chip, a second chip stacked on the first chip so as to be electrically connected to the first chip, a pad to which a first voltage is supplied, a first logic circuit provided on the first chip and operating based on the first voltage from the pad, a regulator circuit provided on the first chip or the second chip and adjusting the first voltage from the pad to output a second voltage, and a second logic circuit provided on the second chip and operating based on the second voltage from the regulator circuit.

[0007] A semiconductor device according to one aspect of the present disclosure includes a pad to which a voltage is supplied, an analog circuit that operates based on the voltage from the pad, a regulator circuit that adjusts the voltage from the pad and outputs a first voltage, and a logic circuit that operates based on the first voltage from the regulator circuit.

[0008] 1 is a diagram showing an example of a schematic configuration of a part of an electronic device 100 in which a semiconductor device 2 according to an embodiment is used. A diagram showing an example of a schematic configuration of a part of the electronic device 100. A diagram showing a comparative example. A diagram showing a first modified example. A diagram showing a second modified example. A diagram showing a third modified example. A diagram showing a fourth modified example. A diagram showing a fifth modified example. A diagram showing an application example. A diagram showing an example of a schematic configuration of a chip 4. A diagram showing an example of a pixel circuit. A diagram showing an example of a layout of a chip 4. A diagram showing a comparative example. A diagram showing an example of a schematic configuration of a semiconductor device 2. A block diagram showing an example of a schematic configuration of a vehicle control system. An explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit. A diagram showing an example of a schematic configuration of an endoscopic surgery system. A block diagram showing an example of the functional configuration of a camera head and a CCU.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same elements are designated by the same reference numerals, and redundant description will be omitted.

[0010] The present disclosure will be described in the following order: 0. Introduction 1. Embodiment 2. Modifications 2.1 First Modification 2.2 Second Modification 2.3 Third Modification 2.4 Fourth Modification 2.5 Fifth Modification 3. Example of Application to an Imaging Device 4. Example of Chip Layout 5. Example of Adjustment of Regulator Circuit 6. Conclusion 7. Example of Application to a Moving Body 8. Example of Application to an Endoscopic Surgery System

[0011] 0. Introduction There is a demand for miniaturization of semiconductor devices. At the same time, semiconductor devices may contain multiple circuits that operate at different power supply voltages. Conventionally, pads were provided for each power supply voltage. Increasing the number of pads leads to an increase in chip area, which in turn leads to an increase in the size of the device. For example, if the semiconductor device is a solid-state imaging device (image sensor), there is also a concern about reflections.

[0012] There is also a known technique of stacking multiple chips so that they are electrically connected to each other. If each chip is manufactured using a different process, the power supply voltage may differ for each chip. Even if the same manufacturing process is used, the optimal power supply voltage may differ, resulting in a problem of reduced yield if the same power supply voltage is supplied. To address this, it is necessary to prepare different power supply voltages.

[0013] When a package for wire bonding is used, if the number of pads increases, it becomes necessary to take measures such as staggering the pads, which also leads to an increase in the chip area.

[0014] For example, at least some of the above-mentioned problems are addressed by the disclosed technology. As will be described in detail later, a power supply voltage is generated within the chip, and the generated power supply voltage is supplied to the corresponding circuit without going through a pad. An increase in the number of pads can be suppressed, and the associated wiring can also be reduced. An increase in chip area, and therefore an increase in the size of the device, can be suppressed. The above-mentioned problems such as a decrease in yield can also be addressed.

[0015] 1 is a diagram showing an example of a schematic configuration of a portion of an electronic device 100 in which a semiconductor device 2 according to an embodiment is used. The electronic device 100 includes a substrate 1 and a semiconductor device 2. The substrate 1 is, for example, a printed circuit board (PCB). The semiconductor device 2 is provided on the substrate 1.

[0016] The semiconductor device 2 includes a package 3 and a chip 4. The package 3 covers the chip 4 and is provided on the substrate 1. The chip 4 is a plurality of stacked semiconductor chips, and two chips are illustrated in FIG. 1. The first chip is referred to as chip 41 and the second chip is referred to as chip 42 and the same is illustrated.

[0017] The chip 41 and the chip 42 may be chips of different processes. For example, the process of the chip 41 may be a relatively high voltage process (high voltage process), and the process of the chip 42 may be a relatively low voltage process (low voltage process).

[0018] The chip 41 and the chip 42 may be collectively referred to simply as the chip 4 or each chip 4. An XYZ coordinate system is also shown in FIG. 1. The X-axis direction and the Y-axis direction (XY plane direction) correspond to the surface direction of each chip 4. The Z-axis direction corresponds to the thickness direction (stacking direction) of the chip 4. The same can be said for the surface direction and thickness direction of the substrate 1 and the package 3.

[0019] The chips 4 adjacent to each other in the stacking direction are stacked so as to be electrically connected to each other. In this example, the chip 42 is stacked on the chip 41 so as to be electrically connected to the chip 41. The electronic device 100 will be further described with reference to FIG. 2.

[0020] 2 is a diagram showing an example of a schematic configuration of a portion of the electronic device 100. The substrate 1, package 3, and chip 41 each include pads for electrical connection. The pads provided on the substrate 1 are referred to as pads 11. The pads provided on the package 3 are referred to as pads 31. The pads provided on the chip 41 are referred to as pads 411. These pads may be, for example, pads for wire bonding.

[0021] The pads 11 of the substrate 1 include a pad 11-1 and a pad 11-2. The pad 11-1 has a voltage VDD1 (first voltage). The voltage VDD1 is a DC power supply voltage used by the chip 41. The pad 202 has a voltage VSS. The voltage VSS is a DC reference voltage (e.g., a ground voltage) used in common by the chips 41 and 42.

[0022] The pads 31 of the package 3 include pads 31-1, 31-2, and 31-3. Pad 31-1 is electrically connected to pad 11-1 and has a voltage VDD1. Pads 31-2 and 31-3 are each electrically connected to pad 11-2 and have a voltage VSS. The voltage VSS of pad 31-2 is referred to as voltage VSS1. The voltage VSS of pad 31-3 is referred to as voltage VSS2.

[0023] The pads 411 of the chip 41 include a pad 411-1, a pad 411-2, and a pad 411-3. A voltage VDD1 is supplied to the pad 411-1, and a reference voltage is supplied to the pads 411-2 and 411-3.

[0024] Specifically, pad 411-1 is electrically connected to pad 31-1 and has a voltage VDD1, pad 411-2 is electrically connected to pad 31-2 and has a voltage VSS1, and pad 411-3 is electrically connected to pad 31-3 and has a voltage VSS2.

[0025] As described above, the chip 41 and the chip 42 are electrically connected to each other. For example, the surfaces (contact surfaces) of the chip 41 and the chip 42 that contact each other each have a conductive terminal (e.g., electrode wiring) exposed on that surface. Corresponding terminals of the chip 41 and the chip 42 are joined together, thereby achieving electrical connection between the chip 41 and the chip 42.

[0026] A terminal of the chip 41 is referred to as a terminal C1, and a terminal of the chip 42 is referred to as a terminal C2. The corresponding terminals C1 of the chip 41 and C2 of the chip 42 are electrically connected to each other.

[0027] Specifically, the terminal C1 of the chip 41 includes a terminal C1-1 and a terminal C1-2. The terminal C2 of the chip 42 includes a terminal C2-1 and a terminal C2-2. The terminal C2-1 of the chip 42 is electrically connected to the terminal C1-1 of the chip 41. The terminal C2-22 of the chip 42 is electrically connected to the terminal C1-2 of the chip 41.

[0028] The chip 4 will be further described. The chip 4 includes a logic circuit 5, a regulator circuit 6, and an LV circuit 7.

[0029] The logic circuit 5, as its name suggests, is configured to execute, for example, various logical operations. A logic circuit 5 is provided on each of the chips 41 and 42. The logic circuit 5 provided on the chip 41 is referred to as logic circuit 5-1 and is illustrated. The logic circuit 5 provided on the chip 42 is referred to as logic circuit 5-2 and is illustrated.

[0030] The logic circuit 5-1 of the chip 41 operates based on the voltage VDD1 from the pad 11-1. In this example, the logic circuit 5-1 is electrically connected between the pad 411-1 and the pad 411-2, and operates using the voltage VDD1 as a power supply voltage. The logic circuit 5-2 of the chip 42 will be described later.

[0031] The regulator circuit 6 adjusts the input DC voltage and outputs the DC voltage. The regulator circuit 6 can also be called a voltage conversion circuit, etc. The regulator circuit 6 is provided on the chip 41 or the chip 42, adjusts the voltage VDD1 from the pad 11-1, and outputs a voltage VDD2 (second voltage).

[0032] The voltage VDD2 is a voltage different from the voltage VDD1, and is, for example, a voltage lower than the voltage VDD1. As an example of the voltage values, the voltage VDD1 may be about 1.1V, and the voltage VDD2 may be about 0.8V.

[0033] An example of the regulator circuit 6 is an LDO (Low Drop Out) circuit, but the regulator circuit 6 is not limited to this and various known circuits may be employed.

[0034] 2, the regulator circuit 6 is provided on the chip 41. The regulator circuit 6 is electrically connected between the pad 411-1 and the terminal C1-1, adjusts the voltage VDD1 from the pad 411-1, and outputs the voltage VDD2 to the terminal C1-1. The terminal C1-1 has the voltage VDD2. The terminal C2-1, which is electrically connected to the terminal C1-1, also has the voltage VDD2.

[0035] Terminal C1-2 is electrically connected to pad 411-3 and has voltage VSS2. Terminal C2-2, electrically connected to C2-1, also has voltage VSS2.

[0036] The logic circuit 5-2 of the chip 42 operates based on the voltage VDD2 from the regulator circuit 6. In the example shown in Fig. 2, the logic circuit 5-2 is electrically connected between the terminal C2-1 and the terminal C2-2, and operates using the voltage VDD2 as the power supply voltage.

[0037] The LV circuit 7 is a level shift circuit (level shifter) used to shift the level of the signal voltage output by the logic circuit 5. The LV circuit 7 is provided on the chip 41 or the chip 42, and shifts the level of the signal voltage from the logic circuit 5-1 to the logic circuit 5-2 based on the voltage VDD2 from the regulator circuit 6.

[0038] The signal voltage before level shifting by the LV circuit 7 has a voltage level suitable for use by the logic circuit 5-1, which operates based on the voltage VDD1, and the signal voltage after level shifting has a voltage level suitable for use by the logic circuit 5-2, which operates based on the voltage VDD2.

[0039] 2, the LV circuit 7 is provided on the chip 41. The LV circuit 7 is electrically connected between the regulator circuit 6 and the pad 411-2.

[0040] In the semiconductor device 2 described above, the regulator circuit 6 adjusts the voltage VDD1 from the pad 411-1 and outputs the voltage VDD2. The logic circuit 5-2 operates based on the voltage VDD2 from the regulator circuit 6. Since there is no need to supply the voltage VDD2 to the semiconductor device 2 from outside the semiconductor device 2 (for example, from the substrate 1), there is no need to provide a pad for the voltage VDD2. This makes it possible to suppress an increase in chip area and suppress an increase in the size of the device. A comparative example will also be used for explanation.

[0041] 3 is a diagram showing a comparative example. Electronic device 100E according to the comparative example includes substrate 1E and semiconductor device 2E. Semiconductor device 2E includes package 3E and chip 4E. Chip 4E includes chip 41E and chip 42.

[0042] The electronic device 100E differs from the electronic device 100 (FIG. 2) particularly in that the semiconductor device 2E does not include the regulator circuit 6. The voltage VDD2 is supplied to the semiconductor device 2 from outside the semiconductor device 2, i.e., from the substrate 1. A pad for this purpose is further provided.

[0043] Specifically, the substrate 1E further includes a pad 11E. The pad 11E has a voltage VDD2. The package 3E further includes a pad 31E. The pad 31E is electrically connected to the pad 11E and has a voltage VDD2. The chip 41E of the semiconductor device 2E further includes a pad 411E. The pad 411E is electrically connected to the pad 31E and has a voltage VDD2. The terminal C1-1 is electrically connected to the pad 411E and has a voltage VDD2. The terminal C2-2, which is electrically connected to the terminal C1-1, also has a voltage VDD2.

[0044] As described above, the electronic device 100E requires additional pads 11E, 31E, and 411E compared to the electronic device 100 (FIG. 2). This increases the number of pads. For example, the chip area increases. This problem is addressed by the above-described embodiment (FIG. 2).

[0045] 2, the regulator circuit 6 that outputs the voltage VDD2 is provided on the chip 41. For example, even if the process of the chip 41 is a high-voltage process and the voltage VDD1 is higher than the voltage VDD2, the high voltage VDD1 is not supplied to the chip 42. This has the advantage of making it easier to design the withstand voltage of the chip 42.

[0046] In the above embodiment, the voltage VSS is supplied as voltages VSS1 and VSS2, but these may be merged and supplied as a single voltage VSS. For example, the pads 411-2 and 411-3 may be shared, thereby further reducing the number of pads.

[0047] 2. Modifications Several modifications based on the technology described above will be described. Note that the configuration of the above-described embodiment and the configuration of each modification described below may be appropriately combined and used within a range where no contradiction exists.

[0048] 4 is a diagram showing a first modified example. The first modified example differs from the previously described embodiment (FIG. 2) in that the regulator circuit 6 is provided on a chip 42.

[0049] Terminal C1-1 of chip 41 is electrically connected to pad 411-1 and has voltage VDD1. Terminal C2-1 of chip 42 is electrically connected to terminal C1-1 and has voltage VDD1. Regulator circuit 6 is electrically connected between terminal C2-1 and logic circuit 5-2, adjusts voltage VDD1 from terminal C2-1 (and further from pad 411-1), and outputs voltage VDD2 to logic circuit 5-2. Logic circuit 5-2 operates based on voltage VDD2 from regulator circuit 6.

[0050] To supply voltage VDD2 from regulator circuit 6 to the LV circuit 7 of chip 41, terminal C1 of chip 41 includes terminal C1-3, and terminal C2 of chip 42 includes terminal C2-3. Terminals C1-3 and C2-3 are electrically connected to each other. Regulator circuit 6 is also electrically connected between terminals C2-1 and C2-3, and outputs voltage VDD2 to terminal C2-3 as well. Terminal C2-3 has voltage VDD2. Terminal C1-3, which is electrically connected to terminal C2-3, also has voltage VDD2. LV circuit 7 is electrically connected between terminal C1-3 and pad 411-2.

[0051] In the first modification, there is no need to provide a pad for the voltage VDD2, so an increase in chip area and an increase in the size of the device can be suppressed. Furthermore, since the logic circuit 5-2 and the regulator circuit 6 are provided on the same chip 42, it is possible to perform a test on the chip 42 alone, including the regulator circuit 6, for example.

[0052] 5 shows a second modification example, which differs from the first modification example (FIG. 4) described above in that the chip 41 further includes a stabilizing regulator circuit 60.

[0053] The stabilizing regulator circuit 60 is electrically connected between the pad 411-1 and the logic circuit 5-1, and adjusts the voltage VDD1 from the pad 411-1 to output the voltage VDD1. An example of the stabilizing regulator circuit 60 is an LDO circuit. The logic circuit 5-1 operates based on the voltage VDD1 from the stabilizing regulator circuit 60.

[0054] The voltage VDD1 output by the stabilizing regulator circuit 60 may be the optimum operating voltage for the logic circuit 5-1. For example, if the optimum operating voltage for the logic circuit 5-1 varies for each manufactured chip 41, supplying the voltage VDD1 from the pad 411-1 to the logic circuit 5-1 as is may result in the logic circuit 5-1 not operating at its optimum operating voltage. By having the stabilizing regulator circuit 60 supply the voltage VDD1 to the logic circuit 5-1, the possibility that the logic circuit 5-1 will operate at its optimum operating voltage can be increased.

[0055] In the second modification, there is no need to provide a pad for the voltage VDD2, which prevents an increase in chip area and an increase in the size of the device. Furthermore, by using a stabilizing regulator circuit 60 to supply the voltage VDD1 to the logic circuit 5-1, it becomes possible to provide a power supply that also addresses variations. The voltage VDD1 supplied to the logic circuit 5-1 can be made closer to the optimum operating voltage for the logic circuit 5-1.

[0056] 6 is a diagram showing a third modification example, which differs from the first modification example (FIG. 4) described above in that the LV circuit 7 is provided on a chip 42.

[0057] The LV circuit 7 is electrically connected between the regulator circuit 6 and the terminal C2-2. Since the regulator circuit 6 and the LV circuit 7 are provided on the same chip 42, there is no need to supply the voltage VDD2 output by the regulator circuit 6 to the chip 41.

[0058] 7 and 8 are diagrams showing a fourth modification. This modification differs from the previously described embodiment (FIGS. 1 and 2) in that the semiconductor device 2 further includes a chip 43.

[0059] Chip 43 is a third chip stacked on chip 42 on the opposite side of chip 42 from chip 41 so as to be electrically connected to chip 42. For example, the surfaces (contact surfaces) of chips 42 and 43 that contact each other each have a conductive terminal exposed on the surface. Corresponding terminals of chip 42 and chip 43 are joined together, thereby achieving electrical connection between chip 42 and chip 43. The process for chip 43 may be different from the process for chip 42. For example, the process for chip 43 may be a lower voltage process than the process for chip 42.

[0060] As before, the terminal of chip 41 will be referred to as terminal C1. As before, the terminal of chip 42 will be referred to as terminal C2. As before, the terminal of chip 43 will be referred to as terminal C3. Corresponding terminals C1 of chip 41 and terminals C2 of chip 42 are electrically connected to each other, and corresponding terminals C2 of chip 42 and terminals C3 of chip 43 are electrically connected to each other.

[0061] 8, the pads 31 of the package 3 further include a pad 31-4. The pad 31-4 is electrically connected to the pad 11-2 and has a voltage VSS. The voltage VSS held by the pad 31-4 will be referred to as a voltage VSS3. The pads 411 of the chip 41 further include a pad 411-4. The pad 411-4 is electrically connected to the pad 31-4 and has a voltage VSS3.

[0062] Terminal C1 of chip 41 further includes terminal C1-4. Terminal C2 of chip 42 further includes terminal C2-4, terminal C2-5, and terminal C2-6. Terminal C3 of chip 43 includes terminal C3-5 and terminal C3-6. In this example, terminal C3-5 of chip 43 is electrically connected to terminal C2-5 of chip 42. Terminal C3-6 of chip 43 is electrically connected to terminal C2-6 of chip 42.

[0063] Terminal C1-4 is electrically connected to pad 411-4 and has a voltage VSS3. Terminal C2-4, electrically connected to terminal C1-4, also has a voltage VSS3. Terminal C2-6 is electrically connected to terminal C2-4 and has a voltage VSS3. Terminal C3-6, electrically connected to terminal C2-6, also has a voltage VSS3.

[0064] With the addition of chip 43, a regulator circuit 6 is also added. The regulator circuit 6 described so far is illustrated as regulator circuit 6-1 in FIG. 8. In this example, regulator circuit 6-1 is provided on chip 41. The added regulator circuit 6 is illustrated as additional regulator circuit 6-2.

[0065] The additional regulator circuit 6-2 is provided on chip 42 or chip 43, and adjusts the voltage VDD2 from the regulator circuit 6-1 to output a voltage VDD3 (third voltage). The voltage VDD3 is a voltage different from the voltage VDD2, and is, for example, a voltage lower than the voltage VDD2. As an example of the voltage values, the voltage VDD2 may be about 0.8 V, and the voltage VDD3 may be about 0.75 V.

[0066] 8, the additional regulator circuit 6-2 is provided on the chip 42. Specifically, the additional regulator circuit 6-2 is electrically connected between the terminal C2-1 and the terminal C2-5, adjusts the voltage VDD2 from the terminal C2-1, and outputs the voltage VDD3 to the terminal C2-5. The terminal C2-5 has the voltage VDD3. The terminal C3-5, which is electrically connected to the terminal C2-5, also has the voltage VDD3.

[0067] A logic circuit 5 is also provided on chip 43. The logic circuit 5 provided on chip 43 is illustrated and referred to as logic circuit 5-3. Logic circuit 5-3 is a third logic circuit that operates based on voltage VDD3 from stabilizing regulator circuit 60. In this example, logic circuit 5-3 is connected between terminals C3-5 and C3-6, and operates using voltage VDD3 as a power supply voltage.

[0068] With the addition of chip 43, an LV circuit 7 is also added. The LV circuit 7 described so far is illustrated as LV circuit 7-1 in FIG. 8. In this example, LV circuit 7-1 is provided on chip 42. The added LV circuit 7 is illustrated as additional LV circuit 7-2.

[0069] The additional LV circuit 7-2 is provided on chip 42 or chip 43, and shifts the level of the signal voltage from logic circuit 5-2 to logic circuit 5-3 based on voltage VDD3 from the additional regulator circuit 6-2. The signal voltage before the level shift by the additional LV circuit 7-2 has a voltage level suitable for use by the logic circuit 5-2, which operates based on voltage VDD2. The signal voltage after the level shift has a voltage level suitable for use by the logic circuit 5-3, which operates based on voltage VDD3.

[0070] 8, the additional LV circuit 7-2 is provided on the chip 42. Specifically, the additional LV circuit 7-2 is electrically connected between the additional regulator circuit 6-2 and the terminal C2-2.

[0071] According to the fourth modification, there is no need to supply the voltages VDD2 and VDD3 to the semiconductor device 2 from outside the semiconductor device 2, and therefore there is no need to provide pads for the voltages VDD2 and VDD3. This prevents an increase in chip area and prevents the device from becoming larger. By using three chips 4, chips 41 to 43, it is more likely that multi-functionality and high functionality can be achieved than when using two chips 4, for example, chips 41 and 42.

[0072] Of course, four or more chips 4 may be used, which can contribute to further multi-functionality and high functionality. Even in this case, by generating the power supply voltage with the regulator circuit 6 in the chip 4, an increase in the number of power supply pads can be suppressed.

[0073] 2.5 Fifth Modification Figure 9 is a diagram showing a fifth modification. As in the previously described embodiment (Figure 2), the number of chips 4 is two, chip 41 and chip 42. Chip 41 further includes an analog circuit 8. The analog circuit 8 is as its name suggests, and is configured to perform, for example, various analog calculations.

[0074] In this example, pad 11-1 of substrate 1 has voltage VDD_ANA. Voltage VDD_ANA is a power supply voltage used by analog circuit 8 of chip 41. Voltage VDD_ANA is supplied to pad 411-1 of chip 41. That is, pad 31-1 of package 3, which is electrically connected to pad 11-1, has voltage VDD_ANA, and pad 411-1 of chip 41, which is connected to pad 31-1, also has voltage VDD_ANA.

[0075] The analog circuit 8 operates based on the voltage VDD_ANA from the pad 411-1. In this example, the analog circuit 8 is electrically connected between the pad 411-1 and the pad 411-2, and operates using the voltage VDD_ANA as a power supply voltage.

[0076] Two regulator circuits 6 are provided on the chip 4. To be able to distinguish between the regulator circuits 6, they are illustrated as regulator circuit 6-1-1 and regulator circuit 6-1-2.

[0077] The regulator circuit 6-1-1 is provided on the chip 41 and adjusts the voltage VDD_ANA from the pad 411-1 to output the voltage VDD1. The voltage VDD1 is a different voltage from the voltage VDD_ANA, and is, for example, a lower voltage than the voltage VDD_ANA. As an example of the voltage values, the voltage VDD_ANA may be about 3.3 V, and the voltage VDD1 may be about 1.1 V.

[0078] Specifically, the regulator circuit 6-1-1 is electrically connected between the pad 411-1 and the logic circuit 5-1, adjusts the voltage VDD_ANA from the pad 411-1, and outputs the voltage VDD1 to the logic circuit 5-1. The logic circuit 5-1 is electrically connected between the regulator circuit 6-1-1 and the pad 411-2, and operates using the voltage VDD1 as a power supply voltage.

[0079] The regulator circuit 6-1-2 differs from the regulator circuit 6 of the previously described embodiment (FIG. 2) in that the source of the voltage VDD1 is the regulator circuit 6-1-1 rather than the pad 411-1. The regulator circuit 6-1-2 is provided on the chip 41 or 42, and adjusts the voltage VDD1 from the regulator circuit 6-1-1 to output the voltage VDD2. In this example, the regulator circuit 6-1-2 is provided on the chip 41. The regulator circuit 6-1-2 is connected between the regulator circuit 6-1-1 and C1-1, adjusts the voltage VDD1 from the regulator circuit 6-1-1, and outputs the voltage VDD2 to the terminal C1-1.

[0080] Other parts may be the same as those in the previous embodiment (FIG. 2), and the description thereof will be omitted.

[0081] According to the fifth modification, the voltage VDD1 can be generated by utilizing the voltage VDD_ANA. Since there is no need to supply the voltage VDD1 to the semiconductor device 2 from outside the semiconductor device 2, there is no need to provide a pad for the voltage VDD1. This can further enhance the effect of suppressing an increase in chip area and an increase in the size of the device.

[0082] 3. Example of Application to an Imaging Device One specific example of the semiconductor device 2 is an imaging device, which will be described with reference to FIGS.

[0083] FIG. 10 is a diagram showing an application example. As shown in FIG. 10, chip 4 further includes chip 40 in addition to chip 41 and chip 42 described above. Chip 40 is stacked on chip 41 so as to be electrically connected to chip 41 on the side opposite chip 42 across chip 41. Chip 40 is a pixel chip and includes multiple photoelectric conversion units (described later). When chips 40 to 42 are not particularly distinguished from one another, they are also simply referred to as chip 4. Chip 4 will be described with reference to FIGS. 11 and 12.

[0084] FIG. 11 is a diagram showing an example of the schematic configuration of the chip 4. The chip 4 is a solid-state imaging device (also called an image sensor, etc.). Each element of the chip 4 is provided, for example, in and on a silicon semiconductor substrate. The chip 4 includes a pixel array section 9, as well as peripheral circuits and signal lines. Examples of the peripheral circuits are indicated by reference numerals: a control circuit 101, a vertical drive circuit 102, a column signal processing circuit 103, a horizontal drive circuit 104, and an output circuit 105. Examples of the wiring are indicated by reference numerals: a signal line 106, a signal line 107, and a signal line 108.

[0085] The pixel array unit 9 includes a plurality of pixels 90. The plurality of pixels 90 are arranged in a two-dimensional array. In this example, the X-axis direction corresponds to the row direction of the array, for example, the lateral direction (horizontal direction) of the chip 4. The Y-axis direction corresponds to the column direction of the array, for example, the longitudinal direction (vertical direction) of the chip 4. The positive Z-axis direction and the negative Z-axis direction are also referred to as the upward direction and downward direction.

[0086] The pixel array unit 9 detects incident light. The incident light here may be light traveling in the negative direction of the Z axis.

[0087] The pixel 90 includes a photoelectric conversion unit. The photoelectric conversion unit generates an electric charge according to the amount of incident light. An example of the photoelectric conversion unit is a photodiode (PD). A circuit is also provided that generates and outputs a voltage signal (pixel signal) according to the amount of electric charge generated in the photoelectric conversion unit. The pixel 90 may be interpreted as including such a circuit, and in this case, the pixel 90 may also be called a pixel circuit.

[0088] The control circuit 101 receives data instructing an input clock, an operation mode, etc., and outputs data such as internal information of the chip 4. Based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock, the control circuit 101 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 102, the column signal processing circuit 103, the horizontal drive circuit 104, etc. The control circuit 101 inputs (supplies) these generated signals to the vertical drive circuit 102, the column signal processing circuit 103, the horizontal drive circuit 104, etc.

[0089] The vertical drive circuit 102 includes, for example, a shift register. The vertical drive circuit 102 is connected to the pixel array unit 9 via a plurality of signal lines 106 (horizontal signal lines) extending in the row direction (X-axis direction) of the pixels 90. Each signal line 106 extends, for example, for each pixel row, and each signal line 106 may include a plurality of signal lines. The vertical drive circuit 102 supplies a drive signal (for example, a pulse signal) for driving the pixels 90 to a selected signal line 106.

[0090] Driving the pixels 90 by the vertical drive circuit 102 includes driving pixel transistors (transistors 91 to 94 in FIG. 12 ) described below. The pixel transistors are driven to output voltage signals (pixel signals) corresponding to the amount of charge generated in the photoelectric conversion units in the pixels 90 to corresponding signal lines 107 among a plurality of signal lines 107 (vertical signal lines) extending in the column direction (Y-axis direction) of the pixels 90.

[0091] The column signal processing circuits 103 are connected to the pixel array unit 9 via signal lines 107. Each signal line 107 may include a plurality of signal lines. The column signal processing circuits 103 are arranged, for example, for each pixel column, and perform signal processing such as noise removal on pixel signals from one row of pixels 90 for each pixel column. The column signal processing circuits 103 perform signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels 90, signal amplification, and AD (Analog to Digital) conversion. A horizontal selection switch (not shown) may be connected between the output stage of the column signal processing circuit 103 and the signal line 107.

[0092] The horizontal drive circuit 104 includes, for example, a shift register. The horizontal drive circuit 104 sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 103 in turn, and causes each of the column signal processing circuits 103 to output a pixel signal to a signal line 108.

[0093] The output circuit 105 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuits 103 through the signal line 108, and outputs the processed signals. For example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. are performed on the pixel signals.

[0094] Fig. 12 is a diagram showing an example of a pixel circuit. The photoelectric conversion unit included in pixel 90 is shown as photoelectric conversion unit PD1. As mentioned above, photoelectric conversion unit PD1 generates electric charges according to the amount of incident light. In Fig. 12, photoelectric conversion unit PD1 is shown as a photodiode with an anode connected to GND (ground).

[0095] Elements of the circuit (pixel circuit) provided around the photoelectric conversion unit PD1 are exemplified by a plurality of pixel transistors and a floating diffusion 95. The plurality of pixel transistors are exemplified by transistors 91 to 94, each of which is given a reference numeral. When no particular distinction is made between these, they are simply referred to as transistors or individual transistors.

[0096] In the following description, when a transistor is connected between two elements, it means that one of the source and drain of the transistor is connected to one element, and the other of the source and drain is connected to the other element.

[0097] The transistor 91 is provided between the photoelectric conversion unit PD1 and the floating diffusion 95. The transistor 91 is a transfer transistor that transfers the charge in the photoelectric conversion unit PD1 to the floating diffusion 95. The gate electrode of the transistor 91 is connected to a corresponding signal line 106. A control signal from the signal line 106 controls the conduction and non-conduction between the drain and source of the transistor 91 (turning the transistor 91 on and off). When the transistor 91 is on, the charge in the photoelectric conversion unit PD1 is transferred to the floating diffusion 95 via the transistor 91.

[0098] The floating diffusion 95 accumulates the charge transferred from the photoelectric conversion unit PD1 by the transistor 91, and generates a voltage signal according to the accumulated charge.

[0099] The transistor 92 is connected between the floating diffusion 95 and a node VDD. The node VDD has, for example, a voltage (power supply voltage) required for the operation of each transistor. The transistor 92 is a reset transistor that drains the charge in the floating diffusion 95. The gate electrode of the transistor 92 is connected to a corresponding signal line 106. The on / off state of the transistor 92 is controlled by a control signal from the signal line 106. When the transistor 92 is on, the charge in the floating diffusion 95 is drained to the node VDD via the transistor 92.

[0100] The transistor 93 is connected between the node VDD and the transistor 94. The gate of the transistor 93 is connected to the floating diffusion 95. The transistor 93 can also be called an amplifying transistor that amplifies and outputs the voltage generated in the floating diffusion 95.

[0101] The transistor 94 is connected between the transistor 93 and a signal line 107. The transistor 94 can also be called a selection transistor that selectively outputs the output voltage of the transistor 93 to the signal line 107. The gate electrode of the transistor 94 is connected to the corresponding signal line 106. The on / off of the transistor 94 is controlled by a control signal from the signal line 106. When the transistor 94 is on, the output voltage of the transistor 93 is output to the signal line 107 via the transistor 94. This voltage signal becomes a pixel signal.

[0102] 11, pixels 90 having the above-described configuration, for example, are arranged in a two-dimensional array to form a pixel array unit 9. Regarding the relationship with chips 40 to 42 (FIG. 10), for example, the pixel array unit 9 is provided on chip 40. Peripheral circuits are provided on chips 41 and 42. A solid-state imaging device having a three-chip stacked structure is obtained.

[0103] 13 is a diagram showing an example of the layout of chip 4. As described above, chip 40 includes a pixel array unit 9. The power supply wiring included in chip 41 and chip 42 is shown as power supply wiring L1 and power supply wiring L2.

[0104] Chip 40 is configured so that pads 411 of chip 41 can be accessed from outside chip 40. For example, holes are formed in portions of chip 40 corresponding to pads 411, and wires are bonded to pads 411 of chip 41 through the holes.

[0105] It should be noted that a pad equivalent to pad 411 may be provided on chip 40, and chip 41 may be electrically connected to that pad via chip 40. To the extent that there is no contradiction, such a pad provided on chip 40 may also be considered to be included in pad 411.

[0106] As mentioned above, the chip 41 and the chip 42 include terminals C1 and C2 for electrical connection with each other, and corresponding terminals C1 and C2 are joined to each other. In Figure 13, terminal C1-1 of the terminals C1 of the chip 41 is indicated with a reference numeral. Also, terminal C2-1 of the terminals C2 of the chip 42 is indicated with a reference numeral.

[0107] In this example, the regulator circuit 6 is provided on the chip 41. In this case, the terminals C1-1 and C2-1 are terminals for supplying the voltage VDD2 output by the regulator circuit 6 from the chip 41 to the chip 42, as previously described with reference to FIG.

[0108] As previously explained with reference to Figure 4 etc., the regulator circuit 6 may be provided on the chip 42, in which case the terminals C1-1 and C2-1 are terminals for supplying the voltage VDD1 input to the regulator circuit 6 from the chip 41 to the chip 42.

[0109] When the chips 41 and 42 are viewed in a plan view (when viewed in the Z-axis direction in FIG. 10), the regulator circuit 6 is disposed near the terminals C1-1 and C2-1. For example, when viewed in a plan view, the regulator circuit 6 is disposed adjacent to the terminals C1-1 and C2-1. In this way, the regulator circuit 6 can be disposed according to the positions of the terminals C1-1 of the chip 41 and the terminals C2-1 of the chip 42, allowing for flexible power supply from the chip 41 to the chip 42. A comparative example will also be used for explanation.

[0110] FIG. 14 is a diagram showing a comparative example. The chip 4E according to the comparative example differs from the chip 4 (FIG. 13) in that it includes chips 40E and 41E instead of chips 40 and 41. The pads 411E described above with reference to FIG. 3 are provided on the chip 41. The chip 40E is formed so that the pads 411E of the chip 41 are also accessible from outside the chip 4E. This increases the area of ​​the chips 40E and 41E. This problem is addressed by the embodiment described above (FIG. 13).

[0111] 5. Example of Regulator Circuit Adjustment The optimum power supply voltage for the logic circuit 5 may differ for each manufactured chip 4. In one embodiment, the regulator circuit 6 may be adjusted so that the regulator circuit 6 outputs the optimum power supply voltage for the logic circuit 5. This will be described with reference to FIG. 15 .

[0112] 15 is a diagram showing an example of a schematic configuration of the semiconductor device 2. Of the components described above, the diagram shows a logic circuit 5-1, a logic circuit 5-2, and a regulator circuit 6. As elements related to the adjustment of the regulator circuit 6, the semiconductor device 2 further includes an oscillator circuit 10, a control circuit 12, and a ROM 13.

[0113] The oscillator circuit 10 is provided on the same chip as the logic circuit 5. An example of the oscillator circuit 10 is a ring oscillator (ROSC). In the example shown in FIG. 15, the oscillator circuit 10 includes an oscillator circuit 10-1 and an oscillator circuit 10-2. The oscillator circuit 10-1 is provided on the same chip (chip 41) as the logic circuit 5-1 and is formed by the same process as the logic circuit 5-1. For example, the oscillator circuit 10-1 includes transistors and the like formed by the same process as the logic circuit 5-1. Similarly, the oscillator circuit 10-2 is provided on the same chip (chip 42) as the logic circuit 5-2 and is formed by the same process as the logic circuit 5-2.

[0114] The control circuit 12 controls the voltage output by the regulator circuit 6 based on the oscillation frequency of the oscillator circuit 10. For example, the voltage output by the regulator circuit 6 to the logic circuit 5-2 (the voltage VDD2 described above) is controlled. In the configuration of FIG. 5 described above, the voltage output by the stabilizing regulator circuit 60 (FIG. 5) to the logic circuit 5-1 (the voltage VDD1) may also be controlled.

[0115] For example, the oscillation frequency of the oscillator circuit 10 is measured during pre-shipment testing of the semiconductor device 2. This oscillation frequency indicates the quality of the chip 4 and further the quality of the logic circuit 5 provided on the same chip 4 as the oscillator circuit 10. From the measurement results of the oscillation frequency, the optimal power supply voltage for the logic circuit 5 can be determined.

[0116] The control circuit 12 writes the value of the optimal power supply voltage for the logic circuit 5 into the ROM 13 as the set value of the voltage to be output by the regulator circuit 6. The ROM 13 may be, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory). The EEPROM may be an OTP (One Time Programmable ROM). During normal operation of the semiconductor device 2, the set value of the voltage stored in the ROM 13 is read, and the control circuit 12 controls the regulator circuit 6 based on the read voltage value.

[0117] For example, as described above, the regulator circuit 6 is adjusted so that it outputs an optimum power supply voltage for the logic circuit 5. Note that the control circuit 12 may control the regulator circuit 6 based on the oscillation frequency of the oscillator circuit 10 each time normal operation is started. In this case, the voltage value may be set in a register or the like. Setting during pre-shipment testing or the like is not necessary, and the ROM 13 may be omitted.

[0118] The configuration is not limited to the above, and any method or configuration that can adjust the output voltage of the regulator circuit 6 by understanding the performance of the logic circuit 5 provided on the chip 4 may be adopted.

[0119] 6. Conclusion The technology described above can be specified, for example, as follows. One of the disclosed technologies is a semiconductor device 2. As described with reference to FIGS. 1, 2, 4 to 8, 10 to 13, and 15, the semiconductor device 2 includes a chip 41 (first chip), a chip 42 (second chip) stacked on the chip 41 so as to be electrically connected to the chip 41, a pad 411-1 to which a voltage VDD1 (first voltage) is supplied, a logic circuit 5-1 (first logic circuit) provided on the chip 41 and operating based on the voltage VDD1 from the pad 411-1, a regulator circuit 6 provided on the chip 41 or the chip 42 and regulating the voltage VDD1 from the pad 411-1 to output a voltage VDD2 (second voltage), and a logic circuit 5-2 provided on the chip 42 and operating based on the voltage VDD2 from the regulator circuit 6. For example, the voltage VDD2 may be lower than the voltage VDD1. The regulator circuit 6 may be an LDO circuit.

[0120] According to the semiconductor device 2 described above, the regulator circuit 6 adjusts the voltage VDD1 from the pad 411-1 and outputs the voltage VDD2. The logic circuit 5-2 operates based on the voltage VDD2 from the regulator circuit 6. Since there is no need to supply the voltage VDD2 to the semiconductor device 2 from outside the semiconductor device 2, there is no need to provide a pad for the voltage VDD2. This helps prevent an increase in chip area and an increase in the size of the device.

[0121] 2 and the like, the regulator circuit 6 may be provided on the chip 41. In this case, for example, the voltage VDD1 is not supplied to the chip 42, which has the advantage of making it easier to design a high voltage tolerance.

[0122] 4 and the like, the regulator circuit 6 may be provided on the chip 42. In this case, the logic circuit 5-2 and the regulator circuit 6 are provided on the same chip 42, so that it is possible to perform a test on the chip 42 alone, including the regulator circuit 6, for example.

[0123] 5 and other figures, the semiconductor device 2 includes a stabilization regulator circuit 60 that is provided on the chip 41 and adjusts the voltage VDD1 from the pad 411-1 to output the voltage VDD1, and the logic circuit 5-1 may operate based on the voltage VDD1 from the stabilization regulator circuit 60. This enables power supply that also addresses variations. The voltage VDD1 supplied to the logic circuit 5-1 can be made closer to the optimum operating voltage for the logic circuit 5-1.

[0124] As described with reference to FIGS. 2 and 4 to 6 , the semiconductor device 2 may include an LV circuit 7 (level shift circuit) provided on the chip 41 or 42, which shifts the level of the signal voltage from the logic circuit 5-1 to the logic circuit 5-2 based on the voltage VDD2 from the regulator circuit 6. The LV circuit 7 may also be operated based on the voltage VDD2 output by the regulator circuit 6. For example, as described with reference to FIGS. 2 , 4 , and 5 , the LV circuit 7 may be provided on the chip 41. Alternatively, as described with reference to FIG. 6 , the LV circuit 7 may be provided on the chip 42. Because the regulator circuit 6 and the LV circuit 7 are provided on the same chip 42, there is no need to supply the voltage VDD2 output by the regulator circuit 6 to the chip 41.

[0125] As described with reference to Figures 7 and 8, the semiconductor device 2 may include: a chip 43 stacked on the chip 42 on the opposite side of the chip 42 from the chip 41 so as to be electrically connected to the chip 42; an additional regulator circuit 6-2 provided on the chip 42 or the chip 43, which adjusts the voltage VDD2 from the regulator circuit 6 and outputs a voltage VDD3 (third voltage); and a logic circuit 5-3 (third logic circuit) provided on the chip 43 and operates based on the voltage VDD3 from the additional regulator circuit 6-2. For example, the voltage VDD3 may be lower than the voltage VDD2. The additional regulator circuit 6-2 may be an LDO circuit. In such a configuration, there is no need to provide pads for the voltages VDD2 and VDD3, which accordingly prevents an increase in chip area and an increase in the size of the device. By using three chips 4, chips 41 to 43, the possibility of realizing multi-functionality and high functionality is increased compared to when two chips 4, for example, chips 41 and 42, are used.

[0126] 10 to 12 , the semiconductor device 2 includes a chip 40 (pixel chip) stacked on the chip 41 so as to be electrically connected to the chip 41 on the side opposite to the chip 42, with the chip 41 sandwiched therebetween, and the chip 40 may include a plurality of photoelectric conversion units PD1. In this manner, for example, the semiconductor device 2 can be used as a solid-state imaging device.

[0127] 13 etc., chip 41 includes terminal C1 for obtaining electrical connection with chip 42, chip 42 includes terminal C2 for obtaining electrical connection with chip 41, terminal C1 of chip 41 and terminal C2 of chip 42 corresponding to each other are joined to each other, and when chips 41 and 42 are viewed in plan, regulator circuit 6 may be disposed near terminals C1-1 and C2-1 for supplying voltage VDD2 output by regulator circuit 6 or voltage VDD1 input to regulator circuit 6 from chip 41 to chip 42. Simply disposing regulator circuit 6 in this manner allows for flexible power supply from chip 41 to chip 42.

[0128] 15 and other figures, the semiconductor device 2 may include an oscillator circuit 10-2 provided on a chip 42 and formed in the same process as the logic circuit 5-2, and a control circuit 12 that controls the voltage VDD2 output by the regulator circuit 6 based on the oscillation frequency of the oscillator circuit 10-2. For example, in this manner, the regulator circuit 6 can be adjusted so that the regulator circuit 6 outputs an optimum power supply voltage for the logic circuit 5.

[0129] The semiconductor device 2 can also be specified as follows. As described with reference to Figures 1, 9 to 13, and 15, the semiconductor device 2 includes a pad 411-1 to which a voltage VDD_ANA is supplied, an analog circuit 8 that operates based on the voltage VDD_ANA from the pad 411-1, a regulator circuit 6-1-1 that adjusts the voltage VDD_ANA from the pad 411-1 and outputs a voltage VDD1 (first voltage), and a logic circuit 5-1 that operates based on the voltage VDD1 from the regulator circuit 6-1-1. For example, the voltage VDD1 may be lower than the voltage VDD_ANA supplied to the pad 411-1.

[0130] According to the semiconductor device 2 described above, the voltage VDD_ANA can also be used to generate the voltage VDD1. Since there is no need to supply the voltage VDD1 to the semiconductor device 2 from outside the semiconductor device 2, there is no need to provide a pad for the voltage VDD1. This can further enhance the effect of suppressing increases in chip area and device size.

[0131] 9 and other figures, the semiconductor device 2 may include a regulator circuit 6-1-2 (second regulator circuit) that adjusts the voltage VDD1 from the regulator circuit 6-1-1 and outputs a voltage VDD2 (second voltage), and a logic circuit 5-2 (second logic circuit) that operates based on the voltage VDD2 from the regulator circuit 6-1-2. Since there is no need to provide a pad for the voltage VDD2, an increase in chip area can be suppressed, and an increase in the size of the device can be suppressed.

[0132] 9 and other drawings, the semiconductor device 2 may also have a chip-stacked structure. That is, as described with reference to FIG. 9 and other drawings, the semiconductor device 2 may include a chip 41 (first chip) and a chip 42 (second chip) stacked on the chip 41 so as to be electrically connected to the chip 41, and the analog circuit 8, regulator circuit 6-1-1, and logic circuit 5-1 may be provided on the chip 41, the regulator circuit 6-1-2 may be provided on the chip 41 or the chip 42, and the logic circuit 5-2 may be provided on the chip 42.

[0133] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0134] FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0135] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0136] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0137] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0138] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0139] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0140] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0141] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0142] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0143] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0144] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 16, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0145] FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.

[0146] In FIG. 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0147] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0148] 17 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0149] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0150] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0151] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0152] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0153] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 of the above-described configuration. Specifically, the semiconductor device 2, which is a solid-state imaging device described above with reference to FIGS. 10 to 12, can be applied to the imaging unit 12031. This allows the imaging unit 12031 to be made smaller and have higher functionality. For example, it is more likely that a captured image that is easy to see can be provided, thereby reducing driver fatigue.

[0154] 8. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0155] FIG. 18 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0156] 18 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0157] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0158] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0159] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0160] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0161] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0162] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0163] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0164] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0165] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0166] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0167] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0168] FIG. 19 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0169] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0170] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0171] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0172] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0173] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0174] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0175] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0176] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0177] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0178] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0179] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0180] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0181] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0182] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0183] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0184] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0185] The foregoing describes an example of an endoscopic surgery system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to, for example, the endoscope 11100, the camera head 11102 (the imaging unit 11402), and the CCU 11201 (the image processing unit 11412) among the above-described configurations. Specifically, the semiconductor device 2, which is a solid-state imaging device described above with reference to FIGS. 10 to 12 , can be applied to the imaging unit 10402, etc. This enables the imaging unit 11402, etc. to be miniaturized and have higher functionality. For example, it can provide clearer images of the surgical site, increasing the likelihood that the surgeon can reliably identify the surgical site.

[0186] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0187] The effects described in this disclosure are merely examples and are not limited to the disclosed contents. Other effects may also be obtained.

[0188] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.

[0189] The present technology may also be configured as follows. (1) A semiconductor device including: a first chip; a second chip stacked on the first chip so as to be electrically connected to the first chip; a pad to which a first voltage is supplied; a first logic circuit provided on the first chip and operating based on the first voltage from the pad; a regulator circuit provided on the first chip or the second chip and adjusting the first voltage from the pad to output a second voltage; and a second logic circuit provided on the second chip and operating based on the second voltage from the regulator circuit. (2) The semiconductor device according to (1), in which the second voltage is lower than the first voltage. (3) The semiconductor device according to (1) or (2), in which the regulator circuit is an LDO circuit. (4) The semiconductor device according to any of (1) to (3), in which the regulator circuit is provided on the first chip. (5) The semiconductor device according to any one of (1) to (3), wherein the regulator circuit is provided on the second chip. (6) The semiconductor device according to any one of (1) to (5), wherein the semiconductor device includes a stabilizing regulator circuit provided on the first chip, adjusting the first voltage from the pad and outputting a first voltage, and the first logic circuit operates based on the first voltage from the stabilizing regulator circuit. (7) The semiconductor device according to any one of (1) to (6), wherein the semiconductor device includes a level shift circuit provided on the first chip or the second chip, shifting the level of a signal voltage from the first logic circuit to the second logic circuit based on the second voltage from the regulator circuit. (8) The semiconductor device according to (7), wherein the level shift circuit is provided on the first chip. (9) The semiconductor device according to (7), wherein the level shift circuit is provided on the second chip.(10) The semiconductor device according to any one of (1) to (9), comprising: a third chip stacked on the second chip on the opposite side of the second chip from the first chip so as to be electrically connected to the second chip; an additional regulator circuit provided on the second chip or the third chip, adjusting the second voltage from the regulator circuit to output a third voltage; and a third logic circuit provided on the third chip and operating based on the third voltage from the additional regulator circuit. (11) The semiconductor device according to (10), wherein the third voltage is lower than the second voltage. (12) The semiconductor device according to (10) or (11), wherein the additional regulator circuit is an LDO circuit. (13) The semiconductor device according to any one of (1) to (12), comprising: a pixel chip stacked on the first chip on the opposite side of the first chip from the second chip so as to be electrically connected to the first chip, the pixel chip including a plurality of photoelectric conversion units. (14) The semiconductor device according to any one of (1) to (13), wherein the first chip includes a terminal for obtaining an electrical connection with the second chip, the second chip includes a terminal for obtaining an electrical connection with the first chip, corresponding terminals of the first chip and the second chip are joined to each other, and when the first chip and the second chip are viewed in a plane, the regulator circuit is disposed near a terminal for supplying a second voltage output by the regulator circuit or the first voltage input to the regulator circuit from the first chip to the second chip. (15) The semiconductor device according to any one of (1) to (14), comprising: an oscillator circuit provided in the second chip and formed by the same process as the second logic circuit; and a control circuit that controls the second voltage output by the regulator circuit based on an oscillation frequency of the oscillator circuit.(16) A semiconductor device comprising: a pad to which a voltage is supplied; an analog circuit operating based on the voltage from the pad; a regulator circuit adjusting the voltage from the pad to output a first voltage; and a logic circuit operating based on the first voltage from the regulator circuit. (17) The semiconductor device according to (16), wherein the first voltage is lower than the voltage supplied to the pad. (18) The semiconductor device according to (16) or (17), wherein the regulator circuit is an LDO circuit. (19) The semiconductor device according to any of (16) to (18), comprising: a second regulator circuit adjusting the first voltage from the regulator circuit to output a second voltage; and a second logic circuit operating based on the second voltage from the second regulator circuit. (20) The semiconductor device according to (19), comprising: a first chip; and a second chip stacked on the first chip so as to be electrically connected to the first chip; wherein the analog circuit, the regulator circuit, and the logic circuit are provided on the first chip; the second regulator circuit is provided on the first chip or the second chip; and the second logic circuit is provided on the second chip.

[0190] 1 Substrate 11 Pad 11-1 Pad 11-2 Pad 2 Semiconductor device 3 Package 31 Pad 31-1 Pad 31-2 Pad 31-3 Pad 31-4 Pad 4 Chip 41 Chip 411 Pad 411-1 Pad 411-2 Pad 411-3 Pad 411-4 Pad 42 Chip 43 Chip 5 Logic circuit 5-1 Logic circuit 5-2 Logic circuit 5-3 Logic circuit 6 Regulator circuit 6-1 Regulator circuit 6-1-1 Regulator circuit 6-1-2 Regulator circuit 60 Stabilizing regulator circuit 7 LV circuit 7-1 LV circuit 7-2 Additional LV circuit 8 Analog circuit 9 Pixel array section 90 Pixel 91 Transistor 92 Transistor 93 Transistor 94 Transistor 95 Floating diffusion 10 Oscillator circuit 10-1 Oscillator circuit 10-2 Oscillator circuit 12 Control circuit 13 ROM 100 Electronic device 101 Control circuit 102 Vertical drive circuit 103 Column signal processing circuit 104 Horizontal drive circuit 105 Output circuit 106 Signal line 107 Signal line 108 Signal line C1 Terminal C1-1 Terminal C1-2 Terminal C1-3 Terminal C2 Terminal C2-1 Terminal C2-2 Terminal C2-3 Terminal C2-4 Terminal C2-5 Terminal C2-6 TerminalC3 terminal C3-5 terminal C3-6 terminal L1 Power supply wiring L2 Power supply wiring PD1 Photoelectric conversion unit VDD1 voltage VDD2 voltage VDD3 voltage VDD_ANA voltage VSS voltage VSS1 voltage VSS2 voltage VSS3 voltage

Claims

1. A semiconductor device comprising: a first chip; a second chip stacked on the first chip so as to be electrically connected to the first chip; a pad to which a first voltage is supplied; a first logic circuit provided on the first chip and operating based on the first voltage from the pad; a regulator circuit provided on the first chip or the second chip and adjusting the first voltage from the pad to output a second voltage; and a second logic circuit provided on the second chip and operating based on the second voltage from the regulator circuit.

2. The semiconductor device according to claim 1, wherein the second voltage is lower than the first voltage.

3. The semiconductor device according to claim 1, wherein the regulator circuit is an LDO circuit.

4. The semiconductor device according to claim 1, wherein the regulator circuit is provided on the first chip.

5. The semiconductor device according to claim 1, wherein the regulator circuit is provided on the second chip.

6. The semiconductor device according to claim 1, further comprising a stabilizing regulator circuit provided on the first chip for adjusting the first voltage from the pad and outputting the first voltage, and the first logic circuit operates based on the first voltage from the stabilizing regulator circuit.

7. The semiconductor device according to claim 1, further comprising a level shift circuit provided on the first chip or the second chip, which shifts the level of a signal voltage from the first logic circuit to the second logic circuit based on the second voltage from the regulator circuit.

8. The semiconductor device according to claim 7, wherein the level shift circuit is provided in the first chip.

9. The semiconductor device according to claim 7, wherein the level shift circuit is provided in the second chip.

10. The semiconductor device according to claim 1, comprising: a third chip stacked on the second chip on the opposite side of the second chip from the first chip so as to be electrically connected to the second chip; an additional regulator circuit provided on the second chip or the third chip, which adjusts the second voltage from the regulator circuit and outputs a third voltage; and a third logic circuit provided on the third chip, which operates based on the third voltage from the additional regulator circuit.

11. The semiconductor device according to claim 10, wherein the third voltage is lower than the second voltage.

12. The semiconductor device according to claim 10, wherein the additional regulator circuit is an LDO circuit.

13. The semiconductor device according to claim 1, further comprising a pixel chip stacked on the first chip on the opposite side of the first chip from the second chip so as to be electrically connected to the first chip, the pixel chip including a plurality of photoelectric conversion units.

14. The semiconductor device described in claim 1, wherein the first chip includes a terminal for obtaining an electrical connection with the second chip, the second chip includes a terminal for obtaining an electrical connection with the first chip, corresponding terminals of the first chip and the second chip are joined to each other, and when the first chip and the second chip are viewed in a plane, the regulator circuit is arranged near a terminal for supplying the second voltage output by the regulator circuit or the first voltage input to the regulator circuit from the first chip to the second chip.

15. The semiconductor device according to claim 1, comprising: an oscillator circuit provided on the second chip and formed by the same process as the second logic circuit; and a control circuit that controls the second voltage output by the regulator circuit based on the oscillation frequency of the oscillator circuit.

16. A semiconductor device comprising: a pad to which a voltage is supplied; an analog circuit that operates based on the voltage from the pad; a regulator circuit that adjusts the voltage from the pad and outputs a first voltage; and a logic circuit that operates based on the first voltage from the regulator circuit.

17. The semiconductor device according to claim 16, wherein the first voltage is lower than the voltage supplied to the pad.

18. The semiconductor device according to claim 16, wherein the regulator circuit is an LDO circuit.

19. The semiconductor device according to claim 16, comprising: a second regulator circuit that adjusts the first voltage from the regulator circuit and outputs a second voltage; and a second logic circuit that operates based on the second voltage from the second regulator circuit.

20. The semiconductor device according to claim 19, comprising: a first chip; and a second chip stacked on the first chip so as to be electrically connected to the first chip; the analog circuit, the regulator circuit, and the logic circuit are provided on the first chip; the second regulator circuit is provided on the first chip or the second chip; and the second logic circuit is provided on the second chip.

Images