Aggregated subordinate control over a serial bus

Abstract

Aggregated subordinate control over a serial bus is described in the present disclosure. Herein, a serial bus circuit includes multiple subordinate circuits each configured to operate based on a respective one or more control bits programmed into a respective control register(s). Understandably, if the control register(s) in each of the subordinate circuits is programmed individually through multiple bus telegrams, then much of the already limited bandwidth of the serial bus will be wasted. In this regard, in embodiments disclosed herein, a single bus telegram can be configured to carry an aggregated control word that can simultaneously program the control register(s) in multiple subordinate circuits. As a result, it is possible to reduce bus telegrams for programming the subordinate circuits, thus helping to conserve bandwidth of the serial bus.

Description

AGGREGATED SUBORDINATE CONTROL OVER A SERIAL BUSRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 657,347, filed on June 7, 2024, the disclosure of which is hereby incorporated herein by reference in its entirety.Field of the Disclosure

[0002] The technology of the disclosure relates generally to controlling a subordinate (a.k.a. slave) circuit over a serial bus.Background

[0003] Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] To provide the redefined user experience, a state-of-the-art wireless communication device (e.g., smartphone) is equipped with a variety of electrical circuits to support various applications and enable various user experiences. In addition, the wireless communication device also employs a variety of communication buses to enable inter-circuit and intra-circuit communications. As an example, a single-wire bus (SuBUS) and / or a two-wire radio frequency frontend (RFFE) bus can enable bidirectional communications between a transceiver circuit(s), a power amplifier circuit(s), a power management circuit(s), and / or an antenna circuit(s).

[0005] Notably, the SuBUS and the RFFE bus are both serial buses, which can only provide a limited bandwidth. It is thus desirable to maximize usage of the limited bandwidth by reducing unnecessary communications over the serial buses.Summary

[0006] Aspects disclosed in the detailed description are related to aggregated subordinate control over a serial bus. Herein, a serial bus circuit includes multiple subordinate circuits each configured to operate based on a respective one or more control bits programmed into a respective control register(s). Understandably, if the control register(s) in each of the subordinate circuits is programmed individually through multiple bus telegrams, then much of the already limited bandwidth of the serial bus will be wasted. In this regard, in embodiments disclosed herein, a single bus telegram can be configured to carry an aggregated control word that can simultaneously program the control register(s) in multiple subordinate circuits. As a result, it is possible to reduce bus telegrams for programming the subordinate circuits, thus helping to conserve bandwidth of the serial bus.

[0007] In one aspect, a serial bus circuit is provided. The serial bus circuit includes a serial bus. The serial bus is coupled to a main circuit. The serial bus circuit also includes multiple subordinate circuits. Each of the multiple subordinate circuits is coupled to the serial bus. Each of the multiple subordinate circuits is identified by a unique subordinate identification (USID) and an assigned virtual subordinate identification (VSID). Each of the multiple subordinate circuits includes at least one control register. The at least one control register is configured to include a respective one or more control bits. Each of the multiple subordinate circuits also includes a register mask. The register mask is configured to indicate one or more valid positions of the respective one or more control bits in the at least one control register. Each of the multiple subordinate circuits also includes a controller. The controller is configured to receive a bus telegram from the main circuit over the serial bus. The bus telegram includes a VSID identifying one or more of the multiple subordinate circuits and an aggregated control word configured to include the respective one or more control bits of the one or more of the multiple subordinate circuits. The controller is also configured to determine that the VSID in the bus telegram matches the assigned VSID. The controller is also configured to extractthe respective one or more control bits from the aggregated control word based at least on the register mask. The controller is also configured to configure the at least one control register with the respective one or more control bits extracted from the aggregated control word.

[0008] In another aspect, a wireless device is provided. The wireless device includes a serial bus circuit. The serial bus circuit includes a serial bus. The serial bus is coupled to a main circuit. The serial bus circuit also includes multiple subordinate circuits. Each of the multiple subordinate circuits is coupled to the serial bus. Each of the multiple subordinate circuits is identified by a unique subordinate identification (USID) and an assigned virtual subordinate identification (VSID). Each of the multiple subordinate circuits includes at least one control register. The at least one control register is configured to include a respective one or more control bits. Each of the multiple subordinate circuits also includes a register mask. The register mask is configured to indicate one or more valid positions of the respective one or more control bits in the at least one control register. Each of the multiple subordinate circuits also includes a controller. The controller is configured to receive a bus telegram from the main circuit over the serial bus. The bus telegram includes a VSID identifying one or more of the multiple subordinate circuits and an aggregated control word configured to include the respective one or more control bits of the one or more of the multiple subordinate circuits. The controller is also configured to determine that the VSID in the bus telegram matches the assigned VSID. The controller is also configured to extract the respective one or more control bits from the aggregated control word based at least on the register mask. The controller is also configured to configure the at least one control register with the respective one or more control bits extracted from the aggregated control word.

[0009] In another aspect, a method for aggregating subordinate control in a serial bus circuit is provided. The method includes receiving, by each of multiple subordinate circuits identified by a USID and an assigned VSID, a bus telegram from a main circuit comprising a VSID identifying one or more of the multiple subordinate circuits and an aggregated control word configured to include arespective one or more control bits for controlling each of the one or more of the multiple subordinate circuits. The method also includes determining that the VSID in the bus telegram matches the assigned VSID. The method also includes extracting the respective one or more control bits from the aggregated control word based at least on a register mask configured to indicate one or more valid positions of the respective one or more control bits in at least one control register. The method also includes configuring the at least one control register with the respective one or more control bits extracted from the aggregated control word.

[0010] Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.Brief Description of the Drawings

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] Figure 1 is a schematic diagram of an exemplary serial bus circuit wherein each of multiple subordinate circuits is configured to support aggregated subordinate control based on embodiments of the present disclosure;

[0013] Figure 2A is a schematic diagram providing an exemplary illustration of default control registers provided in each of the subordinate circuits in Figure 1 ;

[0014] Figure 2B is a schematic diagram providing an exemplary illustration of alternative control registers provided in each of the subordinate circuits in Figure 1 ;

[0015] Figure 3 is a schematic diagram providing an exemplary illustration of a bus telegram wherein an aggregated control word is configured to simultaneously program the subordinate circuits in Figure 1 ;

[0016] Figure 4 is a schematic diagram providing an exemplary illustration of configuration registers provided in each of the subordinate circuits in Figure 1 ;

[0017] Figure 5 is a schematic diagram providing an exemplary illustration as to how each of the subordinate circuits in Figure 1 can extract respective control bits from the aggregated control word in Figure 3 based on information stored in the configuration registers in Figure 4;

[0018] Figure 6 is a flowchart of a process whereby the serial bus circuit of Figure 1 can be configured to support aggregated subordinate control; and

[0019] Figure 7 is a schematic diagram of an exemplary communication device wherein the serial bus circuit of Figure 1 can be provided.Detailed Description

[0020] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0021] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when anelement such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0023] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and therelevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] Aspects disclosed in the detailed description are related to aggregated subordinate control over a serial bus. Herein, a serial bus circuit includes multiple subordinate circuits each configured to operate based on a respective one or more control bits programmed into a respective control register(s). Understandably, if the control register(s) in each of the subordinate circuits is programmed individually through multiple bus telegrams, then much of the already limited bandwidth of the serial bus will be wasted. In this regard, in embodiments disclosed herein, a single bus telegram can be configured to carry an aggregated control word that can simultaneously program the control register(s) in multiple subordinate circuits. As a result, it is possible to reduce bus telegrams for programming the subordinate circuits, thus helping to conserve bandwidth of the serial bus.

[0027] Figure 1 is a schematic diagram of an exemplary serial bus circuit 10 wherein a main circuit 12 (a.k.a. master circuit) and multiple subordinate circuits 14(1 )-14(N) (a.k.a. slave circuits) are configured to support aggregated subordinate control based on embodiments of the present disclosure. Herein, the subordinate circuits 14(1 )-14(N) are coupled to the main circuit 12 via a serial bus 16. In one embodiment, the serial bus 16 can be a single-wire bus (SuBUS) consisting of a single wire. In another embodiment, the serial bus 16 can be a radio frequency frontend (RFFE) bus that includes a clock line SCLK and a data line SDATA.

[0028] For the sake of illustration, the subordinate circuits 14(1 )-14(4) among the subordinate circuits 14(1 )-14(N) are referenced as non-limiting examples hereinafter to help understand how the serial bus circuit 10 can be configured to support the aggregated subordinate control of the present disclosure. It should be appreciated that additional numbers of subordinate circuits may be provided in the serial bus circuit 10 and configured to operate like the subordinate circuits 14(1 )-14(4).

[0029] Herein, each of the subordinate circuits 14(1 )-14(4) is uniquely identified by a respective one of multiple unique subordinate identifications (USIDs) “0011 ,” “0012,” “0013,” and “0014.” Each of the subordinate circuits 14(1 )-14(4) also includes a respective one of multiple controllers 18(1 )-18(4). In an embodiment, each of the controllers 18(1 )-18(4) is configured to execute a respective finite state machine (FSM) to control respective operations of the subordinate circuits 14(1 )-14(4).

[0030] Each of the subordinate circuits 14(1 )-14(4) is further configured to include a respective one of multiple register banks 20(1 )-20(4) (denoted as “REGMAP”). In an embodiment, each of the register banks 20(1 )-20(4) can include two-hundred fifty-six (256) registers labeled as REG_000-REG_255, each of which includes eight (8) bits labeled as b0-b7.

[0031] According to an embodiment, a first one of the registers REG_000- REG_255 (e.g., REG_000) is designated as a default control register, a second one of the registers REG_000-REG_255 (e.g., REGJD03) is designated as an alternative control register, and a third one of the registers REG_000-REG_255 (e.g., REG_004) is designated as a configuration register. Understandably, REG_000, REG_003, and REG_004 are merely provided as non-limiting examples to help explain how the aggregated subordinate control is supported in the serial bus circuit 10. It should be appreciated that the default control register, the alternative control register, and the configuration register can be any of the registers REG_000-REG_255 in the register banks 20(1 )-20(4).

[0032] Figure 2A is a schematic diagram providing an exemplary detailed illustration of the default control registers REG_000 in the subordinate circuits 14(1 )-14(4) in Figure 1. Herein, the default register REG_000 in each of the subordinate circuits 14(1 )-14(4) includes one or more valid control bits (denoted by binary “1”), one or more unused control bits (denoted by binary “0”), and one or more reserved control bits (denoted by letter “R”). The respective position of the valid control bits in the default control register REG_000 in each of the subordinate circuits 14(1 )-14(4) is marked by a respective one of multiple register masks RMASK_1 , RMASK_2, RMASK_3, and RMASK_4.

[0033] In one embodiment, the register masks RMASK_1 , RMASK_2, RMASK_3, and RMASK_4 can be burned into hardware when the subordinate circuits 14(1 )-14(4) are fabricated. In another embodiment, the register masks RMASK_1 , RMASK_2, RMASK_3, and RMASK_4 can be stored in any of the registers REG_000-REG_255 (e.g., REG_005), either statically or dynamically.

[0034] In a non-limiting example, the subordinate circuits 14(1 )-14(4) can each be an antenna tuner having a respective antenna switch. In the example illustrated herein, the subordinate circuit 14(1 ) includes a single-pole, triple-throw (SP3T) switch, and the subordinate circuit 14(2) includes a single-pole, singlethrow (SP1T) switch, whereas the subordinate circuits 14(3) and 14(4) each includes a single-pole, double-throw (SP2T) switch.

[0035] In this regard, the default control register REG_000 in the subordinate circuit 14(1 ) includes three (3) valid control bits b0-b2 corresponding to the three on-off positions of the respective SP3T switch. Accordingly, the respective register mask RMASK_1 is assigned a binary value “ObOOOOOH 1” to mark the 3 valid control bits in the default control register REG_000 of the subordinate circuit 14(1 ).

[0036] Similarly, the default control register REG_000 in the subordinate circuit 14(2) includes one (1 ) valid control bit bO corresponding to the on-off position of the respective SP1T switch. Accordingly, the respective register mask RMASK_2 is assigned a binary value “0b00000001” to mark the only valid control bit in the default control register REG_000 of the subordinate circuit 14(2). Likewise, the default control register REG_000 in the subordinate circuit 14(3) includes two (2) valid control bits b3-b4 corresponding to the on-off positions of the respective SP2T switch and the respective register mask RMASK_3 is assigned a binary value “0b00011000” to mark the two valid control bits in the default control register REG_000 of the subordinate circuit 14(3). The default control register REG_000 in the subordinate circuit 14(4) includes two (2) valid control bits bO and b2 corresponding to the on-off positions of the respective SP2T switch and the respective register mask RMASK_4 is assigned a binaryvalue “ObOOOOOO1 O1 ” to mark the two valid control bits in the default control register REG_000 of the subordinate circuit 14(4).

[0037] As illustrated herein, bit b6 of the default control register REG_000 is a reserved control bit. As such, by assigning a binary “0” into b6 in each of the register masks RMASK_1 , RMASK_2, RMASK_3, and RMASK_4, it is possible to protect the reserved control bit from being overwritten when updating the respective valid control bits in each of the register masks RMASK_1 , RMASK_2, RM ASK_3, and RMASK_4.

[0038] Figure 2B is a schematic diagram providing an exemplary detailed illustration of the alternative control registers REG_003 in the subordinate circuits 14(1 )-14(4) in Figure 1. Common elements between Figures 2A and 2B are shown therein with common element numbers and will not be re-described herein.

[0039] According to an embodiment, the alternative control register REG_003 in each of the subordinate circuits 14(1 )-14(4) is identical to the corresponding default control register REG_000 in the subordinate circuits 14(1 )-14(4), except for the reserved control bit b6. In the example illustrated herein, the control bit b6 in the alternative control register REG_003 is configured to be an unused control bit. In addition, the alternative control register REG_003 in the subordinate circuits 14(1 )-14(4) is masked by the same register masks RMASK_1 , RMASK_2, RMASK_3, and RMASK_4.

[0040] As can be seen from the example in Figure 2B, the alternative control register REG_003 in each of the subordinate circuits 14(1 )-14(4) has some unused control bits. It is thus possible to fill the unused control bits in one alternative control register REG_003 with the valid control bits from one or more other alternative control registers REG_003 to thereby generate an aggregated control word that can simultaneously control all of the subordinate circuits 14(1 )- 14(4). Figure 3 is a schematic diagram providing an exemplary illustration of a bus telegram 22 wherein an aggregated control word 24 is configured to simultaneously program the subordinate circuits 14(1 )-14(4) in Figure 1.

[0041] Like the alternative control register REG_003 in the subordinate circuits 14(1 )-14(4), the aggregated control word 24 includes eight bits labeled as b0-b7. Herein, bits b0-b2 are allocated to the subordinate circuit 14(1 ), b3 and b5 are allocated to the subordinate circuit 14(4), b4 is allocated to the subordinate circuit 14(2), and b6-b7 are allocated to the subordinate circuit 14(3).

[0042] The subject matter as to how the aggregated control word 24 can be generated to contain all the valid control bits in the alternative control register REG_003 illustrated in Figure 3 is out of the scope of the present disclosure. As an example, the aggregated control word 24 can be generated by a design engineer with assistance from machine learning (ML) and / or any other type of software tools.

[0043] Like any other bus telegrams, the bus telegram 22 also includes an address field 26. Herein, the address field 26 includes a virtual subordinate identification (VSID) that is set to any selected one of the USIDs “0011 ,” “0012,” “0013,” and “0014” that uniquely identifies the subordinate circuits 14(1 )-14(4). Herein, the VSID is set to the USID “0011” of the subordinate circuit 14(1 ), as an example. Accordingly, the subordinate circuit 14(1 ) is configured to communicate an acknowledgement (ACK) in response to receiving the bus telegram 22. In the meantime, the subordinate circuits 14(2), 14(3), and 14(4) do not need to acknowledge the bus telegram 22 because the address field 26 does not include their respective USIDs “0012,” “0013,” and “0014.”

[0044] In an embodiment, the subordinate circuits 14(1 )-14(4) are each configured to extract their respective valid control bits from the aggregate control word 24 based on information prestored in their respective configuration register REG_004. In this regard, Figure 4 is a schematic diagram providing an exemplary illustration of the configuration register REG_004 provided in each of the subordinate circuits 14(1 )-14(4) in Figure 1.

[0045] Herein, the configuration register REG_004 in each of the subordinate circuits 14(1 )-14(4) includes a VSID field 28 (a.k.a. second multibit field), a shift field 30 (a.k.a. first multibit field), and a register swap (REGSWAP) flag 32.Specifically, the VS ID field 28 is assigned to bits b0-b3, the shift field 30 is assigned to bits b4-b6, and the REGSWAP flag 32 is assigned to bit b7.

[0046] For each of the subordinate circuits 14(1 )-14(4), the VS ID field 28 is set to the VSID “0011 ” carried in the address field 26 of the bus telegram 22. Accordingly, the subordinate circuits 14(1 )-14(4) can each determine whether the bus telegram 22 includes their respective valid control bits by matching the VSID field 28 in the configuration register REG_004 with the VSID carried in the address field 26 of the bus telegram 22.

[0047] The shift field 30, which will be further discussed in detail in Figure 5, is used to help the subordinate circuits 14(1 )-14(4) to extract their respective valid control bits from the aggregated control word 24. More specifically, the shift field 30 defines a number of bit-shifts the subordinate circuits 14(1 )-14(4) must perform on the aggregated control word 24 to properly align their respective valid control bits in the aggregated control word 24 with their respective register masks RMASK.1, RMASK-2, RMASK 3, and RMASK 4.

[0048] The respective shift field 30 for each of the subordinate circuits 14(1 )- 14(4) may be determined by the same design engineer based on how the aggregated control word 24 is configured. In this example, the shift field 30 has a respective binary value “000” (decimal “0”), “100” (decimal “4”), “011” (decimal “3”), and “011” (decimal “3”) in the configuration register REG_004 of a respective one of the subordinate circuits 14(1 )-14(4). The configuration register REG_004 in each of the subordinate circuits 14(1 )-14(4) may be programmed either statically or dynamically.

[0049] By default, the subordinate circuits 14(1 )-14(4) are configured to operate based on their respective default control register REG_000. The REGSWAP flag 32 is used to cause the subordinate circuits 14(1 )-14(4) to instead operate based on their respective alternative control register REG_003. Specifically, each of the subordinate circuits 14(1 )-14(4) will operate based on the respective alternative control register REG_003 when the REGSWAP flag 32 is set to TRUE (binary “1”). In other words, the alternative control registerREG_003 in each of the subordinate circuits 14(1 )-14(4) replaces the respective default control register REG_000 to function as the default control register.

[0050] In contrast, each of the subordinate circuits 14(1 )-14(4) will operate based on the respective default control register REG_000 when the REGSWAP flag 32 is set to FALSE (binary “0”). This makes it possible for some legacy subordinate circuits in the serial bus circuit 10 of Figure 1 , which are inherently incapable of handling the aggregated control word 24, to benefit from the aggregated control word 24. Since the legacy subordinate circuits may not be able to perform bit-shifts on the aggregated control word 24 to extract their respective valid control bits, the valid control bits of the legacy subordinate circuits must be provided in the aggregated control word 24 at the exact position as indicated by the corresponding register mask in the legacy subordinate circuits.

[0051] Figure 5 is a schematic diagram providing an exemplary illustration as to how each of the subordinate circuits 14(1 )-14(4) in Figure 1 can extract respective valid control bits from the aggregated control word 24 in Figure 3 based on information stored in the respective configuration registers REG_004 in Figure 4. Herein, the subordinate circuit 14(3) is illustrated as a non-limiting example. Understandably, the operation illustrated herein is likewise applicable to any of the subordinate circuits 14(1 )-14(4). Common elements between Figures 3, 4, and 5 are shown therein with common element numbers and will not be re-described herein.

[0052] As previously discussed in Figure 3, the two valid control bits associated with the subordinate circuit 14(3) are provided at bits b6, b7 in the aggregated control word 24. Further, as illustrated in Figure 2B, the corresponding register mask RMASK_3 (0b00011000) indicates that the two valid control bits shall be located at bits b3, b4 in the alternative control register REG_003. In this regard, the controller 18(3) in the subordinate circuit 14(3) must first perform the number of shifts (3 shifts) as defined in the shift field 30 of the corresponding configuration register REG_004 to move the valid control bitsfrom bits b6, b7 to align with the corresponding register mask RMASK_3 at bits b3, b4.

[0053] In an embodiment, the subordinate circuit 14(3) may store the aggregated control word 24 in a shift register or directly in the alternative control register REG_003. Accordingly, the controller 18(3) is configured to perform a barrel shift on the aggregated control word 24 three times (as defined by the configuration register REG_004). As illustrated herein, after performing 3-barrel shifts, the bitwise value of the aggregated control word 24 becomes “01010110” and the valid control bits of the subordinate circuit 14(3) are now aligned with the respective register mask RMASK_3 at bits b3, b4. The controller 18(3) can then apply the respective register mask RMASK_3 (a.k.a. a bitwise AND) onto the shifted aggregated control word to thereby eliminate irrelevant control bits at bits b0-b2 and b5-b7. Should the controller 18(3) perform the barrel shift in the shift register, the controller 18(3) will then overwrite the respective alternative control register REG_003 with values in the shift register.

[0054] As a summary, Figure 6 is a flowchart of a process 50 whereby the serial bus circuit 10 of Figure 1 can be configured to support aggregated subordinate control. Herein, each of the controllers 18(1 )-18(4) is configured to receive the bus telegram 22 that includes the VS ID in the address field 26 and the aggregated control word 24 (step 52). In one embodiment, each of the controllers 18(1 )-18(4) may store the received aggregated control word 24 in a shift register. In another embodiment, each of the controllers 18(1 )-18(4) may store the received aggregated control word 24 in the respective alternative control register REG_003.

[0055] Each of the controllers 18(1 )-18(4) then checks the VSID carried in the address field 26 against the assigned VSID in the respective configuration register REG_004 to determine whether the bus telegram 22 is addressed to the respective subordinate circuits 14(1 )-14(4) (step 54). If the VSID in the bus telegram 22 does not match the assigned VSID in the respective configuration register REG_004, the process 50 returns to step 52 to await another bus telegram. Otherwise, each of the controllers 18(1 )-18(4) further checks whetherthe VSID in the bus telegram 22 matches the USID that uniquely identified the respective subordinate circuits 14(1 )-1 (4) (step 56). In case the received VSID matches the USID of the respective subordinate circuits 14(1 )-1 (4), the respective one of the controllers 18(1 )-18(4) communicates an ACK over the serial bus 16 to acknowledge reception of the bus telegram 22 (step 58).

[0056] Each of the controllers 18(1 )-18(4) will then barrel-shift the aggregated control word 24 by the number of shifts as defined in the shift field 30 in the respective configuration register REG_004 (step 60). Subsequently, each of the controllers 18(1 )-18(4) applies a respective one of the register masks RMASK_1 - RMASK_4 to the shifted aggregated control word 24 to thereby extract the valid control bits for controlling the respective subordinate circuits 14(1 )-14(4) (step 62). Each of the controllers 18(1 )-18(4) then checks to see whether the REGSWAP flag 32 in the respective configuration register REG_004 is set to TRUE (step 64). If the REGSWAP flag 32 is set to TRUE, and if the aggregated control word 24 had been stored in the shift register, each of the controllers 18(1 )-18(4) may then update the respective alternative control register REG_003 with the contents in the shift register (step 66). Understandably, if the aggregated control word 24 had been manipulated in the alternative control register REG_003, step 66 may be skipped. In this regard, when the REGSWAP flag 32 is set to TRUE, the alternative control register REG_003 will become the default control register REG_000 that controls the respective one of the subordinate circuits 14(1 )-14(4). In case the REGSWAP flag 32 is set to FALSE, each of the controllers 18(1 )-18(4) will then write the corresponding valid control bits directly into the respective default control register REG_000 (step 68). Understandably, if the aggregated control word 24 was manipulated in the shift register, then each of the controllers 18(1 )-18(4) will write the corresponding valid control bits from the shift register into the default control register REG_000. In case the aggregated control word 24 was manipulated in the alternative control register REG_003, then each of the controllers 18(1 )-18(4) will write the corresponding valid control bits from the alternative control register REG_003 into the default control register REG_000. In this regard, when the REGSWAPflag 32 is set to FALSE, each of the subordinate circuits 14(1 )-14(4) will instead be controlled by the default control register REG_000.

[0057] The serial bus circuit 10 of Figure 1 can be provided in a communication device to support the embodiments described above. In this regard, Figure 7 is a schematic diagram of an exemplary communication device 100 wherein the serial bus circuit of Figure 1 can be provided.

[0058] Herein, the communication device 100 can be any type of communication device, such as mobile terminal, smart watch, tablet, computer, navigation device, access point, base station (e.g., eNB, gNB), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultrawideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0059] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0060] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0061] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A serial bus circuit comprising: a serial bus coupled to a main circuit; and a plurality of subordinate circuits each coupled to the serial bus and identified by a unique subordinate identification (USID) and an assigned virtual subordinate identification (VSID), each of the plurality of subordinate circuits comprises: at least one control register configured to include a respective one or more control bits; a register mask configured to indicate one or more valid positions of the respective one or more control bits in the at least one control register; and a controller configured to: receive a bus telegram from the main circuit over the serial bus, the bus telegram comprises a VSID identifying one or more of the plurality of subordinate circuits and an aggregated control word configured to include the respective one or more control bits of the one or more of the plurality of subordinate circuits; determine that the VSID in the bus telegram matches the assigned VSID; extract the respective one or more control bits from the aggregated control word based at least on the register mask; and configure the at least one control register with the respective one or more control bits extracted from the aggregated control word.

2. The serial bus circuit of claim 1 , wherein: the at least one control register in each of the plurality of subordinate circuits comprises a default control register and an alternative control register; and the controller in each of the plurality of subordinate circuits is further configured to configure one of the default control register and the alternative control register with the respective one or more control bits extracted from the aggregated control word.

3. The serial bus circuit of claim 2, wherein each of the plurality of subordinate circuits further comprises a configuration register configured to comprise: a register swap flag configured to cause the controller in a respective one of the plurality of subordinate circuits to configure the alternative control register with the respective one or more control bits extracted from the aggregated control word; a first multibit field configured to indicate a number of shifts to be performed on the aggregated control word to thereby align the respective one or more control bits carried in the aggregated control word with the one or more valid positions indicated by the register mask of the respective one of the plurality of subordinate circuits; and a second multibit field configured to indicate the assigned VSID of the respective one of the plurality of subordinate circuits.

4. The serial bus circuit of claim 3, wherein the controller in each of the plurality of subordinate circuits is further configured to perform a barrel shift on the aggregated control word by the number of shifts indicated in the first multibit field to thereby align the respective one or more control bits carried in the aggregated control word with the one or more valid positions indicated by the register mask.

5. The serial bus circuit of claim 3, wherein the controller in each of the plurality of subordinate circuits is further configured to: configure the default control register with the respective one or more control bits extracted from the aggregated control word when the register swap flag is set to FALSE; and configure the alternative control register with the respective one or more control bits extracted from the aggregated control word when the register swap flag is set to TRUE.

6. The serial bus circuit of claim 1 , wherein the VSID carried in the bus telegram is configured to be the USID of a selected one of the plurality of subordinate circuits.

7. The serial bus circuit of claim 6, wherein the selected one of the plurality of subordinate circuits is configured to communicate an acknowledgement (ACK) to the main circuit in response to receiving the bus telegram.

8. The serial bus circuit of claim 1 , wherein: the at least one control register in each of the plurality of subordinate circuits comprises a default control register; and the controller in each of the plurality of subordinate circuits is further configured to configure the default control register with the respective one or more control bits extracted from the aggregated control word.

9. A wireless device comprising a serial bus circuit, the serial bus circuit comprises: a serial bus coupled to a main circuit; and a plurality of subordinate circuits each coupled to the serial bus and identified by a unique subordinate identification (USID) and anassigned virtual subordinate identification (VSID), each of the plurality of subordinate circuits comprises: at least one control register configured to include a respective one or more control bits; a register mask configured to indicate one or more valid positions of the respective one or more control bits in the at least one control register; and a controller configured to: receive a bus telegram from the main circuit over the serial bus, the bus telegram comprises a VSID identifying one or more of the plurality of subordinate circuits and an aggregated control word configured to include the respective one or more control bits of the one or more of the plurality of subordinate circuits; determine that the VSID in the bus telegram matches the assigned VSID; extract the respective one or more control bits from the aggregated control word based at least on the register mask; and configure the at least one control register with the respective one or more control bits extracted from the aggregated control word.

10. The wireless device of claim 9, wherein: the at least one control register in each of the plurality of subordinate circuits comprises a default control register and an alternative control register; and the controller in each of the plurality of subordinate circuits is further configured to configure one of the default control register and the alternative control register with the respective one or more control bits extracted from the aggregated control word.11 . The wireless device of claim 10, wherein each of the plurality of subordinate circuits further comprises a configuration register configured to comprise: a register swap flag configured to cause the controller in a respective one of the plurality of subordinate circuits to configure the alternative control register with the respective one or more control bits extracted from the aggregated control word; a first multibit field configured to indicate a number of shifts to be performed on the aggregated control word to thereby align the respective one or more control bits carried in the aggregated control word with the one or more valid positions indicated by the register mask of the respective one of the plurality of subordinate circuits; and a second multibit field configured to indicate the assigned VSID of the respective one of the plurality of subordinate circuits.

12. The wireless device of claim 11 , wherein the controller in each of the plurality of subordinate circuits is further configured to perform a barrel shift on the aggregated control word by the number of shifts indicated in the first multibit field to thereby align the respective one or more control bits carried in the aggregated control word with the one or more valid positions indicated by the register mask.

13. The wireless device of claim 11 , wherein the controller in each of the plurality of subordinate circuits is further configured to: configure the default control register with the respective one or more control bits extracted from the aggregated control word when the register swap flag is set to FALSE; and configure the alternative control register with the respective one or more control bits extracted from the aggregated control word when the register swap flag is set to TRUE.

14. The wireless device of claim 9, wherein the VSID carried in the bus telegram is configured to be the IISID of a selected one of the plurality of subordinate circuits.

15. The wireless device of claim 14, wherein the selected one of the plurality of subordinate circuits is configured to communicate an acknowledgement (ACK) to the main circuit in response to receiving the bus telegram.

16. A method for aggregating subordinate control in a serial bus circuit comprising: receiving, by each of a plurality of subordinate circuits identified by a unique subordinate identification (USID) and an assigned virtual subordinate identification (VSID), a bus telegram from a main circuit comprising a VSID identifying one or more of the plurality of subordinate circuits and an aggregated control word configured to include a respective one or more control bits for controlling each of the one or more of the plurality of subordinate circuits; determining that the VSID in the bus telegram matches the assigned VSID; extracting the respective one or more control bits from the aggregated control word based at least on a register mask configured to indicate one or more valid positions of the respective one or more control bits in at least one control register; and configuring the at least one control register with the respective one or more control bits extracted from the aggregated control word.

17. The method of claim 16, further comprising performing a barrel shift on the aggregated control word by a number of shifts to thereby align the respective one or more control bits carried in the aggregated control word with the one or more valid positions indicated by the register mask.

18. The method of claim 16, further comprising: configuring a default control register among the at least one control register with the respective one or more control bits extracted from the aggregated control word when a register swap flag in a configuration register in each of the plurality of subordinate circuits is set to FALSE; and configuring an alternative control register among the at least one control register with the respective one or more control bits extracted from the aggregated control word when the register swap flag is set to TRUE.

19. The method of claim 16, further comprising communicating, by a selected one of the plurality of subordinate circuits, an acknowledgement (ACK) to the main circuit in response to receiving the bus telegram when the VS ID carried in the bus telegram matches the USID of the selected one of the plurality of subordinate circuits.

20. The method of claim 16, further comprising configuring a default control register among the at least one control register with the respective one or more control bits extracted from the aggregated control word.

Images