Display panel and display device

Abstract

A display panel (PNL) and a display device, relating to the technical field of display. The display panel (PNL) comprises a plurality of display units (DU) arranged in an array. Second display units (DUR) each comprise a second sub-pixel (PXR) and a pixel driving circuit (PDC), and first display units (DUB) each comprise a first sub-pixel (PXB) and a pixel driving circuit (PDC). In the second display units (DUR) in each second display unit column (VDUR), second sub-pixels (PXR) are electrically connected to output ends of the pixel driving circuits (PDC). In the first display units (DUB) in each first display unit column (VDUB), the first sub-pixels (PXB) are electrically connected to output ends of the pixel driving circuits (PDC). The first sub-pixels (PXB) in at least part of the second display unit columns (VDUR) are electrically connected to the output ends of the pixel driving circuits (PDC) of the second display units (DUR) in the first display unit columns (VDUB). The second sub-pixels (PXR) in at least part of the first display unit columns (VDUB) are electrically connected to the output ends of the pixel driving circuits (PDC) of the first display units (DUB) in the second display unit columns (VDUR). The display panel (PNL) can reduce driving power consumption.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In some display panels, part of data lines are used to drive sub-pixels of different colors, which results in high driving power consumption of the display panel.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The present disclosure aims to overcome the shortcomings of the prior art, and provide a display panel and a display device to reduce the power consumption of the display panel.

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a plurality of display units arranged in an array; the plurality of display units are arranged into a plurality of display unit columns and a plurality of display unit rows;

[0007] The plurality of display unit columns comprises second display unit columns and first display unit columns arranged alternately along the row direction; the second display unit columns and the first display unit columns each comprise second display units and first display units arranged alternately along the column direction; the second display units of the second display unit columns and the second display units of the first display unit columns are located in different display unit rows; the second display unit comprises a second sub-pixel and a pixel driving circuit, and the first display unit comprises a second sub-pixel and a pixel driving circuit;

[0008] The display panel further comprises a plurality of data lines corresponding to each display unit column; each pixel driving circuit of the second display unit column is electrically connected to a corresponding data line; each pixel driving circuit of the first display unit column is electrically connected to a corresponding data line;

[0009] In the second display unit in the second display unit column, the second sub-pixel is electrically connected to the output end of the pixel driving circuit; in the first display unit in the first display unit column, the first sub-pixel is electrically connected to the output end of the pixel driving circuit;

[0010] The first sub-pixel in at least part of the second display unit column is electrically connected with an output terminal of a pixel driving circuit of the second display unit in the first display unit column; and the second sub-pixel in at least part of the first display unit column is electrically connected with an output terminal of a pixel driving circuit of the first display unit in the second display unit column.

[0011] According to an embodiment of the present disclosure, the first sub-pixel in at least part of the second display unit column and the pixel driving circuit electrically connected therewith are located in different display unit rows; and the second sub-pixel in at least part of the first display unit column and the pixel driving circuit electrically connected therewith are located in different display unit rows.

[0012] According to an embodiment of the present disclosure, the plurality of display unit rows include non-heterogeneous display unit rows and heterogeneous display unit rows which are alternately arranged in sequence along the column direction; the second display unit in the second display unit column and the first display unit in the first display unit column are located in the non-heterogeneous display unit row, and the first display unit in the second display unit column and the second display unit in the first display unit column are located in the heterogeneous display unit row.

[0013] The first sub-pixel in at least part of the second display unit column and the pixel driving circuit electrically connected therewith are located in two adjacent heterogeneous display unit rows, respectively.

[0014] The second sub-pixel in at least part of the first display unit column and the pixel driving circuit electrically connected therewith are located in two adjacent heterogeneous display unit rows, respectively.

[0015] According to an embodiment of the present disclosure, the first sub-pixel in the second display unit column is located in an xth heterogeneous display unit row, and the pixel driving circuit electrically connected with the first sub-pixel in the second display unit column is located in an (x+1)th heterogeneous display unit row.

[0016] The second sub-pixel in the first display unit column is located in an xth heterogeneous display unit row, and the pixel driving circuit electrically connected with the second sub-pixel in the first display unit column is located in an (x+1)th heterogeneous display unit row.

[0017] Wherein, x is a positive integer and x

[0018] According to an embodiment of the present disclosure, the display panel further includes an auxiliary pixel driving circuit row, the auxiliary pixel driving circuit row includes a plurality of second auxiliary pixel driving circuits corresponding to each second display unit column one by one and a plurality of first auxiliary pixel driving circuits corresponding to each first display unit column one by one.

[0019] The second auxiliary pixel driving circuit is connected to the same data wire as each pixel driving circuit in the corresponding second display unit column;

[0020] The first auxiliary pixel driving circuit is connected to the same data wire as each pixel driving circuit in the corresponding first display unit column;

[0021] The second sub-pixel in the Mth heterogeneous display unit row is electrically connected to the second auxiliary pixel driving circuit in the auxiliary pixel driving circuit row;

[0022] The first sub-pixel in the Mth heterogeneous display unit row is electrically connected to the first auxiliary pixel driving circuit in the auxiliary pixel driving circuit row.

[0023] According to an embodiment of the present disclosure, the first sub-pixel in the second display unit column is located in the yth second display unit column, and the pixel driving circuit to which the first sub-pixel in the second display unit column is electrically connected is located in the first display unit column between the yth second display unit column and the y+1th second display unit column;

[0024] The second sub-pixel in the first display unit column is located in the zth first display unit column, and the pixel driving circuit to which the second sub-pixel in the first display unit column is electrically connected is located in the second display unit column between the zth first display unit column and the z+1th first display unit column;

[0025] wherein y is a positive integer and y

[0026] According to an embodiment of the present disclosure, the display panel further comprises an auxiliary pixel driving circuit column and an auxiliary data wire, the auxiliary pixel driving circuit column and the auxiliary data wire are located on the side of the Qth first display unit column and the Nth second display unit column away from the N-1th second display unit column; the auxiliary pixel driving circuit column comprises a pixel driving circuit corresponding to each of the display unit rows, and each pixel driving circuit is electrically connected to the auxiliary data wire;

[0027] The Nth second display unit column is located between the Qth first display unit column and the auxiliary pixel driving circuit column, and the pixel driving circuit to which the first sub-pixel on the N second display unit column is electrically connected is located in the auxiliary pixel driving circuit column; and / or, the Qth first display unit column is located between the Nth second display unit column and the auxiliary pixel driving circuit column, and the pixel driving circuit to which the second sub-pixel on the Q first display unit column is electrically connected is located in the auxiliary pixel driving circuit column.

[0028] According to an embodiment of the present disclosure, the plurality of display unit columns further comprises a plurality of third display unit columns, the second display unit column is provided with the third display unit column between the adjacent first display unit column;

[0029] The third display unit column comprises a plurality of third display units arranged in sequence along the column direction, and each third display unit comprises a pixel driving circuit and a third sub-pixel electrically connected to an output terminal of the pixel driving circuit.

[0030] The display panel further comprises a plurality of data wires corresponding to each third display unit column, and the pixel driving circuit of each third display unit column is electrically connected to the corresponding data wire.

[0031] According to an embodiment of the present disclosure, the display panel is provided with a first adapter wire corresponding to each first sub-pixel in the second display unit column, and a second adapter wire corresponding to each second sub-pixel in the first display unit column.

[0032] The first sub-pixel in the second display unit column is electrically connected to the output terminal of the electrically connected pixel driving circuit through the corresponding first adapter wire; and the second sub-pixel in the first display unit column is electrically connected to the output terminal of the electrically connected pixel driving circuit through the corresponding second adapter wire.

[0033] According to an embodiment of the present disclosure, the display panel comprises a substrate, a driving layer and a pixel layer which are sequentially stacked; the pixel driving circuit, the first adapter wire and the second adapter wire are arranged in the driving layer, and the first sub-pixel and the second sub-pixel are arranged in the pixel layer.

[0034] According to an embodiment of the present disclosure, the display panel comprises a substrate, a driving layer and a pixel layer which are sequentially stacked; the pixel driving circuit is arranged in the driving layer, and the first sub-pixel and the second sub-pixel are arranged in the pixel layer.

[0035] The pixel electrode of the first sub-pixel has a connection area, the connection area of the pixel electrode of the first sub-pixel is electrically connected to the pixel driving circuit driving the first sub-pixel through a via hole; the orthographic projection of the connection area of the pixel electrode of the first sub-pixel of the first display unit on the substrate is located in the orthographic projection of the layout area of the pixel driving circuit of the first display unit on the substrate.

[0036] The pixel electrode of the second sub-pixel has a connection region, and the connection region of the pixel electrode of the second sub-pixel is electrically connected with the pixel driving circuit driving the second sub-pixel through a via hole; the orthographic projection of the connection region of the pixel electrode of the second sub-pixel of the second display unit on the substrate is located in the orthographic projection of the layout region of the pixel driving circuit of the second display unit on the substrate.

[0037] According to a second aspect of the present disclosure, a display device is provided, comprising the display panel as described above.

[0038] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0039] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0040] FIG. 1 is a structural schematic diagram of a display panel in an embodiment of the present disclosure.

[0041] FIG. 2 is a structural schematic diagram of a display panel in an embodiment of the present disclosure.

[0042] FIG. 3 is a structural schematic diagram of a display panel in an embodiment of the present disclosure.

[0043] FIG. 4 is a structural schematic diagram of a sub-pixel in an embodiment of the present disclosure.

[0044] FIG. 5 is a structural schematic diagram of a sub-pixel in an embodiment of the present disclosure.

[0045] FIG. 6 is a structural schematic diagram of a display unit distribution structure on a display panel in a related art.

[0046] FIG. 7 is a structural schematic diagram of a display unit distribution structure on a display panel in an embodiment of the present disclosure.

[0047] FIG. 8 is a structural schematic diagram of a display unit distribution structure on a display panel in an embodiment of the present disclosure.

[0048] FIG. 9 is a structural schematic diagram of a display unit distribution structure on a display panel in an embodiment of the present disclosure.

[0049] FIG. 10 is a structural schematic diagram of a display unit distribution structure on a display panel in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0051] Although relative terms such as "on", "under", etc. are used herein to describe one component's relationship to another component, these terms are used herein only to facilitate the description of the drawings, and do not denote relative positions, unless otherwise specified. It is understood that when an apparatus is turned over, components described as on one side of other will be on the opposite side. When a structure is on another structure, it can mean that the structure is formed integrally on the other structure, or that the structure is disposed directly on the other structure, or that the structure is disposed indirectly on the other structure via another structure.

[0052] The terms "one", "a", "the", "said", and "at least one" are used to indicate the existence of one or more elements / components / etc.; the terms "include" and "have" are used to indicate an open-ended inclusion of one or more elements / components / etc. not excluding additional elements / components / etc.; the terms "first", "second", and "third" etc. are used only to distinguish one component from another, and not to limit the number of components.

[0053] In the present disclosure, when it is described that structure A and structure B are disposed to overlap, it means that structure A and structure B are disposed on different film layers, and the orthographic projection of structure A on a substrate and the orthographic projection of structure B on the substrate have a coinciding portion.

[0054] In the present disclosure, structure layer C is located on the side of structure layer D away from the substrate, which can be understood as structure layer C being formed on the side of structure layer D away from the substrate. When structure layer C is a patterned structure, part of structure layer C can also be located at the same physical height as structure layer D or below the physical height of structure layer D, wherein the substrate is the height reference.

[0055] The display panel PNL and the display device employing the same are provided. Referring to FIG. 1, the display panel PNL includes a display area AA and a peripheral area BB located at least one side of the display area AA; for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with sub-pixels PX for display; in the peripheral area BB, the display panel PNL can not be provided with sub-pixels PX for display, or the provided sub-pixels PX are not used for displaying a picture.

[0056] In an embodiment of the present disclosure, the sub-pixels PX in the display panel PNL are thin-film self-luminous light-emitting elements, such as OLED (organic light-emitting diode), PLED (polymer light-emitting diode), QLED (quantum dot light-emitting diode), etc. Further, the sub-pixels PX located in the display area AA include sub-pixels PX of multiple different colors. For example, in the example of FIG. 1, the sub-pixels PX include second sub-pixels PXR for emitting light of a first color, first sub-pixels PXB for emitting light of a second color, and third sub-pixels PXG for emitting light of a third color. In an example, the wavelength of the light emitted by the first sub-pixels PXB, the wavelength of the light emitted by the third sub-pixels PXG, and the wavelength of the light emitted by the second sub-pixels PXR increase in turn, for example, the first sub-pixels PXB are used to emit blue light, the third sub-pixels PXG are used to emit green light, and the second sub-pixels PXR are used to emit red light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PX in the display area AA can also have sub-pixels PX of other colors (such as yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, magenta sub-pixels for emitting magenta light, or white sub-pixels for emitting white light, etc.). Of course, in other embodiments of the present disclosure, the sub-pixels PX in the display panel PNL can also not be thin-film light-emitting elements, such as LED (inorganic light-emitting diode), Micro LED (micro light-emitting diode), or Mini LED (mini light-emitting diode), etc.

[0057] In an embodiment of the present disclosure, referring to FIG. 2, the display panel PNL can include a substrate SBT, a driving layer DRL, and a pixel layer PXL stacked in turn, the pixel layer PXL is provided with sub-pixels PX, and the driving layer DRL is provided with pixel driving circuits PDC for driving each sub-pixel PX, each sub-pixel PX emits light under the driving of the pixel driving circuit PDC to which it is electrically connected, for example, each sub-pixel PX independently emits light, thereby realizing picture display.

[0058] Optionally, the substrate SBT can be a substrate of inorganic material, or a substrate of organic material, or a composite substrate of inorganic material and organic material. For example, in some embodiments of the present disclosure, the substrate SBT can be made of glass material such as soda lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the substrate SBT can be made of poly(methyl methacrylate), polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can be a flexible substrate, for example, the substrate SBT can include polyimide.

[0059] Optionally, in the driving layer DRL, any one of the pixel driving circuits can include a thin film transistor and a storage capacitor. Further, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0060] It can be understood that in the pixel driving circuit, the types of any two of the transistors can be the same or different. For example, in some embodiments, in one pixel driving circuit, part of the thin film transistors can be N-type transistors and part of the thin film transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit, part of the thin film transistors can be made of low-temperature polysilicon semiconductor material and part of the thin film transistors can be made of metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, part of the thin film transistors are low-temperature polysilicon transistors and part of the thin film transistors are metal oxide transistors.

[0061] In one embodiment of the present disclosure, referring to FIG. 3, the driving layer DRL can include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, and the like, which are laminated between the substrate base plate SBT and the pixel layer PXL. Each thin film transistor and storage capacitor can be formed by the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source-drain metal layer SD, and the like, or by other film layers. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor (as part of the active layer), and can also be used to form part of the wiring or conductive structure by being made conductive when necessary. The gate layer can be used to form one or more of the gate layer wiring such as the scan wiring, the reset control wiring, the light-emitting control wiring, and the like, and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrodes of the storage capacitor. The source-drain metal layer can be used to form the data wiring, the driving power voltage wiring, and the like, and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, such as an optical shielding layer between the semiconductor layer SCL and the substrate base plate SBT, and the like. Any of the above-mentioned semiconductor layer SCL, gate layer GT, source-drain metal layer SD, and the like, can also be multi-layered as needed, such as two different semiconductor layers SCL in the driving layer DRL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the number or type of insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, and the like) can be increased or decreased adaptively, or new insulating film layers can be added as needed.

[0062] Optionally, the driving layer DRL can also include a passivation layer, which can be provided on the surface of the source-drain metal layer SD away from the substrate base plate SBT, so as to protect the source-drain metal layer SD.

[0063] As an example, referring to FIG. 3, the driving layer DRL can include, in sequence from the side of the substrate SBT, a first inorganic buffer layer BUFA, a first semiconductor layer SCL1, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BUFB, a second gate layer GT2, a second gate insulating layer GI2, a second semiconductor layer SCL2, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, a third source-drain metal layer SD3, a third planarization layer PLN3, and the like. In this example, the driving layer DRL is provided with two semiconductor layers SCL, i.e., the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The materials of the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can be different, for example, the material of the first semiconductor layer SCL1 can be a low-temperature polysilicon material, and the material of the second semiconductor layer SCL2 can be a metal-oxide semiconductor material. In this example, the driving layer DRL is provided with three gate layers GT, i.e., the first gate layer GT1, the second gate layer GT2, and the third gate layer GT3; correspondingly, the driving layer DRL is provided with three gate insulating layers GI, i.e., the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3. In this example, the driving layer DRL is provided with three source-drain metal layers SD, i.e., the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3; correspondingly, the driving layer DRL is provided with three planarization layers PLN, i.e., the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3. It can be understood that the example of FIG. 3 is only a specific example of the driving layer DRL of the embodiments of the present disclosure. According to needs, the driving layer DRL of the display panel PNL can also adopt other structures, for example, the driving layer DRL only includes two source-drain metal layers SD, or the driving layer DRL includes four source-drain metal layers SD, and the like.

[0064] In an embodiment of the present disclosure, referring to FIG. 3, the pixel layer PXL can include a pixel electrode layer PEL, a pixel definition layer PDL, an emission functional layer EFL, and a common electrode layer COML which are sequentially stacked. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE, and any one of the pixel openings exposes at least a partial region of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edges of the pixel electrode and exposes at least a partial inner region of the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective region (a region directly connected to the emission functional layer EFL) of the pixel electrode, and further define the light emitting region and the light emitting area of the sub-pixel PX. In an embodiment of the present disclosure, the region of the pixel electrode PE exposed by the pixel definition layer PDL can be referred to as the light emitting region of the pixel electrode PE. The common electrode layer COML covers the emission functional layer EFL as a common electrode. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the emission functional layer EFL, so that the emission functional layer EFL emits light. The part of the emission functional layer EFL between the pixel electrode PE and the common electrode layer COML can serve as the light emitting functional unit of the sub-pixel PX. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit form the light emitting element of the sub-pixel PX. One of the pixel electrode PE and the common electrode layer COML serves as the anode of the sub-pixel PX, and the other serves as the cathode of the sub-pixel PX.

[0065] In an embodiment of the present disclosure, the planarization layer PLN (for example, the third planarization layer PLN3 in FIG. 3) closest to the pixel layer PXL has a connection via that exposes the source-drain metal layer SD (for example, the third source-drain metal layer SD3 in FIG. 3) closest to the pixel layer PXL, and the pixel electrode PE is electrically connected to the source-drain metal layer SD closest to the pixel layer PXL through the connection via. In an embodiment of the present disclosure, the region of the pixel electrode PE in the connection via is referred to as the connection region CNT of the pixel electrode PE; the connection region CNT of the pixel electrode PE is electrically connected to the source-drain metal layer SD in the driving layer DRL through the via; this makes the connection region CNT of the pixel electrode PE of the sub-pixel PX electrically connected to the output end of the pixel driving circuit PDC driving the sub-pixel PX through the via.

[0066] It can be understood that the type of sub-pixel PX is different, and the material and film layer of the light-emitting functional layer EFL are different. For example, referring to FIG. 4, when the sub-pixel PX is an OLED, the light-emitting functional layer EFL can include an organic light-emitting layer EML, and can include one or more of a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the organic light-emitting layer EML can include a light-emitting layer host material and a light-emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular can be a thermally activated delayed fluorescence material. When the OLED adopts a stacked structure, a charge generation layer can also be provided in the light-emitting functional layer EFL. For another example, referring to FIG. 5, when the sub-pixel PX is a QLED, the light-emitting functional layer EFL can include a quantum dot layer QDL, and can include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the quantum dot layer QDL can have quantum dot particles, which can be connected to each other by surface modification groups. When the QLED adopts a stacked structure, a charge generation layer can also be provided in the light-emitting functional layer EFL.

[0067] In an embodiment of the present disclosure, referring to FIG. 3, the display panel PNL can also be provided with an encapsulation layer, for example, a thin film encapsulation layer TFE. The thin film encapsulation layer TFE can be provided on the surface of the pixel layer PXL away from the substrate substrate SBT, and can include inorganic encapsulation layers and organic encapsulation layers alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, so as to avoid water and oxygen from invading the pixel layer PXL and causing the material in the pixel layer PXL to age. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers, so as to achieve planarization and weaken the stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. For example, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence on the side of the pixel layer PXL away from the substrate substrate SBT. Of course, in other embodiments of the present disclosure, the display panel can also be provided with other types of encapsulation layers, for example, a thin film encapsulation layer using all inorganic materials.

[0068] In the embodiments of the present disclosure, the display panel PNL is provided with sub-pixels PX and pixel driving circuits PDC, the sub-pixels PX emit light under the driving of the pixel driving circuits PDC. The sub-pixels PX and the pixel driving circuits PDC corresponding in space can be taken together as a display unit DU according to the spatial positional relationship between the sub-pixels PX and the pixel driving circuits PDC. In an example, the pixel electrode of the sub-pixel PX has a connection region, and the connection region of the pixel electrode of the sub-pixel PX is electrically connected to the pixel driving circuit PDC for driving the sub-pixel PX through a via hole. In the sub-pixel PX and the pixel driving circuit PDC of the same display unit DU, the orthogonal projection of the connection region of the pixel electrode of the sub-pixel PX on the substrate SBT is located within the orthogonal projection of the layout region of the pixel driving circuit PDC on the substrate SBT. In other words, in this example, when the orthogonal projection of the connection region of the pixel electrode of a sub-pixel PX on the substrate SBT is located within the orthogonal projection of the layout region of a pixel driving circuit PDC on the substrate SBT, the sub-pixel PX and the pixel driving circuit PDC form a display unit DU. It can be understood that each sub-pixel PX and each pixel driving circuit PDC for forming a display unit DU are one-to-one correspondence, each sub-pixel PX only forms a display unit DU with one pixel driving circuit PDC, and each pixel driving circuit PDC only forms a display unit DU with one sub-pixel PX.

[0069] Referring to FIG. 1, the display panel PNL includes display units DU arranged in an array, that is, the display units DU are arranged in an array along the row direction DH and the column direction DV. The display panel PNL can arrange a plurality of display unit columns VDU and a plurality of display unit rows HDU. The display unit column VDU includes a plurality of display units DU arranged in sequence along the column direction DV, and the plurality of display unit columns VDU are arranged in sequence along the row direction DH. The display unit row HDU includes a plurality of display units DU arranged in sequence along the row direction DH, and the plurality of display unit rows HDU are arranged in sequence along the column direction DV. Referring to FIG. 1, the display panel PNL is also provided with a data wire DL corresponding to each display unit column VDU, and each pixel driving circuit PDC of the display unit column VDU is electrically connected to the corresponding data wire DL. In this way, the data wire DL can load a data voltage to the pixel driving circuit PDC, and the pixel driving circuit PDC drives the electrically connected sub-pixel PX according to the data voltage. Referring to FIG. 1, the display panel PNL is also provided with a plurality of GLs corresponding to each display unit row HDU, and each pixel driving circuit PDC of the display unit row HDU is electrically connected to the corresponding GL. In the embodiments of the present disclosure, the direction in which the data wire DL extends as a whole can be referred to as the column direction DV, and the direction in which the GL extends as a whole can be referred to as the row direction DH; the row direction DH and the column direction DV intersect, for example, the row direction DH is perpendicular to the column direction DV.

[0070] FIG. 6 is a schematic diagram of a display panel PNL in the related art. Referring to FIG. 6, in the related art, the display panel PNL includes display units DU arranged in an array, but the sub-pixels PX in the same display unit DU are electrically connected with the pixel driving circuit PDC. In other words, the pixel driving circuit PDC in the display unit DU drives the sub-pixels PX in the display unit DU. However, some display unit columns VDU include sub-pixels PX of multiple colors instead of sub-pixels PX of one color. For example, in the example of FIG. 6, one display unit column VDU includes second sub-pixels (PXR) and first sub-pixels PXB arranged in the column direction DV in an alternating manner, and the data line DL driving the display unit column VDU needs to switch the data voltage back and forth, resulting in a large driving power consumption.

[0071] FIG. 7 is a schematic diagram of a partial structure of a display panel PNL in an embodiment of the present disclosure. Referring to FIG. 7, in the embodiment of the present disclosure, the sub-pixels PX and the pixel driving circuit PDC of at least some display units DU are not electrically connected. The display unit DU with the sub-pixel PX being a second sub-pixel (PXR) is referred to as a second display unit DUR in the embodiment of the present disclosure, and the display unit DU with the sub-pixel PX being a first sub-pixel PXB is referred to as a first display unit DUB in the embodiment of the present disclosure. For example, in the example of FIG. 10, the first sub-pixel PXB at the 1st row and the 2nd column is labeled as PXB12, and the pixel driving circuit PDC at the 1st row and the 2nd column is labeled as PDC12, and the sub-pixel PXB12 and the pixel driving circuit PDC12 form a first display unit DUB. The second sub-pixel (PXR) at the 1st row and the 4th column is labeled as (PXR)14, and the pixel driving circuit PDC at the 1st row and the 4th column is labeled as PDC14, and the sub-pixel (PXR)14 and the pixel driving circuit PDC14 form a second display unit DUR. The first sub-pixel PXB at the 1st row and the 6th column is labeled as PXB16, and the pixel driving circuit PDC at the 1st row and the 6th column is labeled as PDC16, and the sub-pixel PXB16 and the pixel driving circuit PDC16 form a first display unit DUB. The second sub-pixel (PXR) at the 2nd row and the 2nd column is labeled as (PXR)22, and the pixel driving circuit PDC at the 2nd row and the 2nd column is labeled as PDC22, and the sub-pixel (PXR)22 and the pixel driving circuit PDC22 form a second display unit DUR. In the example of FIG. 10, the display panel PNL shown in the example has only four rows of sub-pixels PX, i.e., the display panel PNL has four display unit rows HDU. It can be understood that FIG. 10 only takes the display panel PNL having four display unit rows HDU as an example, and in other embodiments of the present disclosure, the number of display unit rows HDU can be larger, for example, can be 500-8000.

[0072] The plurality of display unit columns VDU include second display unit columns VDUR and first display unit columns VDUB arranged alternately in sequence along the row direction DH; the second display unit columns VDUR and the first display unit columns VDUB each include second display units DUR and first display units DUB arranged alternately in sequence along the column direction DV; the second display units DUR of the second display unit columns VDUR and the second display units DUR of the first display unit columns VDUB are located in different display unit rows HDU; the second display unit DUR includes a second sub-pixel (PXR) and a pixel driving circuit PDC, and the first display unit DUB includes a first sub-pixel PXB and a pixel driving circuit PDC; in the second display unit DUR in the second display unit column VDUR, the second sub-pixel (PXR) is electrically connected to the output end of the pixel driving circuit PDC; in the first display unit DUB in the first display unit column VDUB, the first sub-pixel PXB is electrically connected to the output end of the pixel driving circuit PDC; at least part of the first sub-pixels PXB in the second display unit columns VDUR are electrically connected to the output end of the pixel driving circuit PDC of the second display unit DUR in the first display unit column VDUB; at least part of the second sub-pixels (PXR) in the first display unit columns VDUB are electrically connected to the output end of the pixel driving circuit PDC of the first display unit DUB in the second display unit column VDUR.

[0073] In this embodiment, when the second display unit DUR is located in the second display unit column VDUR, the pixel driving circuit PDC of the second display unit DUR is electrically connected to the second sub-pixel (PXR) of the second display unit DUR; when the second display unit DUR is located in the first display unit column VDUB, the pixel driving circuit PDC of the second display unit DUR is not electrically connected to the second sub-pixel (PXR) of the second display unit DUR. When the first display unit DUB is located in the first display unit column VDUB, the pixel driving circuit PDC of the first display unit DUB is electrically connected to the first sub-pixel PXB of the first display unit DUB; when the first display unit DUB is located in the second display unit column VDUR, the pixel driving circuit PDC of the first display unit DUB is not electrically connected to the first sub-pixel PXB of the first display unit DUB.

[0074] In this embodiment, each pixel driving circuit PDC in the second display unit column VDUR is electrically connected with the data wire DL corresponding to the second display unit column VDUR. The output terminal of the pixel driving circuit PDC of the first display unit DUB in the second display unit column VDUR is not electrically connected with the first sub-pixel PXB of the first display unit DUB; when the pixel driving circuit PDC of the first display unit DUB in the second display unit column VDUR is used to drive the sub-pixel PX, the pixel driving circuit PDC is electrically connected with the second sub-pixel (PXR) in the first display unit column VDUB. Therefore, the pixel driving circuit PDC in the second display unit column VDUR is not used to drive the first sub-pixel PXB, but is partially or entirely used to drive the second sub-pixel (PXR); the data wire DL electrically connected with the second display unit column VDUR only needs to load the driving voltage required by the second sub-pixel (PXR), without switching back and forth between the driving voltage required by the second sub-pixel (PXR) and the driving voltage required by the first sub-pixel PXB, thereby reducing the driving power consumption of the second display unit column VDUR.

[0075] Correspondingly, each pixel driving circuit PDC in the first display unit column VDUB is electrically connected with the data wire DL corresponding to the first display unit column VDUB. The output terminal of the pixel driving circuit PDC of the second display unit DUR in the first display unit column VDUB is not electrically connected with the second sub-pixel (PXR) of the second display unit DUR; when the pixel driving circuit PDC of the second display unit DUR in the first display unit column VDUB is used to drive the sub-pixel PX, the pixel driving circuit PDC is electrically connected with the first sub-pixel PXB in the second display unit column VDUR. Therefore, the pixel driving circuit PDC in the first display unit column VDUB is not used to drive the second sub-pixel (PXR), but is partially or entirely used to drive the first sub-pixel PXB; the data wire DL electrically connected with the first display unit column VDUB only needs to load the driving voltage required by the first sub-pixel PXB, without switching back and forth between the driving voltage required by the first sub-pixel PXB and the driving voltage required by the second sub-pixel (PXR), thereby reducing the driving power consumption of the first display unit column VDUB.

[0076] In an example, the pixel electrode of the first sub-pixel PXB has a connection region, the connection region of the pixel electrode of the first sub-pixel PXB is electrically connected with the pixel driving circuit PDC driving the first sub-pixel PXB through a via; the orthogonal projection of the connection region of the pixel electrode of the first sub-pixel PXB of the first display unit DUB on the substrate SBT is located within the orthogonal projection of the layout region of the pixel driving circuit PDC of the first display unit DUB on the substrate SBT.

[0077] In an example, the pixel electrode of the second sub-pixel (PXR) has a connection region, and the connection region of the pixel electrode of the second sub-pixel (PXR) is electrically connected with the pixel driving circuit PDC driving the second sub-pixel (PXR) through a via hole; the orthographic projection of the connection region of the pixel electrode of the second sub-pixel (PXR) of the second display unit DUR on the substrate SBT is located within the orthographic projection of the layout region of the pixel driving circuit PDC of the second display unit DUR on the substrate SBT.

[0078] In an embodiment of the present disclosure, the sub-pixel PX further includes a third sub-pixel PXG, and correspondingly, the display unit DU further includes a third display unit DUG; the third display unit DUG includes the third sub-pixel PXG and the pixel driving circuit PDC. Wherein, the pixel electrode of the third sub-pixel PXG has a connection region, and the connection region of the pixel electrode of the third sub-pixel PXG is electrically connected with the pixel driving circuit PDC driving the third sub-pixel PXG through a via hole; the orthographic projection of the connection region of the pixel electrode of the third sub-pixel PXG of the third display unit DUG on the substrate SBT is located within the orthographic projection of the layout region of the pixel driving circuit PDC of the third display unit DUG on the substrate SBT. In an example, the third sub-pixel PXG of the third display unit DUG is electrically connected with the pixel driving circuit PDC of the third display unit DUG, that is, the third display unit DUG includes the pixel driving circuit PDC and the third sub-pixel PXG electrically connected with the output end of the pixel driving circuit PDC.

[0079] In an embodiment of the present disclosure, the display unit column VDU includes a third display unit column VDUG, and the third display unit column VDUG includes a plurality of third display units DUG arranged in sequence along the column direction DV, for example, each display unit DU in the third display unit column VDUG is a third display unit DUG. The display panel PNL further includes a plurality of data wires DL corresponding to each third display unit column VDUG, and the pixel driving circuit PDC of each third display unit column VDUG is electrically connected with the corresponding data wire DL. Therefore, the data wire DL corresponding to the third display unit column VDUG only needs to load the driving voltage required by the third sub-pixel PXG to each pixel driving circuit PDC, without reciprocating switching between the driving voltages required by sub-pixels PX of different colors.

[0080] In an embodiment of the present disclosure, the third display unit column VDUG is arranged between the second display unit column VDUR and the adjacent first display unit column VDUB.

[0081] In the embodiments of the present disclosure, the display units DU can be divided into driving display units DU and separated display units DU according to whether the sub-pixels PX and the pixel driving circuit PDC of the display unit DU are electrically connected. When the sub-pixels PX in a display unit DU are electrically connected with the pixel driving circuit PDC in the display unit DU, that is, the pixel driving circuit PDC in the display unit DU is used to drive the sub-pixels PX in the display unit DU, the display unit DU is a driving display unit DU. When the sub-pixels PX in a display unit DU are not electrically connected with the pixel driving circuit PDC in the display unit DU, that is, the pixel driving circuit PDC in the display unit DU is not used to drive the sub-pixels PX in the display unit DU, the display unit DU is a separated display unit DU.

[0082] The display unit columns VDU can be divided into two types of heterogeneous display unit columns VDUM and non-heterogeneous display unit columns VDUN according to whether the sub-pixels PX and the pixel driving circuit PDC of the display unit DU in the display unit column VDU are electrically connected. Each display unit DU in the non-heterogeneous display unit column VDUN is a driving display unit DU, for example, the third display unit column VDUG is a non-heterogeneous display unit column VDUN. At least one display unit DU in the heterogeneous display unit column VDUM is a separated display unit DU, for example, the second display unit column VDUR and the first display unit column VDUB are heterogeneous display unit columns VDUM. In an example, along the row direction DH, the heterogeneous display unit columns VDUM and the non-heterogeneous display unit columns VDUN are arranged alternately; in each heterogeneous display unit column VDUM, the third display unit column VDUG and the second display unit column VDUR are arranged alternately.

[0083] The display unit rows HDU can be divided into two types of heterogeneous display unit rows HDUM and non-heterogeneous display unit rows HDUN according to whether the sub-pixels PX and the pixel driving circuit PDC of the display unit DU in the display unit row HDU are electrically connected. Each display unit DU in the non-heterogeneous display unit row HDUN is a driving display unit DU; for example, the second display unit DUR in the second display unit column VDUR and the first display unit DUB in the first display unit column VDUB can be located in the non-heterogeneous display unit row HDUN. At least one display unit DU in the heterogeneous display unit row HDUM is a separated display unit DU; for example, the first display unit DUB in the second display unit column VDUR and the second display unit DUR in the first display unit column VDUB can be located in the heterogeneous display unit row HDUM. In an example, along the column direction DV, the heterogeneous display unit rows HDUM and the non-heterogeneous display unit rows HDUN are arranged alternately.

[0084] In an embodiment of the present disclosure, the first sub-pixel PXB in at least part of the second display unit column VDUR is located in a different display unit row HDU from the pixel driving circuit PDC electrically connected thereto; the second sub-pixel (PXR) in at least part of the first display unit column VDUB is located in a different display unit row HDU from the pixel driving circuit PDC electrically connected thereto. In this embodiment, the first sub-pixel PXB of the first display unit DUB in one heterogeneous display unit row HDUM is electrically connected to the output end of the pixel driving circuit PDC of the second display unit DUR in another heterogeneous display unit row HDUM; the second sub-pixel (PXR) of the second display unit DUR in one heterogeneous display unit row HDUM is electrically connected to the output end of the pixel driving circuit PDC of the first display unit DUB in another heterogeneous display unit row HDUM. For example, in the non-edge region of the display area, the first sub-pixel PXB in the second display unit column VDUR and the pixel driving circuit PDC electrically connected thereto are located in adjacent two heterogeneous display unit rows HDUM, respectively; in the non-edge region of the display area, the second sub-pixel (PXR) in the first display unit column VDUB and the pixel driving circuit PDC electrically connected thereto are located in adjacent two heterogeneous display unit rows HDUM, respectively. In this embodiment, the sub-pixel PX and the pixel driving circuit PDC of the separated display unit DU are located in adjacent two heterogeneous display unit rows HDUM, which can reduce the difficulty of wiring of the display panel PNL.

[0085] As an example, the first sub-pixel PXB in the second display unit column VDUR is located in the xth heterogeneous display unit row HDUM, and the pixel driving circuit PDC electrically connected to the first sub-pixel PXB in the second display unit column VDUR is located in the (x+1)th heterogeneous display unit row HDUM; the second sub-pixel (PXR) in the first display unit column VDUB is located in the xth heterogeneous display unit row HDUM, and the pixel driving circuit PDC electrically connected to the second sub-pixel (PXR) in the first display unit column VDUB is located in the (x+1)th heterogeneous display unit row HDUM; wherein x is a positive integer and x

[0086] For example, the i-th hetero-display unit row HDUM is denoted as HDUM(i), and the j-th hetero-display unit column VDUM is denoted as VDUM(j). Wherein, i is a positive integer and i < M, j is a positive integer and j < Q+N, N is the number of the second display unit columns VDUR, and Q is the number of the first display unit columns VDUB. The display unit DU(i, j) represents a display unit DU located in the hetero-display unit row HDUM(i) and in the hetero-display unit column VDUM(j), which is a separated display unit DU. The sub-pixel PX of the display unit DU(i, j) is denoted as PX(i, j), and the pixel driving circuit PDC of the display unit DU(i, j) is denoted as PDC(i, j). The sub-pixel PX(i, j) is electrically connected with the pixel driving circuit PDC(i+1, j+1), i.e., the pixel driving circuit PDC(i+1, j+1) drives the sub-pixel PX(i, j).

[0087] In an example, referring to FIG. 8, the display panel PNL further comprises an auxiliary pixel driving circuit row D-HPDC, which comprises a plurality of second auxiliary pixel driving circuits PDCR corresponding to each second display unit column VDUR and a plurality of first auxiliary pixel driving circuits PDCB corresponding to each first display unit column VDUB. The second auxiliary pixel driving circuit PDCR is connected to the same data wire DL as each pixel driving circuit PDC in the corresponding second display unit column VDUR. The first auxiliary pixel driving circuit PDCB is connected to the same data wire DL as each pixel driving circuit PDC in the corresponding first display unit column VDUB. The second sub-pixel (PXR) in the M-th hetero-display unit row HDUM is electrically connected with the second auxiliary pixel driving circuit PDCR in the auxiliary pixel driving circuit row D-HPDC, and the first sub-pixel PXB in the M-th hetero-display unit row HDUM is electrically connected with the first auxiliary pixel driving circuit PDCB in the auxiliary pixel driving circuit row D-HPDC. In this way, the auxiliary pixel driving circuit row D-HPDC can drive the sub-pixels PX of the separated display unit DU in the last hetero-display unit row HDUM, for example, the second sub-pixel (PXR) and the first sub-pixel PXB in the last hetero-display unit row HDUM.

[0088] In some examples, the auxiliary pixel driving circuit row D-HPDC further comprises a third auxiliary pixel driving circuit PDCG corresponding to each third display unit column VDUG, the third auxiliary pixel driving circuit PDCG being connected to the same data wire DL and arranged in a straight line with each pixel driving circuit PDC in the corresponding third display unit column VDUG. Further, the display panel PNL is further provided with a sub-pixel PX corresponding to each pixel driving circuit PDC of the auxiliary pixel driving circuit row D-HPDC, the sub-pixel PX and the corresponding pixel driving circuit PDC forming a display unit DU; this makes the auxiliary pixel driving circuit row D-HPDC and each corresponding sub-pixel PX form an auxiliary display unit row HDU, the sub-pixel PX in the auxiliary display unit row HDU can not be used for display, but can improve the uniformity of the sub-pixels PX in adjacent display unit rows HDU.

[0089] For example, the Mth hetero display unit row HDUM is denoted as hetero display unit row HDUM(M), and the jth hetero display unit column VDUM is denoted as hetero display unit column VDUM(j). j is a positive integer and j < Q+N, N is the number of second display unit columns VDUR, and Q is the number of first display unit columns VDUB. The display unit DU located in the hetero display unit row HDUM(M) and in the hetero display unit column VDUM(j) is denoted as display unit DU(M,j), and the display unit DU is a separate display unit DU; the sub-pixel PX of the display unit DU(M,j) is denoted as sub-pixel PX(M,j), and the pixel driving circuit PDC of the display unit DU(M,j) is denoted as pixel driving circuit PDC(M,j). The pixel driving circuit PDC located in the auxiliary pixel driving circuit row D-HPDC and corresponding to the hetero display unit column VDUM(j) is referred to as pixel driving circuit PDC(M+1,j); the sub-pixel PX(M,j) is electrically connected to the pixel driving circuit PDC(M+1,j+1), i.e., the pixel driving circuit PDC(M+1,j+1) drives the sub-pixel PX(M,j).

[0090] In an embodiment of the present disclosure, the sub-pixel PX and the pixel driving circuit PDC of the separate display unit DU are located in two adjacent hetero display unit columns VDUM, respectively. Specifically, the first sub-pixel PXB of the first display unit DUB in at least part of the second display unit column VDUR is electrically connected to the pixel driving circuit PDC in the second display unit DUR adjacent to the first display unit column VDUB; the second sub-pixel (PXR) of the second display unit DUR in at least part of the first display unit column VDUB is electrically connected to the pixel driving circuit PDC in the first display unit DUB adjacent to the second display unit column VDUR. In this way, the wiring difficulty of the display panel PNL can be reduced.

[0091] In an example, the first sub-pixel PXB in the second display unit column VDUR is located in the yth second display unit column VDUR, and the pixel driving circuit PDC electrically connected to the first sub-pixel PXB in the second display unit column VDUR is located in the first display unit column VDUB between the yth second display unit column VDUR and the (y+1)th second display unit column VDUR; the second sub-pixel (PXR) in the first display unit column VDUB is located in the zth first display unit column VDUB, and the pixel driving circuit PDC electrically connected to the second sub-pixel (PXR) in the first display unit column VDUB is located in the second display unit column VDUR between the zth first display unit column VDUB and the (z+1)th first display unit column VDUB; wherein y is a positive integer and y

[0092] In an example, the i-th heterogeneous display unit row HDUM is denoted as HDUM(i), and the j-th heterogeneous display unit column VDUM is denoted as VDUM(j), where i is a positive integer and i < M, j is a positive integer and j < Q+N, N is the number of the second display unit columns VDUR, and Q is the number of the first display unit columns VDUB. The display unit DU(i,j) is a display unit DU located in the heterogeneous display unit row HDUM(i) and in the heterogeneous display unit column VDUM(j), and the display unit DU is a separate display unit DU. The sub-pixel PX of the display unit DU(i,j) is denoted as PX(i,j), and the pixel driving circuit PDC of the display unit DU(i,j) is denoted as PDC(i,j). The sub-pixel PX(i,j) is electrically connected to the pixel driving circuit PDC(i+1,j+1), i.e., the pixel driving circuit PDC(i+1,j+1) drives the sub-pixel PX(i,j). When the heterogeneous display unit column VDUM(j) is the second display unit column VDUR, the heterogeneous display unit column VDUM(j+1) is the first display unit column VDUB, and the heterogeneous display unit column VDUM(j+2) is the second display unit column VDUR. At this time, the display unit DU(i,j) is the first display unit DUB, and the display unit DU(i+1,j+1) is the second display unit DUR. At this time, the sub-pixel PX(i,j) is the first sub-pixel PXB located in the second display unit column VDUR, and the pixel driving circuit PDC(i+1,j+1) is the pixel driving circuit PDC located in the first display unit column VDUB. When the heterogeneous display unit column VDUM(j) is the first display unit column VDUB, the heterogeneous display unit column VDUM(j+1) is the second display unit column VDUR, and the heterogeneous display unit column VDUM(j+2) is the first display unit column VDUB. At this time, the display unit DU(i,j) is the second display unit DUR, and the display unit DU(i+1,j+1) is the first display unit DUB. At this time, the sub-pixel PX(i,j) is the second sub-pixel PXR located in the first display unit column VDUB, and the pixel driving circuit PDC(i+1,j+1) is the pixel driving circuit PDC located in the second display unit column VDUR.

[0093] In an example, referring to FIG. 9, the display panel PNL further comprises an auxiliary pixel driving circuit column D-VPDC and an auxiliary data line DL located on a side of the Qth first display unit column VDUB and the Nth second display unit column VDUR away from the N-1th second display unit column VDUR, the auxiliary pixel driving circuit column D-VPDC comprises pixel driving circuits PDC corresponding to each display unit column VDU, and each pixel driving circuit PDC is electrically connected with the auxiliary data line DL. Therefore, the auxiliary pixel driving circuit column D-VPDC is located on a side of the Q+Nth heterogeneous display unit column VDUM away from the Q+N-1th heterogeneous display unit column VDUM.

[0094] The Nth second display unit column VDUR is located between the Qth first display unit column VDUB and the Hth pixel driving circuit PDC, and the pixel driving circuit PDC electrically connected with the first sub-pixel PXB on the Nth second display unit column VDUR is located on the Hth pixel driving circuit PDC; and / or, the Qth first display unit column VDUB is located between the Nth second display unit column VDUR and the Hth pixel driving circuit PDC, and the pixel driving circuit PDC electrically connected with the second sub-pixel (PXR) on the Qth first display unit column VDUB is located on the Hth pixel driving circuit PDC.

[0095] In other words, after the last heterogeneous display unit column VDUM, an auxiliary pixel driving circuit column D-VPDC is additionally provided, which can provide the pixel driving circuit PDC required for driving the first sub-pixel PXB or the second sub-pixel (PXR) in the last heterogeneous display unit column VDUM. When the last heterogeneous display unit column VDUM is a second display unit column VDUR, the auxiliary pixel driving circuit column D-VPDC can provide the pixel driving circuit PDC required for driving the first sub-pixel PXB in the last heterogeneous display unit column VDUM; when the last heterogeneous display unit column VDUM is a first display unit column VDUB, the auxiliary pixel driving circuit column D-VPDC can provide the pixel driving circuit PDC required for driving the second sub-pixel (PXR) in the last heterogeneous display unit column VDUM.

[0096] In some examples, the auxiliary pixel driving circuit column D-VPDC further comprises pixel driving circuits PDC corresponding to each non-heterogeneous display unit row HDUN, and each pixel driving circuit PDC is arranged in the same row as each pixel driving circuit PDC in the corresponding non-heterogeneous display unit row HDUN, for example, connected to the same scan wire. Further, the display panel PNL is further provided with sub-pixels PX corresponding to each pixel driving circuit PDC of the auxiliary pixel driving circuit column D-VPDC, and each sub-pixel PX forms a display unit DU with the corresponding pixel driving circuit PDC; this makes the V pixel driving circuit PDC form an auxiliary display unit column VDU with each corresponding sub-pixel PX, and the sub-pixels PX in the auxiliary display unit column VDU can not be used for display, but can improve the uniformity of the sub-pixels PX in the adjacent display unit column VDU.

[0097] In an example, when the display panel PNL is provided with an auxiliary pixel driving circuit row D-HPDC, the auxiliary pixel driving circuit column D-VPDC further comprises pixel driving circuits PDC corresponding to the auxiliary pixel driving circuit row D-HPDC, and each pixel driving circuit PDC is connected to the same scan wire as each pixel driving circuit PDC in the auxiliary pixel driving circuit row D-HPDC.

[0098] For example, the i-th heterogeneous display unit row HDUM is denoted as HDUM(i), and the Q+N-th heterogeneous display unit column VDUM, i.e., the last heterogeneous display unit column VDUM, is denoted as VDUM(Q+N). Wherein, i is a positive integer and i≤M, j is a positive integer. The display unit DU located in the heterogeneous display unit row HDUM(i) and in the heterogeneous display unit column VDUM(Q+N) is denoted as DU(i,Q+N), and the display unit DU is a separate display unit DU; the sub-pixel PX of the display unit DU(i,Q+N) is denoted as PX(i,Q+N), and the pixel driving circuit PDC of the display unit DU(i,Q+N) is denoted as PDC(i,Q+N). The display panel PNL is provided with an auxiliary pixel driving circuit column D-VPDC; the pixel driving circuit PDC corresponding to the heterogeneous display unit row HDUM(i) in the auxiliary pixel driving circuit column D-VPDC can be denoted as PDC(i,Q+N+1); the pixel driving circuit PDC corresponding to the auxiliary pixel driving circuit row D-HPDC in the auxiliary pixel driving circuit column D-VPDC can be denoted as PDC(M+1,Q+N+1). The sub-pixel PX(i,Q+N) is electrically connected to the pixel driving circuit PDC(i+1,Q+N+1), i.e., the pixel driving circuit PDC(i+1,Q+N+1) drives the sub-pixel PX(i,Q+N).

[0099] When the heterogeneous display unit column VDUM(Q+N) is the second display unit column VDUR, the heterogeneous display unit column VDUM(Q+N) is the Nth second display unit column VDUR, the heterogeneous display unit column VDUM(Q+N-1) is the Qth first display unit column VDUB, the heterogeneous display unit column VDUM(Q+N-2) is the (N-1)th second display unit column VDUR, and the heterogeneous display unit column VDUM(Q+N-3) is the (Q-1)th first display unit column VDUB. At this time, the auxiliary pixel driving circuit column D-VPDC is located on the side of the heterogeneous display unit column VDUM(Q+N) away from the heterogeneous display unit column VDUM(Q+N-2).

[0100] When the heterogeneous display unit column VDUM(Q+N) is the first display unit column VDUB, the heterogeneous display unit column VDUM(Q+N) is the Qth first display unit column VDUB, the heterogeneous display unit column VDUM(Q+N-1) is the Nth second display unit column VDUR, the heterogeneous display unit column VDUM(Q+N-2) is the (Q-1)th first display unit column VDUB, and the heterogeneous display unit column VDUM(Q+N-3) is the (N-1)th second display unit column VDUR. At this time, the auxiliary pixel driving circuit column D-VPDC is located on the side of the heterogeneous display unit column VDUM(Q+N) away from the heterogeneous display unit column VDUM(Q+N-2).

[0101] In the above examples, the sub-pixel PX of the split-type display unit DU and the pixel driving circuit PDC electrically connected thereto are not located in the same heterogeneous display unit row HDUM. In some other embodiments of the present disclosure, the sub-pixel PX of the split-type display unit DU and the pixel driving circuit PDC electrically connected thereto can also be located in the same heterogeneous display unit row HDUM.

[0102] For example, in one example, the display panel PNL includes an array of display unit groups DUS, each display unit group DUS including a split-type second display unit DUR and a split-type first display unit DUB arranged in the same row, the split-type second display unit DUR and the split-type first display unit DUB being located in two adjacent heterogeneous display unit columns VDUM. In the same display unit group DUS, the second sub-pixel (PXR) of the second display unit DUR is electrically connected to the pixel driving circuit PDC of the first display unit DUB, and the pixel driving circuit PDC of the second display unit DUR is electrically connected to the first sub-pixel PXB of the first display unit DUB.

[0103] Further, the display panel PNL includes a plurality of display unit columns VDUS arranged in sequence along the row direction DH, each display unit column VDUS including one second display unit column VDUR and one first display unit column VDUB; wherein, in the same display unit column VDUS, the second display unit column VDUR and the first display unit column VDUB located in the same heterogeneous display unit row HDUM are located in the same display unit group DUS. Further, each display unit column VDUS further includes two third display unit columns VDUG; wherein one third display unit column VDUG is located between the second display unit column VDUR and the first display unit column VDUB.

[0104] For example, one display unit column VDUS includes the second display unit column VDUR, the third display unit column VDUG, the first display unit column VDUB and the third display unit column VDUG arranged in sequence along the row direction DH, or one display unit column VDUS includes the first display unit column VDUB, the third display unit column VDUG, the second display unit column VDUR and the third display unit column VDUG arranged in sequence along the row direction DH.

[0105] In an embodiment of the present disclosure, the display panel PNL is provided with a transition wire TRL corresponding to each separate display unit DU, which can include a first transition wire TRLB corresponding to each first sub-pixel PXB in the second display unit column VDUR, and a second transition wire TRLR corresponding to each second sub-pixel PXR in the first display unit column VDUB. Wherein, the first sub-pixel PXB in the second display unit column VDUR is electrically connected to the output end of the pixel driving circuit PDC of the second display unit DUR in the first display unit column VDUB through the corresponding first transition wire TRLB; and the second sub-pixel PXR in the first display unit column VDUB is electrically connected to the output end of the pixel driving circuit PDC of the first display unit DUB in the second display unit column VDUR through the corresponding second transition wire TRLR.

[0106] In an example, the transition wire TRL is arranged on the side of the pixel electrode of the sub-pixel PX close to the substrate SBT; and the connection area of the pixel electrode of the sub-pixel PX of the separate display unit DU is electrically connected to the corresponding transition wire TRL through a via. Further, the material of the transition wire TRL is metal. In this way, on the one hand, it can avoid the problem of wiring difficulty and being easily affected by crosstalk caused by arranging the transition wire TRL on the pixel electrode layer; on the other hand, the transition wire TRL adopts a metal material, which can reduce the resistance between the pixel electrode of the separate display unit DU and the electrically connected pixel driving circuit PDC.

[0107] The transfer wire TRL can be disposed in the same layer or can be transferred between multiple metal layers. In one example, the driving layer DRL includes a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer SD3 disposed in sequence on one side of the substrate base plate SBT; the data wire DL and the power voltage wire VDDL are disposed in the second source-drain metal layer SD2 and extend along the column direction DV; the transfer wire TRL (such as the second transfer wire TRLR and the first transfer wire TRLB) can be disposed in the third source-drain metal layer SD3 to avoid the data wire DL and the power voltage wire VDDL. In another example, the driving layer DRL includes a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer SD3 disposed in sequence on one side of the substrate base plate SBT; the data wire DL and the power voltage wire VDDL are disposed in the second source-drain metal layer SD2 and extend along the column direction DV; the transfer wire TRL (such as the second transfer wire TRLR and the first transfer wire TRLB) can have a wire segment in the second source-drain metal layer SD2 and a wire segment in the third source-drain metal layer SD3, and adjacent wire segments of the same transfer wire TRL are electrically connected by a via to cross over or avoid other conductive structures.

[0108] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. This application is intended to cover any variations, uses or adaptations of the disclosure including departures from the present disclosure as ca me within known or customary practice in the art. The specification and examples are to be construed as exemplary only and not as limiting of the true scope and spirit of the disclosure.

Claims

1. A display panel comprising a plurality of display units arranged in an array; the plurality of display units are arranged into a plurality of display unit columns and a plurality of display unit rows; the plurality of display unit columns comprise second display unit columns and first display unit columns arranged alternately along a row direction; the second display unit columns and the first display unit columns each comprise second display units and first display units arranged alternately along a column direction; the second display units of the second display unit columns and the second display units of the first display unit columns are located in different display unit rows; the second display units comprise second sub-pixels and pixel driving circuits, and the first display units comprise second sub-pixels and pixel driving circuits; the display panel further comprises a plurality of data wires corresponding to each display unit column one by one; each pixel driving circuit of the second display unit columns is electrically connected with a corresponding data wire; each pixel driving circuit of the first display unit columns is electrically connected with a corresponding data wire; in the second display units in the second display unit columns, the second sub-pixels are electrically connected with the output ends of the pixel driving circuits; in the first display units in the first display unit columns, the first sub-pixels are electrically connected with the output ends of the pixel driving circuits; at least part of the first sub-pixels in the second display unit columns are electrically connected with the output ends of the pixel driving circuits of the second display units in the first display unit columns; at least part of the second sub-pixels in the first display unit columns are electrically connected with the output ends of the pixel driving circuits of the first display units in the second display unit columns.

2. The display panel of claim 1, wherein, at least part of the first sub-pixels in the second display unit columns and the pixel driving circuits electrically connected therewith are located in different display unit rows; at least part of the second sub-pixels in the first display unit columns and the pixel driving circuits electrically connected therewith are located in different display unit rows.

3. The display panel of claim 2, wherein, the plurality of display unit rows comprise non-heterogeneous display unit rows and heterogeneous display unit rows arranged alternately along the column direction; the second display units in the second display unit columns and the first display units in the first display unit columns are located in the non-heterogeneous display unit rows, and the first display units in the second display unit columns and the second display units in the first display unit columns are located in the heterogeneous display unit rows; at least part of the first sub-pixels in the second display unit columns and the pixel driving circuits electrically connected therewith are located in adjacent two heterogeneous display unit rows, respectively; at least part of the second sub-pixels in the first display unit columns and the pixel driving circuits electrically connected therewith are located in adjacent two heterogeneous display unit rows, respectively.

4. The display panel of claim 3, wherein, the first sub-pixels in the second display unit columns are located in an xth heterogeneous display unit row, and the pixel driving circuits electrically connected with the first sub-pixels in the second display unit columns are located in an x+1th heterogeneous display unit row; the second sub-pixels in the first display unit columns are located in an xth heterogeneous display unit row, and the pixel driving circuits electrically connected with the second sub-pixels in the first display unit columns are located in an x+1th heterogeneous display unit row; Wherein, x is a positive integer and x 5. The display panel of claim 4, wherein, The display panel further comprises an auxiliary pixel driving circuit row, the auxiliary pixel driving circuit row comprises a plurality of second auxiliary pixel driving circuits corresponding to each second display unit column and a plurality of first auxiliary pixel driving circuits corresponding to each first display unit column; The second auxiliary pixel driving circuit and each pixel driving circuit in the corresponding second display unit column are connected to the same data wire; The first auxiliary pixel driving circuit and each pixel driving circuit in the corresponding first display unit column are connected to the same data wire; The second sub-pixel in the Mth heterogeneous display unit row is electrically connected with the second auxiliary pixel driving circuit in the auxiliary pixel driving circuit row, The first sub-pixel in the Mth heterogeneous display unit row is electrically connected with the first auxiliary pixel driving circuit in the auxiliary pixel driving circuit row.

6. The display panel of claim 1, wherein, The first sub-pixel in the second display unit column is located in the yth second display unit column, and the pixel driving circuit electrically connected with the first sub-pixel in the second display unit column is located in the first display unit column between the yth second display unit column and the y+1th second display unit column; The second sub-pixel in the first display unit column is located in the zth first display unit column, and the pixel driving circuit electrically connected with the second sub-pixel in the first display unit column is located in the second display unit column between the zth first display unit column and the z+1th first display unit column; Wherein, y is a positive integer and y 7. The display panel of claim 6, wherein, The display panel further comprises an auxiliary pixel driving circuit row and an auxiliary data wire, the auxiliary pixel driving circuit row and the auxiliary data wire are located on the side of the Qth first display unit column and the Nth second display unit column away from the N-1th second display unit column; the auxiliary pixel driving circuit row comprises pixel driving circuits corresponding to each display unit row, and each pixel driving circuit is electrically connected with the auxiliary data wire; The Nth second display unit column is located between the Qth first display unit column and the auxiliary pixel driving circuit row, and the pixel driving circuit electrically connected with the first sub-pixel on the Nth second display unit column is located in the auxiliary pixel driving circuit row; And / or, the Qth first display unit column is located between the Nth second display unit column and the auxiliary pixel driving circuit row, and the pixel driving circuit electrically connected with the second sub-pixel on the Qth first display unit column is located in the auxiliary pixel driving circuit row.

8. The display panel of claim 1, wherein, The plurality of display unit columns further comprise a plurality of third display unit columns, the third display unit columns are arranged between the second display unit columns and the adjacent first display unit columns; The third display unit column comprises a plurality of third display units arranged in the column direction in sequence, the third display unit comprises a pixel driving circuit and a third sub-pixel electrically connected with the output end of the pixel driving circuit; The display panel further comprises a plurality of data wires corresponding to each of the third display unit columns, and each of the pixel driving circuits of the third display unit columns is electrically connected to the corresponding data wire.

9. The display panel of claim 1, wherein, The display panel is provided with first switching wires corresponding to the first sub-pixels in the second display unit columns, and second switching wires corresponding to the second sub-pixels in the first display unit columns. The first sub-pixels in the second display unit columns are electrically connected to the output ends of the pixel driving circuits through the corresponding first switching wires, and the second sub-pixels in the first display unit columns are electrically connected to the output ends of the pixel driving circuits through the corresponding second switching wires.

10. The display panel of claim 9, wherein, The display panel comprises a substrate, a driving layer and a pixel layer which are sequentially stacked; the pixel driving circuit, the first switching wire and the second switching wire are arranged in the driving layer, and the first sub-pixel and the second sub-pixel are arranged in the pixel layer.

11. The display panel of claim 1, wherein, The display panel comprises a substrate, a driving layer and a pixel layer which are sequentially stacked; the pixel driving circuit is arranged in the driving layer, and the first sub-pixel and the second sub-pixel are arranged in the pixel layer. The pixel electrode of the first sub-pixel has a connection area, and the connection area of the pixel electrode of the first sub-pixel is electrically connected to the pixel driving circuit driving the first sub-pixel through a via hole. The first sub-pixel of the first display unit has a connection area, and the connection area of the pixel electrode of the first sub-pixel is electrically connected to the pixel driving circuit driving the first sub-pixel through a via hole. The second sub-pixel has a connection area, and the connection area of the pixel electrode of the second sub-pixel is electrically connected to the pixel driving circuit driving the second sub-pixel through a via hole. The second sub-pixel of the second display unit has a connection area, and the connection area of the pixel electrode of the second sub-pixel is electrically connected to the pixel driving circuit driving the second sub-pixel through a via hole.

12. A display device comprising the display panel of any one of claims 1-11. ​

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