Memory and control method

Abstract

Provided in the present disclosure are a memory and a control method. The memory at least comprises: a redundant storage array and a conventional storage array, word lines in the redundant storage array being used for repairing word lines in the conventional storage array, and the capacitance of the smallest storage unit in the redundant storage array being greater than the capacitance of the smallest storage unit in the conventional storage array; and a sense amplifier, used for amplifying bit line voltages in the redundant storage array and the conventional storage array.

Description

Memory and control method

[0001] Cross-reference to related applications

[0002] This application claims priority from the Chinese patent application No. 202410792291.6 filed on June 18, 2024, and entitled "Memory and control method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of semiconductor, in particular to a memory and a control method. BACKGROUND

[0004] With the increase of memory input / output rate and memory capacity, the control logic inside the memory becomes more and more complex, and the noise impact on the storage unit becomes more and more great. With the development of technology, people are increasingly concerned about the data security and data stability of the memory. Common row hammer attack may cause the data in the memory to be destroyed. If the impact of row hammer attack and noise on the memory is reduced, it is an important problem in the industry.

[0005] SUMMARY

[0006] Embodiments of the present application provide a memory and a control method, which at least help to reduce the impact of row hammer attack and noise on the memory.

[0007] According to some embodiments of the present application, in one aspect, a memory is provided, which at least includes: a redundant storage array and a conventional storage array, a word line in the redundant storage array is used to repair a word line in the conventional storage array, and the capacitance of the smallest storage unit in the redundant storage array is greater than the capacitance of the smallest storage unit in the conventional storage array; and a sense amplifier, configured to amplify the voltage of a bit line in the redundant storage array and the conventional storage array.

[0008] In some embodiments, the memory further includes: a gate and a row decoder, the gate is configured to receive a conventional row address, a redundant row address, and a first control signal, and the time of receiving the redundant row address is later than the time of receiving the conventional row address; when the first control signal is in a dormant state, the row decoder receives the conventional row address output by the gate; when the first control signal is in an enabled state, the row decoder receives the redundant row address output by the gate; the first control signal is used to represent whether the word line corresponding to the conventional row address is damaged and repaired, and the first control signal is in the dormant state before entering the enabled state.

[0009] In some embodiments, the memory further comprises: a first decoder, an output of the first decoder being connected to a first input of the gate; a comparator, an output of the comparator being connected to an input of a first encoder, an output of the first encoder being connected to a second input of the gate; the first decoder is configured to receive a target row address and decode the target row address based on a preset decoding mode to output the normal row address; the comparator is configured to compare the target row address with at least one repaired row address, if the target row address matches one of the repaired row addresses, the first control signal with an enable state is generated, and flag information of the matched repaired row address is output; the first encoder is configured to receive the flag information and generate the redundant row address based on the flag information.

[0010] In some embodiments, the memory further comprises: an AND circuit, a first input of the AND circuit being connected to an output of the gate, a second input of the AND circuit being configured to receive an enable signal, the enable signal being high before the gate outputs the normal row address; and an output of the AND circuit being connected to an input of the row decoder.

[0011] In some embodiments, a minimum storage unit in the redundant storage array and a minimum storage unit in the normal storage array are both one storage cell, a capacitance of a storage cell in the redundant storage array is greater than a capacitance of a storage cell in the normal storage array; or, a minimum storage unit in the redundant storage array comprises at least two storage cells, and a minimum storage unit in the normal storage array is one storage cell.

[0012] In some embodiments, the at least two storage cells in the minimum storage unit in the redundant storage array have the same row address and are connected to the same bit line.

[0013] In some embodiments, the at least two storage cells are connected to the same word line, or are connected to at least two word lines with the same row address.

[0014] In some embodiments, the memory comprises: an edge storage array and a middle storage array, in a bit line extension direction, a width of the edge storage array is equal to half of a width of the middle storage array, the redundant storage array is located in the edge storage array, and the normal storage array is located in the middle storage array.

[0015] In some embodiments, the memory is further configured to eliminate bias of internal transistors by compensating a bit line or a reference bit line.

[0016] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a control method applied to any of the above-mentioned memories, the control method comprising: comparing whether a target row address matches at least one repaired row address, and performing first decoding on the target row address to generate a normal row address; after the normal row address is generated, performing subsequent decoding on the normal row address to determine a normal to-be-activated word line; controlling a sense amplifier corresponding to the normal to-be-activated word line to perform a bias cancellation operation; if the target row address matches one of the repaired row addresses, generating a redundant row address based on flag information of the matched repaired row address, and controlling the sense amplifier corresponding to the normal to-be-activated word line and not corresponding to the redundant row address to interrupt the bias cancellation operation, or controlling the sense amplifier corresponding to the normal to-be-activated word line to interrupt the bias cancellation operation; after the redundant row address is generated, performing subsequent decoding on the redundant row address to determine a redundant to-be-activated word line; and controlling a sense amplifier corresponding to the redundant to-be-activated word line to perform a bias cancellation operation.

[0017] In some embodiments, the sense amplifier corresponding to the normal to-be-activated word line performs a bias cancellation operation for a first preset time before the bias cancellation operation is interrupted, and the sense amplifier corresponding to the redundant to-be-activated word line performs a bias cancellation operation for a second preset time, the sum of the first preset time and the second preset time is a fixed value, or the second preset time has a minimum value.

[0018] In some embodiments, if the target row address does not match all the repaired row addresses, the sense amplifier corresponding to the normal to-be-activated word line performs a bias cancellation operation for a third preset time, the sum of the first preset time and the second preset time is a fixed value, the third preset time is less than or equal to the fixed value, and the second preset time is less than the third preset time. BRIEF DESCRIPTION OF DRAWINGS

[0019] One or more embodiments are illustrated by way of example in the figures that are part of this document, and which illustrate by way of example the principles of the embodiments. The drawings listed below are each hereby incorporated into this document as if each were individually incorporated by reference. Unless otherwise indicated, the drawings are not necessarily drawn to scale.

[0020] FIG. 1 is a structural schematic diagram of a memory provided by embodiments of the present application;

[0021] FIG. 2 is a circuit schematic diagram of a memory provided by some embodiments of the present application

[0022] FIGS. 3 to 6 are structural schematic diagrams of minimum storage units of a redundant storage array provided by some embodiments of the present application;

[0023] FIG. 7 is a layout schematic diagram of a memory provided by some embodiments of the present application;

[0024] Figure 8 is a circuit diagram of a sensing amplifier provided in some embodiments of this application;

[0025] Figure 9 is a timing diagram of a memory control method provided in some embodiments of this application. Detailed Implementation

[0026] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figure 1 is a schematic diagram of the structure of the memory provided in an embodiment of this application.

[0028] Referring to Figure 1, the memory includes: a redundant memory array 00 and a conventional memory array 01. The word lines in the redundant memory array 00 are used to repair the word lines in the conventional memory array 01. The capacitance of the smallest memory unit 001 in the redundant memory array 00 is greater than the capacitance of the smallest memory unit 011 in the conventional memory array 01. A sensing amplifier (not shown) is used to amplify the voltage of the bit lines in the redundant memory array 00 and the conventional memory array 01.

[0029] By setting a larger capacitance for the smallest storage unit 001 in the redundant storage array 00, the impact of charge leakage caused by row hammer (RHR) on the smallest storage unit 001 in the redundant storage array is reduced, ensuring that the redundant storage array 00 can effectively store data. At the same time, due to the larger capacitance, after the charge sharing phase (CS), the bit line corresponding to the smallest storage unit 001 in the redundant storage array 00 has more charge and a higher potential, or less charge and a lower potential (this is compared with the bit line in the conventional storage array 01 after the charge sharing phase). This helps to reduce the impact of noise on data reading, ensures a reasonable voltage difference between the bit line and the reference bit line, and thus ensures that the data amplified by the sensing amplifier is the data stored in the smallest storage unit 001.

[0030] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0031] The memory can include a plurality of regular storage arrays 01 and one or more redundant storage arrays 00. When the number of redundant storage arrays 00 is equal to the number of regular storage arrays 01, each regular storage array 01 has a corresponding and unique redundant storage array 00, and the regular storage array and the redundant storage array constitute a complete storage array; when the number of redundant storage arrays 00 is less than the number of regular storage arrays 01, usually, a plurality of regular storage arrays 01 share a redundant storage array 00, thereby improving the utilization rate of redundant resources.

[0032] It can be understood that the redundant storage array 00 and the regular storage array 01 are only named based on the difference in function, and there is no limitation in position. In the data writing process, the data is preferentially stored in the smallest storage unit in the regular storage array 01, and the smallest storage unit is connected with the word line and the bit line and is limited by the row address and the bit line. When the word line in the regular storage array 01 is damaged due to various reasons, resulting in that the data writing cannot be performed, the redundant word line is used to replace the regular word line, and the data is written into the smallest storage unit corresponding to the redundant word line, so as to realize the word line repair. The row address of the damaged regular word line is recorded in the storage medium such as the register, the fuse device or the anti-fuse device, and the mapping relationship between the row address and the redundant word line is reserved, so as to ensure the subsequent normal reading and writing.

[0033] In the embodiment of the application, the number of data stored in the smallest storage unit 001 in the redundant storage array 00 is equal to the number of data stored in the smallest storage unit of the regular storage array 01. In some embodiments, the smallest storage unit 011 of the regular storage array 01 only stores one data, for example, 0 or 1. In some embodiments, the smallest storage unit includes an access transistor and a storage capacitor, the gate of the storage transistor is connected with the word line, the source and the drain of the storage transistor are respectively connected with the bit line and the storage capacitor, and when the storage transistor is turned on, the charge sharing is performed between the storage capacitor and the bit line. The capacitance of the smallest storage unit refers to the storage capacitor.

[0034] In some embodiments, referring to FIG. 2, the memory further includes a gate 10 and a row decoder 11, the gate 10 is used to receive the regular row address, the redundant row address and the first control signal CT1, and the time of receiving the redundant row address is later than the time of receiving the regular row address, when the first control signal CT1 is in the dormant state, the row decoder 11 receives the regular row address output by the gate 10, when the first control signal CT1 is in the enabled state, the row decoder 11 receives the redundant row address output by the gate 10, and the first control signal T1 is used to represent whether the word line corresponding to the regular row address is damaged and repaired, and the first control signal CT1 is in the dormant state before entering the enabled state.

[0035] It can be understood that in this embodiment, when the first control signal CT1 is in the enable state, the word line corresponding to the regular row address is damaged, and the word line corresponding to the regular row address is in the regular storage array 01. Since the word line corresponding to the regular row address is damaged and is repaired through the word line in the redundant storage array 00, when the first control signal CT1 is in the enable state, the gatet 10 needs to output a redundant row address, and the word line corresponding to the redundant row address is in the redundant storage array 00, which is used to repair the damaged word line in the regular storage array 01 mentioned above. The word line in the regular storage array 01 can be referred to as a regular word line, and the word line in the redundant storage array 00 can be referred to as a redundant word line. If the word line corresponding to the regular row address is not damaged, the gatet 10 will not receive the redundant row address. When the gatet 10 receives the redundant row address, the first control signal CT1 must be in the enable state.

[0036] In this embodiment, the gatet 10 also receives the first control signal CT1 in the sleep state before receiving the first control signal CT1 in the enable state. The gatet 10 can output the regular row address to the row decoder 11 based on the first control signal CT1 in the sleep state. Compared with the first control signal CT1 having only one of the enable state or the sleep state, the gatet 10 waits for the redundant row address after receiving the regular row address, and finally outputs the row address only once. This embodiment is beneficial to optimize the timing and avoid the influence of the small probability event of the damage of the regular word line on the overall timing. In addition, even if the regular row address is decoded by the row decoder 11 in advance and the subsequent operation in advance occupies part of the operation time, since the capacitance of the smallest storage unit 001 in the redundant storage array 00 is large, the voltage difference required for the sense amplifier to amplify can still be provided in the case that the operation time of the subsequent operation is shortened. Therefore, the gatet 10 outputs the regular row address in advance, and still can ensure that the data corresponding to the redundant row address can be correctly read out.

[0037] In some embodiments, continuing to refer to FIG. 2, the memory further comprises: a first decoder 12, an output of the first decoder 12 being connected with a first input end of the gatet 10; a comparator 13, an output end of the comparator 13 being connected with an input end of a first encoder 14; and the first encoder 14, an output end of the first encoder 14 being connected with a second input end of the gatet 10; the first decoder 12 is used to receive a target row address and decode the target row address based on a preset decoding manner to output a regular row address; the comparator 13 is used to compare the target row address with at least one repaired row address, and if the target row address matches one of the repaired row addresses, generate a first control signal CT1 having an enable state, and output flag information of the matched repaired row address; and the first encoder 14 is used to receive the flag information and generate a redundant row address based on the flag information.

[0038] In this embodiment, the comparator 13 and the first decoder 12 both receive a target row address, which is the row address of the word line to be activated. The first decoder 12 decodes the target row address for the first time, and the row decoder 11 decodes the regular row address for the second time. It can be understood that the first decoding is partial decoding, and the result of the second decoding can be either partial decoding or complete decoding. In some embodiments, the second decoding is partial decoding, and the final complete decoding is performed by a sub-word line driver (SWD). The target row address and the regular row address only differ in the degree of decoding, and both point to the same word line. Whether it is decoding or encoding, the same word line is pointed to before and after decoding, and the same word line is also pointed to before and after encoding, unless information changes or other address mapping occurs in the middle. Since the time spent on the comparison action is usually longer, the time when the first decoder 12 outputs the regular row address is generally earlier than the time when the first encoder 14 outputs the redundant row address 14, or earlier than the time when the comparator 13 outputs the flag information.

[0039] In some embodiments, the comparator 13 stores the repaired row address or receives the repaired row address sent by other devices. Different repaired row addresses correspond to different flag information, and each flag information corresponds to a redundant row address. For example, when the first regular word line is damaged, the first redundant row address is used for replacement repair. At this time, the comparator 13 not only stores or receives the repaired row address (i.e., the first regular word line), but also stores or receives the flag information of the first redundant row address and forms a mapping relationship with the repaired row address. The repaired row address is the same as the row address of the damaged regular word line. When the target row address matches one of the repaired row addresses, the comparator 13 sends the flag information corresponding to the matched repaired row address to the first encoder 14, and the first encoder 14 generates a redundant row address based on the flag information.

[0040] For the sake of simplicity of expression, the following is described by taking the way of receiving the repaired row address by the comparator 13. It can be understood that the comparator 13 can only receive one repaired row address, or does not receive any repaired address (i.e., no regular word line is damaged). When no repaired address is received, the comparator 13 does not output the flag information, and the first encoder 14 does not output the redundant row address.

[0041] In different embodiments of the present application, the presentation of the flag information varies in at least two structural features: 1) the correspondence between the regular storage arrays and the redundant storage arrays; 2) the order of use of the redundant word lines or the redundant row addresses. Regarding the first structural feature, there are the following possibilities: (1.1) the number of redundant storage arrays is equal to the number of regular storage arrays, each regular storage array has a corresponding redundant storage array, and the corresponding redundant storage arrays of different regular storage arrays are different; or (1.2) the number of redundant storage arrays is less than the number of regular storage arrays, the memory contains multiple redundant storage arrays, and the regular storage arrays are divided into multiple groups, each group shares one of the redundant storage arrays; or (1.3) all regular storage arrays correspond to the same redundant storage array. Regarding the second structural feature, there are the following possibilities: (2.1) the order of use of the redundant row addresses is according to the positional relationship, for example, the first redundant word line used for replacement repair is arranged in the first position, the second redundant word line used for replacement repair is arranged in the second position, and the redundant row addresses corresponding to the redundant word lines are sequentially arranged according to the positional relationship; (2.2) the order of use of the redundant word lines is according to other rules other than the positional relationship; (2.3) the order of use of the redundant row addresses has no rules.

[0042] For (1.1) and (1.2) mentioned above, the comparator 13 needs to determine which redundant storage array the target row address corresponds to based on the address information of the target row address before comparison, and then compare it with the repaired row address corresponding to the redundant storage array to determine whether it matches. If it matches, the comparator 13 outputs the first flag information of the redundant storage array and the second flag information of the matched repaired row address in the one or more repaired addresses corresponding to the redundant storage array, for example, there are 5 redundant storage arrays in total, each redundant storage array uses 5 redundant word lines for replacement repair, then the target row address can correspond to the 3rd redundant storage array, and match the 4th repaired row address of the 3rd redundant storage array, at this time, the first flag information represents the 3rd redundant storage array, the second flag information represents the 4th repaired row address, and the first flag information and the second flag information constitute the flag information mentioned above, and the first encoder 14 generates the corresponding redundant row address based on the first flag information and the second flag information. For (1.3) mentioned above, the flag information only contains the second flag information, and the first encoder 14 generates the corresponding redundant row address based on the second flag information.

[0043] For the above-mentioned (2.1), since there is a mapping relationship between the position information and the redundant row address, for example, the first word line corresponds to the redundant row address numbered 1, the second word line corresponds to the redundant row address numbered 2, and so on, after determining the redundant storage array (not needed when there is only one redundant storage array), the first encoder 14 can generate the redundant row address of the redundant word line according to the position information and the redundant storage array information, and if there is only one redundant storage array, the redundant row address is generated only according to the position information; for the above-mentioned (2.2), since there is a certain rule between the position information and the redundant row address, the first encoder 14 can generate the redundant row address of the redundant word line based on the rule and the position relationship, or generate the redundant row address of the redundant word line based on the rule, the position relationship and the redundant storage array information; for the above-mentioned (2.3), the flag information of the repaired address is the address information of the redundant row address in the redundant storage array, and the first encoder 14 outputs the redundant row address based on the address information or based on the address information and the redundant storage array information.

[0044] In some embodiments, for the combination of the above-mentioned structural feature (1.3) and structural feature (2.3), the first encoder 14 can not be set, and the comparator 13 directly outputs the flag information corresponding to the matched repaired row address, and the flag information can be the redundant row address with the same decoding degree as the conventional row address.

[0045] It can be understood that the above-mentioned (1.1) to (1.3) can be combined with the above-mentioned (2.1) to (2.3) in any combination, and any combination is within the protection scope of the present application, and the essence is whether the part of the address bits of the target row address needs to be decoded to identify which redundant storage array is applied and how to map the relationship between the repaired row address and the redundant row address. These all belong to the range of expression ways of decoding and marking information, and those skilled in the art can know how to realize the corresponding technical solutions, and the present application will not be repeated here.

[0046] In some embodiments, the multiplexer 10 receives the first control signal CT1 from the comparator 13 through a first connection line, the first control signal CT1 is in a sleep state by default and becomes an enable state when the comparator 13 matches successfully, that is, the first connection line transmits the first control signal CT1 in the sleep state first and then transmits the first control signal CT1 in the enable state. In yet some embodiments, the first decoder is connected to the first control terminal of the multiplexer through a second connection line, used to transmit the first control signal in the sleep state when the target row address is received or in the decoding process, so that the multiplexer outputs the decoded normal row address; the comparator is connected to the second control terminal of the multiplexer through a third connection line, used to transmit the first control signal in the enable state when the matching is successful, so that the multiplexer outputs the encoded redundant row address, at this time, the second connection line and the third connection line only transmit one of the sleep state or the enable state.

[0047] In some embodiments, the memory further comprises a latch 16, the output terminal of the latch 16 is connected to the input terminal of the first decoder 12 and the input terminal of the comparator 13, used to latch the input target row address, so that the first decoder 12 and the comparator 13 can effectively receive the target row address.

[0048] In some embodiments, the memory further comprises a with circuit 15, the output terminal of the with circuit 15 is connected to the output terminal of the multiplexer 10, the second input terminal of the with circuit 15 is used to receive an enable signal En, and the output terminal of the with circuit 15 is connected to the input terminal of the row decoder 11, the enable signal En jumps to high level before the multiplexer 10 outputs the normal row address. In this embodiment, by controlling the setting of the enable signal En and controlling the enable signal En to jump to high level before the multiplexer 10 outputs the normal row address, it can not only ensure that the row decoder 11 can timely receive the normal row address or the redundant row address output by the multiplexer 10, but also control the enable signal En to be disabled in the idle stage to interrupt the subsequent operation, avoid the error decoding of the row decoder 11 and reduce the power consumption of the memory.

[0049] In some embodiments, the minimum storage unit in the redundant storage array 00 and the minimum storage unit in the normal storage array are both a storage cell, the storage capacitance of the storage cell in the redundant storage array is greater than the storage capacitance of the storage cell in the normal storage array; or, the minimum storage unit in the redundant storage array contains at least two storage cells, the minimum storage unit in the normal storage array is a storage cell, and the storage capacitance of the storage cell in the redundant storage array is less than or equal to the storage capacitance of the storage cell in the normal storage array. The storage cell includes an access transistor and a storage capacitor, the gate of the storage transistor is connected to a word line, the source and the drain of the storage transistor are connected to a bit line and the storage capacitor respectively, and the storage capacitor and the bit line share charges when the storage transistor is turned on. The capacitance of the storage cell refers to the storage capacitance.

[0050] In some embodiments, the minimum storage unit in the redundant storage array 00 contains at least two storage cells having the same row address and connected to the same bit line. It should be noted that the connection to the same bit line here means that the minimum storage unit is finally connected to the sense amplifier through the same wire, so that after charge sharing, the bit line can have more or less charge (here, the comparison is made in the case where the minimum storage unit contains only one storage cell), thereby forming a larger voltage difference between the bit line and the reference bit line, ensuring that the sense amplifier can correctly amplify the bit line data. At the same time, since two storage cells simultaneously provide charge for the bit line, it is beneficial to still form a voltage difference that meets the amplification requirement in the case where the charge sharing time is insufficient or the offset cancellation time is insufficient, thereby correctly reading out the data.

[0051] Referring to FIG. 3, the bit line BL can contain a first part BL1 and a second part BL2 arranged side by side, and the first part BL1 and the second part BL2 are both connected to the sense amplifier SA through BL3, and the sense amplifier SA is used to amplify the voltage difference between the bit line BL and the reference bit line BLB.

[0052] In some embodiments, after the sense amplifier exits the idle stage, it enters the offset cancellation (OC), charge sharing (CS), develop or amplifier, and precharge four stages in turn, and then reenters the idle stage, and performs corresponding operations in different stages. The offset cancellation stage is used to eliminate the parameter mismatch of the internal transistor, and the result is to make a certain potential difference exist between the bit line and the reference bit line before charge sharing, thereby making up for the defect formed by the first threshold voltage being greater than or less than the second threshold voltage, the first threshold voltage being the threshold voltage of the transistor whose gate is connected to the bit line, and the second threshold voltage being the threshold voltage of the transistor whose gate is connected to the reference bit line, thus playing a charge compensation role, so the offset cancellation stage is also sometimes referred to as a mismatch compensation stage. In the charge sharing stage, the word line is opened, and the storage capacitor starts to share charge with the bit line. If the storage cell stores data 1, the bit line charge increases, and the potential increases. If the storage cell stores data 0, the bit line charge decreases, and the potential decreases. If the offset cancellation time is shorter than the preset cancellation time or the charge sharing time is shorter than the preset sharing time, then when storing data 1, the bit line charge is lower than the expected charge, and the bit line potential is lower. When storing data 0, the bit line charge is higher than the expected charge, and the bit line potential is higher.

[0053] It should be noted that in different embodiments of the present application, the different stages of the sense amplifier are not strictly continuous, and there can be a certain interval in between to achieve a relaxed timing.

[0054] In some embodiments, the minimum storage unit in the redundant storage array comprises at least two storage cells connected to the same word line. Referring to FIG. 4, the bit line BL is bent and intersects the same word line WL at different positions, the storage cell Cl is located at the intersection of the word line WL and the bit line BL, and two storage cells Cl arranged along the extension direction of the word line WL constitute the minimum storage unit 001 of the redundant storage array 00; or, referring to FIG. 5, the word line WL is bent and intersects the same bit line BL at different positions, and two storage cells Cl arranged along the extension direction of the bit line BL constitute the minimum storage unit 001 of the redundant storage array 00.

[0055] In yet some embodiments, the minimum storage unit in the redundant storage array comprises at least two storage cells connected to at least two word lines having the same row address. Referring to FIG. 6, the first word line WL1 and the second word line WL2 have the same row address, the first word line WL1 and the second word line WL2 are connected to the same bit line respectively, and form two storage cells Cl, at this time, two storage cells Cl arranged along the extension direction of the bit line BL constitute the minimum storage unit 001 of the redundant storage array 00.

[0056] It should be noted that in any of the above embodiments, the word line bending and the bit line bending can be performed simultaneously, so that the minimum storage unit in the redundant storage array comprises more than two storage cells.

[0057] In yet some embodiments, the memory comprises an edge storage array and a middle storage array, the width of the edge storage array is equal to half of the width of the middle storage array in the extension direction of the bit line, the edge storage array serves as the redundant storage array, and the middle storage array serves as the regular storage array. Referring to FIG. 7, the memory comprises a row decoder 11 and a half bank located on the opposite sides of the row decoder 11, each half bank is provided with a plurality of storage sections in the direction of the bit line, a sense amplifier array 23 is arranged between adjacent storage sections, and the sense amplifier array 23 comprises a plurality of sense amplifiers 231.

[0058] In this embodiment, the two storage units on opposite sides are defined as edge storage units 21, and the storage arrays in the edge storage units 21 are defined as edge storage arrays 211. The edge storage units 21 generally include a plurality of edge storage arrays 211 arranged along the word line WL direction. Correspondingly, the non-edge storage units are defined as intermediate storage units 22, and each half of the storage bank generally includes a plurality of intermediate storage units 22, and each intermediate storage unit 22 is generally composed of a plurality of intermediate storage arrays 221 extending in the word line WL direction. In the bit line BL extension direction, the width L1 of the edge storage array 211 is half of the width L2 of the intermediate storage array 221, the redundant storage array is located in the edge storage array 211, and the conventional storage array is located in at least the intermediate storage array 221.

[0059] In some embodiments, the edge storage array 211 is a redundant storage array, and the intermediate storage array 221 is a conventional storage array; in other embodiments, the edge storage array 211 includes both a redundant storage array and a conventional storage array, and the intermediate storage array is a conventional storage array; in yet other embodiments, both the edge storage array and the intermediate storage array include a redundant storage array and a conventional storage array.

[0060] It can be understood that the above-mentioned half is only an approximate value and does not need to be strictly limited, and a certain deviation range in size is allowed due to process reasons, layout arrangement, power supply settings, and the like.

[0061] In some embodiments, continuing to refer to FIG. 7, the memory adopts an open-BL mode, which refers to two adjacent bit lines (for example, the first bit line BL11 and the second bit line BL12) connected to the same word line extending upward and downward, respectively, amplified by a sensing amplifier 231 in a different sensing amplifier array 23, and the bit line and the reference bit line connected to the sensing amplifier are respectively derived from two storage arrays (including the edge storage array 211 and the intermediate storage array 221) on the upper and lower sides of the sensing amplifier array 23. However, since the storage array cannot be infinitely expanded in the bit line direction, if the outermost side is a sensing amplifier array, it will cause part of the bit lines to have no reference bit line available, and if the outermost side is a storage array and the size of the edge storage array is the same as that of the intermediate storage array, it will cause half of the bit lines to be unable to be amplified by the sensing amplifier. Therefore, the size of the edge storage array is set to be half of the size of the intermediate storage array, and the bit line is bent, so that the length of the bit line in the edge storage array is similar to the length of the bit line in the intermediate storage array, which is beneficial to making the parasitic capacitances of any bit line and reference bit line similar, facilitating amplification by the sensing amplifier.

[0062] In some embodiments, while the bit line BL of the edge storage array 211 is stored at the bending edge, the bit line BL is connected with two storage units C1, thus, it is beneficial to enhance the accuracy of data reading in the edge storage array 211, reduce the influence of noise or row hammer effect on data reading. However, since the two storage units C1 in the edge storage array 211 together constitute a minimum storage unit in the redundant storage array, the data stored by the two storage units C1 need to be the same, and one storage unit C1 in the middle storage array 221 constitutes a minimum storage unit. Therefore, when the redundant storage array is located in the edge storage array 211, and the conventional storage array is located in the middle storage array 221, the sum of the number of minimum storage units on the two redundant word lines is equal to the number of minimum storage units on a conventional word line; similarly, when the conventional storage array is not only located in the edge storage array 211, but also located in the middle storage array 221, the number of minimum storage units on the conventional word line in the part of the conventional storage array (defined as the first conventional storage array) located in the edge storage array 211 is equal to the number of minimum storage units on the redundant word line, and the number of minimum storage units on the conventional word line in the other part of the conventional storage array (defined as the second conventional storage array) located in the middle storage array 221 is equal to the sum of the number of minimum storage units on the two redundant word lines.

[0063] According to the above description, when the redundant word line in the edge storage array is used to replace and repair the conventional word line in the middle storage array, the one-for-one mode cannot be used, but the two-for-one mode should be used; when the redundant word line in the edge storage array is used to replace and repair the conventional word line in the edge storage array, the two-for-two mode should be used. The reason why it is two-for-two instead of one-for-one is that the two conventional word lines in the edge storage array have the same row address, work at the same time when data reading and writing is performed, and are generally damaged at the same time.

[0064] In some embodiments, the memory includes a first edge storage section at the upper left corner, which contains the first edge storage array 212, a second edge storage section at the upper right corner, which contains the second edge storage array 213, a third edge storage section at the lower left corner, which contains the third edge storage array 214, and a fourth edge storage section at the lower right corner, which contains the fourth edge storage array 215. In the two-for-one mode, either two redundant word lines in the same edge storage array can be used to replace a damaged regular word line, or two redundant word lines in different edge storage arrays can be used to replace a damaged regular word line. The different edge storage arrays can be located at the same side of the row decoder 11, such as the first edge storage array 212 and the third edge storage array 214, or at different sides of the row decoder 11, such as the first edge storage array 212 and the second edge storage array 213, or the first edge storage array 212 and the fourth edge storage array 215. The two redundant word lines used for replacement have the same row address, but if the two redundant word lines are in the same edge storage array, the timing of the two word lines needs to be staggered to amplify and read and write the corresponding memory cells, respectively, i.e., the above four stages of bias cancellation, charge sharing, amplification, and pre-charge are performed twice in succession.

[0065] It can be understood that in other embodiments, in the two-for-two mode, the two regular word lines to be replaced are usually in the same edge storage array as the two redundant word lines used for replacement. For example, assuming that the two regular word lines include a first regular word line and a second regular word line, and the two redundant word lines include a first redundant word line and a second redundant word line, if the first regular word line and the second regular word line are in the first edge storage array, then the first redundant word line and the second redundant word line are in the first edge storage array; if the first regular word line is in the first edge storage array and the second regular word line is in the second edge storage array, then the first redundant word line is in the first edge storage array and the second redundant word line is in the second edge storage array. In yet other embodiments, the two regular word lines to be replaced can usually be in different edge storage arrays as the two redundant word lines used for replacement, as long as the two regular word lines to be replaced have the same row address and the two redundant word lines used for replacement have the same row address.

[0066] In some embodiments, the memory further comprises a sense amplifier for amplifying the voltage of the bit line in the redundant memory array and the regular memory array, and eliminating the bias of the internal transistor through the compensation of the bit line or the reference bit line. Referring to FIG. 8, the sense amplifier can comprise a first P-type amplifier M1, a second P-type amplifier M2, a first N-type amplifier M7, a second N-type amplifier M8, a first isolation tube M3, a second isolation tube M4, a first bias cancellation tube M5, a second bias cancellation tube M6, a pre-charge tube M9, a first end of the first P-type amplifier M1 and a first end of the second P-type amplifier M2 are connected to a first voltage node PCS, a second end of the first P-type amplifier M1 and a first end of the first N-type amplifier M7 are connected, a second end of the second P-type amplifier M2 and a first end of the second N-type amplifier M8 are connected, a second end of the first N-type amplifier M7 and a second end of the second N-type amplifier M8 are connected to a second voltage node NCS, the second end of the first P-type amplifier M1 serves as a second node S2, the second end of the second P-type amplifier M2 serves as a first node S1, the first node S1 is connected to a first end of the first isolation tube M3, a second end of the first isolation tube M3, a second end of the first bias cancellation tube M5 and a gate of the first N-type amplifier M7 are connected to the bit line BL, a first end of the first bias cancellation tube M5 is connected to the second node S2, the second node S2 is connected to a first end of the second isolation tube M4, a second end of the second isolation tube M4, a second end of the second bias cancellation tube M6 and a gate of the second N-type amplifier M8 are connected to the reference bit line BLB, a first end of the second bias cancellation tube M6 and a first end of the pre-charge tube M9 are connected to the first node S1, the first isolation tube M3 and the second isolation tube M4 are turned on based on an isolation signal ISO, the first bias cancellation tube M5 and the second bias cancellation tube M6 are turned on based on a bias cancellation signal OC, the pre-charge tube M9 is turned on based on a pre-charge signal PreEq and transmits a pre-charge potential to the first node S1, so that the first node S1 and the second node S2 are at the pre-charge potential, and the pre-charge signal PreEq enables the sense amplifier to be in the pre-charge phase.

[0067] The structure of the sense amplifier shown in FIG. 8 and its common operation method are known technologies, and will not be described here. It is emphasized here that in the structure shown in FIG. 8, the first bias cancellation tube M5 and the second bias cancellation tube M6 play a bias cancellation role, mainly used to eliminate the performance deviation of the first N-type amplifier M7 and the second N-type amplifier M8, and other sense amplifier circuits with bias cancellation function are also within the protection scope of the present application. In the bias cancellation phase, the first bias cancellation tube M5 and the second bias cancellation tube M6 are turned on, and the first isolation tube M3 and the second isolation tube M4 are turned off.

[0068] The embodiment of the present application further provides a control method applied to any of the above memory embodiments. The control method provided by the embodiment of the present application only requires minimum hardware support, does not limit other functions and implementation manners of the hardware, and does not require hardware with other functions. The person skilled in the art can involve the corresponding structure according to the need, and only needs to meet the corresponding part function. The control method comprises the following steps:

[0069] Step 1: comparing whether the target row address matches at least one repaired address, and performing first decoding on the target row address to generate a normal row address;

[0070] Step 2: after the normal row address is generated, performing subsequent decoding on the normal row address to determine a normal to-be-activated word line;

[0071] Step 3: controlling a sense amplifier corresponding to the normal to-be-activated word line to perform a bias cancellation operation;

[0072] Step 4: if the target row address matches one of the repaired row addresses, generating a redundant row address based on the flag information of the matched repaired address, and controlling the sense amplifier corresponding to the normal to-be-activated word line and not corresponding to the redundant row address to interrupt the bias cancellation operation, or controlling the sense amplifier corresponding to the normal to-be-activated word line to interrupt the bias cancellation operation;

[0073] Step 5: after the redundant row address is generated, performing subsequent decoding on the redundant row address to determine a redundant to-be-activated word line;

[0074] Step 6: controlling a sense amplifier corresponding to the redundant to-be-activated word line to perform a bias cancellation operation.

[0075] The control method will be specifically described below by taking the memory embodiment comprising a strobe, a row decoder, a first decoder, a comparator, an AND circuit and a first encoder as an example. Meanwhile, reference is made to FIG. 2 and FIG. 9, and the filled area in FIG. 9 represents a state temporarily not entering the subsequent unfilled area description:

[0076] In step 1, the first decoder 12 and the comparator 13 simultaneously receive the target row address, the comparator 13 compares whether the target row address matches at least one repaired address, and the first decoder 12 performs first decoding, and the comparison action and the first decoding are performed simultaneously. The first decoder 12 outputs the normal row address after receiving the target row address for a period of time, and if the target row address matches (i.e., is the same as) one of the at least one repaired address, the first encoder 14 generates the redundant row address based on the flag information output by the comparator 13. Since the time of the comparison operation is usually longer than the time of the first decoding, if the matching is successful, the time when the first encoder 14 outputs the redundant row address will be later than the time when the first decoder 12 outputs the normal row address.

[0077] In step 2, the first decoder 12 is the first decoding, and the subsequent row decoder 11 and other devices also need to be further decoded. In the control method, the decoding after the first decoding is collectively referred to as subsequent decoding. In addition, in step 2, only the regular to-be-activated word line is determined, and the regular to-be-activated word line is not directly activated. The activation of the word line represents the charge sharing operation, and the bias cancellation operation is before the charge sharing operation. Therefore, the purpose of determining the regular to-be-activated word line is to find the subsequent sensing amplifier for amplification, and then control the sensing amplifier to perform the bias cancellation operation.

[0078] In step 3, since the storage array has not received the column selection signal, it is necessary to control all the sensing amplifiers corresponding to the regular to-be-activated word line to perform the bias cancellation operation. It should be noted that if the intermediate storage part where the regular to-be-activated word line is located is adjacent to at least one edge storage part where the redundant to-be-activated word line / redundant row address is located, then part of the sensing amplifiers corresponding to the regular to-be-activated word line are the same as part of the sensing amplifiers corresponding to the redundant to-be-activated word line. Further, if the two redundant word lines used to replace the regular word line are in the same edge storage part and the regular to-be-activated word line is in the intermediate storage part, then the sensing amplifiers corresponding to the regular to-be-activated word line completely contain the sensing amplifiers corresponding to the redundant to-be-activated word line. If the two redundant word lines used to replace the regular word line are in different edge storage parts and the regular to-be-activated word line is in the intermediate storage part, then the sensing amplifiers corresponding to the redundant to-be-activated word line are partially the same as the sensing amplifiers corresponding to the regular to-be-activated word line. If the two regular word lines to be replaced are in the same edge storage part as the two redundant word lines used for replacement, then the sensing amplifiers corresponding to the regular to-be-activated word line are completely the same as the sensing amplifiers corresponding to the redundant to-be-activated word line.

[0079] In step 4, if the target row address matches one of the repaired row addresses, it means that the two redundant word lines are used to replace and repair the damaged regular word line. At this time, it is no longer necessary to attempt to amplify the data in the storage cells corresponding to the regular word line, and therefore the bias cancellation operation of the sensing amplifiers corresponding to the regular to-be-activated word line can be interrupted.

[0080] In some embodiments, if the intermediate storage part where the regular to-be-activated word line is located is adjacent to at least one edge storage part where the redundant row address is located, then due to the overlap of at least part of the sensing amplifiers, the bias cancellation operation of only the non-overlapping part of the sensing amplifiers can be interrupted, and the bias cancellation operation of the overlapping part of the sensing amplifiers is not interrupted. If the edge storage part where the regular to-be-activated word line is located is the same as the edge storage part where the redundant row address is located, then the sensing amplifiers corresponding to the regular to-be-activated word line completely overlap the sensing amplifiers corresponding to the redundant row address, and therefore any sensing amplifier that is performing the bias cancellation operation can not be interrupted.

[0081] The first control signal and the redundant row address can be received by setting a separate control unit, and the regular to-be-activated word line or the regular row address is received to determine the sense amplifiers that need to be interrupted from the bias cancellation operation and the sense amplifiers that do not need to be interrupted from the bias cancellation operation. It should be noted that, since the sense amplifiers corresponding to the word lines in the same storage unit are the same, as long as the part of the redundant row address that has been decoded can represent the storage unit in which the redundant row address is located, it can be determined whether the sense amplifiers corresponding to the redundant row address and the regular to-be-activated word line overlap. In some embodiments, a decoding module can also be arranged in the control unit, and when the decoding degree of the redundant row address and the regular row address is insufficient, further decoding is performed to know the storage unit in which the redundant row address and the regular row address are located.

[0082] In other embodiments, even if the sense amplifiers corresponding to the redundant row address and the sense amplifiers corresponding to the regular to-be-activated word line at least partially overlap, all the sense amplifiers corresponding to the regular to-be-activated word line are interrupted, thereby simplifying the control logic.

[0083] For steps 5 and 6, in some embodiments, after determining the redundant to-be-activated word line, the corresponding sense amplifiers are controlled to perform the bias cancellation operation, and since part or even all of the sense amplifiers can have been in the bias cancellation stage (corresponding to the regular to-be-activated word line, but not interrupted because they also correspond to the redundant row address), only the remaining sense amplifiers need to be controlled to perform the bias cancellation operation; in other embodiments, since the bias cancellation operation of all the sense amplifiers corresponding to the regular to-be-activated word line is interrupted, the sense amplifiers corresponding to the redundant to-be-activated word line need to be controlled to re-perform the bias cancellation operation.

[0084] Referring to FIG. 9, in the third row timing, if the matching is successful, the first encoder outputs the redundant row address corresponding to the target row address, and if the matching is not successful, no row address is output or the default state is in; in the fourth row timing and the fifth row timing, the enable signal is enabled before the regular row address is received at the strobe input end, so that the strobe can timely output the regular row address; for the sixth row and the seventh row, before the matching result is determined, the sense amplifiers corresponding to the regular to-be-activated word line enter the bias cancellation stage OC from the idle stage IDLE, after the matching is successful, the bias cancellation stage is interrupted and the idle stage IDLE is re-entered, at this time, the sense amplifiers corresponding to the redundant to-be-activated word line enter the bias cancellation stage OC from the idle stage IDLE and perform subsequent operations; the ninth row represents that when the matching fails, the sense amplifiers corresponding to the regular to-be-activated word line continue to be in the bias cancellation stage OC and perform subsequent operations, and when the matching is successful, the partially overlapping sense amplifiers do not need to be interrupted and can continue to be in the bias cancellation stage OC and perform subsequent operations.

[0085] It should be noted that if the bias cancellation operation of the sensing amplifier corresponding to all redundant row addresses is controlled before the matching result is given, and the bias cancellation operation of the sensing amplifier corresponding to the normal row address corresponding to the target row address is controlled, and the bias cancellation operation of part of the sensing amplifier is interrupted until the matching result is given, and the bias cancellation operation of the required sensing amplifier is retained, the power consumption of the bias cancellation operation will be very large. It is equivalent to starting a large number of useless bias cancellation operations in each activation operation in order to match a small probability, which will greatly increase the power consumption, and the power supply reliability requirement and noise will also increase.

[0086] In the timing diagram shown in FIG. 9, the start time of the bias sensing stage OC of the sensing amplifier corresponding to the redundant to-be-activated word line is the same as the end time of the bias sensing stage OC of the sensing amplifier corresponding to the normal to-be-activated word line, but in other embodiments, the former can be later than the latter.

[0087] In some embodiments, further referring to FIG. 9, the bias cancellation operation of the sensing amplifier corresponding to the normal to-be-activated word line is performed for a first preset time T1 before the bias cancellation operation is interrupted, and the bias cancellation operation of the sensing amplifier corresponding to the redundant to-be-activated word line is performed for a second preset time T2. The sum of the first preset time T1 and the second preset time T2 can be a fixed value, thereby ensuring the stability of the bias cancellation operation timing, or the second preset time T2 has a minimum value for ensuring that the sensing amplifier can perform the minimum bias cancellation.

[0088] In some embodiments, further referring to FIG. 9, if the target row address does not match all the repaired addresses, the bias cancellation of the sensing amplifier corresponding to the normal to-be-activated word line is performed for a third preset time T3, the first preset time T1 and the second preset time T2 are fixed values, the third preset time T3 is less than or equal to the fixed value, and the second preset time T2 is less than the third preset time. In this way, it is beneficial to ensure that the sensing amplifier corresponding to the redundant to-be-activated word line can perform the minimum bias cancellation operation in the case of successful matching.

[0089] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A memory, comprising: a redundant memory array and a regular memory array, word lines in the redundant memory array are used to repair word lines in the regular memory array, a minimum storage unit in the redundant memory array has a larger capacitance than a minimum storage unit in the regular memory array; a sense amplifier, configured to amplify bit line voltages in the redundant memory array and the regular memory array.

2. The memory of claim 1, further comprising: a gate and a row decoder, the gate is configured to receive a regular row address, a redundant row address, and a first control signal, the gate receives the redundant row address later than the regular row address, when the first control signal is in a sleep state, the row decoder receives the regular row address output by the gate, when the first control signal is in an enable state, the row decoder receives the redundant row address output by the gate, the first control signal is used to indicate whether a word line corresponding to the regular row address is damaged and repaired, and the first control signal is in the sleep state before entering the enable state.

3. The memory of claim 2, further comprising: a first decoder, a comparator, and a first encoder, an output terminal of the first decoder is connected with a first input terminal of the gate, an output terminal of the comparator is connected with an input terminal of the first encoder, and an output terminal of the first encoder is connected with a second input terminal of the gate; the first decoder is configured to receive a target row address and decode the target row address based on a preset decoding manner to output the regular row address; the comparator is configured to compare the target row address with at least one repaired row address, if the target row address matches one of the repaired row addresses, the first control signal in the enable state is generated, and flag information of the matched repaired row address is output; the first encoder is configured to receive the flag information and generate the redundant row address based on the flag information.

4. The memory of claim 2, further comprising: an AND circuit, a first input terminal of the AND circuit is connected with an output terminal of the gate, a second input terminal of the AND circuit is configured to receive an enable signal, the enable signal jumps to a high level before the gate outputs the regular row address, and an output terminal of the AND circuit is connected with an input terminal of the row decoder.

5. The memory of claim 1, wherein, the minimum storage unit in the redundant memory array and the minimum storage unit in the regular memory array are both one storage unit, and a capacitance of the storage unit in the redundant memory array is larger than a capacitance of the storage unit in the regular memory array; alternatively, the minimum storage unit in the redundant memory array includes at least two storage units, and the minimum storage unit in the regular memory array is one storage unit.

6. The memory of claim 5, wherein, the at least two storage units included in the minimum storage unit in the redundant memory array have the same row address and are connected with the same bit line.

7. The memory of claim 6, wherein, the at least two storage units are connected with the same word line, or are connected with at least two word lines having the same row address.

8. The memory of claim 1, comprising: The edge memory array and the middle memory array have the same width in the bit line extension direction, the width of the edge memory array is half of the width of the middle memory array, the redundant memory array is located in the edge memory array, and the normal memory array is located in the middle memory array.

9. The memory of claim 1, wherein, The memory is also used for bias cancellation of internal transistors by compensating bit lines or reference bit lines.

10. A control method applied to the memory of any one of claims 1-9, comprising: comparing whether the target row address matches at least one repaired row address, and first decoding the target row address to generate a normal row address; after the normal row address is generated, subsequently decoding the normal row address to determine a normal to-be-activated word line; controlling the sensing amplifier corresponding to the normal to-be-activated word line to perform bias cancellation operation; if the target row address matches one of the repaired row addresses, generating a redundant row address based on the flag information of the matched repaired row address, and controlling the sensing amplifier corresponding to the normal to-be-activated word line and not corresponding to the redundant row address to interrupt the bias cancellation operation, or controlling the sensing amplifier corresponding to the normal to-be-activated word line to interrupt the bias cancellation operation; after the redundant row address is generated, subsequently decoding the redundant row address to determine a redundant to-be-activated word line; controlling the sensing amplifier corresponding to the redundant to-be-activated word line to perform bias cancellation operation.

11. The control method according to claim 10, wherein The sensing amplifier corresponding to the normal to-be-activated word line performs bias cancellation operation for a first preset time before the bias cancellation operation is interrupted, and the sensing amplifier corresponding to the redundant to-be-activated word line performs bias cancellation operation for a second preset time, the sum of the first preset time and the second preset time is a fixed value, or the second preset time has a minimum value.

12. The control method according to claim 11, wherein If the target row address does not match all the repaired row addresses, the sensing amplifier corresponding to the normal to-be-activated word line performs bias cancellation operation for a third preset time, the sum of the first preset time and the second preset time is a fixed value, the third preset time is less than or equal to the fixed value, and the second preset time is less than the third preset time.

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