Solar cell and preparation method therefor

Abstract

The present application relates to the technical field of solar cell manufacturing. Disclosed are a solar cell and a preparation method therefor. The solar cell comprises: a silicon substrate; an emitter and a first passivation and anti-reflection structure that are arranged from inside to outside on one side of the silicon substrate in the direction of thickness, wherein the first passivation and anti-reflection structure comprises a first passivation and anti-reflection layer and a second passivation and anti-reflection layer; and a tunneling oxide layer, a doped polysilicon layer and a second passivation and anti-reflection structure that are arranged from inside to outside on the other side of the silicon substrate in the direction of thickness, wherein the second passivation and anti-reflection structure comprises a third passivation and anti-reflection layer and a fourth passivation and anti-reflection layer, and the second passivation and anti-reflection layer and the fourth passivation and anti-reflection layer are arranged in an edge region of the silicon substrate. The embodiment effectively increases the thickness of the passivation and anti-reflection layers at the edge of the silicon substrate, thereby improving the passivation performance and photoelectric conversion efficiency at the edge of the solar cell.

Description

A solar cell and its preparation method

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410806816.7, filed on June 20, 2024, entitled “A Solar Cell and a Method for Preparing the Same”, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the field of solar cell manufacturing technology, and in particular to a method for preparing a solar cell and a back-contact solar cell. Background Technology

[0004] Existing tunneling oxide passivated contact solar cells effectively suppress minority carrier recombination on the silicon surface and improve the cell's turn-on voltage by fabricating an ultrathin silicon oxide layer (i.e., a tunneling oxide layer) and a highly doped polycrystalline silicon layer on the silicon surface. This is achieved by utilizing the selective permeability of the ultrathin silicon oxide layer to charge carriers and the excellent field passivation effect between the highly doped polycrystalline silicon layer and the substrate. However, with the continuous increase in solar cell area, uneven heating occurs during the mass production of solar cells due to edge airflow, resulting in a thinner silicon oxide layer at the edges. This affects the passivation uniformity of the entire cell and thus impacts the cell's conversion efficiency.

[0005] Summary of the Invention

[0006] In view of this, the present disclosure provides a solar cell and a method for preparing the same.

[0007] To solve the above-mentioned technical problems, this disclosure provides the following technical solutions:

[0008] In a first aspect, this disclosure provides a solar cell, comprising: a silicon substrate; an emitter and a first passivation anti-reflection structure disposed from the inside to the outside on one side of the silicon substrate in the thickness direction, wherein the first passivation anti-reflection structure includes a first passivation anti-reflection layer and a second passivation anti-reflection layer, the second passivation anti-reflection layer being disposed on an edge region of the silicon substrate; and a tunneling oxide layer, a doped polycrystalline silicon layer, and a second passivation anti-reflection structure disposed from the inside to the outside on the other side of the silicon substrate, wherein the second passivation anti-reflection structure includes a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, the fourth passivation anti-reflection layer being disposed on an edge region of the silicon substrate.

[0009] According to one or more embodiments of this disclosure, the first passivation antireflection layer is formed simultaneously with the fourth passivation antireflection layer, and the second passivation antireflection layer is formed simultaneously with the third passivation antireflection layer.

[0010] According to one or more embodiments of this disclosure, the fourth passivation antireflection layer is formed by controlling the bonding distance between the silicon substrate and the carrier during the preparation of the first passivation antireflection layer by wire bonding; the second passivation antireflection layer is formed by controlling the bonding distance between the silicon substrate and the carrier during the preparation of the third passivation antireflection layer by wire bonding.

[0011] According to one or more embodiments of this disclosure, the second passivation antireflection layer is disposed outside the first passivation antireflection layer; the fourth passivation antireflection layer is disposed between the doped polysilicon layer and the third passivation antireflection layer.

[0012] According to one or more embodiments of this disclosure, the second passivation antireflection layer is disposed between the first passivation antireflection layer and the emitter; the fourth passivation antireflection layer is disposed outside the third passivation antireflection layer.

[0013] According to one or more embodiments of this disclosure, the width of the second passivation antireflection layer is 0.5 mm to 10 mm; and / or, the width of the fourth passivation antireflection layer is 0.5 mm to 10 mm.

[0014] According to one or more embodiments of this disclosure, the first passivation antireflection layer and / or the fourth passivation antireflection layer comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride; and / or, the second passivation antireflection layer and / or the third passivation antireflection layer comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

[0015] According to one or more embodiments of this disclosure, the thickness of the first passivation antireflection layer and / or the fourth passivation antireflection layer is 20 nm to 180 nm; and / or, the thickness of the second passivation antireflection layer and / or the third passivation antireflection layer is 25 nm to 200 nm.

[0016] According to one or more embodiments of this disclosure, the thickness of the tunneling oxide layer is 0.5 nm to 5 nm; and / or, the thickness of the doped polycrystalline silicon layer is 30 nm to 200 nm.

[0017] Secondly, this disclosure provides a method for preparing the above-mentioned solar cell, comprising:

[0018] Step 1: Fabricate an emitter on one side of the silicon substrate in the thickness direction;

[0019] Step 2: On the other side of the silicon substrate in the thickness direction, a tunneling oxide layer and a doped polycrystalline silicon layer are sequentially prepared from the inside to the outside.

[0020] Step 3: Prepare a first passivation anti-reflection structure and a second passivation anti-reflection structure on the outer side of the emitter and on the outer side of the doped polysilicon layer, respectively; wherein, the first passivation anti-reflection structure includes a first passivation anti-reflection layer and a second passivation anti-reflection layer, the second passivation anti-reflection layer being disposed in the edge region of the silicon substrate; the second passivation anti-reflection structure includes a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, the fourth passivation anti-reflection layer being disposed in the edge region of the silicon substrate. Attached Figure Description

[0021] The accompanying drawings are provided to better understand this disclosure and do not constitute an undue limitation thereof. Wherein:

[0022] Figure 1 is a schematic diagram of the overall structure of a graphite boat carrier according to an embodiment of the present disclosure;

[0023] Figure 2 is a front view of a graphite boat carrier with a silicon substrate inserted according to an embodiment of the present disclosure;

[0024] Figure 3 is a cross-sectional structural schematic diagram of a solar cell structure according to an embodiment of the present disclosure;

[0025] Figure 4 is a cross-sectional structural schematic diagram of another solar cell structure provided according to an embodiment of the present disclosure;

[0026] Figure 5 is a schematic flowchart of a method for preparing a solar cell according to an embodiment of the present disclosure;

[0027] Figure 6 is a schematic cross-sectional structure of the silicon substrate prepared by step S501 according to an embodiment of the present disclosure.

[0028] Figure 7 is a schematic cross-sectional structure of the silicon substrate prepared by step S502 according to an embodiment of the present disclosure.

[0029] Figure 8 is a schematic diagram of a specific process for preparing a first passivation antireflection structure and a second passivation antireflection structure according to an embodiment of the present disclosure;

[0030] Figure 9 is a schematic cross-sectional structure of the silicon substrate prepared by step S801 according to an embodiment of the present disclosure.

[0031] Figure 10 is a schematic cross-sectional structure of the silicon substrate prepared by step S802 according to an embodiment of the present disclosure.

[0032] Figure 11 is a schematic diagram of another specific process for preparing the first passivation antireflection structure and the second passivation antireflection structure according to an embodiment of the present disclosure;

[0033] Figure 12 is a schematic cross-sectional structure of the silicon substrate prepared by step S1101 according to an embodiment of the present disclosure.

[0034] Figure 13 is a schematic cross-sectional structure of the silicon substrate prepared by step S1102 according to an embodiment of the present disclosure.

[0035] Figure 14 shows the PL results of the solar cell obtained according to Embodiment 1 provided in this disclosure;

[0036] Figure 15 shows the PL results of the solar cell obtained according to Comparative Example 1 provided in the embodiments of this disclosure.

[0037] The attached figures are labeled as follows:

[0038] 1-Silicon substrate; 2-Emitter; 3-First passivation anti-reflection structure; 31-First passivation anti-reflection layer; 32-Second passivation anti-reflection layer; 4-First metal electrode; 5-Tunneling oxide layer; 6-Doped polycrystalline silicon layer; 7-Second passivation anti-reflection structure; 71-Third passivation anti-reflection layer; 72-Fourth passivation anti-reflection layer; 8-Second metal electrode. Detailed Implementation

[0039] A solar cell is a thin-film photovoltaic semiconductor that directly generates electricity using sunlight. Also known as a "solar chip" or "photovoltaic cell," it can instantly output voltage and generate current when a circuit is established, provided it receives sufficient illumination. In physics, this is called photovoltaic (PV). To facilitate and clearly describe the fabrication method and the solar cell of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings. These embodiments include various details to aid understanding and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0040] In recent years, with the development of monocrystalline solar cells, especially the successful industrialization of passivated emitter and back field (PERC) technology, the efficiency improvement of mass-produced cells on P-type silicon wafers has approached its limit. More attention has been turned to N-type cells, which offer higher minority carrier lifetime and lower degradation. Three cell structures—N-type PERT, heterojunction (HJT), and tunnel oxide passivated contact (TOPCon)—have gradually gained industry attention. Among them, TOPCon cells, or passivated contact cells, are constructed by preparing an ultrathin silicon oxide layer and a highly doped polycrystalline silicon layer on the silicon surface. The selective permeability of the ultrathin silicon oxide to charge carriers and the excellent field passivation effect between the highly doped polycrystalline silicon and the substrate effectively suppress minority carrier recombination on the silicon surface, thereby improving the cell's turn-on voltage.

[0041] However, existing passivated contact solar cells typically employ a continuous deposition method, sequentially depositing an oxide layer and a doped polycrystalline silicon layer. During the mass production of solar cells, uneven heating occurs due to edge airflow, resulting in thinner oxide and doped polycrystalline silicon layers at the edges. This affects the passivation uniformity of the entire cell, thereby impacting its conversion efficiency. Current solutions aim to achieve a more uniform film by improving the structure of production equipment or adjusting the deposition process parameters. However, these methods are costly, complex, and yield poor results. Therefore, this disclosure addresses this issue by improving the structure of the solar cell.

[0042] In one embodiment of this disclosure, a solar cell is provided, comprising: a silicon substrate 1; an emitter 2 and a first passivation antireflection structure 3 disposed from the inside to the outside on one side of the silicon substrate 1 in the thickness direction, wherein the first passivation antireflection structure 3 includes a first passivation antireflection layer 31 and a second passivation antireflection layer 32, the second passivation antireflection layer 32 being disposed in the edge region of the silicon substrate 1; and a tunneling oxide layer 5, a doped polycrystalline silicon layer 6, and a second passivation antireflection structure 7 disposed from the inside to the outside on the other side of the silicon substrate 1, wherein the second passivation antireflection structure 7 includes a third passivation antireflection layer 71 and a fourth passivation antireflection layer 72, the fourth passivation antireflection layer 72 being disposed in the edge region of the silicon substrate 1.

[0043] The solar cell and its fabrication method provided in this disclosure, by setting a first passivation and antireflection structure 3 including a first passivation and antireflection layer 31 and a second passivation and antireflection layer 32, and a second passivation and antireflection structure 7 including a third passivation and antireflection layer 71 and a fourth passivation and antireflection layer 72, can effectively increase the thickness of the passivation and antireflection layer at the edge of the silicon substrate 1, improve the passivation performance at the edge of the solar cell, and thereby increase the overall photoelectric conversion efficiency of the solar cell.

[0044] The first passivation antireflection layer 31 and the third passivation antireflection layer 71 can be understood as the front passivation antireflection layer and the back passivation antireflection layer of the conventional structure in the prior art. They are deposited on the outer side of the emitter 2 on the front side of the silicon substrate 1 and the outer side of the doped polysilicon layer 6 on the back side, respectively, covering the outer side of the emitter 2 and the outer side of the doped polysilicon layer 6. The second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 are only disposed on the edge region of the silicon substrate 1. It can be understood that if the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 are also disposed on the entire layer, although the thickness of the edge region of the silicon substrate 1 can be increased, it will also affect the light absorption of the middle part of the silicon substrate 1. Therefore, in order to solve the problem of uneven edge oxide layer thickness in the embodiments of this disclosure, the passivation antireflection layer is additionally disposed on the edge region to increase the thickness of the passivation antireflection layer in the edge region. In one optional embodiment, the first passivation antireflection layer 31 and the fourth passivation antireflection layer 72 are formed simultaneously, and the second passivation antireflection layer 32 and the third passivation antireflection layer 71 are formed simultaneously. It should be noted that this embodiment does not add any additional fabrication process. Instead, based on the existing fabrication of the first and third passivation antireflection layers 31, the second and fourth passivation antireflection layers 32 are formed simultaneously without requiring additional processes. This adds additional technical effects while maintaining the existing process.

[0045] Specifically, in this embodiment, the simultaneous fabrication of the passivation and antireflection layers on different sides is achieved by controlling the contact distance between the silicon substrate 1 and the carrier. The carrier can be understood as a support or container for loading the silicon substrate 1 and depositing the passivation and antireflection layers, typically a graphite boat carrier. In an optional embodiment, the fourth passivation and antireflection layer 72 is formed by controlling the contact distance between the silicon substrate 1 and the carrier during the fabrication of the first passivation and antireflection layer 31; the second passivation and antireflection layer 32 is formed by controlling the contact distance between the silicon substrate 1 and the carrier during the fabrication of the third passivation and antireflection layer 71. It is understood that since the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 are formed by wrap-around plating, they can be formed by wrap-around plating in multiple edge areas around the silicon substrate 1. That is, taking the silicon substrate 1 as a rectangular silicon wafer as an example, it can be formed by wrap-around plating on the four sides of the rectangle respectively. Alternatively, it can be formed by wrap-around plating only on the two sides parallel to the metal electrode or the two sides perpendicular to the metal electrode, depending on actual needs. This disclosure does not make specific limitations in this regard and can be set according to actual conditions.

[0046] For example, Figures 1 and 2 illustrate the positional relationship between the silicon substrate 1 and the graphite boat carrier. Figure 1 is a schematic diagram of the overall structure of the graphite boat carrier, and Figure 2 is a front view of the graphite boat carrier with the silicon substrate 1 inserted. As shown in Figure 1, the graphite boat carrier 100 includes multiple partitions, and a longitudinal loading space for accommodating the silicon substrate 1 is formed between every two partitions (as indicated by the arrows in Figure 1). That is, during the fabrication process, the silicon substrate 1 is longitudinally inserted into the graphite boat carrier 100 for deposition. As shown in Figures 1 and 2, multiple graphite boat locking points a are provided on the graphite boat carrier 100, which are fulcrums used to engage the silicon substrate 1. By controlling the left-right and up-down positions of multiple graphite boat clamping points, the silicon substrate 1 can be firmly clamped inside the graphite boat carrier 100, preventing displacement. Furthermore, the specific placement of the silicon substrate 1 within the graphite boat carrier 100 and its contact distance with the carrier can be controlled. The contact distance between the silicon substrate 1 and the graphite boat carrier 100 determines whether wrap-around plating occurs during the passivation anti-reflection layer deposition process. It is understandable that, within a certain range, the greater the contact distance between the silicon substrate 1 and the graphite boat carrier 100 (i.e., the larger the gap), the wider the wrap-around passivation anti-reflection layer; conversely, the smaller the contact distance (i.e., the smaller the gap), the narrower the wrap-around passivation anti-reflection layer. However, the width of the wrap-around plating is limited, and it is impossible for the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 formed by wrap-around plating to cover the outside of the first passivation antireflection layer 31 and the third passivation antireflection layer on the entire surface. Therefore, by controlling the bonding distance between the silicon substrate 1 and the graphite boat carrier 100, the width of the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 formed by wrap-around plating can be effectively controlled, thereby controlling the quality of the final solar cell.

[0047] In an optional embodiment, the widths of the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 should not be too large or too small. Specifically, the width of the second passivation antireflection layer 32 is 0.5mm to 10mm, such as 0.5mm, 1mm, 2.5mm, 3.5mm, 5mm, 6.5mm, 8mm, 9mm, 10mm, etc.; without changing the positional relationship between the silicon substrate 1 and the graphite boat carrier 100, the width of the fourth passivation antireflection layer 72 can also be set to 0.5mm to 10mm, such as 0.5mm, 1mm, 2.5mm, 3.5mm, 5mm, 6.5mm, 8mm, 9mm, 10mm, etc. It is understandable that if the widths of the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 are set too large, the light absorption in the middle part of the silicon substrate 1 will be lost, affecting the light conversion efficiency of the solar cell. On the other hand, if the widths of the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 are set too small, the problem of thin oxide layer thickness cannot be effectively improved. Therefore, in this embodiment, the widths of the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 are set to 0.5 mm to 10 mm, which can achieve the technical effect to be achieved by this disclosure without affecting the performance of the solar cell.

[0048] In the embodiments of this disclosure, different solar cell structures are formed when the passivation antireflection layer is prepared using different preparation sequences. Therefore, this disclosure describes the solar cell structures obtained by prioritizing the preparation of the front passivation antireflection layer and prioritizing the preparation of the back passivation antireflection layer, as shown in Figures 3 and 4. Figure 3 shows the solar cell structure obtained by prioritizing the preparation of the front passivation antireflection layer, and Figure 4 shows the solar cell structure obtained by prioritizing the preparation of the back passivation antireflection layer.

[0049] As shown in Figure 3, the second passivation antireflection layer 32 is disposed outside the first passivation antireflection layer 31, and the fourth passivation antireflection layer 72 is disposed between the doped polycrystalline silicon layer 6 and the third passivation antireflection layer 71. It can be understood that since the first passivation antireflection layer 31 and the fourth passivation antireflection layer 72 are formed simultaneously, when the first passivation antireflection layer 31 is preferentially prepared on the front side of the silicon substrate 1, the fourth passivation antireflection layer 72 will be simultaneously formed at both ends of the edge on the back side of the silicon substrate 1. Thus, when the third passivation antireflection layer 71 is prepared outside the fourth passivation antireflection layer on the back side of the silicon substrate 1, the simultaneously formed second passivation antireflection layer 32 will be outside the first passivation antireflection layer 31.

[0050] As shown in Figure 4, the second passivation antireflection layer 32 is disposed between the first passivation antireflection layer 31 and the emitter 2, and the fourth passivation antireflection layer 72 is disposed outside the third passivation antireflection layer 71. Similar to the above process, when the passivation antireflection layer on the back side of the silicon substrate 1 is preferentially prepared, the third passivation antireflection layer 71 will be located between the fourth passivation antireflection layer 72 and the doped polysilicon layer 6. When the fourth passivation antireflection layer 72 is preferentially prepared, the second passivation antireflection layer 32 will be formed on the front side first, and then the first passivation antireflection layer 31 will be formed outside the second passivation antireflection layer 32.

[0051] As can be seen from Figures 3 and 4 above, the embodiments of this disclosure can obtain solar cells with different structures by using two different preparation sequences. Both can achieve the purpose of increasing the thickness of the passivation and antireflection layer at the edge of the silicon substrate, thereby improving the passivation performance of the solar cell edge and increasing the overall photoelectric conversion efficiency of the solar cell.

[0052] Regarding the material of the passivation antireflection layers, since the first passivation antireflection layer 31 and the fourth passivation antireflection layer 72 are formed simultaneously, and the second passivation antireflection layer 32 and the third passivation antireflection layer 71 are formed simultaneously, the first passivation antireflection layer 31 and the fourth passivation antireflection layer 72 are made of the same material, and the second passivation antireflection layer 32 and the third passivation antireflection layer 71 are made of the same material. In an optional embodiment, the first passivation antireflection layer 31 and the fourth passivation antireflection layer 72 include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride; the second passivation antireflection layer 32 and the third passivation antireflection layer 71 include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride. It should be noted that the passivation antireflection layer actually includes a passivation layer and an antireflection layer, and is usually a multi-layer structure stacked together. Therefore, in the embodiments of this disclosure, the first passivation antireflection layer 31 and the fourth passivation antireflection layer 72 are actually formed by at least two combinations of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

[0053] It is understood that when the first passivation antireflection layer 31, the second passivation antireflection layer 32, the third passivation antireflection layer 71, and the fourth passivation antireflection layer 72 are all made of the same material, the structures of Figures 3 and 4 provided in this embodiment are substantially the same. However, when the first passivation antireflection layer 31 and the second passivation antireflection layer 32 are made of different materials, the structures of Figures 3 and 4 provided in this embodiment are different.

[0054] Regarding the deposition thickness, typically, the first passivation antireflection layer 31 and the fourth passivation antireflection layer 72 deposited simultaneously have the same thickness, as do the second passivation antireflection layer 32 and the third passivation antireflection layer 71 deposited simultaneously. In an optional embodiment, the thickness of the first passivation antireflection layer 31 and / or the fourth passivation antireflection layer 72 is 20nm to 180nm, for example, 20nm, 30nm, 50nm, 80nm, 100nm, 120nm, 150nm, 160nm, 180nm, etc. Meanwhile, the thickness of the second passivation antireflection layer 32 and / or the third passivation antireflection layer 71 is 25nm to 200nm, for example, 25nm, 40nm, 60nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, etc.

[0055] For the thickness of the tunneling oxide layer 5, in one optional embodiment, it can be 0.5 nm to 5 nm, such as 0.5 nm, 0.8 nm, 1.2 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc. For the thickness of the doped polycrystalline silicon layer 6, in one optional embodiment, it can be 30 nm to 200 nm, such as 30 nm, 80 nm, 150 nm, 200 nm, etc. To ensure the photoelectric conversion performance of the solar cell, the concentration of dopant elements in the doped polycrystalline silicon layer 6 needs to be maintained at 1E20 to 1E21 atom / cm³. 3 In this context, E can be understood as the value 10, and 1E20 = 1 * 10 20 At the same time, it is also necessary to ensure that the concentration of doped elements in emitter 2 is 1E18~1E19 atom / cm³. 3 .

[0056] In another optional embodiment, a first metal electrode 4 is provided on one side of the silicon substrate 1 in the thickness direction, and a second metal electrode 8 is provided on the other side of the silicon substrate 1 in the thickness direction. The first metal electrode 4 penetrates the first passivation antireflection layer 31 and is electrically connected to the emitter 2, and the second metal electrode 8 penetrates the third passivation antireflection layer 71 and is electrically connected to the doped polycrystalline silicon layer 6.

[0057] In summary, the solar cell provided in this disclosure, by setting a first passivation and antireflection structure including a first passivation and antireflection layer and a second passivation and antireflection layer, and a second passivation and antireflection structure including a third passivation and antireflection layer and a fourth passivation and antireflection layer, can effectively increase the thickness of the passivation and antireflection layer at the edge of the silicon substrate, improve the passivation performance at the edge of the solar cell, and thereby increase the overall photoelectric conversion efficiency of the solar cell.

[0058] Figure 5 shows a schematic flowchart of a method for preparing a solar cell according to an embodiment of this disclosure. As shown in Figure 5, the method for preparing a solar cell according to this disclosure includes:

[0059] Step S501: An emitter 2 is fabricated on one side of the silicon substrate 1 in the thickness direction;

[0060] Step S502: On the other side of the silicon substrate 1 in the thickness direction, a tunneling oxide layer 5 and a doped polycrystalline silicon layer 6 are sequentially prepared from the inside to the outside.

[0061] In step S503, a first passivation antireflection structure 3 and a second passivation antireflection structure 7 are prepared on the outer side of the emitter 2 and the outer side of the doped polycrystalline silicon layer 6, respectively. The first passivation antireflection structure 3 includes a first passivation antireflection layer 31 and a second passivation antireflection layer 32, with the second passivation antireflection layer 32 disposed in the edge region of the silicon substrate 1. The second passivation antireflection structure 7 includes a third passivation antireflection layer 71 and a fourth passivation antireflection layer 72, with the fourth passivation antireflection layer 72 disposed in the edge region of the silicon substrate 1.

[0062] The silicon substrate structure prepared in step S501 is shown in Figure 6, and the silicon substrate structure prepared in step S502 is shown in Figure 7. As can be seen from Figures 6 and 7, after steps S501 and S502, P+ emitters and passivation contact structures (tunneling oxide layer and doped polysilicon layer) have been formed on both sides of the silicon substrate 1 in the thickness direction. Whether the passivation antireflection layer on the front side or the back side is prepared first, steps S501 and S502 are the same before the passivation antireflection layer is prepared.

[0063] In an optional embodiment, when the passivation antireflection layer on the front side of the silicon substrate 1 is preferentially prepared, step S503 may include, as shown in FIG8:

[0064] In step S801, while the first passivation antireflection layer 31 is prepared on the outside of the emitter 2, the fourth passivation antireflection layer 72 is formed on the outside of the doped polysilicon layer 6.

[0065] In step S802, while preparing the third passivation antireflection layer 71 on the outside of the fourth passivation antireflection layer 72 and the outside of the doped polysilicon layer 6, a second passivation antireflection layer 32 is formed on the outside of the first passivation antireflection layer 31.

[0066] The process shown in Figure 8 will be explained in detail below with reference to Figures 9 and 10. Figure 9 is a schematic cross-sectional view of the silicon substrate formed after step S801; Figure 10 is a schematic cross-sectional view of the silicon substrate formed after step S802. As can be seen from Figures 9 and 10, after step S801, a full-length first passivation antireflection layer 31 is deposited on the front side of the silicon substrate 1. At the same time, a fourth passivation antireflection layer 72 is formed around the back side of the silicon substrate 1, located at both ends in the width direction of the silicon substrate 1. Then, after step S802, based on the formation of the fourth passivation antireflection layer 72, a third passivation antireflection layer 71 is prepared on the back side of the silicon substrate 1, and a second passivation antireflection layer 32 is formed by being deposited around the outside of the first passivation antireflection layer 31. Here, W1 represents the width of the second passivation antireflection layer 32, and W2 represents the width of the fourth passivation antireflection layer 72.

[0067] In another optional embodiment, when the passivation antireflection layer on the back side of the silicon substrate 1 is preferentially prepared, step S503 may include, as shown in FIG11, the following:

[0068] In step S1101, while preparing the third passivation antireflection layer 71 on the outside of the doped polycrystalline silicon layer 6, a second passivation antireflection layer 32 is formed on the outside of the emitter 2.

[0069] In step S1102, while preparing the first passivation antireflection layer 31 on the outside of the second passivation antireflection layer 32 and the outside of the emitter 2, a fourth passivation antireflection layer 72 is formed on the outside of the third passivation antireflection layer 71.

[0070] The process shown in Figure 11 will be explained in detail below with reference to Figures 12 and 13. Figure 12 is a schematic cross-sectional view of the silicon substrate formed after step S1101; Figure 13 is a schematic cross-sectional view of the silicon substrate formed after step S1102. As can be seen from Figures 12 and 13, after step S1101, a full-layer third passivation antireflection layer 71 is deposited on the back side of the silicon substrate 1. At the same time, a second passivation antireflection layer 32 is formed around the front side of the silicon substrate 1, located at both ends in the width direction of the silicon substrate 1. Then, after step S1102, based on the formation of the second passivation antireflection layer 32, a first passivation antireflection layer 31 is prepared on the front side of the silicon substrate 1, and a fourth passivation antireflection layer 72 is formed by being deposited around the outside of the third passivation antireflection layer 71. Here, W1 represents the width of the second passivation antireflection layer 32, and W2 represents the width of the fourth passivation antireflection layer 72.

[0071] In an optional embodiment, in order to precisely control the width of the second passivation antireflection layer 32 and the fourth passivation antireflection layer 72 formed by the wrap-around plating, the bonding distance between the silicon substrate 1 and the carrier is set at 80μm-400μm to prepare the first passivation antireflection structure 3 and the second passivation antireflection structure 7, such as 80μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, etc., so that the width of the second passivation antireflection layer 32 and / or the fourth passivation antireflection layer 72 is between 0.5mm and 10mm.

[0072] In an optional embodiment, after step S503, the method further includes: fabricating a first metal electrode 4 and a second metal electrode 8 on both sides of the silicon substrate 1 in the thickness direction. The silicon substrate structure obtained after fabricating the metal electrodes is the solar cell structure shown in Figures 3 and 4.

[0073] In summary, the method for fabricating solar cells provided in this disclosure can effectively increase the thickness of the passivation and antireflection layer at the edge of the silicon substrate by fabricating a first passivation and antireflection structure including a first passivation and antireflection layer and a second passivation and antireflection layer on one side of the silicon substrate thickness direction, and fabricating a second passivation and antireflection structure including a third passivation and antireflection layer and a fourth passivation and antireflection layer on the other side of the silicon substrate thickness direction, thereby improving the passivation performance at the edge of the solar cell and increasing the overall photoelectric conversion efficiency of the solar cell.

[0074] Example 1

[0075] S1. The n-type silicon substrate is texturized with an alkaline solution (the alkaline solution is a 1% sodium hydroxide solution by volume, the texturization temperature is 80℃, and the immersion time is 400s) to form a textured surface structure on both sides of the silicon substrate in the thickness direction.

[0076] S2. The n-type silicon wafer with the textured surface is placed in a high-temperature diffusion furnace (the reactants, such as boron trichloride and boron tribromide, are mixed with oxygen and reacted at a temperature of 1000℃ for 3 hours) to carry out the diffusion / oxidation process of boron doping elements, so as to form a p+ emitter on the positive surface of the n-type silicon substrate; wherein, the boron doping concentration in the p+ emitter is 5E18 atoms / cm3.

[0077] S3. Use a 30% hydrofluoric acid solution to remove the silicon glass layer formed by wrapping around the back and sides of the n-type silicon substrate;

[0078] S4. Perform alkaline polishing on the front surface of the n-type silicon substrate (the alkaline solution is a 2% sodium hydroxide solution by volume, the reaction temperature is 60℃, and the immersion time is 200s);

[0079] S5. A tunneling oxide layer and an n+ doped polycrystalline silicon layer are sequentially prepared on the back surface of an n-type silicon substrate; wherein, the tunneling oxide layer is a silicon oxide layer obtained by LPCVD deposition at a reaction temperature of 600℃, a deposition time of 15min, and a thickness of 2nm; the doping concentration of the n+ doped polycrystalline silicon layer is 4.5E20 atoms / cm3.

[0080] S6. Use hydrofluoric acid with a volume concentration of 10% to remove the boron + phosphosilicate glass layer coated on the front side of the n-type silicon substrate, the uncoated area on the front side, and the phosphosilicate glass layer coated on the side.

[0081] S7. Clean the n-type silicon substrate (using RCA cleaning technology);

[0082] S8. A first passivation and antireflection layer is deposited on the front side of a silicon substrate using ALD (atomic layer deposition) at 320℃ and PECVD at 550℃, 255Pa pressure, and 10000W RF power, and a fourth passivation and antireflection layer is simultaneously deposited around the back side of the silicon substrate. The first and fourth passivation and antireflection layers are both composite films of aluminum oxide (passivation layer) and silicon oxynitride (antireflection layer), with an overall thickness of 95nm and a width of 8mm for the fourth passivation and antireflection layer.

[0083] S9. A third passivation antireflection layer is deposited on one side of the back side of the silicon substrate using PECVD at 550℃, 255Pa pressure, and 10000W RF power, and a second passivation antireflection layer is simultaneously deposited around the front side of the silicon substrate. The second and third passivation antireflection layers are silicon oxynitride layers with an overall thickness of 100nm and a width of 8mm for the second passivation antireflection layer.

[0084] S10. A first metal electrode and a second metal electrode are fabricated on the front and back sides of a silicon substrate by screen printing. The first metal electrode penetrates the first passivation antireflection layer and is electrically connected to the p+ emitter, and the second metal electrode penetrates the third passivation antireflection layer and is electrically connected to the n+ doped polycrystalline silicon layer.

[0085] Example 2

[0086] S1. The n-type silicon substrate is texturized with an alkaline solution (the alkaline solution is a 1% sodium hydroxide solution by volume, the texturization temperature is 80℃, and the immersion time is 400s) to form a textured surface structure on both sides of the silicon substrate in the thickness direction.

[0087] S2. The n-type silicon wafer with the textured surface is placed in a high-temperature diffusion furnace (the reactants, such as boron trichloride and boron tribromide, are mixed with oxygen and reacted at a temperature of 1000℃ for 3 hours) to carry out the diffusion / oxidation process of boron doping elements, so as to form a p+ emitter on the positive surface of the n-type silicon substrate; wherein, the boron doping concentration in the p+ emitter is 5E18 atoms / cm3.

[0088] S3. Use a 30% hydrofluoric acid solution to remove the silicon glass layer formed by wrapping around the back and sides of the n-type silicon substrate;

[0089] S4. Perform alkaline polishing on the front surface of the n-type silicon substrate (the alkaline solution is a 2% sodium hydroxide solution by volume, the reaction temperature is 60℃, and the immersion time is 200s);

[0090] S5. A tunneling oxide layer and an n+ doped polycrystalline silicon layer are sequentially prepared on the back surface of an n-type silicon substrate; wherein, the tunneling oxide layer is a silicon oxide layer obtained by LPCVD deposition at a reaction temperature of 600℃, a deposition time of 15min, and a thickness of 2nm; the doping concentration of the n+ doped polycrystalline silicon layer is 4.5E20 atoms / cm3.

[0091] S6. Use hydrofluoric acid with a volume concentration of 10% to remove the boron + phosphosilicate glass layer coated on the front side of the n-type silicon substrate, the uncoated area on the front side, and the phosphosilicate glass layer coated on the side.

[0092] S7. Clean the n-type silicon substrate (using RCA cleaning technology);

[0093] S8. A third passivation antireflection layer is deposited on the back side of a silicon substrate using ALD (atomic layer deposition) at 320℃ and PECVD at 550℃, 255Pa pressure, and 10000W RF power, while a second passivation antireflection layer is simultaneously deposited around the front side of the silicon substrate. The third and second passivation antireflection layers are both composite films of aluminum oxide (passivation layer) and silicon oxynitride (antireflection layer), with an overall thickness of 95nm and a width of 8mm for the second passivation antireflection layer.

[0094] S9. A first passivation antireflection layer is deposited on one side of the front side of the silicon substrate using PECVD at 550℃, 255Pa pressure, and 10000W RF power, and a fourth passivation antireflection layer is simultaneously deposited around the back side of the silicon substrate. The first and fourth passivation antireflection layers are silicon oxynitride layers with an overall thickness of 100nm and a width of 8mm for the fourth passivation antireflection layer.

[0095] S10. A first metal electrode and a second metal electrode are fabricated on the front and back sides of a silicon substrate by screen printing. The first metal electrode penetrates the first passivation antireflection layer and is electrically connected to the p+ emitter, and the second metal electrode penetrates the third passivation antireflection layer and is electrically connected to the n+ doped polycrystalline silicon layer.

[0096] Comparative Example 1

[0097] S1. The n-type silicon substrate is texturized with an alkaline solution (the alkaline solution is a 1% sodium hydroxide solution by volume, the texturization temperature is 80℃, and the immersion time is 400s) to form a textured surface structure on both sides of the silicon substrate in the thickness direction.

[0098] S2. The n-type silicon wafer with the textured surface is placed in a high-temperature diffusion furnace (the reactants, such as boron trichloride and boron tribromide, are mixed with oxygen and reacted at a temperature of 1000℃ for 3 hours) to carry out the diffusion / oxidation process of boron doping elements, so as to form a p+ emitter on the positive surface of the n-type silicon substrate; wherein, the boron doping concentration in the p+ emitter is 5E18 atoms / cm3.

[0099] S3. Use a 30% hydrofluoric acid solution to remove the silicon glass layer formed by wrapping around the back and sides of the n-type silicon substrate;

[0100] S4. Perform alkaline polishing on the front surface of the n-type silicon substrate (the alkaline solution is a 2% sodium hydroxide solution by volume, the reaction temperature is 60℃, and the immersion time is 200s);

[0101] S5. A tunneling oxide layer and an n+ doped polycrystalline silicon layer are sequentially prepared on the back surface of an n-type silicon substrate; wherein, the tunneling oxide layer is a silicon oxide layer obtained by LPCVD deposition at a reaction temperature of 600℃, a deposition time of 15min, and a thickness of 2nm; the doping concentration of the n+ doped polycrystalline silicon layer is 4.5E20 atoms / cm3.

[0102] S6. Use hydrofluoric acid with a volume concentration of 10% to remove the boron + phosphosilicate glass layer coated on the front side of the n-type silicon substrate, the uncoated area on the front side, and the phosphosilicate glass layer coated on the side.

[0103] S7. Clean the n-type silicon substrate (using RCA cleaning technology);

[0104] S8. Using ALD (Atomic Layer Deposition) at 320℃ and PECVD at 550℃, 255Pa, and 10000W, only a first passivation and antireflection layer with a thickness of 95nm is deposited on the front side of the silicon substrate, and using PECVD at 550℃, 255Pa, and 10000W, only a third passivation and antireflection layer with a total thickness of 100nm is deposited on the back side of the silicon substrate.

[0105] S9. A first metal electrode and a second metal electrode are fabricated on the front and back sides of a silicon substrate by screen printing. The first metal electrode penetrates the first passivation antireflection layer and is electrically connected to the p+ emitter, and the second metal electrode penetrates the third passivation antireflection layer and is electrically connected to the n+ doped polycrystalline silicon layer.

[0106] The performance comparison results of the solar cells prepared in the above embodiments and comparative examples are shown in the table below:

[0107] Table 1

[0108] As shown in Table 1, the open-circuit voltage (Voc) of the solar cells prepared in Examples 1 and 2 is about 1 mV higher than that of Comparative Example 1. The fill factor (FF) of the solar cells prepared in Examples 1 and 2 is about 0.1% higher than that of Comparative Example 1. The cell conversion efficiency (Eta) of the solar cells prepared in Examples 1 and 2 is about 0.06% higher than that of Comparative Example 1. The proportion of black edge defects in the solar cells prepared in Examples 1 and 2 is about 1% lower than that of Comparative Example 1.

[0109] Meanwhile, PL (photoluminescence) detection was performed on the solar cells prepared in Example 1 and Comparative Example 1, respectively, and the PL results are shown in Figures 14 and 15, where Figure 14 shows the PL result of the solar cell obtained in Example 1, and Figure 15 shows the PL result of the solar cell obtained in Comparative Example 1. It can be clearly seen from Figures 14 and 15 that the black edge defect area of ​​the solar cell prepared in Example 1 of this disclosure is significantly reduced.

[0110] As can be seen from the above performance comparison results, by setting a first passivation and antireflection structure including a first passivation and antireflection layer and a second passivation and antireflection layer, and a second passivation and antireflection structure including a third passivation and antireflection layer and a fourth passivation and antireflection layer, the thickness of the passivation and antireflection layer at the edge of the silicon substrate can be effectively increased, the passivation performance at the edge of the solar cell can be improved, and thus the overall photoelectric conversion efficiency of the solar cell can be increased.

[0111] The above steps are provided only to help understand the structure, method, and core ideas of this disclosure. Those skilled in the art can make various improvements and modifications to this disclosure without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A solar cell, comprising: a silicon substrate (1) ; an emitter (2) and a first passivation anti-reflection structure (3) disposed from inside to outside on one side of the silicon substrate (1) in a thickness direction of the silicon substrate (1), wherein the first passivation anti-reflection structure (3) comprises a first passivation anti-reflection layer (31) and a second passivation anti-reflection layer (32), and the second passivation anti-reflection layer (32) is disposed in an edge region of the silicon substrate (1) ; a tunnel oxide layer (5), a doped polysilicon layer (6) and a second passivation anti-reflection structure (7) disposed from inside to outside on the other side of the silicon substrate (1) in the thickness direction of the silicon substrate (1), wherein the second passivation anti-reflection structure (7) comprises a third passivation anti-reflection layer (71) and a fourth passivation anti-reflection layer (72), and the fourth passivation anti-reflection layer (72) is disposed in the edge region of the silicon substrate (1). 2.The solar cell of claim 1, wherein: the first passivation anti-reflection layer (31) and the fourth passivation anti-reflection layer (72) are formed synchronously, and the second passivation anti-reflection layer (32) and the third passivation anti-reflection layer (71) are formed synchronously. 3.The solar cell of claim 2, wherein: the fourth passivation anti-reflection layer (72) is formed by around-plating when the first passivation anti-reflection layer (31) is prepared by controlling a fitting distance between the silicon substrate (1) and a carrier; and the second passivation anti-reflection layer (32) is formed by around-plating when the third passivation anti-reflection layer (71) is prepared by controlling the fitting distance between the silicon substrate (1) and the carrier. 4.The solar cell of any one of claims 1 to 3, wherein: the second passivation anti-reflection layer (32) is disposed outside the first passivation anti-reflection layer (31) ; and the fourth passivation anti-reflection layer (72) is disposed between the doped polysilicon layer (6) and the third passivation anti-reflection layer (71). 5.The solar cell of any one of claims 1 to 3, wherein: the second passivation anti-reflection layer (32) is disposed between the first passivation anti-reflection layer (31) and the emitter (2) ; and the fourth passivation anti-reflection layer (72) is disposed outside the third passivation anti-reflection layer (71). 6.The solar cell of claim 1, wherein: a width of the second passivation anti-reflection layer (32) is 0.5mm to 10mm; and / or a width of the fourth passivation anti-reflection layer (72) is 0.5mm to 10mm. 7.The solar cell of claim 1, wherein: the first passivation anti-reflection layer (31) and / or the fourth passivation anti-reflection layer (72) comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride; and / or the second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) comprises at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride. 8.The solar cell of claim 1, wherein: a thickness of the first passivation anti-reflection layer (31) and / or the fourth passivation anti-reflection layer (72) is 20nm to 180nm; and / or a thickness of the second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) is 20nm to 180nm. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The thickness of the second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) is 25nm-200nm; and / or, The thickness of the tunneling oxide layer (5) is 0.5nm-5nm; and / or, The thickness of the doped polysilicon layer (6) is 30nm-200nm.

9. A method for preparing the solar cell of any one of claims 1-8, comprising: Step 1: preparing an emitter (2) on one side of the silicon substrate (1) in the thickness direction; Step 2: preparing a tunneling oxide layer (5) and a doped polysilicon layer (6) from inside to outside on the other side of the silicon substrate (1) in the thickness direction; Step 3: preparing a first passivation anti-reflection structure (3) and a second passivation anti-reflection structure (7) on the outside of the emitter (2) and the doped polysilicon layer (6), respectively; wherein the first passivation anti-reflection structure (3) comprises a first passivation anti-reflection layer (31) and a second passivation anti-reflection layer (32), and the second passivation anti-reflection layer (32) is arranged at the edge region of the silicon substrate (1); the second passivation anti-reflection structure (5) comprises a third passivation anti-reflection layer (71) and a fourth passivation anti-reflection layer (72), and the fourth passivation anti-reflection layer (72) is arranged at the edge region of the silicon substrate (1).

10. The production method according to claim 9, wherein The step 3 comprises: forming the fourth passivation anti-reflection layer (72) on the outside of the doped polysilicon layer (6) while preparing the first passivation anti-reflection layer (31) on the outside of the emitter (2); forming the second passivation anti-reflection layer (32) on the outside of the first passivation anti-reflection layer (31) while preparing the third passivation anti-reflection layer (71) on the outside of the fourth passivation anti-reflection layer (72) and the doped polysilicon layer (6); Alternatively, the step 3 comprises: forming the second passivation anti-reflection layer (32) on the outside of the emitter (2) while preparing the third passivation anti-reflection layer (71) on the outside of the doped polysilicon layer (6); forming the fourth passivation anti-reflection layer (72) on the outside of the third passivation anti-reflection layer (71) while preparing the first passivation anti-reflection layer (31) on the outside of the second passivation anti-reflection layer (32) and the emitter (2); and / or, the step 3 further comprises: setting the fitting distance of the silicon substrate (1) and the carrier to 80μm-400μm to prepare the first passivation anti-reflection structure (3) and the second passivation anti-reflection structure (7).

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