Pixel driving circuit, display apparatus and driving method

Abstract

The present application relates to the technical field of displays. Disclosed are a pixel driving circuit, a display apparatus and a driving method. The pixel driving circuit comprises: a driving transistor, a light-emitting device, a light emission control sub-circuit, a data writing sub-circuit, a first switching control sub-circuit and a second switching control sub-circuit, wherein the data writing sub-circuit provides a data voltage of a data voltage terminal to a first terminal of the driving transistor; in response to a signal of a first switching control terminal, the first switching control sub-circuit connects a first node to a second terminal of the driving transistor; in response to a signal of a second switching control terminal, the second switching control sub-circuit connects the first node to a control terminal of the driving transistor; the driving transistor generates a driving current on the basis of the data voltage; and the light emission control sub-circuit provides the driving current to the light-emitting device. During the implementation of dynamic frequency display of a display panel, current leakage of the display panel during high-low frequency transitions is mitigated, a bias reset is provided, and an increase in a bezel width is avoided.

Description

A pixel driving circuit, display device and driving method

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410804442.5, filed on June 20, 2024, entitled "A Pixel Driving Circuit, Display Device and Driving Method", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and provides a pixel driving circuit, a display device, and a driving method. Background Technology

[0004] To achieve dynamic frequency display on the display panel, the pixel driving circuit in each pixel needs to receive relevant control signals from the shift register unit and cooperate with the gating module in cascade to achieve time-division and area-division dynamic display.

[0005] In related technologies, problems such as leakage current and low-frequency flicker may occur when implementing high-frequency and low-frequency switching displays. Summary of the Invention

[0006] This application provides a pixel driving circuit, a display device, and a driving method to alleviate leakage current in the display panel during high-low frequency switching, provide bias reset, and without increasing the bezel.

[0007] The specific technical solution provided in this application is as follows:

[0008] In a first aspect, embodiments of this application provide a pixel driving circuit, including: a driving transistor, a light-emitting device, a light-emitting control sub-circuit, a data writing sub-circuit, a first conduction control sub-circuit, and a second conduction control sub-circuit;

[0009] The data writing sub-circuit is coupled to the first terminal of the driving transistor and is configured to provide the data voltage from the data voltage terminal to the first terminal of the driving transistor in response to the signal at the scan signal terminal.

[0010] The first conduction control subcircuit is coupled to the first node and the second terminal of the driving transistor, and is configured to connect the first node and the second terminal of the driving transistor in response to a signal at the first conduction control terminal.

[0011] The second conduction control subcircuit is coupled to the first node and the control terminal of the driving transistor, and is configured to connect the first node and the control terminal of the driving transistor in response to a signal from the second conduction control terminal.

[0012] The driving transistor is configured to generate a driving current based on the data voltage;

[0013] The light-emitting control sub-circuit is coupled to the first terminal and the second terminal of the driving transistor and is configured to provide driving current to the light-emitting device in response to a signal from the light-emitting control terminal.

[0014] Optionally, the second conduction control sub-circuit includes: a first switching transistor;

[0015] The control terminal of the first switching transistor is coupled to the second conduction control terminal, the first terminal of the first switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the first switching transistor is coupled to the first node.

[0016] Optionally, the data writing sub-circuit includes: a second switching transistor;

[0017] The control terminal of the second switching transistor is coupled to the scan signal terminal, the first terminal of the second switching transistor is coupled to the first terminal of the drive transistor, and the second terminal of the second switching transistor is coupled to the data voltage terminal.

[0018] Optionally, the first conduction control sub-circuit includes: a third switching transistor;

[0019] The control terminal of the third switching transistor is coupled to the first conduction control terminal, the first terminal of the third switching transistor is coupled to the first node, and the second terminal of the third switching transistor is coupled to the second terminal of the driving transistor.

[0020] Optionally, the light-emitting control sub-circuit includes: a fourth switching transistor and a fifth switching transistor;

[0021] The control terminal of the fourth switching transistor is coupled to the light-emitting control terminal, the first terminal of the fourth switching transistor is coupled to the first power supply terminal, and the second terminal of the fourth switching transistor is coupled to the first terminal of the driving transistor.

[0022] The control terminal of the fifth switching transistor is coupled to the light-emitting control terminal, the first terminal of the fifth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth switching transistor is coupled to the light-emitting device.

[0023] Optionally, it also includes a first reset sub-circuit;

[0024] The first reset circuit is coupled to the first terminal of the driving transistor and is configured to provide the first initialization voltage of the first initialization voltage terminal to the first terminal of the driving transistor in response to a signal at the first reset signal terminal.

[0025] Optionally, the first reset circuit includes: a sixth switching transistor;

[0026] The control terminal of the sixth switching transistor is coupled to the first reset signal terminal, the first terminal of the sixth switching transistor is coupled to the first initialization voltage terminal, and the second terminal of the sixth switching transistor is coupled to the first terminal of the driving transistor.

[0027] Optionally, it also includes a second reset circuit;

[0028] The second reset circuit is coupled to the anode of the light-emitting device and is configured to provide the second initialization voltage of the second initialization voltage terminal to the anode of the light-emitting device in response to a signal at the second reset signal terminal.

[0029] Optionally, the second reset circuit includes: a seventh switching transistor;

[0030] The control terminal of the seventh switching transistor is coupled to the second reset signal terminal, the first terminal of the seventh switching transistor is coupled to the anode of the light-emitting device, and the second terminal of the seventh switching transistor is coupled to the second initialization voltage terminal.

[0031] Optionally, a third reset circuit may also be included;

[0032] The third reset sub-circuit is coupled to the first node and is configured to provide the third initialization voltage of the third initialization voltage terminal to the first node in response to a signal at the third reset signal terminal.

[0033] Optionally, the third reset circuit includes: an eighth switching transistor;

[0034] The control terminal of the eighth switching transistor is coupled to the third reset signal terminal, the first terminal of the eighth switching transistor is coupled to the first node, and the second terminal of the eighth switching transistor is coupled to the third initialization voltage terminal.

[0035] Optionally, it also includes: a first capacitor;

[0036] The first terminal of the first capacitor is coupled to the first power supply terminal, and the second terminal of the first capacitor is coupled to the first terminal of the second switching transistor.

[0037] Optionally, it also includes: a second capacitor;

[0038] The first terminal of the second capacitor is coupled to the second terminal of the driving transistor, and the second terminal of the second capacitor is coupled to the first power supply terminal.

[0039] Optionally, it also includes: a third capacitor;

[0040] The first terminal of the third capacitor is coupled to the first power supply terminal, and the second terminal of the third capacitor is coupled to the first node.

[0041] Optionally, it also includes: a fourth capacitor;

[0042] The first terminal of the fourth capacitor is coupled to the first power supply terminal, and the second terminal of the fourth capacitor is coupled to the control terminal of the driving transistor.

[0043] Optionally, the signal of the second turn-on control terminal is input from the shift register in the first shift register unit, and the signal of the first turn-on control terminal is input from the shift register in the second shift register unit.

[0044] Optionally, the signal at the second turn-on control terminal is input from the nth stage shift register in the third shift register unit, and the signal at the first turn-on control terminal is input from the (n+k)th stage shift register in the third shift register unit.

[0045] Secondly, embodiments of this application also provide a display device including the pixel driving circuit of any of the above.

[0046] Thirdly, embodiments of this application also provide a driving method for the pixel driving circuit of any of the above claims, comprising:

[0047] First stage: The first reset sub-circuit responds to the signal at the first reset signal terminal and provides the first initialization voltage at the first initialization voltage terminal to the first terminal of the driving transistor; the second reset sub-circuit responds to the signal at the second reset signal terminal and provides the second initialization voltage at the second initialization voltage terminal to the anode of the light-emitting device; the third reset sub-circuit responds to the signal at the third reset signal terminal and provides the third initialization voltage at the third initialization voltage terminal to the first node; the second conduction control sub-circuit responds to the signal at the second conduction control terminal and connects the first node to the control terminal of the driving transistor.

[0048] Second stage: The data writing sub-circuit responds to the signal at the scan signal terminal and provides the data voltage at the data voltage terminal to the first terminal of the driving transistor. The first conduction control sub-circuit responds to the signal at the first conduction control terminal and connects the first node to the second terminal of the driving transistor. The second conduction control sub-circuit responds to the signal at the second conduction control terminal and connects the first node to the control terminal of the driving transistor.

[0049] Third stage: The first reset sub-circuit responds to the signal at the first reset signal terminal and provides the first initialization voltage at the first initialization voltage terminal to the first terminal of the driving transistor; the second reset sub-circuit responds to the signal at the second reset signal terminal and provides the second initialization voltage at the second initialization voltage terminal to the anode of the light-emitting device; the third reset sub-circuit responds to the signal at the third reset signal terminal and provides the third initialization voltage at the third initialization voltage terminal to the first node.

[0050] Fourth stage: The light-emitting control sub-circuit responds to the signal at the light-emitting control terminal and provides driving current to the light-emitting device.

[0051] The beneficial effects of this application are as follows:

[0052] In summary, this application provides a pixel driving circuit, a display device, and a driving method. The pixel driving circuit includes: a driving transistor, a light-emitting device, a light-emitting control sub-circuit, a data writing sub-circuit, a first conduction control sub-circuit, and a second conduction control sub-circuit. The data writing sub-circuit is coupled to a first terminal of the driving transistor and configured to provide a data voltage from a data voltage terminal to the first terminal of the driving transistor in response to a signal from a scan signal terminal. The first conduction control sub-circuit is coupled to a first node and a second terminal of the driving transistor and configured to connect the first node and the second terminal of the driving transistor in response to a signal from a first conduction control terminal. The second conduction control sub-circuit is coupled to the first node and a control terminal of the driving transistor and configured to connect the first node and the control terminal of the driving transistor in response to a signal from a second conduction control terminal. The driving transistor is configured to generate a driving current based on the data voltage. The light-emitting control sub-circuit is coupled to the first terminal and the second terminal of the driving transistor and configured to provide a driving current to the light-emitting device in response to a signal from a light-emitting control terminal. In the process of realizing dynamic frequency display of the display panel, this alleviates leakage current of the display panel during high-low frequency switching, provides bias reset, and does not increase the bezel.

[0053] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0054] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0055] Figure 1 is a connection diagram of the first pixel driving circuit in an embodiment of this application;

[0056] Figure 2 is a circuit diagram of the first pixel driving circuit in the embodiment of this application;

[0057] Figure 3 is a connection diagram of the second pixel driving circuit in an embodiment of this application;

[0058] Figure 4 is a circuit diagram of the second pixel driving circuit in an embodiment of this application;

[0059] Figure 5 is a circuit connection diagram of the third pixel driving circuit in the embodiments of this application;

[0060] Figure 6 is a circuit connection diagram of the fourth pixel driving circuit in the embodiments of this application;

[0061] Figure 7 is a circuit connection diagram of the third shift register unit coupled to the fourth pixel driving circuit in an embodiment of this application;

[0062] Figure 8 is a circuit connection diagram of the fifth pixel driving circuit in the embodiments of this application;

[0063] Figure 9 is a circuit connection diagram of the sixth pixel driving circuit in the embodiments of this application;

[0064] Figure 10 is a circuit connection diagram of the seventh pixel driving circuit in the embodiments of this application;

[0065] Figure 11 is a circuit connection diagram of the eighth pixel driving circuit in the embodiments of this application;

[0066] Figure 12 is a circuit connection diagram of the ninth pixel driving circuit in the embodiments of this application;

[0067] Figure 13 is a circuit connection diagram of the tenth pixel driving circuit in the embodiments of this application;

[0068] Figure 14 is a circuit connection diagram of the eleventh pixel driving circuit in the embodiments of this application;

[0069] Figure 15 is a timing diagram of the first pixel driving circuit in the embodiment of this application;

[0070] Figure 16 is a connection diagram of the first type of shift register unit connected to the pixel driving circuit in an embodiment of this application;

[0071] Figure 17 is a connection diagram of the second type of shift register unit connected to the pixel driving circuit in an embodiment of this application;

[0072] Figure 18 is a connection diagram of the third type of shift register unit connected to the pixel driving circuit in an embodiment of this application;

[0073] Figure 19 is a timing diagram of the second pixel driving circuit in the embodiments of this application;

[0074] Figure 20 is a timing diagram of the third pixel driving circuit in the embodiments of this application;

[0075] Figure 21 is a timing diagram of the fourth pixel driving circuit in the embodiments of this application;

[0076] Figure 22 is a flowchart of a pixel driving circuit driving method according to an embodiment of this application. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application. Obviously, the described embodiments are only some embodiments of the technical solutions of this application, and not all embodiments. Based on the embodiments recorded in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this application.

[0078] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0079] In related technologies, the dynamic frequency display process of a display panel requires the update frequency of the data voltage in the pixel driving circuit to achieve this. Specifically, this requires two gating modules working in conjunction with switching transistors related to the data voltage. However, these two gating modules are relatively large, resulting in a wide bezel for the display panel.

[0080] The preferred embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0081] Referring to Figure 1, a pixel driving circuit proposed in this application embodiment includes: a driving transistor DTFT, a light-emitting device OLED, a light-emitting control sub-circuit 40, a data writing sub-circuit 10, a first conduction control sub-circuit 20, and a second conduction control sub-circuit 30.

[0082] The data writing sub-circuit 10 is coupled to the first terminal of the driving transistor DTFT and is configured to provide the data voltage Vdata of the data voltage terminal Data to the first terminal of the driving transistor DTFT in response to the signal of the scan signal terminal Pgate.

[0083] During implementation, when the signal at the scanning signal terminal Pgate is valid, the data writing sub-circuit 10 is turned on, and the data voltage Vdata at the data voltage terminal Data is provided to the first terminal of the driving transistor DTFT through the data writing sub-circuit 10.

[0084] The first conduction control sub-circuit 20 is coupled to the first node N1 and the second terminal of the driving transistor DTFT, and is configured to connect the first node N1 and the second terminal of the driving transistor DTFT in response to the signal of the first conduction control terminal Ngate2.

[0085] During implementation, when the signal of the first conduction control terminal Ngate2 is valid, the first conduction control sub-circuit 20 is turned on, and the first node N1 is connected to the second terminal of the driving transistor DTFT through the first conduction control sub-circuit 20.

[0086] The second conduction control sub-circuit 30 is coupled to the first node N1 and the control terminal of the driving transistor DTFT, and is configured to connect the first node N1 and the control terminal of the driving transistor DTFT in response to the signal of the second conduction control terminal Ngate1.

[0087] During implementation, when the signal of the second conduction control terminal Ngate1 is valid, the second conduction control sub-circuit 30 is turned on, and the first node N1 is connected to the control terminal of the driving transistor DTFT through the second conduction control sub-circuit 30.

[0088] The driving transistor DTFT is configured to generate a driving current based on the data voltage Vdata.

[0089] In this embodiment, the driving transistor DTFT can generate a driving current based on the data voltage Vdata. It should be noted that when the turn-on frequency of the scan signal terminal Pgate is high, and the turn-on frequencies of the signals at the first conduction control terminal of the first switching transistor T1 and the second conduction control terminal of the third switching transistor T3 are also high, the data voltage Vdata can be written to the driving transistor at a high frequency, thereby enabling high-frequency display of the display screen; when the turn-on frequency of the scan signal terminal Pgate is low, and / or the turn-on frequencies of the signals at the first conduction control terminal of the first switching transistor T1 and the second conduction control terminal of the third switching transistor T3 are also low, the data voltage Vdata can be written to the driving transistor at a low frequency, thereby enabling low-frequency display of the display screen.

[0090] The light emission control sub-circuit 40 is coupled to the first terminal and the second terminal of the driving transistor DTFT and is configured to provide driving current to the light emission device OLED in response to the signal of the light emission control terminal EM.

[0091] During implementation, when the signal of the light-emitting control terminal EM is valid, the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the light-emitting control sub-circuit 40, the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device OLED through the light-emitting control sub-circuit 40, the cathode of the light-emitting device OLED is connected to the second power supply terminal VSS, and the driving current generated by the driving transistor DTFT is provided to the light-emitting device OLED through the light-emitting control sub-circuit 40, thereby causing the light-emitting device OLED to emit light.

[0092] The working process of each sub-circuit will be introduced below with reference to a specific circuit diagram.

[0093] For example, referring to FIG2, the second conduction control sub-circuit 30 mentioned above includes: a first switching transistor T1.

[0094] Referring to Figure 2, the connection relationship between the first switching transistor T1 and other components is as follows: the control terminal of the first switching transistor T1 is coupled to the second conduction control terminal Ngate1, the first terminal of the first switching transistor T1 is coupled to the control terminal of the driving transistor DTFT, and the second terminal of the first switching transistor T1 is coupled to the first node N1.

[0095] During implementation, when the signal at the second control terminal Ngate1 is high, the first switching transistor T1 is turned on, and the control terminal of the driving transistor DTFT is connected to the first node N1 via the turned-on first switching transistor T1.

[0096] It should be further noted that, referring to Figure 2, the polarity of the first switching transistor T1 in this embodiment is N-type, and the polarity of the first switching transistor T1 is the same as that of the third switching transistor T3. Furthermore, the polarities of the first switching transistor T1 and the third switching transistor T3 are different from the polarities of the other switching transistors. In some other embodiments, the polarity of the first switching transistor T1 may also be P-type.

[0097] It should also be noted that the first switching transistor T1 is a low-temperature poly-silicon (LTPS) transistor, and the corresponding third switching transistor T3 is an oxide transistor; or, the first switching transistor T1 is an oxide transistor, and the corresponding third switching transistor T3 is an LTPS transistor. When the third switching transistor T3 is an LTPS transistor, the control terminals of the third switching transistor T3 and the second switching transistor T2 are connected to the same scan signal terminal Pgate.

[0098] For example, referring to FIG2, the above data writing sub-circuit 10 includes: a second switching transistor T2.

[0099] Referring to Figure 2, the connection relationship between the second switching transistor T2 and other components is as follows: the control terminal of the second switching transistor T2 is coupled to the scan signal terminal Pgate, the first terminal of the second switching transistor T2 is coupled to the first terminal of the driving transistor DTFT, and the second terminal of the second switching transistor T2 is coupled to the data voltage terminal Data.

[0100] During implementation, when the signal at the scan signal terminal Pgate is low, the second switching transistor T2 is turned on, and the data voltage Vdata at the data voltage terminal Data is supplied to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2. Since the driving transistor DTFT is also in the turned-on state, the aforementioned data voltage Vdata is further supplied to the second terminal of the driving transistor DTFT.

[0101] For example, referring to Figure 2, the polarity of the second switching transistor T2 in this embodiment is N-type, and the polarity of the second switching transistor T2 is the same as that of the first switching transistor T1. Furthermore, the polarities of the second switching transistor T2 and the first switching transistor T1 are different from the polarities of the other switching transistors. In other embodiments, the polarity of the second switching transistor T2 may also be P-type.

[0102] For example, referring to Figure 2, the first conduction control sub-circuit 20 mentioned above includes: a third switching transistor T3.

[0103] Referring to Figure 2, the connection relationship between the third switching transistor T3 and other components is as follows: the control terminal of the third switching transistor T3 is coupled to the first conduction control terminal Ngate2, the first terminal of the third switching transistor T3 is coupled to the first node N1, and the second terminal of the third switching transistor T3 is coupled to the second terminal of the driving transistor DTFT.

[0104] During implementation, when the signal at the first control terminal Ngate2 is high, the third switching transistor T3 is turned on, and the second terminal of the driving transistor DTFT is connected to the first node N1 via the turned-on third switching transistor T3.

[0105] For example, referring to Figure 2, the above-mentioned light-emitting control sub-circuit 40 includes: a fourth switching transistor T4 and a fifth switching transistor T5.

[0106] Referring to Figure 2, the connection relationship between the fourth switching transistor T4 and other components is as follows: the control terminal of the fourth switching transistor T4 is coupled to the light-emitting control terminal EM, the first terminal of the fourth switching transistor T4 is coupled to the first power supply terminal VDD, and the second terminal of the fourth switching transistor T4 is coupled to the first terminal of the driving transistor DTFT.

[0107] During implementation, when the signal at the light-emitting control terminal EM is low, the fourth switching transistor T4 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fourth switching transistor T4.

[0108] Referring to Figure 2, the connection relationship between the fifth switching transistor T5 and other components is as follows: the control terminal of the fifth switching transistor T5 is coupled to the light-emitting control terminal EM, the first terminal of the fifth switching transistor T5 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the fifth switching transistor T5 is coupled to the light-emitting device OLED.

[0109] During implementation, when the signal at the light-emitting control terminal EM is low, the fifth switching transistor T5 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device OLED through the turned-on fifth switching transistor T5.

[0110] In addition, as shown in Figure 3, the pixel driving circuit also includes a first reset circuit 50.

[0111] The first reset circuit 50 is coupled to the first terminal of the driving transistor DTFT and is configured to provide the first initialization voltage Vinit1 of the first initialization voltage Vinit1 terminal to the first terminal of the driving transistor DTFT in response to the signal of the first reset signal terminal Reset_P.

[0112] During implementation, when the signal of the first reset signal terminal Reset_P is valid, the first initialization voltage Vinit1 of the first initialization voltage Vinit1 terminal is provided to the first terminal of the driving transistor DTFT through the first reset sub-circuit 50, thereby realizing the initialization of the first terminal of the driving transistor DTFT.

[0113] For example, referring to FIG4, the first reset circuit 50 mentioned above includes: a sixth switching transistor T6.

[0114] Referring to Figure 4, the connection relationship between the sixth switching transistor T6 and other components is as follows: the control terminal of the sixth switching transistor T6 is coupled to the first reset signal terminal Reset_P, the first terminal of the sixth switching transistor T6 is coupled to the first initialization voltage Vinit1 terminal, and the second terminal of the sixth switching transistor T6 is coupled to the first terminal of the driving transistor DTFT.

[0115] During implementation, when the signal at the first reset signal terminal Reset_P is low, the sixth switching transistor T6 is turned on. The first initialization voltage Vinit1 at the first initialization voltage terminal is provided to the first terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6, thereby realizing the initialization of the first terminal of the driving transistor DTFT.

[0116] In addition, as shown in Figure 3, the pixel driving circuit also includes a second reset circuit 60.

[0117] The second reset circuit 60 is coupled to the anode of the OLED and is configured to provide the second initialization voltage Vinit2 at the second initialization voltage Vinit2 terminal to the anode of the OLED in response to the signal of the second reset signal terminal Reset_P.

[0118] During implementation, when the signal at the second reset signal terminal Reset_P is valid, the second reset sub-circuit 60 is turned on, and the second initialization voltage Vinit2 at the second initialization voltage Vinit2 terminal is provided to the anode of the light-emitting device OLED through the turned-on second reset sub-circuit 60.

[0119] For example, referring to FIG4, the second reset circuit 60 mentioned above includes a seventh switching transistor T7.

[0120] Referring to Figure 4, the connection relationship between the seventh switching transistor T7 and other components is as follows: the control terminal of the seventh switching transistor T7 is coupled to the second reset signal terminal Reset_P, the first terminal of the seventh switching transistor T7 is coupled to the anode of the light-emitting device OLED, and the second terminal of the seventh switching transistor T7 is coupled to the second initialization voltage Vinit2 terminal.

[0121] During implementation, when the second reset signal terminal Reset_P is low, the seventh switching transistor T7 is turned on, and the second initialization voltage Vinit2 at the second initialization voltage Vinit2 terminal is provided to the anode of the light-emitting device OLED through the turned-on seventh switching transistor T7, thereby realizing the initialization of the anode of the light-emitting device OLED.

[0122] In addition, as shown in Figure 3, the pixel driving circuit also includes a third reset circuit 70.

[0123] The third reset sub-circuit 70 is coupled to the first node N1 and is configured to provide the third initialization voltage Vinit3 at the third initialization voltage Vinit3 terminal to the first node N1 in response to the signal of the third reset signal terminal Reset_P.

[0124] During implementation, when the signal at the third reset signal terminal Reset_P is valid, the third reset sub-circuit 70 is turned on, and the third initialization voltage Vinit3 at the third initialization voltage terminal is provided to the first node N1 through the turned-on third reset sub-circuit 70, thereby realizing the initialization of the first node N1.

[0125] For example, referring to FIG4, the third reset circuit 70 mentioned above includes an eighth switching transistor T8.

[0126] Referring to Figure 4, the connection relationship between the eighth switching transistor T8 and other components is as follows: the control terminal of the eighth switching transistor T8 is coupled to the third reset signal terminal Reset_P, the first terminal of the eighth switching transistor T8 is coupled to the first node N1, and the second terminal of the eighth switching transistor T8 is coupled to the third initialization voltage Vinit3 terminal.

[0127] During implementation, when the signal at the third reset signal terminal Reset_P is low, the eighth switching transistor T8 is turned on, and the third initialization voltage Vinit3 at the initialization voltage terminal is provided to the first node N1 through the turned-on eighth switching transistor T8, thereby realizing the initialization of the first node N1.

[0128] Considering that the signals of the control terminals of multiple switching transistors in the above pixel driving circuit all originate from the shift register unit, in one embodiment, as shown in Figures 4 and 5, the signal of the second turn-on control terminal Ngate1 is input from the shift register in the first shift register unit, and the signal of the first turn-on control terminal Ngate2 is input from the shift register in the second shift register unit.

[0129] Referring to Figures 4 and 5, the signal at the control terminal (i.e., the second turn-on control terminal Ngate1) of the first switching transistor T1 is input from the shift register in the first shift register unit Ngate1. The signal at the control terminal (i.e., the first turn-on control terminal Ngate2) of the third switching transistor T3 is input from the shift register in the second shift register unit Ngate2.

[0130] In addition, in order to reduce the number of shift register units connected to the pixel driving circuit mentioned above, in another embodiment, referring to FIG6, the signal of the second turn-on control terminal Ngate1 is input from the nth stage shift register in the third shift register unit, and the signal of the first turn-on control terminal Ngate2 is input from the (n+k)th stage shift register in the third shift register unit.

[0131] Referring to Figures 7 and 8, the signal of the control terminal of the first switching transistor T1, i.e., the second conduction control terminal Ngate1, is input from the nth stage shift register Ngate(n-5) in the third shift register unit. The signal of the control terminal of the third switching transistor T3, i.e., the first conduction control terminal Ngate2, is input from the (n+k)th stage shift register Ngate(n) in the third shift register unit.

[0132] Similarly, the first reset signal terminal Reset_P, the second reset signal terminal Reset_P, and the third reset signal terminal Reset_P in the pixel driving circuit described above can be coupled to the same signal terminal, i.e., Reset_P, or they can be coupled to different signal terminals respectively. For example, referring to Figure 4, the control terminals of the sixth switching transistor T6, the seventh switching transistor T7, and the eighth switching transistor T8 are all coupled to the signal terminal Reset_P. Referring to Figure 5, the control terminal of the sixth switching transistor T6 is coupled to the signal terminal Reset_H, the control terminal of the seventh switching transistor T7 is coupled to the signal terminal Reset_N, and the control terminals of the eighth switching transistor T8 are all coupled to the signal terminal Reset_P.

[0133] In addition, as shown in Figure 8, the pixel driving circuit also includes a first capacitor C1.

[0134] Referring to Figure 8, the connection relationship between the first capacitor C1 and other components is as follows: the first end of the first capacitor C1 is coupled to the first power supply terminal VDD, and the second end of the first capacitor C1 is coupled to the first end of the second switching transistor T2.

[0135] Considering that the time for the data voltage Vdata to be written to the control terminal of the driving transistor DTFT is short when the display refreshes at a high frequency, for example, when the refresh rate is 120Hz, the writing time of the data voltage Vdata is... Since the writing time is relatively short, in order to avoid the situation where the data voltage Vdata cannot be completely written to the control terminal of the driving transistor DTFT within the writing time, in this embodiment of the application, a first capacitor C1 is provided between the first power supply terminal VDD and the first terminal of the second switching transistor T2.

[0136] During implementation, while the data voltage Vdata is written to the first terminal of the driving transistor DTFT via the second switching transistor T2, the data voltage Vdata is stored through the first capacitor C1. In this way, when the second switching transistor T2 is turned off, the data voltage Vdata can still be written to the first terminal of the driving transistor DTFT through the first capacitor C1, thereby ensuring that the data voltage Vdata can be completely written to the control terminal of the driving transistor DTFT.

[0137] For example, referring to Figure 9, the pixel driving circuit described above further includes a second capacitor C2.

[0138] Referring to Figure 9, the connection relationship between the second capacitor C2 and other components is as follows: the first end of the second capacitor C2 is coupled to the second end of the driving transistor DTFT, and the second end of the second capacitor C2 is coupled to the first power supply terminal VDD.

[0139] Similarly, in order to avoid the situation where the data voltage Vdata cannot be fully written to the control terminal of the driving transistor DTFT within the aforementioned writing time, in this embodiment of the application, a second capacitor C2 is provided between the first power supply terminal VDD and the second terminal of the driving transistor DTFT.

[0140] During implementation, while the data voltage Vdata is written to the first terminal of the driving transistor DTFT via the second switching transistor T2, the data voltage Vdata is stored through the second capacitor C2. In this way, when the second switching transistor T2 is turned off, the data voltage Vdata can still be written to the second terminal of the driving transistor DTFT through the second capacitor C2, thereby ensuring that the data voltage Vdata can be completely written to the control terminal of the driving transistor DTFT.

[0141] For example, referring to Figure 10, the pixel driving circuit described above also includes a third capacitor C3.

[0142] Referring to Figure 10, the connection relationship between the third capacitor C3 and other components is as follows: the first end of the third capacitor C3 is coupled to the first power supply terminal VDD, and the second end of the third capacitor C3 is coupled to the first node N1.

[0143] Similarly, in order to avoid the situation where the data voltage Vdata cannot be fully written to the control terminal of the driving transistor DTFT within the above-mentioned writing time, in this embodiment of the application, a second capacitor C2 is provided between the first power supply terminal VDD and the first node N1.

[0144] During implementation, while the data voltage Vdata is written to the first terminal of the driving transistor DTFT via the second switching transistor T2, the data voltage Vdata is stored through the third capacitor C3. In this way, when the second switching transistor T2 is turned off, the data voltage Vdata can still be written to the first node N1 through the third capacitor C3, thereby ensuring that the data voltage Vdata can be completely written to the control terminal of the driving transistor DTFT.

[0145] In this embodiment of the application, in order to enable the data voltage Vdata to be written more completely to the control terminal of the driving transistor DTFT after the second switching transistor T2 is turned off, in one embodiment, any two of the first capacitor C1, the second capacitor C2 and the third capacitor C3 can be selected to compensate for the data voltage Vdata.

[0146] Referring to Figure 11, a first capacitor C1 and a second capacitor C2 are simultaneously provided in the above pixel driving circuit. In this way, after the second switching transistor T2 is turned off, the data voltage Vdata of the driving transistor DTFT can be written simultaneously through the first capacitor C1 and the second capacitor C2.

[0147] Referring to Figure 12, in the above pixel driving circuit, a first capacitor C1 and a third capacitor C3 are simultaneously provided. In this way, after the second switching transistor T2 is turned off, the first capacitor C1 and the third capacitor C3 can simultaneously write the data voltage Vdata to the driving transistor DTFT.

[0148] Referring to Figure 13, in the above pixel driving circuit, a second capacitor C2 and a third capacitor C3 are simultaneously provided. In this way, after the second switching transistor T2 is turned off, the data voltage Vdata of the driving transistor DTFT can be written simultaneously through the second capacitor C2 and the third capacitor C3.

[0149] In another embodiment, referring to FIG14, a first capacitor C1, a second capacitor C2, and a third capacitor C3 are simultaneously provided in the above pixel driving circuit. In this way, after the second switching transistor T2 is turned off, the first capacitor C1, the second capacitor C2, and the third capacitor C3 can simultaneously write the data voltage Vdata to the driving transistor DTFT.

[0150] Furthermore, as shown in Figure 15, after the signal of the aforementioned scanning signal terminal Pgate becomes invalid, there is a certain threshold time before the signal of the second conduction control terminal Ngate1 is turned off. The threshold time can be greater than the on-time of a scanning signal terminal Pgate. At this time, the second conduction control terminal Ngate1 can continue to be turned on and the third capacitor C3 can continue to charge the first node N1, thereby achieving full writing of the data voltage Vdata without adding a border.

[0151] It should be noted that the first terminal of the first capacitor C1, the second terminal of the second capacitor C2, and the first terminal of the third capacitor C3 can also be coupled to other DC power supplies besides the first power supply terminal VDD.

[0152] Furthermore, as exemplarily shown in FIG14, the pixel driving circuit described above also includes a fourth capacitor C4.

[0153] Referring to Figure 14, the connection relationship between the fourth capacitor C4 and other components is as follows: the first end of the fourth capacitor C4 is coupled to the first power supply terminal VDD, and the second end of the fourth capacitor C4 is coupled to the control terminal of the driving transistor DTFT.

[0154] In this embodiment, the fourth capacitor C4 is disposed between the first power supply terminal VDD and the control terminal of the driving transistor DTFT, thereby enabling the data voltage Vdata written to the driving transistor DTFT to be preserved.

[0155] Additionally, it should be noted that, in order to make the bezel of the display panel where the pixel driving circuit is located narrower, in this embodiment, the shift register units that provide signals to the pixel driving circuit can adopt a combination of single-sided driving and double-sided driving to achieve a narrow bezel. For example, the related shift register units Reset_P, Ngate1, Ngate2, Pgate, and EM in this case can achieve a left or right bezel by using double-sided driving of Pgate and single-sided driving of the remaining Reset_P, Ngate1, Ngate2, and EM. At the same time, Reset_P resets multiple times, and Ngate1 and Ngate2 have a large pulse width, so single-sided driving of Reset_P will not affect the reset and bias effects.

[0156] For example, the driving method of the shift register unit in the circuit diagram shown in Figure 4 is shown in Figure 16. As can be seen from Figure 16, the first conduction control sub-circuit and the second conduction control sub-circuit are driven by signals from different conduction control terminals, that is, the signals from the different conduction control terminals come from different shift register units. The driving method of the shift register unit in the circuit diagram shown in Figure 6 is shown in Figure 17. As can be seen from Figure 17, the first conduction control sub-circuit and the second conduction control sub-circuit are driven by signals from the same conduction control terminal, that is, the signals from the conduction control terminal come from the same shift register unit. In the implementation process, in order to further compress the bezel and save power consumption, the first switching transistor T1 and the third switching transistor T3 can share the same shift register unit, and the sixth switching transistor T6, the seventh switching transistor T7, and the eighth switching transistor T8 can share another shift register unit. The driving method of the shift register unit can be all single-sided driving, as shown in Figure 18.

[0157] The working process of the pixel driving circuit in the embodiment of this application during frame refresh is described in detail below with reference to Figures 4 and 19. Here, the frequency of the refresh frame is not specifically limited.

[0158] Timing T1 stage: Ngate1 = 1, Reset_P = 0

[0159] When the first reset signal terminal Reset_P is low, the sixth switching transistor T6 is turned on, and the first initialization voltage Vinit1 at the first initialization voltage Vinit1 terminal is supplied to the first terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6. When the second reset signal terminal Reset_P is low, the seventh switching transistor T7 is turned on, and the second initialization voltage Vinit2 at the second initialization voltage Vinit2 terminal is supplied to the anode of the light-emitting device OLED through the turned-on seventh switching transistor T7. When the third reset signal terminal Reset_P is low, the eighth switching transistor T8 is turned on, and the third initialization voltage Vinit3 at the third initialization voltage Vinit3 terminal is supplied to the first node N1 through the turned-on eighth switching transistor T8. When the second conduction control terminal Ngate1 is high, the first switching transistor T1 is turned on, and the aforementioned third initialization voltage Vinit3 at the first node N1 is supplied to the control terminal of the driving transistor DTFT through the turned-on first switching transistor T1, thereby resetting the first terminal, second terminal, and control terminal of the driving transistor DTFT, and thus putting the driving transistor DTFT into the conducting state.

[0160] Timing T2 stage: Ngate1 = 1, Ngate2 = 1, Pgate = 0

[0161] When the signal at the scan signal terminal Pgate is low, the second switching transistor T2 is turned on. The data voltage Vdata at the data voltage terminal Data is supplied to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2. Since the driving transistor DTFT is in the on state, the aforementioned data voltage Vdata is further supplied to the second terminal of the driving transistor DTFT. When the signal at the first conduction control terminal Ngate2 is high, the third switching transistor T3 is turned on. When the signal at the second conduction control terminal Ngate1 is high, the first switching transistor T1 is turned on. The aforementioned data voltage Vdata at the second terminal of the driving transistor DTFT is further supplied to the control terminal of the driving transistor DTFT via the turned-on third switching transistor T3 and first switching transistor T1, thereby realizing the writing of the data voltage Vdata of the driving transistor DTFT. It should be noted that, in order to make the driving current generated by the driving transistor DTFT more accurate, the threshold voltage of the driving transistor DTFT can also be obtained at this stage. Specifically, when the voltage at the control terminal of the driving transistor DTFT is Vdata + Vth, the driving transistor DTFT is turned off, and the threshold voltage Vth can be obtained at this time.

[0162] Furthermore, to prevent the data voltage Vdata from being completely written to the control terminal of the driving transistor DTFT when the display screen refreshes at a high frequency, the first capacitor C1, the second capacitor C2, and / or the third capacitor C3 can be used to store the data voltage Vdata during this stage. In this way, when the signal at the scan signal terminal Pgate is high and the second switching transistor T2 is turned off, the data voltage Vdata can still be written to the control terminal of the driving transistor DTFT through the first capacitor C1, the second capacitor C2, and / or the third capacitor C3.

[0163] Timing T3 stage: Reset_P = 0

[0164] To ensure that the second terminal potential of the driving transistor DTFT in the write frame and hold frame is the same under the same grayscale image before the OLED emits light, when the first reset signal terminal Reset_P is low, the sixth switching transistor T6 is turned on, and the first initialization voltage Vinit1 at the first initialization voltage Vinit1 terminal is provided to the first terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6. When the second reset signal terminal Reset_P is low, the seventh switching transistor T7 is turned on, and the second initialization voltage Vinit2 at the second initialization voltage Vinit2 terminal is provided to the anode of the OLED through the turned-on seventh switching transistor T7. When the third reset signal terminal Reset_P is low, the eighth switching transistor T8 is turned on, and the third initialization voltage Vinit3 at the third initialization voltage Vinit3 terminal is provided to the first node N1 through the turned-on eighth switching transistor T8. That is, by resetting again, the frequency switching flicker problem caused by the difference in the second terminal potential of the driving transistor DTFT in the write frame / hold frame is improved.

[0165] Timing T4 stage: EM=0

[0166] When the signal at the light-emitting control terminal EM is low, the fourth switching transistor T4 is turned on, and the first power supply terminal VDD is coupled to the first terminal of the driving transistor DTFT through the turned-on fourth switching transistor T4. When the signal at the light-emitting control terminal EM is low, the fifth switching transistor T5 is turned on, and the second terminal of the driving transistor DTFT is coupled to the anode of the light-emitting device OLED through the turned-on fifth switching transistor T5, thereby providing the driving current generated by the driving transistor DTFT to the light-emitting device OLED, realizing the lighting of the light-emitting device OLED.

[0167] The working process of the pixel driving circuit in the embodiment of this application during frame holding is described in detail below with reference to Figures 4 and 20.

[0168] Timing t1: Ngate1 = 0, Reset_P = 0

[0169] When the first reset signal terminal Reset_P is low, the sixth switching transistor T6 is turned on, and the first initialization voltage Vinit1 at the first initialization voltage terminal is supplied to the first terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6. When the second reset signal terminal Reset_P is low, the seventh switching transistor T7 is turned on, and the second initialization voltage Vinit2 at the second initialization voltage terminal is supplied to the anode of the light-emitting device OLED through the turned-on seventh switching transistor T7. When the third reset signal terminal Reset_P is low, the eighth switching transistor T8 is turned on, and the third initialization voltage Vinit3 at the third initialization voltage terminal is supplied to the first node N1 through the turned-on eighth switching transistor T8.

[0170] Timing t2 stage: Ngate2 = 1, Pgate = 0

[0171] When the signal at the scan signal terminal Pgate is low, the second switching transistor T2 is turned on. The data voltage Vdata at the data voltage terminal Data is supplied to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2. Since the driving transistor DTFT is in the on state, the aforementioned data voltage Vdata is further supplied to the second terminal of the driving transistor DTFT. When the signal at the first conduction control terminal Ngate2 is high, the third switching transistor T3 is turned on. The aforementioned data voltage Vdata at the second terminal of the driving transistor DTFT is further supplied to the first node N1 via the turned-on third switching transistor T3, controlling the driving transistor DTFT and updating the data voltage Vdata.

[0172] Timing t3 stage: Reset_P = 0

[0173] To ensure that the second terminal potential of the driving transistor DTFT in the write frame and hold frame is the same under the same grayscale image before the OLED emits light, when the first reset signal terminal Reset_P is low, the sixth switching transistor T6 is turned on, and the first initialization voltage Vinit1 at the first initialization voltage Vinit1 terminal is provided to the first terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6. When the second reset signal terminal Reset_P is low, the seventh switching transistor T7 is turned on, and the second initialization voltage Vinit2 at the second initialization voltage Vinit2 terminal is provided to the anode of the OLED through the turned-on seventh switching transistor T7. When the third reset signal terminal Reset_P is low, the eighth switching transistor T8 is turned on, and the third initialization voltage Vinit3 at the third initialization voltage Vinit3 terminal is provided to the first node N1 through the turned-on eighth switching transistor T8. That is, by resetting again, the frequency switching flicker problem caused by the difference in the second terminal potential of the driving transistor DTFT in the write frame / hold frame is improved.

[0174] Timing t4 stage: EM=0

[0175] When the signal at the light-emitting control terminal EM is low, the fourth switching transistor T4 is turned on. The first power supply terminal VDD is coupled to the first terminal of the driving transistor DTFT through the turned-on fourth switching transistor T4. When the signal at the light-emitting control terminal EM is low, the fifth switching transistor T5 is turned on. The second terminal of the driving transistor DTFT is coupled to the anode of the light-emitting device OLED through the turned-on fifth switching transistor T5, thereby providing the driving current generated by the driving transistor DTFT to the light-emitting device OLED, thus lighting up the light-emitting device OLED. It should be noted that since the data voltage Vdata has not been updated, the driving current used to light up the light-emitting device OLED in this stage is still the driving current corresponding to the previous frame of the display.

[0176] Additionally, referring to Figure 21, in this embodiment of the application, when the display panel is performing low-frequency display, the light emission control terminal EM, the first reset signal terminal Reset_P, the second reset signal terminal Reset_P, and the third reset signal terminal Reset_P still maintain high-frequency driving, while the first conduction control terminal Ngate2, the second conduction control terminal Ngate1, and the scanning signal terminal Pgate maintain low-frequency driving.

[0177] Based on the same inventive concept, this application provides a display device including the pixel driving circuit of any of the above.

[0178] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0179] Based on the same inventive concept, this application provides a driving method for a pixel driving circuit, as shown in Figure 22, including:

[0180] Step 201: First stage: The first reset sub-circuit 50 responds to the signal of the first reset signal terminal Reset_P by providing the first initialization voltage Vinit1 of the first initialization voltage Vinit1 terminal to the first terminal of the driving transistor DTFT. The second reset sub-circuit 60 responds to the signal of the second reset signal terminal Reset_P by providing the second initialization voltage Vinit2 of the second initialization voltage Vinit2 terminal to the anode of the light-emitting device OLED. The third reset sub-circuit 70 responds to the signal of the third reset signal terminal Reset_P by providing the third initialization voltage Vinit3 of the third initialization voltage Vinit3 terminal to the first node N1. The second conduction control sub-circuit 30 responds to the signal of the second conduction control terminal Ngate1 by connecting the first node N1 with the control terminal of the driving transistor DTFT.

[0181] Step 202: Second stage: Data writing sub-circuit 10 responds to the signal at scan signal terminal Pgate and provides the data voltage Vdata at data voltage terminal Data to the first terminal of driving transistor DTFT. First conduction control sub-circuit 20 responds to the signal at first conduction control terminal Ngate2 and connects the first node N1 with the second terminal of driving transistor DTFT. Second conduction control sub-circuit 30 responds to the signal at second conduction control terminal Ngate1 and connects the first node N1 with the control terminal of driving transistor DTFT.

[0182] Step 203: Third stage: In response to the signal of the first reset signal terminal Reset_P, the first reset sub-circuit 50 provides the first initialization voltage Vinit1 of the first initialization voltage Vinit1 terminal to the first terminal of the driving transistor DTFT. In response to the signal of the second reset signal terminal Reset_P, the second initialization voltage Vinit2 of the second initialization voltage Vinit2 terminal is provided to the anode of the light-emitting device OLED. In response to the signal of the third reset signal terminal Reset_P, the third initialization voltage Vinit3 of the third initialization voltage Vinit3 terminal is provided to the first node N1.

[0183] Step 204: Fourth stage: The light emission control sub-circuit 40 responds to the signal from the light emission control terminal EM and provides driving current to the light emission device OLED.

[0184] Based on the same inventive concept, this application provides a display device including the pixel driving circuit of any of the above.

[0185] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0186] Based on the same inventive concept, this application provides a driving method for a pixel driving circuit, as shown in Figure 22, including:

[0187] Step 201: First stage: The first reset sub-circuit responds to the signal at the first reset signal terminal by providing the first initialization voltage at the first initialization voltage terminal to the first terminal of the driving transistor. The second reset sub-circuit responds to the signal at the second reset signal terminal by providing the second initialization voltage at the second initialization voltage terminal to the anode of the light-emitting device. The third reset sub-circuit responds to the signal at the third reset signal terminal by providing the third initialization voltage at the third initialization voltage terminal to the first node. The second conduction control sub-circuit responds to the signal at the second conduction control terminal by connecting the first node to the control terminal of the driving transistor.

[0188] Step 202: Second stage: The data writing sub-circuit responds to the signal at the scan signal terminal and provides the data voltage at the data voltage terminal to the first terminal of the driving transistor. The first conduction control sub-circuit responds to the signal at the first conduction control terminal and connects the first node to the second terminal of the driving transistor. The second conduction control sub-circuit responds to the signal at the second conduction control terminal and connects the first node to the control terminal of the driving transistor.

[0189] Step 203: Third stage: The first reset sub-circuit responds to the signal at the first reset signal terminal by providing the first initialization voltage at the first initialization voltage terminal to the first terminal of the driving transistor; the second reset sub-circuit responds to the signal at the second reset signal terminal by providing the second initialization voltage at the second initialization voltage terminal to the anode of the light-emitting device; and the third reset sub-circuit responds to the signal at the third reset signal terminal by providing the third initialization voltage at the third initialization voltage terminal to the first node.

[0190] Step 204: Fourth stage: The light-emitting control sub-circuit responds to the signal at the light-emitting control terminal and provides driving current to the light-emitting device.

[0191] In summary, this application provides a pixel driving circuit, a display device, and a driving method. The pixel driving circuit includes: a driving transistor, a light-emitting device, a light-emitting control sub-circuit, a data writing sub-circuit, a first conduction control sub-circuit, and a second conduction control sub-circuit. The data writing sub-circuit is coupled to a first terminal of the driving transistor and configured to provide a data voltage from a data voltage terminal to the first terminal of the driving transistor in response to a signal from a scan signal terminal. The first conduction control sub-circuit is coupled to a first node and a second terminal of the driving transistor and configured to connect the first node and the second terminal of the driving transistor in response to a signal from a first conduction control terminal. The second conduction control sub-circuit is coupled to the first node and a control terminal of the driving transistor and configured to connect the first node and the control terminal of the driving transistor in response to a signal from a second conduction control terminal. The driving transistor is configured to generate a driving current based on the data voltage. The light-emitting control sub-circuit is coupled to the first terminal and the second terminal of the driving transistor and configured to provide a driving current to the light-emitting device in response to a signal from a light-emitting control terminal. In the process of realizing dynamic frequency display of the display panel, this alleviates leakage current of the display panel during high-low frequency switching, provides bias reset, and does not increase the bezel.

[0192] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program product systems. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0193] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0194] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0195] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0196] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A pixel driving circuit, wherein, include: The components include a driving transistor, a light-emitting device, a light-emitting control sub-circuit, a data writing sub-circuit, a first conduction control sub-circuit, and a second conduction control sub-circuit. The data writing sub-circuit is coupled to the first terminal of the driving transistor and is configured to provide the data voltage of the data voltage terminal to the first terminal of the driving transistor in response to the signal of the scan signal terminal. The first turn-on control sub-circuit is coupled to the first node and the second terminal of the driving transistor, and is configured to connect the first node and the second terminal of the driving transistor in response to a signal at the first turn-on control terminal; The second turn-on control sub-circuit is coupled to the first node and the control terminal of the driving transistor, and is configured to connect the first node and the control terminal of the driving transistor in response to a signal from the second turn-on control terminal. The driving transistor is configured to generate a driving current based on the data voltage; The light-emitting control sub-circuit is coupled to the first terminal and the second terminal of the driving transistor and is configured to provide the driving current to the light-emitting device in response to a signal from the light-emitting control terminal.

2. The pixel driving circuit as described in claim 1, wherein, The second conduction control sub-circuit includes: a first switching transistor; The control terminal of the first switching transistor is coupled to the second conduction control terminal, the first terminal of the first switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the first switching transistor is coupled to the first node.

3. The pixel driving circuit as described in claim 1, wherein, The data writing sub-circuit includes: a second switching transistor; The control terminal of the second switching transistor is coupled to the scan signal terminal, the first terminal of the second switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the second switching transistor is coupled to the data voltage terminal.

4. The pixel driving circuit as described in claim 1, wherein, The first conduction control sub-circuit includes: a third switching transistor; The control terminal of the third switching transistor is coupled to the first conduction control terminal, the first terminal of the third switching transistor is coupled to the first node, and the second terminal of the third switching transistor is coupled to the second terminal of the driving transistor.

5. The pixel driving circuit as described in claim 1, wherein, The light-emitting control sub-circuit includes: a fourth switching transistor and a fifth switching transistor; The control terminal of the fourth switching transistor is coupled to the light-emitting control terminal, the first terminal of the fourth switching transistor is coupled to the first power supply terminal, and the second terminal of the fourth switching transistor is coupled to the first terminal of the driving transistor. The control terminal of the fifth switching transistor is coupled to the light-emitting control terminal, the first terminal of the fifth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth switching transistor is coupled to the light-emitting device.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein, It also includes the first reset circuit; The first reset sub-circuit is coupled to the first terminal of the driving transistor and is configured to provide the first initialization voltage of the first initialization voltage terminal to the first terminal of the driving transistor in response to a signal at the first reset signal terminal.

7. The pixel driving circuit as described in claim 6, wherein, The first reset circuit includes: a sixth switching transistor; The control terminal of the sixth switching transistor is coupled to the first reset signal terminal, the first terminal of the sixth switching transistor is coupled to the first initialization voltage terminal, and the second terminal of the sixth switching transistor is coupled to the first terminal of the driving transistor.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein, It also includes a second reset circuit; The second reset sub-circuit is coupled to the anode of the light-emitting device and is configured to provide the second initialization voltage of the second initialization voltage terminal to the anode of the light-emitting device in response to a signal at the second reset signal terminal.

9. The pixel driving circuit as described in claim 8, wherein, The second reset circuit includes: a seventh switching transistor; The control terminal of the seventh switching transistor is coupled to the second reset signal terminal, the first terminal of the seventh switching transistor is coupled to the anode of the light-emitting device, and the second terminal of the seventh switching transistor is coupled to the second initialization voltage terminal.

10. The pixel driving circuit according to any one of claims 1 to 9, wherein, It also includes a third reset circuit; The third reset sub-circuit is coupled to the first node and is configured to provide the third initialization voltage of the third initialization voltage terminal to the first node in response to a signal at the third reset signal terminal.

11. The pixel driving circuit as claimed in claim 10, wherein, The third reset circuit includes: an eighth switching transistor; The control terminal of the eighth switching transistor is coupled to the third reset signal terminal, the first terminal of the eighth switching transistor is coupled to the first node, and the second terminal of the eighth switching transistor is coupled to the third initialization voltage terminal.

12. The pixel driving circuit according to any one of claims 1 to 11, wherein, It also includes: the first capacitor; The first end of the first capacitor is coupled to the first power supply terminal, and the second end of the first capacitor is coupled to the first end of the second switching transistor.

13. The pixel driving circuit according to any one of claims 1 to 12, wherein, It also includes: a second capacitor; The first end of the second capacitor is coupled to the second end of the driving transistor, and the second end of the second capacitor is coupled to the first power supply terminal.

14. The pixel driving circuit according to any one of claims 1 to 13, wherein, It also includes: a third capacitor; The first end of the third capacitor is coupled to the first power supply terminal, and the second end of the third capacitor is coupled to the first node.

15. The pixel driving circuit according to any one of claims 1 to 14, wherein, It also includes: the fourth capacitor; The first end of the fourth capacitor is coupled to the first power supply terminal, and the second end of the fourth capacitor is coupled to the control terminal of the driving transistor.

16. The pixel driving circuit according to any one of claims 1 to 15, wherein, The signal of the second turn-on control terminal is input from the shift register in the first shift register unit, and the signal of the first turn-on control terminal is input from the shift register in the second shift register unit.

17. The pixel driving circuit according to any one of claims 1 to 15, wherein, The signal at the second turn-on control terminal is input from the nth stage shift register in the third shift register unit, and the signal at the first turn-on control terminal is input from the (n+k)th stage shift register in the third shift register unit.

18. A display device, wherein, Includes the pixel driving circuit as described in any one of claims 1 to 17.

19. A driving method for a pixel driving circuit as described in any one of claims 1 to 17, wherein, include: First stage: In response to the signal at the first reset signal terminal, the first reset sub-circuit provides the first initialization voltage at the first initialization voltage terminal to the first terminal of the driving transistor; in response to the signal at the second reset signal terminal, the second initialization voltage at the second initialization voltage terminal provides the second initialization voltage at the second initialization voltage terminal to the anode of the light-emitting device; in response to the signal at the third reset signal terminal, the third initialization voltage at the third initialization voltage terminal provides the third initialization voltage at the third initialization voltage terminal to the first node; in response to the signal at the second conduction control terminal, the second conduction control sub-circuit connects the first node with the control terminal of the driving transistor. Second stage: The data writing sub-circuit responds to the signal at the scan signal terminal and provides the data voltage at the data voltage terminal to the first terminal of the driving transistor. The first conduction control sub-circuit responds to the signal at the first conduction control terminal and connects the first node to the second terminal of the driving transistor. The second conduction control sub-circuit responds to the signal at the second conduction control terminal and connects the first node to the control terminal of the driving transistor. Third stage: In response to the signal at the first reset signal terminal, the first reset sub-circuit provides the first initialization voltage at the first initialization voltage terminal to the first terminal of the driving transistor; in response to the signal at the second reset signal terminal, the second initialization voltage at the second initialization voltage terminal provides the second initialization voltage at the second initialization voltage terminal to the anode of the light-emitting device; in response to the signal at the third reset signal terminal, the third initialization voltage at the third initialization voltage terminal provides the third initialization voltage at the third initialization voltage terminal to the first node. Fourth stage: The light-emitting control sub-circuit responds to the signal from the light-emitting control terminal and provides the driving current to the light-emitting device.

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