Driving circuit, display panel and driving method

Abstract

A driving circuit, a display panel and a driving method. A driving circuit (1000) comprises a plurality of cascaded shift registers (100), wherein each shift register (100) comprises a starting signal end (10), a first output end (21) and a second output end (31), and the first output end (21) of each stage of shift register (100) except the last stage of shift register (100) is connected to a starting signal end (10) of the next stage of shift register (100). Each shift register (100) comprises: a first output unit (20), which is configured to generate, in response to a starting signal received at the starting signal end (10), a cascade signal of the starting signal end (10) that is provided to the first output end (21), so as to serve as a starting signal provided to the starting signal end (10) of the next stage of shift register (100); and a second output unit (30), which is configured to generate, in response to the starting signal received at the starting signal end (10), a driving signal provided to the second output end (31), wherein the driving signal is configured to drive a pixel circuit (200).

Description

Driving circuit, display panel and driving method

[0001] This application claims priority to Chinese Patent Application No. 202410805257.8, filed on June 20, 2024, entitled "Driving Circuit, Display Panel and Driving Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display panel technology, and more specifically, to a driving circuit, a display panel, and a driving method. Background Technology

[0003] In related technologies, the gate-on-array (GOA) circuit includes multiple shift registers. These shift registers operate in a cascaded manner, with the output signal of one stage shift register serving not only as the drive signal for the pixel circuit but also as the start signal for the next stage shift register.

[0004] The driving signal of the pixel circuit is the same as the start signal of the shift register. However, in some combination schemes of pixel circuit and GOA circuit, due to the inconsistency of materials between the pixel circuit and GOA circuit, the start signal of the shift register is difficult to use as the driving signal of the pixel circuit. The combination scheme of pixel circuit and GOA circuit is limited, and the display panel cannot give full play to the advantages of combining pixel circuit and GOA circuit. Summary of the Invention

[0005] This application provides a driving circuit, a display panel, and a driving method.

[0006] The driving circuit provided in this application includes multiple cascaded shift registers. Each shift register has a start signal terminal, a first output terminal, and a second output terminal. Except for the last stage, the first output terminal of each stage shift register is connected to the start signal terminal of the next stage shift register. The shift register includes: a first output unit, which is connected to the start signal terminal and the first output terminal respectively. The first output unit is configured to generate a cascaded signal provided to the start signal terminal of the first output terminal in response to a start signal received at the start signal terminal, so as to serve as the start signal provided to the start signal terminal of the next stage shift register; and a second output unit, which is connected to the start signal terminal and the second output terminal respectively. The second output unit is configured to generate a driving signal provided to the second output terminal in response to a start signal received at the start signal terminal. The driving signal is configured to drive a pixel circuit.

[0007] In some possible implementations, the drive signal is a first-level signal, and the start signal and the cascaded signal are both second-level signals, wherein the first level is higher than the second level.

[0008] In some possible implementations, the shift register further includes a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal. The first clock signal terminal is used to receive a first clock signal, the second clock signal terminal is used to receive a second clock signal, and the third clock signal terminal is used to receive a third clock signal. The first output unit is also connected to the first clock signal terminal and the second clock signal terminal respectively, and the first output unit is configured to generate the cascaded signal under the control of the first clock signal, the second clock signal, and the start signal. The second output unit is also connected to the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal respectively, and the second output unit is configured to output a drive signal under the control of the first clock signal, the second clock signal, the third clock signal, and the start signal. The first clock signal, the second clock signal, and the third clock signal have the same clock period, and the duration of the third clock signal being at the second level in each clock period is greater than the duration of the first clock signal being at the second level in each clock period and the duration of the second clock signal being at the second level in each clock period.

[0009] In some possible implementations, the first output unit includes: a first transistor, whose gate is connected to the first clock signal terminal and whose first electrode is connected to the start signal terminal; a second transistor, whose gate is connected to the second electrode of the first transistor and whose first electrode is connected to a signal line providing the first level; a first capacitor, whose two ends are respectively connected to the second electrode of the second transistor and the second clock signal terminal; a third transistor, whose gate is connected to the second electrode of the second transistor and whose first electrode is connected to the second clock signal terminal; a fourth transistor, whose gate is connected to the second clock signal terminal and whose first electrode is connected to the second electrode of the first transistor; a fifth transistor, whose gate is connected to the second electrode of the third transistor, whose first electrode is connected to the second electrode of the fourth transistor, and whose second electrode is connected to the first clock signal terminal; and a sixth transistor, whose gate is connected to... The first transistor has a second terminal connected to the first clock signal terminal and the second terminal connected to the second terminal of the third transistor; the seventh transistor has a gate connected to the signal line providing the second level, a first terminal connected to the second terminal of the first transistor, and the second terminal connected to the first node; the eighth transistor has a gate connected to the first node, a first terminal connected to the second clock signal terminal, and the second terminal connected to the first output terminal; a second capacitor has its two ends connected to the first node and the first output terminal respectively; the ninth transistor has a gate connected to the second terminal of the third transistor, a first terminal connected to the first output terminal, and the second terminal connected to the signal line providing the first level; the third capacitor has its two ends connected to the gate and the second terminal of the ninth transistor respectively; wherein, all transistors in the first output unit are P-type transistors.

[0010] In some possible implementations, the second output unit includes: a tenth transistor, whose gate is connected to the first node and whose first terminal is connected to the second clock signal terminal; an eleventh transistor, whose gate is connected to the second clock signal terminal and whose first terminal is connected to the second terminal of the tenth transistor; a twelfth transistor, whose gate is connected to the gate of the ninth transistor, whose first terminal is connected to the second terminal of the eleventh transistor and whose second terminal is connected to the signal line providing the first level; a thirteenth transistor, whose gate is connected to the signal line providing the second level and whose first terminal is connected to the second terminal of the tenth transistor; a fourteenth transistor, whose gate is connected to the signal line providing the second level, whose first terminal is connected to the gate of the ninth transistor and whose second terminal is connected to the second node; a fifteenth transistor, whose gate is connected to the second terminal of the thirteenth transistor, whose first terminal is connected to the third clock signal terminal and whose second terminal is connected to the second output terminal; a fourth capacitor, whose two ends are respectively connected to the gate and the second terminal of the fifteenth transistor; and a sixteenth transistor, whose gate is connected to the second node, whose first terminal is connected to the second output terminal and whose second terminal is connected to the signal line providing the second level; wherein, all transistors in the second output unit are P-type transistors.

[0011] In some possible implementations, the second output unit further includes a fifth capacitor, the two ends of which are respectively connected to the second node and the first clock signal terminal.

[0012] In some possible implementations, within each clock cycle, the period during which the first clock signal is at the second level is earlier than the period during which the second clock signal is at the second level, and the period during which the third clock signal is at the first level is within the period during which the third clock signal is at the second level.

[0013] In some possible implementations, among multiple cascaded shift registers, the first, second, and third clock signal terminals of the odd-numbered shift registers are connected to three clock signal lines in the first clock signal line group, and the first, second, and third clock signal terminals of the even-numbered shift registers are connected to three clock signal lines in the second clock signal line group. The first, second, and third clock signals provided by the first clock signal line group are different from the first, second, and third clock signals provided by the second clock signal line group.

[0014] This application also provides a display panel, which includes any of the above-described driving circuits and multiple pixel circuits, each of the pixel circuits being connected to the second output terminal of at least one of the multiple cascaded shift registers.

[0015] In some possible implementations, the pixel circuit includes an oxide thin-film transistor, and the cascaded signal is configured as a gate-on voltage signal of the oxide thin-film transistor; the transistors in the driving circuit are all low-temperature polycrystalline silicon thin-film transistors.

[0016] In some possible implementations, the pixel circuit includes multiple rows of sub-pixels, and the driving circuit includes a first driving unit and a second driving unit, wherein the first driving unit is configured to drive the odd-numbered rows of sub-pixels, and the second driving unit is configured to drive the even-numbered rows of sub-pixels.

[0017] This application also provides a driving method for any of the above-mentioned driving circuits, the method comprising: providing a start signal to the start signal terminal of the first-stage shift register in the plurality of cascaded shift registers, so that the plurality of cascaded shift registers output the driving signal stage by stage through the second output terminal. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0019] Figure 1 is a schematic diagram of the driving circuit and display panel according to an embodiment of this application;

[0020] Figure 2 is a schematic diagram of the first output unit in the shift register according to an embodiment of this application;

[0021] Figure 3 is a schematic diagram of the second output unit in the shift register according to an embodiment of this application;

[0022] Figure 4 is a schematic diagram of the first driving unit in the display panel according to an embodiment of this application;

[0023] Figure 5 is a schematic diagram of the second driving unit in the display panel according to an embodiment of this application;

[0024] Figure 6 is a timing diagram of the shift register signals according to an embodiment of this application;

[0025] Figure 7 is a timing diagram of the cascaded signals and drive signals in an embodiment of this application;

[0026] Figure 8 is a schematic diagram of the voltage change of the first node in an embodiment of this application;

[0027] Figure 9 is a schematic diagram of the voltage change of the second node in an embodiment of this application.

[0028] Key component symbols: Drive circuit 1000, shift register 100, start signal terminal 10, first output unit 20, first output terminal 21, first transistor device 22, first capacitor device 23, second output unit 30, second output terminal 31, second transistor device 32, third transistor device 33, second capacitor device 34, first clock line 40, second clock line 50, pixel circuit 200, odd row sub-pixels 210, even row sub-pixels 220, first drive unit 300, second drive unit 400, display panel 2000. Detailed Implementation

[0029] The embodiments of this application are described in detail below. These embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0030] In related technologies, the gate-on-array (GOA) circuit includes multiple shift registers. These shift registers operate in a cascaded manner, with the output signal of one stage shift register serving not only as the drive signal for the pixel circuit but also as the start signal for the next stage shift register.

[0031] The driving signal of the pixel circuit is the same as the start signal of the shift register. However, in some combination schemes of pixel circuit and GOA circuit, due to the inconsistency of materials between the pixel circuit and GOA circuit, the start signal of the shift register is difficult to use as the driving signal of the pixel circuit. The combination scheme of pixel circuit and GOA circuit is limited, and the display panel cannot give full play to the advantages of combining pixel circuit and GOA circuit.

[0032] For example, oxide pixel circuits offer advantages such as low leakage current, low hysteresis, and good large-size uniformity. However, due to the low mobility and low stability of oxide, its application in gate-on-array (GOA) circuits is not as advanced as that of low-temperature polysilicon (LTPS). Therefore, combining oxide pixel circuits with LTPS GOA circuits can be considered.

[0033] However, due to the different materials of the thin-film transistors in the Oxide pixel circuit and the LTPS GOA circuit, the cascaded signal output from the shift register of the LTPS GOA circuit is difficult to use as a driving signal to drive the Oxide pixel circuit. This limits the application of combining the Oxide pixel circuit and the LTPS GOA circuit and makes it difficult to fully utilize the advantages of combining the Oxide pixel circuit and the LTPS GOA circuit.

[0034] Referring to FIG1, this application embodiment provides a driving circuit 1000 and a display panel 2000. The display panel 2000 includes a driving circuit 1000 and a pixel circuit 200, and the driving circuit 1000 is configured to drive the pixel circuit 200. The driving circuit 1000 includes a plurality of cascaded shift registers 100.

[0035] This application also provides a driving method, including: acquiring a start signal of a shift register 100; generating a cascaded signal based on the start signal, and using the cascaded signal as the start signal of the next-level shift register 100; and outputting a driving signal based on the start signal to drive the pixel circuit 200. The driving method provided by this application can be implemented by the driving circuit provided by this application.

[0036] The shift register 100 includes a start signal terminal 10, a first output unit 20, and a second output unit 30. The start signal terminal 10 is configured to receive a start signal. The first output unit 20 is configured to generate a cascaded signal under the control of the start signal and serve as the start signal for the next stage shift register 100. The second output unit 30 is configured to output a drive signal under the control of the start signal, and the drive signal is configured to drive the pixel circuit 200.

[0037] The cascaded signal generated by the first output unit 20 and the driving signal provided by the second output unit 30 can be separate signals to adapt to the combination circuit of the Oxide pixel circuit and the LTPS GOA circuit, so that the driving circuit 1000 provided in this embodiment can be adapted to the Oxide pixel circuit and the LTPS GOA circuit, giving full play to the advantages of the combination of the Oxide pixel circuit and the LTPS GOA circuit, and improving the performance of the display panel 2000.

[0038] Specifically, referring to FIG2, the first output unit 20 may include a first output terminal 21, which outputs a cascaded signal in the presence of a start signal. The start signal terminal 10 may be set to signal terminal STV1, and the first output terminal 21 may be set to signal terminal Cr1.

[0039] Referring to Figure 3, the second output unit 30 may include the first output unit 20 or a portion thereof (e.g., a common transistor or signal line between the second output unit 30 and the first output unit 20). The second output unit 30 may also be configured as a unit independent of the first output unit 20. The second output unit 30 may include a second output terminal 31, which outputs a drive signal in the presence of a start signal. The second output terminal 31 may be configured as a signal terminal Gout1. Signal terminal Gout1 and signal terminal Cr1 are separate signal terminals, making the cascaded signal and the drive signal separate signals.

[0040] The driving circuit 1000 may include multiple cascaded shift registers 100. Each shift register 100 can provide a start signal to the start signal terminal 10 of the next-level shift register 100, and each shift register 100 can provide a driving signal to the pixel circuit 200 to drive the pixel circuit 200. The driving signal can be a gate driving signal or a source driving signal, and the driving signal can drive the transistors in the pixel circuit 200 to drive the corresponding pixel to work.

[0041] Shift registers GOAn and GOAn+1 can be configured as two adjacent cascaded shift registers 100, and shift register GOAn+1 can be configured as the next level shift register 100 after shift register GOAn.

[0042] The cascaded signal output by shift register GOAn can be provided to shift register GOAn+1, and the drive signal output by shift register GOAn can be provided to pixel circuit 200.

[0043] When the start signal is received at the start signal terminal 10 of the shift register GOAn, the first output unit 20 of the shift register GOAn can generate the corresponding cascade signal. The first output unit 20 of the shift register GOAn can send the cascade signal to the start signal terminal 10 of the next-level shift register 100. The second output unit 30 of the shift register GOAn can output the corresponding drive signal to drive the corresponding pixel of the shift register GOAn.

[0044] The shift register GOAn+1 can use the cascade signal sent by the shift register GOAn as a start signal. When the start signal terminal 10 of the shift register GOAn+1 receives the cascade signal sent by GOAn, the second output unit 30 of the shift register GOAn+1 can output the corresponding drive signal to drive the pixel corresponding to the shift register GOAn+1.

[0045] It is understandable that the cascade signal and the drive signal are separate signals. The cascade signal can be provided to the shift register 100 in the drive circuit 1000, and the cascade signal can be designed according to the usage requirements of the shift register 100. The drive signal can be provided to the pixel circuit 200, and the drive signal can be designed according to the usage requirements of the pixel circuit 200. The transistors in the pixel circuit 200 and the shift register 100 can use transistors of different materials, allowing the display panel 2000 to adapt to various combinations of pixel circuit 200 and shift register 100, which is beneficial for fully utilizing the advantages of these combinations.

[0046] Optionally, in some embodiments, the pixel circuit 200 includes an oxide thin-film transistor, and a cascaded signal is configured to drive the oxide thin-film transistor. The driving circuit 1000 includes a low-temperature polycrystalline silicon thin-film transistor, and a driving signal is configured to drive the low-temperature polycrystalline silicon thin-film transistor.

[0047] Specifically, the driving circuit 1000 can be configured as an LTPS GOA circuit, and the driving circuit 1000 includes a low-temperature polycrystalline silicon thin-film transistor. The pixel circuit 200 can be configured as an Oxide pixel circuit, and the Oxide pixel circuit includes an oxide thin-film transistor. Cascaded signals can drive the low-temperature polycrystalline silicon thin-film transistor to adapt to the LTPS GOA circuit, and driving signals can drive the oxide thin-film transistor to adapt to the Oxide pixel circuit.

[0048] Thus, the cascaded signal can be adapted to the LTPS GOA circuit, and the driving signal can be adapted to the Oxide pixel circuit, so that the driving circuit 1000 provided in this embodiment can be adapted to the Oxide pixel circuit and the LTPS GOA circuit, giving full play to the advantages of the combination of the Oxide pixel circuit and the LTPS GOA circuit, and improving the performance of the display panel 2000.

[0049] In some embodiments, the pixel circuit 200 includes multiple rows of sub-pixels, and the driving circuit 1000 includes a first driving unit 300 and a second driving unit 400. The first driving unit 300 is configured to drive odd-numbered row sub-pixels 210, and the second driving unit 400 is configured to drive even-numbered row sub-pixels 220.

[0050] Specifically, the odd-numbered row sub-pixels 210 can be set as the 2m-1th row sub-pixels in the pixel circuit 200, and the even-numbered row sub-pixels 220 can be set as the 2mth row sub-pixels in the pixel circuit 200, where m can be set as any positive integer greater than 1.

[0051] The first driving unit 300 may include multiple cascaded shift registers 100, each shift register 100 providing a driving signal to drive the corresponding odd-numbered row sub-pixels 210. Taking Figure 4 as an example, the first driving unit 300 may include cascaded shift registers GOA1 and GOA3. Signal terminal STV1 can be set as the start signal terminal 10 of shift register GOA1. Signal terminal Cr1 can be set as the first output terminal 21 of shift register GOA1 and the start signal terminal 10 of shift register GOA3. Signal terminal Gout1 can be set as the second output terminal 31 of shift register GOA1, and signal terminal Gout3 can be set as the second output terminal 31 of shift register GOA3.

[0052] When the start signal is connected to signal terminal STV1, signal terminal Gout1 can output a drive signal to drive the first row of sub-pixels, and signal terminal Cr1 simultaneously generates a cascade signal. When the cascade signal is connected to signal terminal Cr1, signal terminal Gout3 can output a drive signal to drive the third row of sub-pixels.

[0053] The second driving unit 400 may include multiple cascaded shift registers 100, each shift register 100 providing a driving signal to drive the corresponding even-numbered row sub-pixels 220. Taking Figure 5 as an example, the second driving unit 400 may include cascaded shift registers GOA2 and GOA4. Signal terminal STV2 can be set as the start signal terminal 10 of shift register GOA2. Signal terminal Cr2 can be set as the first output terminal 21 of shift register GOA2 and the start signal terminal 10 of shift register GOA4. Signal terminal Gout2 can be set as the second output terminal 31 of shift register GOA2, and signal terminal Gout4 can be set as the second output terminal 31 of shift register GOA4.

[0054] With the start signal connected to signal terminal STV2, signal terminal Gou2 can output a drive signal to drive the second row of sub-pixels, and signal terminal Cr2 simultaneously generates a cascade signal. With the cascade signal connected to signal terminal Cr2, signal terminal Gout4 can output a drive signal to drive the fourth row of sub-pixels.

[0055] Thus, the first driving unit 300 can drive each odd-numbered row sub-pixel 210 in sequence, and the second driving unit 400 can drive each even-numbered sub-pixel in sequence.

[0056] In some implementations, when the driving signal is at a first level, the driving signal is configured to drive the pixel circuit 200 to operate, and the start signal and cascade signal are both at a second level, with the first level being higher than the second level.

[0057] Specifically, referring to Figures 4 and 6, signal terminal STV1 is configured to receive signal stv1, and signal stv1 can be set as a start signal. Signal terminal Cr1 is configured to receive signal cr1, and signal cr1 can be set as a cascade signal. Signal terminal Gout1 is configured to receive signal gout1, and signal gout1 can be set to the level of a drive signal. The first level can be set to a high level signal VGH, and the second level can be set to a low level signal VGL. The effective levels of signals stv1 and cr1 can be set to the low level signal VGL, and the effective level of signal gout1 can be set to the high level signal VGH.

[0058] When signal stv1 is at the second level, signal gout1 can switch from the second level to the first level. Pixel circuit 200 includes an N-type oxide transistor. When signal gout1 is at the first level, signal gout1 can drive the N-type oxide transistor, at which time both signal stv1 and signal cr1 are at the second level.

[0059] When signal stv1 is at the second level, signal cr1 can switch from the first level to the second level, so that the start signal connected to the next-level shift register 100 is at the second level, thereby enabling the next-level shift register 100 to drive the pixel circuit 200 to work.

[0060] Thus, by setting the effective levels of the start signal, cascade signal, and drive signal, the drive circuit 1000 can be adapted to the Oxide pixel circuit and the LTPS GOA circuit.

[0061] In some embodiments, the drive circuit 1000 includes a first clock line 40 and a second clock line 50. The first clock line 40 is configured to receive a first clock signal. The second clock line 50 is configured to receive a second clock signal. A first output unit 20 is configured to generate a cascaded signal under the control of the first clock signal, the second clock signal, and a start signal. A second output unit 30 is configured to output a drive signal under the control of the first clock signal, the second clock signal, and the start signal.

[0062] Specifically, referring to Figures 2 and 3, the first clock line 40 can be set as clock line CLK1, and the second clock line 50 can be set as clock line CLK3. The first clock signal and the second clock signal can be used as control signals for the shift register 100. The shift register 100 can provide a drive signal at signal terminal Gout1 and a cascade signal at signal terminal Cr1 according to the first clock signal and the second clock signal.

[0063] Optionally, the first clock signal and the second clock signal can be used as common control signals for multiple cascaded shift registers 100, and each cascaded shift register 100 can provide corresponding cascaded signals and drive signals according to the first clock signal and the second clock signal.

[0064] Taking Figure 4 as an example, the first clock line 40 can be set as clock line CLK1, and the second clock line 50 can be set as clock line CLK3. The first clock signal and the second clock signal can serve as common control signals for multiple shift registers 100. Under the control of the first clock signal and the second clock signal, one shift register 100 can provide a drive signal at signal terminal Gout1 and a cascading signal at signal terminal Cr1. Under the control of the first clock signal and the second clock signal, another shift register 100 can also provide a drive signal at signal terminal Gout3 and a cascading signal at signal terminal Cr3.

[0065] Taking Figure 5 as an example, the first clock line 40 can be set as clock line CLK2, and the second clock line 50 can be set as clock line CLK4. The first clock signal and the second clock signal can serve as common control signals for multiple shift registers 100. Under the control of the first clock signal and the second clock signal, one shift register 100 can provide a drive signal at signal terminal Gout2 and a cascading signal at signal terminal Cr2. Under the control of the first clock signal and the second clock signal, another shift register 100 can also provide a drive signal at signal terminal Gout4 and a cascading signal at signal terminal Cr4.

[0066] Thus, shift register 100 can also provide cascade signals and drive signals under the control of the first clock signal and the second clock signal.

[0067] The first clock signal and the second clock signal can be set to clock signals with the same period and duty cycle. For example, the first clock signal and the second clock signal can be set to clock signals with a period of 4H, and the first clock signal and the second clock signal are at a low level VGL for 1.5H time period in each period. When the first clock signal or the second clock signal is at a low level VGL, the first output unit 20 of the shift register 100 can provide a cascaded signal.

[0068] Referring to Figure 6, the first clock signal provided by clock line CLK1 can be set to signal CLK1, the second clock signal provided by clock line CLK3 can be set to signal CLK3, the start signal provided by signal terminal STV1 can be set to signal stv1, and the cascade signal provided by signal terminal Cr1 can be set to signal cr1.

[0069] Referring to Figure 3, when signal CLK3 is at a low level (VGL), signal CLK1 is at a high level (VGH). The high level (VGH) is written to the control electrode of transistor T8, turning on transistor T8. When the transistor is on, signal cr1 is the same as signal CLK3, and signal cr1 is at a low level (VGL).

[0070] Optionally, in some embodiments, the driving circuit 1000 may further include multiple third clock signal lines, each of which is configured to provide a third clock signal to a corresponding shift register 100, and the second output unit 30 of the shift register 100 outputs a driving signal under the control of the third clock signal.

[0071] Specifically, referring to Figure 3, CK1 can be set as a third clock line. The signal terminal Gout1 can provide a drive signal based on the start signal provided by the signal terminal STV1, the first clock signal provided by the clock line CLK1, the second clock signal provided by the clock line CLK3, and the third clock signal provided by the clock line CK1.

[0072] Transistor T15 can be turned on under the control of the start signal, the first clock signal, and the second clock signal. When transistor T15 is turned on, the signal terminal Gout1 can output a third clock signal.

[0073] The third clock signal can be set to a clock signal with a period of 4H, and the third clock signal is at a high level VGH for 0.6H time period in each period. When the third clock signal is at a high level VGH, the second output unit 30 of the shift register 100 can provide a drive signal to drive the pixel circuit 200.

[0074] Referring to Figure 6, the third clock signal provided by clock line CK1 can be set as signal ck1, the start signal provided by signal terminal STV1 can be set as signal stv1, and the cascade signal provided by signal terminal Cr1 can be set as signal cr1.

[0075] Referring to Figure 3, when signal stv1 is at a low level VGL, transistor T15 can be turned on under the control of the first clock signal and the second clock signal. When transistor T15 is turned on, signal ck1 switches from a low level VGL to a high level VGH, causing signal gout to switch from a low level VGL to a high level VGH.

[0076] Referring to Figure 4, CK3 can be set as a third clock line. The signal terminal Gout3 can provide a drive signal based on the cascaded signal provided by the signal terminal Cr1, the first clock signal provided by the clock line CLK1, the second clock signal provided by the clock line CLK3, and the third clock signal provided by the clock line CK3.

[0077] Referring to Figure 5, CK2 can be configured as a third clock line. Signal terminal Gout2 can provide drive signals based on the start signal provided by signal terminal STV2, the first clock signal provided by clock line CLK2, the second clock signal provided by clock line CLK4, and the third clock signal provided by clock line CK2. CK4 can also be configured as a third clock line. Signal terminal Gout4 can provide drive signals based on the cascade signal provided by signal terminal Cr2, the first clock signal provided by clock line CLK2, the second clock signal provided by clock line CLK4, and the third clock signal provided by clock line CK4.

[0078] The implementation methods for providing drive signals at signal terminals Gout2, Gout3, and Gout4 can refer to the implementation methods for providing drive signals at signal terminal 1, and will not be elaborated here.

[0079] Referring to Figure 7, the third clock signal provided by clock line CK1 can be set to signal ck1, the third clock signal provided by clock line CK2 can be set to signal ck2, the third clock signal provided by clock line CK3 can be set to signal ck3, and the third clock signal provided by clock line CK4 can be set to signal ck4. When signal ck1 is pulled high, signal terminal Gout1 provides a drive signal to drive the first row of sub-pixels in pixel circuit 200. When signal ck2 is pulled high, signal terminal Gout2 provides a drive signal to drive the second row of sub-pixels in pixel circuit 200. When signal ck3 is pulled high, signal terminal Gout3 provides a drive signal to drive the third row of sub-pixels in pixel circuit 200. When signal ck4 is pulled high, signal terminal Gout4 provides a drive signal to drive the fourth row of sub-pixels in pixel circuit 200.

[0080] Signals CLK1, CLK2, CLK3, and CLK4 can all be set to clock signals with a period of 4H. The time difference between the pull-down of signals CLK1 and CLK2 is 1H, the time difference between the pull-down of signals CLK2 and CLK3 is 1H, and the time difference between the pull-down of signals CLK3 and CLK4 is 1H. This ensures that the cascaded signals provided by signal terminals Cr1, Cr2, Cr3, and Cr4 are 1H apart, allowing the four shift registers 100 to sequentially provide cascaded signals to the cascaded shift registers 100 according to a period of 4H.

[0081] Signals ck1, ck2, ck3, and ck4 can all be set as clock signals with a period of 4H. The time difference between the pull-up of signals ck1 and ck2, the time difference between the pull-up of signals ck2 and ck3, and the time difference between the pull-up of signals ck3 and ck4 is 1H. This ensures that the time difference between the drive signals provided by signal terminals Gout1, Gout2, Gout3, and Gout4 to drive the pixel circuit 200 is 1H. The four shift registers 100 can drive the pixel circuit 200 sequentially according to a period of 4H.

[0082] In some embodiments, the driving circuit 1000 may further include a first voltage line and a second voltage line, the first voltage line providing a high-level voltage VGH and the second voltage line providing a low-level voltage VGL. The first output unit 20 may include transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9. The first output unit 20 may also include capacitors C1, C2, and C3.

[0083] The first terminal of transistor T1 is connected to the signal terminal STV1, the control terminal of transistor T1 is connected to the clock line CLK1, the second terminal of transistor T1 is connected to the first terminal of transistor T7, the control terminal of transistor T7 is connected to the second voltage line, the second terminal of transistor T7 is connected to the control terminal of transistor T8, the first terminal of transistor T8 is connected to the clock line CLK3, the second terminal of transistor T8 is connected to the signal terminal Cr1, and capacitor C2 is connected between the second terminals of transistor T7 and transistor T8.

[0084] Transistor T3's first terminal is connected to clock line CLK3, and its control terminal is connected to the first terminal of transistor T2. Capacitor C1 is connected between the first and control terminals of transistor T3. Transistor T3's second terminal is connected to the first terminal of transistor T6. Transistor T2's second terminal is connected to the first voltage line, and its control terminal is connected to the control terminal of transistor T6. Transistor T6's second terminal is connected to clock line CLK1.

[0085] The first terminal of transistor T5 is connected to the clock line CLK1, the control terminal of transistor T5 is connected to the second terminal of transistor T3, the second terminal of transistor T5 is connected to the first terminal of transistor T4, the control terminal of transistor T4 is connected to the clock line CLK3, and the second terminal of transistor T4 is connected to the second terminal of transistor T1.

[0086] The control electrode of transistor T9 is connected to the second electrode of transistor T3, the first electrode of transistor T9 is connected to the first voltage line, the second electrode of transistor T9 is connected to the signal terminal Cr1, and capacitor C3 is connected between the control electrode and the first electrode of transistor T9.

[0087] The second output unit 30 may include transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9. The second output unit 30 may also include capacitors C1, C2, and C3. The connection relationships of transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, and capacitors C1, C2, and C3 can be referenced to those of the first output unit 20.

[0088] The second output unit may also include transistors T10, T11, T12, T13, T14, T15, and T16, and capacitors C4 and C5.

[0089] The first terminal of transistor T10 is connected to the clock line CLK3, the control terminal of transistor T10 is connected to the control terminal of transistor T8, the second terminal of transistor T10 is connected to the first terminal of transistor T11, the control terminal of transistor T11 is connected to the clock line CLK3, the second terminal of transistor T11 is connected to the first terminal of transistor T12, the control terminal of transistor T12 is connected to the control terminal of transistor T9, and the second terminal of transistor T12 is connected to the first voltage line.

[0090] The first terminal of transistor T13 is connected to the second terminal of transistor T11. The control terminal of transistor T13 is connected to the second voltage line. The second terminal of transistor T13 is connected to the control terminal of transistor T15. The first terminal of transistor T15 is connected to the clock line CK1. The second terminal of transistor T15 is connected to the signal terminal Gout1. Capacitor C4 is connected between the control terminal of transistor T15 and the second terminal of transistor T15.

[0091] The first terminal of transistor T14 is connected to the control terminal of transistor T12. The control terminal of transistor T14 is connected to the second voltage line. The second terminal of transistor T14 is connected to the control terminal of transistor T16. The first terminal of transistor T16 is connected to the first voltage line. The second terminal of transistor T16 is connected to the signal terminal Gout1. The first terminal of capacitor C5 is connected to the signal line CLK1. The second terminal of capacitor C5 is connected to the control terminal of transistor T16.

[0092] In some embodiments, the first output unit 20 includes a first transistor device 22 and a first capacitor device 23. The first terminal of the first transistor device 22 is coupled to a second clock line 50, the second terminal of the first transistor device 22 is coupled to a first output terminal 21, and the control terminal of the first transistor device 22 is coupled to a first node. The first terminal of the first capacitor device 23 is coupled to the first node, and the second terminal of the first capacitor device 23 is coupled to the first output terminal 21.

[0093] Specifically, referring to Figure 3, the first transistor device 22 can be set as transistor T8, the first capacitor device 23 can be set as capacitor C2, and the first node can be set as first node Nq.

[0094] When the control electrode of transistor T7 is written with a low level VGL, transistor T7 is turned on. When the first clock signal provided by clock line CLK1 is a low level VGL, the control electrode of transistor T1 is written with a low level VGL, causing transistor T1 to turn on.

[0095] With transistors T1 and T7 turned on, if the start signal connected to STV1 is low level VGL, the first node Nq can be written with low level VGL. When the clock signal provided by clock line CLK3 is high level VGH, transistor T8 is turned on.

[0096] When the clock signal provided by clock line CLK3 switches from high level VGH to low level VGL, capacitor C2 can stabilize the voltage difference between the control electrode and the second electrode of transistor T8, so that transistor T8 remains in the conducting state. Signal terminal Cr1 is connected to clock line CLK3, ensuring that signal terminal Cr1 can provide low level VGL.

[0097] Thus, by setting the first capacitor 23, the voltage difference between the control electrode and the second electrode of the first transistor 22 can be stabilized, ensuring that the second transistor 32 is in the conducting state when the second output unit 30 outputs the cascaded signal. The drive circuit 1000 does not need to set up a new low-level signal source, simplifying the circuit design.

[0098] In some implementations, under the control of a second clock signal, the first node is written with a third-level voltage signal, which is lower than the second level.

[0099] Specifically, referring to Figure 8, the third level can be set to a low level VGL2, where low level VGL2 is less than low level VGL. When signal CLK3 switches from high level VGH to low level VGL, the voltage written to the first node Nq is further pulled low, and the first node Nq is written to low level VGL2.

[0100] Referring to Figure 3, when transistor T8 is turned on, signal terminal Cr1 is connected to clock line CLK3, and the first node Nq can be written with a low level VGL.

[0101] When the clock signal provided by clock line CLK3 switches from high level VGH to low level VGL, signal terminal Cr1 switches from high level VGH to low level VGL. Signal terminal Cr1 can charge capacitor C2, further pulling down the voltage written to the first node Nq. At this time, the voltage written to the first node Nq is low level VGL2. Since low level VGL2 is lower than low level VGL1, transistor T8 can continue to remain in the on state.

[0102] Thus, under the control of the second clock signal, the first node can discharge the first capacitor 23 to reduce the voltage written to the first node, ensuring that the first transistor 22 is turned on. The drive circuit 1000 does not need to set up a new low-level signal source, simplifying the circuit design.

[0103] In some embodiments, the second output unit 30 includes a second transistor device 32, the control electrode of the second transistor device 32 being coupled to the first node. Under the control of the second clock signal, the first node is written with a third-level voltage signal, which is lower than the second level.

[0104] Specifically, the second transistor device 32 can be configured as transistor T10, and the first terminal of transistor T10 can be connected to the clock line CLK3. When the clock signal provided by the clock line CLK3 switches from a high level VGH to a low level VGL, the voltage written to the first node Nq is a low level VGL2. Since the low level VGL2 is less than the low level VGL1, transistor T10 can continue to remain in the on state.

[0105] Thus, under the control of the second clock signal, the first node can discharge the first capacitor 23 to reduce the voltage written to the first node, ensuring that the second transistor 32 is turned on. The drive circuit 1000 does not need to set up a new low-level signal source, simplifying the circuit design.

[0106] In some embodiments, the second output unit 30 includes a third transistor device 33 and a second capacitor device 34. The first terminal of the third transistor device 33 is configured to receive a second-level voltage signal, the second terminal of the third transistor device 33 is coupled to the second output terminal 31, and the control terminal of the third transistor device 33 is coupled to the second node. The first terminal of the second capacitor device 34 is coupled to the second node, and the second terminal of the second capacitor device 34 is coupled to the first clock line 40.

[0107] Specifically, referring to Figure 3, the third transistor device 33 can be set as transistor T16, the second capacitor device 34 can be set as capacitor C5, and the second node can be set as second node Np.

[0108] Capacitor C5 stabilizes the voltage difference between the clock line CLK1 and the voltage written to the second node Np, ensuring the on and off states of transistor T16. Specifically, when signal terminal Gout1 provides a low level VGL, the second node Np is written with a low level voltage VGL.

[0109] Thus, by setting the second capacitor 34, the voltage written to the second node can be adjusted by adjusting the first clock signal, ensuring the conduction and disconnection states of the third transistor device 33.

[0110] In some implementations, under the control of a first clock signal, a first-level voltage signal is written to the second node to control the third transistor device 33 to turn on.

[0111] When the second node Np is written with a low level VGL, transistor T16 is turned on, and the signal provided at the Gout terminal is low level VGL, at which point the pixel circuit 200 cannot be driven. When the drive signal provided at the Gout terminal is set to a high level VGH, transistor T16 is turned off, and the voltage written to the second node Np is set to a high level voltage VGH.

[0112] Referring to Figure 9, by adjusting the voltage signal provided by the clock line CLK1, it can be ensured that the second node Np is at a low level VGL when the second output unit does not drive the pixel circuit 200 to work, thereby ensuring that the signal provided by the signal terminal Gout is at a low level VGL, affecting the operation of the pixel circuit 200.

[0113] Thus, by adjusting the first clock signal, the voltage written to the second node can be adjusted, ensuring the conduction state of the third transistor device 33 and avoiding affecting the operation of the pixel circuit 200.

[0114] In the description of this specification, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, without contradiction, those skilled in the art can combine and integrate different embodiments or examples described in this specification, as well as features of different embodiments or examples.

[0115] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connections, detachable connections, or integral connections; it can include direct connections or indirect connections through an intermediate medium; and it can also include internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0116] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0117] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0118] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A drive circuit characterized by comprising: The driving circuit comprises a plurality of cascaded shift registers, the shift registers have a start signal terminal, a first output terminal and a second output terminal, the first output terminal of each shift register except the last one is connected to the start signal terminal of the next shift register, and the shift register comprises: a first output unit connected to the start signal terminal and the first output terminal respectively, the first output unit is configured to generate a cascade signal provided to the start signal terminal of the first output terminal as a start signal provided to the start signal terminal of the next shift register in response to a start signal received at the start signal terminal; and a second output unit connected to the start signal terminal and the second output terminal respectively, the second output unit is configured to generate a driving signal provided to the second output terminal in response to a start signal received at the start signal terminal, the driving signal is configured to drive the pixel circuit.

2. The drive circuit according to claim 1, characterized by The start signal and the cascade signal are both signals of a second level, and the first level is higher than the second level.

3. The drive circuit according to claim 2, characterized in that, The shift register further has a first clock signal terminal, a second clock signal terminal and a third clock signal terminal, the first clock signal terminal is used to receive a first clock signal, the second clock signal terminal is used to receive a second clock signal, and the third clock signal terminal is used to receive a third clock signal; The first output unit is further connected to the first clock signal terminal and the second clock signal terminal respectively, and the first output unit is configured to generate the cascade signal under the control of the first clock signal, the second clock signal and the start signal; The second output unit is further connected to the first clock signal terminal, the second clock signal terminal and the third clock signal terminal respectively, and the second output unit is configured to output the driving signal under the control of the first clock signal, the second clock signal, the third clock signal and the start signal; The first clock signal, the second clock signal and the third clock signal have the same clock period, and the length of time that the third clock signal is at the second level in each clock period is greater than the length of time that the first clock signal is at the second level in each clock period and the length of time that the second clock signal is at the second level in each clock period.

4. The drive circuit according to claim 3, characterized in that, The first output unit comprises: a first transistor having a gate connected to the first clock signal terminal and a first electrode connected to the start signal terminal; a second transistor having a gate connected to the second electrode of the first transistor and a first electrode connected to a signal line providing the first level; a first capacitor having two electrodes connected to the second electrode of the second transistor and the second clock signal terminal respectively; a third transistor having a gate connected to the second electrode of the second transistor and a first electrode connected to the second clock signal terminal; a fourth transistor having a gate connected to the second clock signal terminal and a first electrode connected to the second electrode of the first transistor; A fifth transistor having a gate connected to a second terminal of the third transistor, a first terminal connected to a second terminal of the fourth transistor, and a second terminal connected to the first clock signal terminal; A sixth transistor having a gate connected to a second terminal of the first transistor, a first terminal connected to the first clock signal terminal, and a second terminal connected to a second terminal of the third transistor; A seventh transistor having a gate connected to a signal terminal providing the second level, a first terminal connected to a second terminal of the first transistor, and a second terminal connected to a first node; An eighth transistor having a gate connected to the first node, a first terminal connected to the second clock signal terminal, and a second terminal connected to the first output terminal; A second capacitor having two terminals connected to the first node and the first output terminal, respectively; A ninth transistor having a gate connected to a second terminal of the third transistor, a first terminal connected to the first output terminal, and a second terminal connected to a signal terminal providing the first level; A third capacitor having two terminals connected to a gate and a second terminal of the ninth transistor, respectively; The transistors in the first output unit are P-type transistors.

5. The drive circuit according to claim 4, characterized in that, The second output unit comprises: A tenth transistor having a gate connected to the first node, a first terminal connected to the second clock signal terminal; An eleventh transistor having a gate connected to the second clock signal terminal, a first terminal connected to a second terminal of the tenth transistor; A twelfth transistor having a gate connected to a gate of the ninth transistor, a first terminal connected to a second terminal of the eleventh transistor, and a second terminal connected to a signal terminal providing the first level; A thirteenth transistor having a gate connected to a signal terminal providing the second level, a first terminal connected to a second terminal of the tenth transistor; A fourteenth transistor having a gate connected to a signal terminal providing the second level, a first terminal connected to a gate of the ninth transistor, and a second terminal connected to a second node; A fifteenth transistor having a gate connected to a second terminal of the thirteenth transistor, a first terminal connected to the third clock signal terminal, and a second terminal connected to the second output terminal; A fourth capacitor having two terminals connected to a gate and a second terminal of the fifteenth transistor, respectively; A sixteenth transistor having a gate connected to the second node, a first terminal connected to the second output terminal, and a second terminal connected to a signal terminal providing the second level; The transistors in the second output unit are P-type transistors.

6. The drive circuit according to claim 5, characterized in that, The second output unit further comprises a fifth capacitor having two terminals connected to the second node and the first clock signal terminal, respectively.

7. The drive circuit according to claim 3, characterized by In each clock cycle, the first clock signal is at the second level for a time period earlier than the second clock signal is at the second level, and the third clock signal is at the first level for a time period within the time period when the second clock signal is at the second level.

8. The drive circuit according to claim 3, characterized by In the plurality of cascaded shift registers, the first clock signal end, the second clock signal end and the third clock signal end of the odd-numbered shift registers are correspondingly connected to three clock signal lines in a first clock signal line group, and the first clock signal end, the second clock signal end and the third clock signal end of the even-numbered shift registers are correspondingly connected to three clock signal lines in a second clock signal line group, wherein the first clock signal, the second clock signal and the third clock signal provided by the first clock signal line group are different from the first clock signal, the second clock signal and the third clock signal provided by the second clock signal line group.

9. A display panel, characterized by, The display panel comprises the driving circuit and a plurality of pixel circuits according to any one of claims 1-8, and each of the pixel circuits is connected to the second output end of at least one shift register in the plurality of cascaded shift registers.

10. The display panel of claim 9, wherein, The pixel circuit comprises an oxide thin film transistor, and the cascaded signal is configured as a gate-on voltage signal of the oxide thin film transistor; and the transistors in the driving circuit are all low-temperature polysilicon thin film transistors.

11. The display panel of claim 9, wherein, The pixel circuit comprises a plurality of rows of sub-pixels, and the driving circuit comprises a first driving unit and a second driving unit, wherein the first driving unit is configured to drive the sub-pixels in odd-numbered rows, and the second driving unit is configured to drive the sub-pixels in even-numbered rows.

12. A driving method of the driving circuit according to any one of claims 1 to 8, characterized by, The method comprises: providing a start signal to a start signal end of a first shift register in the plurality of cascaded shift registers, so that the plurality of cascaded shift registers output the driving signal through the second output end step by step.

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