Control method and apparatus, and optical module

Abstract

A control method and apparatus, and an optical module. The method comprises: a transmitting end device acquiring a first data frame, and on the basis of the traffic volume of service data carried in the first data frame, or on the basis of the number of slots occupied by the service data in the first data frame, executing any one of the following: controlling Q first-type algorithm processing circuits among P first-type algorithm processing circuits to perform FEC encoding processing on the first data frame to obtain a second data frame; or controlling first-type algorithm processing circuits for A clock cycles among B clock cycles to perform FEC encoding processing on the first data frame to obtain the second data frame, wherein P, Q, B and A are each a positive integer; and the transmitting end device transmitting the second data frame. The technical solution can be applied to the field of optical communications. When the effective bandwidth in an optical module for service data transmission is relatively low, some algorithm processing circuits or algorithm processing units in the optical module can be turned off, thereby facilitating a reduction in the power consumption of the optical module and thus reducing power waste.

Description

Control methods, devices and optical modules

[0001] This application claims priority to Chinese Patent Application No. 202410782143.6, filed on June 17, 2024, entitled "Control Method, Apparatus and Optical Module", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of optical communication technology, and more specifically, to a control method, apparatus, and optical module. Background Technology

[0003] An optical transport network (OTN) is a type of transport network capable of transmitting, multiplexing, routing, and monitoring service data. In an OTN, data transmission between transmitting and receiving devices occurs in the form of optical signals. Specifically, the transmitting device maps service data to OTN frames, performs forward error correction (FEC) encoding and other algorithmic processing on the OTN frames, and then converts the resulting electrical signal into an optical signal, which is then transmitted from the optical port to the optical fiber. The receiving device receives the optical signal and performs the reverse process to obtain the service data.

[0004] In the current technological context, both the transmitting and receiving devices use fixed bandwidth (such as the bandwidth of an optical module) for algorithm processing. However, in practical applications, service data dynamically increases or decreases, and the effective bandwidth changes. In this situation, using fixed bandwidth for algorithm processing leads to unnecessary power consumption waste at both the transmitting and receiving ends.

[0005] Therefore, a control scheme that can reduce the power consumption waste of optical modules urgently needs to be developed. Summary of the Invention

[0006] This application provides a control method, apparatus, and optical module. When the effective bandwidth of the service data transmitted in the optical module decreases or there is idle time slot in the data frame, it can control the shutdown of some algorithm processing circuits or algorithm processing units in the optical module, which helps to reduce the power consumption of the optical module and thus reduce power waste.

[0007] The first aspect provides a control method that can be executed by a transmitting device or by a component of the transmitting device (such as a chip or chip system).

[0008] The method includes: acquiring a first data frame; and, based on the traffic of service data carried by the first data frame, or based on the number of time slots occupied by the service data in the first data frame, performing either of the following: controlling Q of the P first-type algorithm processing circuits to perform FEC encoding on the first data frame to obtain a second data frame; or controlling A of the B clock cycles of the first-type algorithm processing circuits to perform FEC encoding on the first data frame to obtain a second data frame; wherein P, Q, B, and A are all positive integers; and sending the second data frame.

[0009] In the above technical solution, when the traffic of service data is less than the maximum bandwidth of the optical module, or when the number of time slots occupied by the service data in the first data frame is less than the total number of time slots in the time slot period corresponding to the first data frame (i.e., there are idle time slots in the data frame), controlling part of the FEC algorithm processing circuit in the transmitting device to perform FEC encoding processing on the first data frame helps to reduce the power consumption waste of the transmitting device.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the second data frame includes flow indication information, which indicates at least one of the following required to parse the second data frame: the number q of the first type of algorithm processing circuits, or the number a of clock cycles; wherein q is greater than or equal to Q, and a is greater than or equal to A.

[0011] The first type of algorithm processing circuit can be understood as the algorithm processing circuit in the FEC processor. More specifically, the FEC processor includes an FEC encoder and an FEC decoder. In the transmitting device, the first type of algorithm processing circuit can be the circuit in the FEC encoder; in the receiving device, the first type of algorithm processing circuit can be the circuit in the FEC decoder.

[0012] In the above technical solution, the flow indication information can indicate to the receiving device the number of algorithm processing circuits or clock cycles required to parse the second data frame, which helps to reduce the power consumption waste of the receiving device when processing data frames.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the flow indication information is located at a first position in the second data frame, the first position being associated with a first processing unit or a first clock cycle, the first processing unit being an algorithm processing unit in the receiving device that includes an algorithm processing circuit that is kept on, and the first clock cycle being a clock cycle in the receiving device that is kept on.

[0014] In the above technical solution, setting the flow indication information in the algorithm processing circuit or clock cycle that is kept on at the receiving end device helps the receiving end device to obtain the flow indication information in a timely manner, thereby determining the number of algorithm processing circuits or the number of clock cycles required to process the second data frame.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: performing time slot rearrangement processing on the first data frame according to the traffic of the service data, or the number of time slots occupied by the service data in the first data frame, to obtain a third data frame and a fourth data frame, wherein the third data frame includes a first overhead area and a first payload area, wherein some or all of the time slots of the first payload area carry the service data, and all the time slots of the fourth frame carry the fill; and determining Q first-type algorithm processing circuits or A clock cycles according to the first overhead area.

[0016] In the above technical solution, by performing time slot rearrangement processing on the first data frame, the sending device can determine the traffic of the service data or the number of time slots occupied by the service data based on the first overhead area of ​​the third data frame.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, Q first-type algorithm processing circuits are disposed in N algorithm processing units, and P first-type algorithm processing circuits are disposed in M ​​algorithm processing units, where M and N are both positive integers, and the M algorithm processing units include N algorithm processing units.

[0018] For example, N algorithm processing units can be N FEC encoders.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, obtaining the first data frame includes: mapping valid data in the business data to the fifth data frame according to the traffic of the business data; and mapping the fifth data frame to the first data frame according to the bandwidth of the fifth data frame.

[0020] The above technical solution can remove invalid data (such as padding) from the business data, making the business data in the first data frame more compact. As a result, when the third data frame is obtained from the first data frame, the utilization rate of the time slots in the third data frame is higher. Compared with the data frame with a lower time slot utilization rate, the first data frame can be carried by fewer third data frames. Therefore, fewer algorithm processors are needed to process the data frames, which helps to further reduce power consumption waste.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: obtaining time slot allocation information, which indicates the occupancy of time slots of the first data frame by the service data; and determining the traffic of the service data based on the time slot allocation information.

[0022] In the above technical solution, the traffic of business data can be directly determined based on the occupation of the time slots of the first data frame by the business data. The implementation method is simple and helps to reduce the processing complexity of this control scheme.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: when it is determined that R first-type algorithm processing circuits need to be turned on so that Q first-type algorithm processing circuits perform FEC encoding processing on the first data frame, the voltage of the control power supply is increased, the power supply is used to supply power to P first-type algorithm processing circuits, where R is a positive integer and R is less than or equal to Q; and the R first-type algorithm processing circuits are turned on.

[0024] When the algorithm processing circuit needs to be turned on, the increased circuit load will cause a voltage drop. If the voltage drops below a certain threshold, it may cause abnormal circuit operation. In the above technical solution, the power supply is boosted in advance before the algorithm processing circuit is turned on, which can offset the voltage drop and thus avoid abnormal circuit operation.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: controlling the voltage of the power supply to decrease at a first moment; wherein the first moment is the moment when the R first-type algorithm processing circuits are turned on and completed, or the first moment is the moment after the second moment when the R first-type algorithm processing circuits are turned on, and the time interval between the first moment and the second moment is a first duration.

[0026] In the above technical solution, after the control power supply is boosted and the control algorithm processing circuit is turned on, the control power supply is reduced after the circuit load stabilizes, which can avoid the extra power consumption caused by long-term high voltage.

[0027] Secondly, a control method is provided, which can be executed by a receiving device or by a component of the receiving device (such as a chip or chip system).

[0028] The method includes: acquiring a second data frame; controlling q of the p first-type algorithm processing circuits to perform FEC decoding on the second data frame to obtain a first data frame; or controlling a of the b clock cycles of the first-type algorithm processing circuits to perform FEC decoding on the second data frame to obtain a first data frame; wherein p, q, b, and a are all positive integers.

[0029] In the above technical solution, when the traffic of service data is less than the maximum bandwidth of the optical module, or when the number of time slots occupied by the service data in the first data frame is less than the total number of time slots in the time slot period corresponding to the first data frame (i.e., there are idle time slots in the data frame), controlling part of the FEC algorithm processing circuit in the receiving device to perform FEC decoding processing on the first data frame helps to reduce the power consumption waste of the receiving device.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, obtaining the second data frame includes: receiving a sixth data frame; controlling t of the s second-type algorithm processing circuits to process the sixth data frame to obtain the second data frame, or controlling d of the c clock cycles of the second-type algorithm processing circuits to process the sixth data frame to obtain the second data frame; wherein the second-type algorithm processing circuits are used to perform at least one of the following processes: clock recovery, equalization, sequence detection, signal decision, phase tracking, scaling compensation, dispersion compensation, link length equalization compensation, crosstalk compensation, and laser linewidth compensation.

[0031] For example, the second type of algorithm circuit is the algorithm processing circuit in a DSP processor.

[0032] In the above technical solution, when the traffic of service data is less than the maximum bandwidth of the optical module, or when the number of time slots occupied by the service data in the first data frame is less than the total number of time slots in the time slot period corresponding to the first data frame, the DSP algorithm processing circuit of the control part is turned off, which helps to further reduce the power consumption waste of the receiving device.

[0033] In conjunction with the second aspect, in some implementations of the second aspect, the second data frame includes flow indication information, which indicates at least one of the following required to parse the second data frame: the number q of first-type algorithm processing circuits, or the number a of clock cycles; performing FEC decoding on the second data frame to obtain the first data frame includes: controlling q of the first-type algorithm processing circuits to perform FEC decoding on the second data frame to obtain the first data frame according to the flow indication information; or, controlling the first-type algorithm processing circuits in a clock cycles to perform FEC decoding on the second data frame to obtain the first data frame according to the flow indication information.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the flow indication information is located at a first position in the second data frame. The first position is associated with a first processing unit or a first clock cycle of the receiving device. The first processing unit is an algorithm processing unit that includes an algorithm processing circuit that is kept on, and the first clock cycle is a clock cycle that is kept on in the receiving device.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: when it is determined from the flow indication information that r first-type algorithm processing circuits need to be turned on so that q first-type algorithm processing circuits can perform FEC decoding processing on the second data frame, the voltage of the control power supply is increased, the power supply is used to supply power to p first-type algorithm processing circuits, where r is a positive integer and r is less than or equal to q; and the r first-type algorithm processing circuits are turned on.

[0036] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: controlling the voltage of the power supply to decrease at a third time; wherein the third time is the time when the r first-type algorithm processing circuits are turned on, or the third time is the time after the fourth time when the r first-type algorithm processing circuits are turned on, and the time interval between the third time and the fourth time is a first duration.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, q first-type algorithm processing circuits are disposed in n1 algorithm processing units, and p first-type algorithm processing circuits are disposed in m1 algorithm processing units, where m1 and n1 are both positive integers, and m1 algorithm processing units include n1 algorithm processing units.

[0038] Thirdly, embodiments of this application provide a control device. This device is used to execute the method provided in the first aspect, or to execute the method provided in the second aspect. Specifically, the device may include units and / or modules for executing the method provided in the first aspect or any of the above-described implementations of the first aspect; alternatively, the device may include units and / or modules for executing the method provided in the second aspect or any of the above-described implementations of the second aspect, such as a processing module and a transceiver module.

[0039] In one implementation, the control device may include units and / or modules for performing the method provided in the first aspect or any of the above implementations of the first aspect, and is a transmitting end device. The transceiver module may be a transceiver, or an input / output interface. The processing module may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0040] Alternatively, the control device may be a chip, chip system, or circuit in the transmitting device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0041] In another implementation, the control device may include units and / or modules for performing the methods provided in the second aspect or any of the above implementations of the second aspect, serving as a receiving device. The transceiver module may be a transceiver, or an input / output interface. The processing module may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0042] Alternatively, the data transmission device may be a chip, chip system, or circuit in the receiving device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0043] Fourthly, a processor is provided for executing the methods provided in the above aspects.

[0044] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0045] Fifthly, an optical module is provided, comprising a signal processor and an optical transmitting component. The signal processor is configured to: execute the method provided in the first aspect or any of the above implementations of the first aspect to obtain a second data frame. The optical transmitting component is configured to: convert the second data frame into an optical signal and transmit the optical signal.

[0046] In a sixth aspect, an optical module is provided, comprising a signal processor and an optical transmitting component. The optical receiving component is used to receive optical signals and convert the optical signals into second data frames; the signal processor is used to: execute the method provided in the second aspect or any of the above implementations of the second aspect to demap the second data frames.

[0047] In a seventh aspect, a computer-readable storage medium is provided. This computer-readable storage medium stores program code for execution by a device, the program code including methods for performing any implementation of the first or second aspect described above.

[0048] Eighthly, a computer program product comprising instructions is provided. When the computer program product is run on a computer or processor, it causes the computer or processor to perform the method provided by any implementation of the first or second aspect described above.

[0049] Ninthly, a chip is provided. The chip includes a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided in any implementation of the first or second aspect described above.

[0050] Optionally, as one implementation, the chip also includes a memory storing computer programs or instructions, and a processor for executing the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the method provided by any of the implementations of the first or second aspect described above.

[0051] The beneficial effects of the third to ninth aspects mentioned above can be found in the descriptions of the beneficial effects in the first or second aspects, and will not be repeated here. Attached Figure Description

[0052] Figure 1 is a schematic block diagram of an optical network architecture;

[0053] Figure 2 is a schematic diagram of the hardware structure of an OTN device provided in an embodiment of this application;

[0054] Figure 3 is a schematic diagram of an optical transmission architecture according to an embodiment of this application;

[0055] Figure 4 is a schematic diagram of the hardware structure of an optical module provided in an embodiment of this application;

[0056] Figure 5 is a schematic diagram of the architecture of the transmitting device provided in an embodiment of this application;

[0057] Figure 6 is a schematic flowchart of a control method provided in an embodiment of this application;

[0058] Figure 7 is a schematic diagram of the data frame processing procedure provided in an embodiment of this application;

[0059] Figure 8 is another schematic diagram of the data frame processing process provided in the embodiments of this application;

[0060] Figure 9 is a schematic diagram of the position of the traffic level in the data frame provided in the embodiment of this application;

[0061] Figure 10 is a schematic diagram showing the correspondence between the traffic flow levels and the number of algorithm processors provided in the embodiments of this application;

[0062] Figure 11 is a schematic diagram showing the correspondence between the flow rate levels and the number of clock cycles provided in the embodiments of this application;

[0063] Figure 12 is a schematic diagram showing the correspondence between the traffic of service data and the number of processors that need to be activated according to the embodiments of this application;

[0064] Figure 13 is a schematic diagram showing the correspondence between the traffic of service data and the number of processors or clock cycles that need to be activated according to the embodiments of this application;

[0065] Figure 14 is another schematic diagram showing the correspondence between the traffic of service data and the number of processors or clock cycles that need to be activated according to the embodiments of this application;

[0066] Figure 15 is another schematic diagram showing the correspondence between the traffic of service data and the number of clock cycles that need to be activated according to the embodiments of this application;

[0067] Figure 16 is a schematic flowchart of a method for controlling power supply voltage boosting and / or voltage bucking provided in an embodiment of this application;

[0068] Figure 17 is another schematic flowchart of the control method provided in the embodiments of this application;

[0069] Figure 18 is a schematic block diagram of the control device provided in an embodiment of this application;

[0070] Figure 19 is a schematic block diagram of the OTN device provided in an embodiment of this application. Detailed Implementation

[0071] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0072] The embodiments of this application are applicable to optical networks, such as OTN. An OTN is typically composed of multiple devices connected by optical fibers, and can be configured into different topologies such as linear, ring, and mesh, depending on specific needs.

[0073] Figure 1 is a schematic diagram of an OTN optical network system applicable to an embodiment of this application. As shown in Figure 1, OTN 100 includes eight interconnected OTN devices 101, namely devices A to H. 102 indicates an optical fiber used to connect two devices; 103 indicates a customer service interface used to receive or transmit customer service data. As shown in Figure 1, OTN 100 is used to transmit service data for customer devices 1 to 3. Customer devices 1 to 3 can be Ethernet devices, and the service data can be Ethernet service data. The customer devices are connected to the OTN devices through the customer service interface. For example, in Figure 1, customer devices 1 to 3 are connected to OTN devices A, H, and F, respectively.

[0074] Depending on the specific needs, an OTN device may possess different functions. Generally speaking, OTN devices are categorized into optical layer devices, electrical layer devices, and hybrid optoelectronic devices. Optical layer devices refer to those capable of processing optical layer signals, such as optical amplifiers and optical add-drop multiplexers. Optical amplifiers amplify optical signals to support longer transmission distances while maintaining specific optical signal performance. Optical add-drop multiplexers perform spatial transformations on optical signals, allowing them to be output from different output ports (sometimes referred to as directions). Electrical layer devices refer to those capable of processing electrical layer signals, such as devices capable of processing OTN signals. Hybrid optoelectronic devices refer to devices capable of processing both optical and electrical layer signals. It should be noted that, depending on specific integration requirements, an OTN device can integrate multiple different functions. The technical solutions provided in this application are applicable to OTN devices with different forms and integration levels that include electrical layer functions.

[0075] Figure 2 is a schematic diagram of the hardware structure of an OTN device provided in an embodiment of this application. Exemplarily, the OTN device can be the OTN device 101 shown in Figure 1. Specifically, the OTN device may include one or more of a tributary board, a line board, and a cross-connect board, and may also include system control boards, as well as one or more of power supply, fan, and auxiliary boards. The line board can also be an optical layer processing board. Depending on specific needs, the type and number of boards included in each device may differ. For example, an OTN device acting as a core node may not have a tributary board. An OTN device acting as an edge node may have multiple tributary boards. The power supply board is used to power the OTN device and may include primary and backup power supplies. The fan board is used for heat dissipation. The auxiliary boards are used to provide auxiliary functions such as external alarms or access to external clocks. The tributary board, cross-connect board, and line board are mainly used to process the electrical layer signals of the OTN (also known as OTN frames). The tributary board is used to receive and transmit various service data. Service data can include constant bit rate (CBR) services (e.g., Synchronous Digital Hierarchy (SDH) services) and packet services (e.g., Ethernet services). Furthermore, the tributary board can include a customer-side optical module and a signal processor. The customer-side optical module is used to receive and / or transmit service data. The signal processor is used to perform mapping and demapping processing of service data to OTN frames. The signal processor can be located inside or outside the customer-side optical module. If the signal processor is a combination of multiple chips, one (or some) of the chips can be inside the customer-side optical module, while the others are outside. The cross-connect board is used to implement the switching of OTN frames, for example, to perform the switching of one or more types of OTN frames. The line board mainly implements the processing of line-side OTN frames. Specifically, the line board can include a line-side optical module and a signal processor. The line-side optical module is used to receive and / or transmit optical signals carrying OTN frames. The signal processor is used to perform multiplexing and demultiplexing, or mapping and demapping processing of line-side OTN frames. The signal processor can be located inside or outside the line-side optical module. If the signal processor is a combination of multiple chips, one (or some) of these chips may be inside the line-side optical module, while the others may be outside. The customer-side optical module or the line-side optical module can also be collectively referred to as an optical module or optical transceiver.The signal processors in the customer-side optical module or the line-side optical module can be optical digital signal processors (oDSPs) or framers, or a combination of framers and oDSPs. System control boards are used for system control. Specifically, the system control board can collect information from different boards or send control commands to the corresponding boards. Unless otherwise specified, specific components (e.g., tributary boards) can be one or more; this application does not impose any limitations.

[0076] Figure 3 illustrates an optical transmission architecture applicable to an embodiment of this application. Specifically, service data is accessed through the client side of the OTN device (e.g., a client-side optical module). The client side maps the service data to low-rate (or low-order) ODU frames and sends these low-rate ODU frames to the line side. The line side maps the low-rate ODU frames to high-rate (or high-order) OTU frames, and after processing such as FEC encoding and transmitter pre-shaping, drives a light source to emit a modulated optical signal based on the processed electrical signal. This modulated optical signal is then sent to the optical fiber network through an optical port. Upon receiving the optical signal, the OTN device at the other end of the optical fiber performs the reverse process to recover the service data.

[0077] Figure 4 is a schematic diagram of the hardware structure of an optical module provided in an embodiment of this application. The optical module may include a signal processor, an optical transmitting component, and an optical receiving component. As mentioned above, the signal processor may include a Framer or an oDSP, or a combination of a Framer and an oDSP. The optical module can be a unidirectional optical module, that is, it includes one of an optical transmitting component and an optical receiving component. The optical module can also be a bidirectional optical module, that is, it includes both an optical transmitting component and an optical receiving component.

[0078] Framer, also known as a service chip or physical layer (PHY) chip, is primarily used to perform OTN electrical layer encapsulation / decapsulation (or mapping / demapping). Framers encapsulate service data into OTN frames or decapsulate OTN frames to obtain service data. For example, a framer can encapsulate service data into an ODU, encapsulate a low-rate ODU into a high-rate ODU, encapsulate an ODU into a FlexO, or directly encapsulate service data into a FlexO, etc. Decapsulation is the reverse process of encapsulation.

[0079] The oDSP is used to perform digital signal processing on OTN frames generated by the Framer, or on electrical signals obtained from the optical receiving component. The oDSP performs one or more of the following processing functions: FEC, clock recovery, equalization, sequence detection, and signal decision.

[0080] FEC is an error control method that refers to pre-encoding the signal according to a certain algorithm before it is sent into the transmission channel, adding redundant data with the characteristics of the signal itself, and then decoding the received signal at the receiving end according to the corresponding algorithm to find and correct the error codes generated during transmission.

[0081] Optical transmitting module (TOSA), also known as a transmitter optical subassembly, is used to convert electrical signals into optical signals. A TOSA may include a light source, a driver chip, and a modulator. The light source can be a semiconductor laser (also known as a laser diode (LD)) or a light emitting diode (LED). The driver chip processes the electrical signals generated by the oDSP and drives the light source to emit modulated optical signals. The modulated optical signals are transmitted to the fiber optic line via an optical fiber interface.

[0082] Optical receiver assembly (ROSA), also known as a receiver optical subassembly, is used to convert optical signals into electrical signals. ROSA may include photodetectors, amplifiers, etc. The photodetector can be an avalanche photodiode (APD) or a PIN photodiode. The amplifier may include a preamplifier and a post-amplifier. After the optical signal enters from the fiber optic interface, it is converted into an electrical signal by the photodetector, and then amplified by the amplifier to output an amplified electrical signal.

[0083] It should be noted that the aforementioned service data can refer to services carried by optical transport networks or metropolitan area transport networks, such as Ethernet services, packet services, wireless backhaul services, etc. Service data can also be referred to as client signal, client-side signal, client signal, service signal, client service, client data, or client service data, etc.

[0084] It should also be noted that the OTN frames involved in this application embodiment are used to carry various service data and provide rich management and monitoring functions. OTN frames can be optical payload units (OPUs), optical transport units (ODUs), optical transport units (OTUs), flexible OTN (FlexO) frames, etc. OPUs can be OPUk, OPUcn, or OPUflex; ODUs can be ODUk, ODUcn, or ODUflex; and OTUs can be OTUk or OTUcn. Specifically, an OTU frame includes an ODU frame and OTU overhead, and an ODU frame includes an OPU frame and ODU overhead. k represents different rate levels. For example, k=1 represents 2.5 Gbit / s, k=2 represents a bit rate of 10 Gbit / s, k=3 represents a bit rate of 40 Gbit / s, k=4 represents 100 Gbit / s, and k=2e represents 10 Gbit / s. Cn represents a variable rate, specifically a positive integer multiple of 100 Gbit / s. "Flex" signifies flexibility. OTUCn, OPUCn, and ODUCn can each include n subframes. For example, ODUCn includes n ODUCs, each with a rate of approximately 100G (specifically 105,258,138.053 kbit / s). FlexO frames can also include FlexO instance frames and FlexO interface frames (e.g., FlexO-n, FlexO-ne, FlexO-x-FEC, FlexO-x-FEC-m). It should also be noted that with the development of optical transport network technology, new types of OTN frames may be defined, which will also apply to this application.

[0085] As mentioned above, under the current technological background, both the transmitting and receiving devices perform algorithm processing (such as forward error correction, clock recovery, equalization, sequence detection, signal decision, phase tracking, proportional compensation, dispersion compensation, link length compensation, crosstalk compensation, laser linewidth compensation, etc.) with a fixed bandwidth. However, in practical applications, service data dynamically increases or decreases, and its effective bandwidth (or effective traffic) changes. For example, if the optical port rate of the transmitting and receiving devices is 800G, under the current technological background, even if the service data rate is only 200G, the transmitting device still maps the 200G service data with an 800G bandwidth, loads the 200G service data into a high-speed OTU container, and then sends the high-speed OTU to the algorithm module for algorithm processing using the 800G container (as shown in Figure 5). Furthermore, the algorithm processing circuit continuously processes the high-speed OTU frame according to the 800G bandwidth and then sends the processed data frame through the optical port. Correspondingly, after receiving the optical signal, the receiving device performs the reverse process described above to obtain 200G service data. That is, the receiving device processes the optical signal using an algorithm based on an 800G bandwidth to obtain a high-speed OTU frame, and then performs demapping processing on the high-speed OTU frame to obtain the service data. It is evident that the algorithm processing circuits of both the receiving and transmitting devices continuously operating at an 800G bandwidth will waste a significant amount of power.

[0086] In view of this, embodiments of this application provide a control method, an optical module, and a communication system that can control the shutdown and / or startup of the algorithm processing circuit according to the actual bandwidth of the service data, thereby adjusting the actual operating bandwidth of the algorithm module and helping to reduce power consumption waste.

[0087] Figure 6 shows a schematic flowchart of a control method provided in an embodiment of this application. The method 600 shown in Figure 6 can be executed by the OTN device shown in Figure 1 or Figure 2, and more specifically, by the transmitting device. The method includes:

[0088] S610 maps business data to data frame 1.

[0089] For example, data frame 1 can be a high-speed ODU frame, ODU Cn frame, FlexO instance frame, etc., with overhead (OH) added, and after being processed by an algorithm, it can be transmitted through the optical transmission component. Alternatively, data frame 1 can also be a high-speed OTU frame, ODU Cn frame, FlexO interface frame, etc., which can be transmitted through the optical transmission component after being processed by an algorithm.

[0090] Mapping business data to data frame 1 can include any of the following:

[0091] 1) Map the business data to a low-rate ODU frame, and map the low-rate ODU frame to a high-rate ODU frame 1, that is, data frame 1 is a high-rate ODU frame 1.

[0092] 2) Map the service data to an ODUCN frame or an ODUflex frame, and then map the ODUCN frame or ODUflex frame to FlexO frame 1, i.e., data frame 1 is FlexO frame 1. FlexO frame 1 can be a FlexO instance frame or a FlexO interface frame. More specifically, the sending device can map valid data from the service data to an ODUCN frame, and then map the ODUCN frame to FlexO frame 1; or the sending device can map all the service data to an ODUCN frame, and then map the ODUCN frame to FlexO frame 1.

[0093] 3) Map the service data to FlexO frame 1, that is, data frame 1 is FlexO frame 1. More specifically, the sending device can map the valid data in the service data to FlexO frame 1, or the sending device can also map all the service data to FlexO frame 1.

[0094] 4) Map the business data to the ODUCN frame, that is, data frame 1 is the ODUCN frame.

[0095] S620: Based on the traffic of service data in data frame 1 or the number of time slots occupied by service data in data frame 1, traffic indication information is set to obtain data frame 2.

[0096] For example, data frame 1' is obtained by time slot rearrangement based on the traffic of service data in data frame 1 or the number of time slots occupied by service data in data frame 1.

[0097] The time slot reordering process involves merging time slots that do not carry data (such as padding time slots) together, and merging time slots that carry data together. It should be noted that the data carried by a data-carrying time slot can be entirely valid business data; or it can be partially valid business data, with the remaining portion being invalid padding data (such as IDLE). The reordered data frame (e.g., data frame 1') includes invalid and valid data frames. In the valid data frame, some or all time slots carry data, and the valid data frame includes overhead. In the invalid data frame, all time slots do not carry data, and the invalid data frame does not include overhead. The overhead in the valid data frame includes a time slot pattern. Based on the time slot pattern of the overhead in the valid data frame in data frame 1', data frame 1 can be reconstructed from data frame 1'. It is understood that after time slot reordering, time slots carrying data in multiple original data frames may be included in a single valid data frame, and time slots carrying data in a single original data frame may be distributed across valid data frames (e.g., included in two separate valid data frames). The controller of the transmitting device can determine whether a data frame is valid or invalid based on whether there is overhead in the data frame after the time slot rearrangement, and then determine the effective traffic of the transmitted data frames based on the number of valid data frames; or, a valid indication signal is set for the valid data frame, and the downstream circuit of the transmitting device can determine that the data frame is valid based on the valid indication signal.

[0098] Taking data frame 1 as a high-speed ODU frame 1 as an example, in some implementations, as shown in Figure 7, the transmitting device maps a low-speed ODU frame to a high-speed ODU frame 1, and then performs time slot rearrangement on the high-speed ODU frame 1 according to the time slot occupancy status, to obtain high-speed ODU frame 2. Generally, the time slots allocated to each service flow on the client side of the transmitting device in high-speed ODU frame 1 are fixed. Therefore, the effective traffic of high-speed ODU frame 1 can be determined based on the time slot occupancy status. For example, if the client-side port supports 8*100G service flow access, and only the time slots corresponding to 2*100G service flows in high-speed ODU frame 1 are occupied, then the high-speed ODU frame 2 after time slot rearrangement only needs to be processed by the processor corresponding to the 2*100G service flows. In some implementations, as shown in Figure 8, the sending device detects the actual traffic of service data. Based on the actual traffic, it maps the valid data of the service data (i.e., data other than invalid data such as padding data) to low-rate ODU frames. Simultaneously, it calculates the actual bandwidth of the low-rate ODU frames and allocates time slots for high-rate ODU frame 1 based on the actual bandwidth. That is, the low-rate ODU frames are mapped to the corresponding allocated time slots to obtain high-rate ODU frame 1. Then, high-rate ODU frame 1 undergoes time slot rearrangement to obtain high-rate ODU frame 3. The rate of high-rate ODU frame 1 is greater than or equal to the rate of high-rate ODU frame 2, and the rate of high-rate ODU frame 3 is greater than or equal to the rate of high-rate ODU frame 3.

[0099] Furthermore, the effective traffic of the data frame transmitted by the sending device can be determined based on the number of valid data frames in data frame 1'. For example, data frame 1' can include a maximum of m' sub-data frames. When all m' sub-data frames are valid data frames, the algorithm processor of the sending device operates at full bandwidth (i.e., all circuits in the algorithm processor are turned on). That is, if the traffic of each valid data frame is x, then the maximum traffic corresponding to the algorithm processor in the sending device operating at full bandwidth is m'*x. Furthermore, if data frame 1' includes n' valid data frames (n' is less than m'), then the effective traffic of the transmitted data frame is n'*x. In this case, it is not necessary for all algorithm processors or algorithm processing circuits in the sending device to be turned on. Taking Figures 7 and 8 as examples, data frame 1' includes a maximum of 4 sub-data frames, of which 2 are valid data frames and 2 are invalid data frames. Then the effective traffic of the transmitted data frame is 2*x.

[0100] The transmitting device determines the traffic level based on the effective traffic of the transmitted data frames, and then sets traffic indication information indicating the traffic level for the effective data frames in data frame 1' to obtain data frame 2. For example, as shown in FIG9(a), the traffic indication information can be periodically set in data stream 1 sent to the FEC processor. This data stream 1 includes multiple data frames, including data frame 2. A traffic indication information is set at fixed intervals in data stream 1 to indicate the traffic level of subsequent data frames. For example, for data frame 2, the traffic indication information can be set in the time slot overhead of data frame 2. In some implementations, in addition to the traffic indication information and the effective data frames in data frame 1', data frame 2 may also include other redundant information, such as redundant data to fill in so that an FEC processor can operate at full bandwidth.

[0101] In some implementations, the location of the flow indication information setting can correspond to the algorithm processor 1 or clock cycle 1 of the receiving device, so that the algorithm processor 1 or clock cycle 1 can parse data frame 2 to obtain the flow indication information. The algorithm processor 1 can be a normally active FEC decoder in the receiving device, and clock cycle 1 can be a normally active clock cycle in the receiving device. In other implementations, when the effective flow of the transmitted data frame is 0, the FEC processors in both the sending and receiving devices can be completely turned off, or one or more cyclic FEC processors in both the sending and receiving devices can be completely turned off. In this case, the location of the flow indication information setting can correspond to the algorithm processor 2 or clock cycle 2 of the receiving device. The algorithm processor 2 can be a periodically active FEC decoder in the receiving device, and clock cycle 2 can be a periodically active clock cycle in the receiving device. Here, one cyclic cycle can correspond to a fixed interval for setting the flow indication information.

[0102] For example, the relationship between the effective traffic and traffic tier of the transmitted data frame can be shown in Table 1, which uses three traffic tiers as an example for illustration.

[0103] Table 1

[0104] It should be understood that the values ​​shown in Table 1 are for illustrative purposes only. In actual implementation, more or fewer traffic tiers can be defined depending on the number of algorithm processors.

[0105] In some implementations, one or more bits can be used as flow rate indication information to indicate the flow rate level. For example, if there are three flow rate levels, two bits can be used as flow rate indication information: bit "00" represents flow rate level "1", bit "01" represents flow rate level "2", and bit "11" represents flow rate level "3". In practice, more or fewer bits can also be used as flow rate indication information to indicate the flow rate level.

[0106] In some implementations, the sending and receiving devices can pre-configure or negotiate the relationship between traffic tiers and the required algorithm processors or clock cycles. This allows the receiving device to determine the traffic tier based on traffic indication information, and then control some or all of its own algorithm processors to process the data frames. For example, taking a three-tier traffic system, Figures 10 and 11 illustrate the relationship between the algorithm processor's activation status and the traffic tiers, and the relationship between the clock cycle's activation status and the traffic tiers, respectively.

[0107] As shown in Figure 10, the receiving device includes three algorithm processors. Traffic level 3 corresponds to all three algorithm processors being enabled, traffic level 2 corresponds to two algorithm processors being enabled (e.g., algorithm processor 1 and algorithm processor 2 are enabled), and traffic level 1 corresponds to one algorithm processor being enabled (e.g., algorithm processor 1 is enabled). In some implementations, the algorithm processors shown in Figure 10 are FEC processors. The correspondence between FEC processors and DSP processors is fixed, or the relationship between the number of enabled FEC processors and the number of enabled DSP processors is fixed. In other words, once the receiving device determines which FEC processors or their number are enabled, it determines the number of DSP processors and / or DSP processors that need to be enabled.

[0108] As shown in Figure 11, one cycle of the algorithm processor in the receiving device consists of 3 clock cycles. Flow level 3 corresponds to all 3 clock cycles being active, flow level 2 corresponds to 2 clock cycles being active (e.g., clock cycles 1 and 2 are active), and flow level 1 corresponds to 1 algorithm processor being active (e.g., clock cycle 1 is active). In one cycle, the algorithm processor processes the aforementioned data frame 2; the activation of a clock cycle can be understood as the activation of the algorithm processor or algorithm processing circuit corresponding to that clock cycle.

[0109] S630, based on the traffic of service data in data frame 1 or the number of time slots occupied by service data in data frame 1, control Q of the P FEC processing circuits to execute the algorithm to obtain data frame 3; or, control A of the B clock cycles of the FEC processing circuits to execute the algorithm to obtain data frame 3.

[0110] In some implementations, the transmitting device includes M FEC encoders, P FEC processing circuits are contained within the M FEC encoders, Q FEC processing circuits are contained within the N FEC encoders, and the M FEC encoders include the N FEC encoders.

[0111] For example, the FEC encoder is used to add redundant information, enabling the receiving device to directly recover error-free data packets using this redundant information after network errors occur. Each FEC encoder can correspond to one or more DSP processors, meaning the processing result output by each FEC encoder requires further processing by one or more DSP processors; or multiple FEC encoders can correspond to one DSP processor, meaning the processing results output by multiple FEC encoders require further processing by one DSP processor. The DSP processor of the transmitting device is used for one or more processing operations such as shaping filtering, link skew pre-compensation, nonlinear pre-compensation, and x-talk crosstalk pre-compensation. In some implementations, the functions of the FEC encoder and the DSP processor can be housed in a single processor entity, with each function implemented by different algorithm processing circuits.

[0112] More specifically, based on the traffic of service data in data frame 1, or the number of time slots occupied by service data in data frame 1, time slot rearrangement is performed on data frame 1 to obtain data frame 1'. The effective traffic of the transmitted data frame is determined based on the number of valid data frames in data frame 1', and then the activation of Q FEC processing circuits or A clock cycles is determined based on the effective traffic of the transmitted data frame.

[0113] In some implementations, if data frame 1' includes n' valid data frames, each valid data frame has a flow rate (or rate of flow) of x, and each FEC processing circuit has a processing rate of y, then the number Q of FEC processing circuits that need to be activated can be greater than or equal to Alternatively, if the processing rate of each FEC encoder is z, then the number N of FEC encoders that need to be activated can be greater than or equal to z. The N FEC encoders include Q FEC processing circuits. Among them, This indicates rounding up to the nearest integer.

[0114] In some implementations, different sub-data frames in data frame 1' correspond to different clock cycles within a loop. That is, within one clock cycle, the algorithm processor processes one or more sub-data frames in data frame 1'. In different clock cycles within a loop, the transmitting device may have the same or different numbers of algorithm processors or algorithm processing circuits running (to execute algorithm processing). For example, a loop may include B clock cycles, with M algorithm processors or P algorithm processing circuits running in each of the B clock cycles, or fewer than M algorithm processors or fewer than P algorithm processing circuits running in each of the B clock cycles. Further, the transmitting device can determine the number of clock cycles to be activated based on the number of valid data frames in data frame 1'. For example, if the processing rate of the algorithm processor in each clock cycle is X, and data frame 1' includes m' sub-data frames, then when all m' sub-data frames are valid data frames (each valid data frame has a throughput of x), B clock cycles need to be activated, i.e., B = ... If data frame 1' comprises n' valid data frames, and these valid data frames are the first n' sub-data frames of data frame 1', then the number A of clock cycles that need to be activated can be greater than or equal to The A clock cycles are contained within the B clock cycles.

[0115] Furthermore, by activating the FEC encoder or FEC processing circuit, data frame 2 is subjected to FEC encoding to obtain data frame 3.

[0116] S640, send data frame 3.

[0117] For example, data frame 3 is sent to a DSP processor or DSP processing circuit. The DSP processor or DSP processing circuit further processes data frame 3 (such as shaping filtering, link length pre-compensation, nonlinear pre-compensation, x-talk crosstalk pre-compensation, or one or more other processing) to obtain data frame 4, and then sends data frame 4 to the receiving device through the optical port.

[0118] In some implementations, S630 can be executed before S620. That is, after performing FEC encoding on the valid data frames in data frame 1' to obtain data frame 2', flow indication information is set for data frame 2' to obtain data frame 3'. For example, as shown in Figure 9(b), the flow indication information can be periodically set in the data stream 2 sent to the DSP processor. This data stream 2 includes multiple data frames, including data frame 3' (or data frame 3' filled with redundant data). A flow indication information is set at fixed intervals in data stream 2, which is used to indicate the flow level of subsequent data frames. Further, data frame 3' is processed by the DSP processor or DSP processing circuit to obtain data frame 4', and data frame 4' is sent to the receiving device through the optical port. In some implementations, to ensure the security of the flow indication information in data frame 3', FEC can be set for the flow indication information, or the flow indication information can be copied and / or interleaved.

[0119] In some implementations, to maintain stable transmitted optical power and spectrum, all DSP processors or DSP processing circuits of the transmitting device need to remain on. To ensure all DSP processors or DSP processing circuits of the transmitting device are operational (i.e., performing algorithmic processing on the data frames), redundant data needs to be padded to data frame 3 or data frame 3' before being sent to the DSP processors or DSP processing circuits. The DSP processors or DSP processing circuits then process the padded data frame 3 or data frame 3' to obtain data frame 4 or data frame 4'. It is understandable that since the receiving device does not need to consider the stability of transmitted optical power and spectrum, it can control some or all of the DSP processing circuits to perform algorithmic processing on the received data frames based on the bandwidth of the transmitted data frames. Specifically, the DSP processors of the receiving device are used to perform one or more of the following processes: clock recovery, equalization, sequence detection, signal decision, phase tracking, scaling, dispersion compensation, link skew compensation, x-talk crosstalk compensation, laser linewidth compensation, matched filtering, etc. As mentioned earlier, the relationship between the flow rate level and the required DSP processing circuit (or DSP processor) can be determined based on the correspondence between the flow rate level and the FEC processing circuit or FEC encoder, which will not be elaborated here.

[0120] When the receiving device receives data frame 4 or data frame 4', it determines the flow rate level based on the flow rate indication information in data frame 4 or data frame 4'. More specifically, upon receiving data frame 4, the flow rate indication information can only be obtained after sequential processing by the DSP processor and FEC decoder; after receiving data frame 4', the flow rate indication information can be obtained through processing by the DSP processor. Then, based on the flow rate level, the number of FEC decoders (or FEC processing circuits) and / or DSP processors (or DSP processing circuits) required to perform algorithm processing is determined, and the corresponding number of FEC decoders (or FEC processing circuits) and / or DSP processors (or DSP processing circuits) are controlled to process data frame 4 or data frame 4' to obtain data frame 1.

[0121] It should be noted that when the flow rate needs to be changed, the sending device must send the new flow rate indication information earlier than the time when the new flow rate takes effect. This ensures that the receiving side has sufficient time to respond to the new flow rate (i.e., to control enough algorithm processors to process the data frame). For example, if the receiving device requires three DSP processors to process data frame 4 or data frame 4', but only two DSP processors are currently active, the new flow rate can take effect at the time when the data frame requiring processing by the third DSP processor of the receiving device is sent, or before that time. Furthermore, the sending device must send the new flow rate indication information earlier than the time when the new flow rate takes effect to ensure that the third DSP processor is active before it needs to perform processing.

[0122] To facilitate understanding of the technical solution of this application, the switching states of the corresponding algorithm processors (such as FEC processors or DSP processors) of the transmitting and receiving devices are described in detail below with reference to Figures 12 to 15. The algorithm processors shown in Figures 12 to 15 all include FEC processors and DSP processors. For the transmitting device, the FEC processor can specifically be an FEC encoder; for the receiving device, the FEC processor can specifically be an FEC decoder. The high-order OTU service flows 1 to k can be the k sub-data frames included in the aforementioned data frame 1'.

[0123] The algorithm processors of both the transmitting and receiving devices shown in Figure 12 are space-division multiplexing processors, meaning they can perform algorithmic processing on the data frames based on the effective flow control of some or all processors. As shown in Figure 12(a), in some implementations, k high-order OTU service flows are processed by rate adaptation module A and then evenly distributed to m FEC processors; the FEC processor output data is processed by rate adaptation module B and then evenly distributed to n DSP processors for processing. In other implementations, when the high-order OTU service flows and FEC processors are proportionally matched (e.g., each e high-order OTU service flow is processed by a fixed f FEC processors for FEC encoding), the high-order OTU service flows can be directly input into the FEC processors. Similarly, if the FEC processors and DSP processors are proportionally matched (e.g., the processing results of each E FEC processor are processed by F DSP processors), the processed data frames output by the FEC processors can be directly input into the DSP processors. For example, if only high-order OTU service flows 1 and 2 are valid data frames, and only FEC processors 1 and 2 are required for FEC encoding processing, then the controller controls FEC processors 3 to 2 to be turned off. It should be understood that the specific implementation for determining the number of FEC processors based on valid data frames can be found in the description in S630, and will not be repeated here. Furthermore, to maintain stable transmitted optical power and spectrum, all DSP processors of the transmitting device need to remain on. As shown in Figure 12(b), the receiving device, based on the traffic indication information carried in the data frame, determines that only DSP processor 1, DSP processor 2, FEC processor 1, and FEC processor 2 need to be turned on. It then controls other algorithm processors to be turned off and uses the already turned-on algorithm processors to process the received data frames to obtain high-order OTU service flows 1 and 2.

[0124] In one example, the flow indication information can be set through rate adaptation module A, or it can be set through rate adaptation module B. In yet another example, when the transmitting device does not include rate adaptation modules A and B, the flow indication information can also be set in the overhead of higher-order OTU service flow 1 or the overhead of higher-order OTU service flow 2 during time slot rescheduling.

[0125] The FEC processors of both the transmitting and receiving devices shown in Figure 13 are space-division processors; the DSP processors are time-division processors, meaning they can control the processing of data frames based on the effective flow of the transmitted data frames, either partially or for all clock cycles. As shown in Figure 13(a), in some implementations, k high-order OTU service flows are processed by the rate adaptation module A and then evenly distributed to m FEC processors. In other implementations, when the high-order OTU service flows and FEC processors are proportionally matched (e.g., each e high-order OTU service flow is processed by a fixed f FEC processors for FEC encoding), the high-order OTU service flows can be directly input into the FEC processors. The FEC processor output data is processed by the rate adaptation module B and then evenly distributed to n clock cycles of DSP processors for processing. For example, if only high-order OTU service flows 1 and 2 are valid data frames, and only two FEC processors (FEC processor 1 and FEC processor 2) are needed for FEC encoding, the controller controls FEC processors 3 to m to be turned off. Furthermore, to maintain stable transmitted optical power and spectrum, the DSP processors of the transmitting device need to remain on for all clock cycles. As shown in Figure 13(b), the receiving device determines, based on the flow indication information carried in the data frame, that only the DSP processors for cycles 2 and n, FEC processor 1, and FEC processor 2 need to be on. It then controls the DSP processors for other clock cycles to be off, controls the other FEC processors to be off, and uses the already on algorithm processors to process the received data frames to obtain high-order OTU service flow 1 and high-order OTU service flow 2.

[0126] The DSP processors of both the transmitting and receiving devices shown in Figure 14 are space-division multiplexing processors; the FEC processors are time-division multiplexing processors. As shown in Figure 14(a), after the k high-order OTU service streams are processed by the rate adaptation module A, they are then evenly distributed to the FEC processors for m time slot cycles for FEC encoding. The output data of the FEC processors is processed by the rate adaptation module B, and then evenly distributed to the n DSP processors for processing. For example, if only high-order OTU service streams 1 and 2 are valid data frames, and only the FEC processors for cycles 2 and m need to perform FEC encoding, the controller controls the FEC processors for other clock cycles to be turned off. In addition, in order to maintain the stability of the transmitted optical power and spectrum, all DSP processors of the transmitting device need to be kept on. As shown in Figure 14(b), the receiving device determines that only the FEC processor, DSP processor 1 and DSP processor 2 with period 2 and period m need to be turned on according to the flow indication information carried in the data frame. Then, it controls the FEC processor with other clock cycles to be turned off, controls the other DSP processors to be turned off, and uses the already turned-on algorithm processor to process the received data frame to obtain high-order OTU service flow 1 and high-order OTU service flow 2.

[0127] The FEC processor and DSP processor of the transmitting and receiving devices shown in Figure 15 are both time-division multiplexing (TDM) processors. As shown in Figure 15(a), after the k high-order OTU service streams are processed by the rate adaptation module A, they are then evenly distributed to the FEC processors for m time slots for FEC encoding. In some implementations, the output data of the FEC processors is processed by the rate adaptation module B and then evenly distributed to the DSP processors for n time slots. In still other implementations, the m and n time slots are proportionally related (e.g., the processing result of the FEC processor for every E time slots is processed by the DSP processor for F time slots), so the processing result obtained by the FEC processor can be directly input into the DSP processor for processing. For example, if only high-order OTU service streams 1 and 2 are valid data frames, and only the FEC processors for period 2 and period m need to perform FEC encoding, the controller controls the FEC processors for other clock cycles to be turned off. In addition, in order to maintain the stability of the transmitted optical power and spectrum, all DSP processors of the transmitting device need to be kept on. As shown in Figure 15(b), the receiving device determines that only the FEC processor with period 2 and period m and the DSP processor with period 2 and period n need to be turned on according to the flow indication information carried in the data frame. Then, it controls the FEC processor and DSP processor with other clock cycles to be turned off, and uses the already turned-on algorithm processor to process the received data frame to obtain high-order OTU service flow 1 and high-order OTU service flow 2.

[0128] It should be noted that the functions of rate adaptation modules C and D shown in Figures 12 to 15 are similar to those of rate adaptation modules B and A, respectively, and are used to perform the reverse process of the processing performed by rate adaptation modules B and A. Furthermore, when a rate adaptation module in Figures 12 to 15 is represented by a dashed box, it indicates that the rate adaptation module is an optional module.

[0129] In some implementations, the aforementioned shutdown of the FEC processor and DSP processor can be understood as shutting down the algorithm processing circuits within the FEC processor and DSP processor that can be disabled. In other words, while the FEC processor and DSP processor are off, some algorithm processing circuits remain on. For example, for the DSP processor, the algorithm processing circuits used for clock recovery and some of the algorithm processing circuits used for dispersion compensation need to remain on at all times.

[0130] In some implementations, rate adaptation module A in Figures 12 to 15 only sends valid data frames to the FEC processor. For the transmitting device, when not all high-order OTU service flows 1 to k are valid, the operating clock frequency of the transmitting device's FEC processor can be reduced to decrease dynamic power consumption. Furthermore, the supply voltage can be reduced simultaneously to gain even more power savings. To maintain stable output optical power and spectrum, the DSP processor still operates at a fixed bandwidth. By increasing overhead through rate adaptation module B, the data flow output to the DSP processor can be kept constant. For the receiving device, rate adaptation module C removes the overhead added by rate adaptation module B in the transmitting direction and only transmits the data processed by FEC encoding to the FEC processor. When not all high-order OTU service flows 1 to k are valid, the operating clock frequencies of the receiving device's DSP processor and FEC processor can be reduced to decrease dynamic power consumption. Furthermore, the supply voltage can be reduced simultaneously to gain even more power savings.

[0131] When the transmitting device detects a change in flow rate, it controls the corresponding algorithm processor or clock slot to turn on or off based on the new flow rate. Similarly, when the receiving device detects a new flow rate level, it controls the corresponding algorithm processor or clock slot to turn on or off based on the flow rate level. Large-scale switching on and off of processing circuits in the algorithm processor can cause fluctuations in the power network. For example, switching from a low flow rate level to a high flow rate level increases the circuit load, causing a voltage drop, which may lead to abnormal circuit operation. Therefore, when it is necessary to activate the algorithm processor or algorithm processing circuit, it is necessary to pre-control the power supply voltage boost to offset this voltage drop and thus avoid abnormal circuit operation. Specifically, as shown in Figure 16, after the receiving device detects a new flow rate level, it can perform the following steps:

[0132] S1, a new flow rate level has been detected.

[0133] S2, determine whether to increase the gear.

[0134] For example, determine whether the new traffic level is larger than the current traffic level. If the traffic level is larger, execute S3; otherwise, execute S2'.

[0135] S3 controls voltage boosting.

[0136] For example, the number of newly activated processing circuits is determined based on the flow rate level, and the required voltage increase is determined based on the number of newly activated processing circuits. For instance, if the algorithm processing circuit in one algorithm processor needs to be activated, a voltage increase of 10 millivolts (mV) is required; if the algorithm processing circuits in two algorithm processors need to be activated, a voltage increase of 15 mV is required; and if more algorithm processing circuits in more algorithm processors need to be activated, an even greater voltage increase is required. The aforementioned algorithm processors and voltage increase amounts are for illustrative purposes only; in actual implementation, the voltage increase amount can be determined based on simulation tests or actual measurements.

[0137] S4, turn on the corresponding circuit.

[0138] In one example, the newly added algorithm processor or algorithm processing circuit corresponding to the new flow rate level is turned on.

[0139] In another example, the algorithm processor or algorithm processing circuit that controls the new clock cycle corresponding to the new flow rate level is turned on.

[0140] S5 controls voltage reduction.

[0141] For example, the voltage of the control power supply decreases after a duration of 1 after the control circuit is turned on, and / or when the algorithm processing circuit has finished turning on. For example, the duration of 1 can be 1 ms, or 2 ms, or other values.

[0142] In some implementations, when the flow rate level changes, to ensure the receiving side has sufficient time to respond to the new flow rate level, the new flow rate indication information is sent earlier than the effective time of the new flow rate level. When the flow rate level increases (i.e., the algorithm processing circuit needs to be activated), the time interval between sending the new flow rate indication information and the effective time of the new flow rate level needs to be greater than or equal to the sum of the power supply boost time and the algorithm processing circuit activation time to ensure that the algorithm processing circuit is fully activated.

[0143] S2' determines whether the gear should be downshifted.

[0144] For example, determine whether the new traffic level is smaller than the current traffic level. If the traffic level is smaller, execute S6; otherwise, it means that the traffic level has not changed, and continue to monitor whether there is a new traffic level.

[0145] S6, shut down the corresponding circuit.

[0146] It should be noted that when the transmitting device needs to enable the algorithm processing circuit, S3 and S4 can also be executed to avoid voltage drop caused by enabling the algorithm processing circuit.

[0147] Figure 17 shows another schematic flowchart of the control method provided in an embodiment of this application. This method 1700 can be executed by the OTN device 101 shown in Figure 1, or by the OTN device shown in Figure 2. More specifically, the method can be executed by a transmitting end device and a receiving end device, and the method includes:

[0148] S1710, the sending device acquires the first data frame.

[0149] For example, the first data frame can be data frame 1 in method 600, or the first data frame can also be data frame 2 in method 600.

[0150] In some implementations, S1710 can be further refined as follows: based on the traffic of the service data, map the valid data in the service data to the fifth data frame; based on the bandwidth of the fifth data frame, map the fifth data frame to the first data frame. For example, the fifth data frame can be a low-order ODU frame in S610, or it can be an ODUCN frame or an ODUflex frame in S610.

[0151] In some implementations, this method further includes: obtaining time slot occupancy information, whereby the time slot allocation information indicates the occupancy status of the service data's time slots in the first data frame; and determining the traffic of the service data based on the time slot allocation information. The time slot allocation information can be information used by network management software to control the allocation of higher-order time slots.

[0152] S1720, the transmitting device performs either of the following based on the traffic of service data carried in the first data frame, or based on the number of time slots occupied by the service data in the first data frame: controls Q of the P first-type algorithm processing circuits to perform FEC encoding on the first data frame to obtain a second data frame; or controls A of the B clock cycles of the first-type algorithm processing circuits to perform FEC encoding on the first data frame to obtain a second data frame.

[0153] For example, the P first-type algorithm processing circuits can be algorithm processing circuits in an FEC encoder, the P first-type algorithm processing circuits can include the P FEC processing circuits in method 600, and the Q first-type algorithm processing circuits can include the Q FEC processing circuits in method 600. The specific implementation of determining the Q first-type algorithm processing circuits or A clock cycles can be referred to the description in S630, and will not be repeated here. In some implementations, Q, P, A, and B are all positive integers.

[0154] In one example, taking the aforementioned data frame 2 as the first data frame, FEC encoding is performed on data frame 2 to obtain the second data frame. The second data frame can be the aforementioned data frame 3.

[0155] In another example, taking the first data frame as the aforementioned data frame 1, S1720 can be refined as follows: based on the traffic of the service data, or the number of time slots occupied by the service data in the first data frame, the first data frame is time-slot rearranged to obtain a third data frame and a fourth data frame. The third data frame includes a first overhead area and a first payload area. Part or all of the time slots in the first payload area carry service data, and all time slots in the fourth data frame carry filler. Q first-type algorithm processing circuits or A clock cycles are determined based on the first overhead area. The third data frame can be a valid data frame in the aforementioned embodiment, and the fourth data frame can be an invalid data frame in the aforementioned embodiment. Further, FEC encoding of the first data frame to obtain a second data frame can be refined as follows: time-slot rearrangement of data frame 1 is performed to obtain data frame 1', and FEC encoding of the valid data frames in data frame 1' is performed to obtain the second data frame. The second data frame can be the aforementioned data frame 2'. Further, the transmitting device can set traffic indication information in data frame 2' to obtain data frame 3'.

[0156] In some implementations, Q type I algorithm processing circuits are disposed in N algorithm processing units, and P type I algorithm processing circuits are disposed in M ​​algorithm processing units, where M and N are both positive integers, and the M algorithm processing units include N algorithm processing units. The M or N algorithm processing units can be M or N FEC encoders.

[0157] In some implementations, this method further includes: when it is determined that R first-type algorithm processing circuits need to be turned on so that Q first-type algorithm processing circuits can perform FEC encoding processing on the first data frame, the voltage of the control power supply is increased, and the power supply is used to supply power to P first-type algorithm processing circuits, where R is a positive integer and R is less than or equal to Q; and the R first-type algorithm processing circuits are turned on. A more specific implementation of the control power supply voltage increase can be found in the description of the corresponding part of Figure 16, and will not be repeated here.

[0158] It is understandable that the R first-class algorithm processing circuits are the algorithm processing circuits in the FEC encoder.

[0159] In some implementations, this method further includes: controlling the voltage of the power supply to decrease at a first moment; wherein the first moment is the moment when the R first-type algorithm processing circuits have completed their activation, or the first moment is the moment after the second moment when the R first-type algorithm processing circuits are activated, and the time interval between the first moment and the second moment is a first duration. For example, the first duration can be duration 1 in the aforementioned embodiments, which can be 1ms, 2ms, or other values.

[0160] S1730, the sending device sends a second data frame to the receiving device.

[0161] When the second data frame is data frame 3, the sending end device may send the second data frame to the receiving end device by: processing the data frame 3 after filling it with redundant data through the DSP processor, and then sending the data frame processed by the DSP processor to the receiving end device.

[0162] When the second data frame is data frame 2', the sending end device may send the second data frame to the receiving end device by: setting flow indication information for data frame 2' to obtain data frame 3', processing data frame 3' after filling redundant data by the DSP processor, and then sending the data frame processed by the DSP processor to the receiving end device.

[0163] It should be noted that when the transmitting device processes the data frame through the DSP processor, it needs to use all DSP processors or all clock cycles of the DSP processor to process the data frame in order to maintain the stability of optical power and spectrum. That is, the redundant data filled into data frame 3 or data frame 3' is to ensure that the data frame can be evenly distributed to all DSP processors of the transmitting device or to each clock cycle in a loop, thereby maintaining the stability of optical power and spectrum.

[0164] S1740, the receiving device controls q of the p first-type algorithm processing circuits to perform FEC decoding on the second data frame to obtain the first data frame; or controls a of the b clock cycles of the first-type algorithm processing circuits to perform FEC decoding on the second data frame to obtain the first data frame.

[0165] In some implementations, p, q, a, and b are all positive integers, with q greater than or equal to Q and a greater than or equal to A.

[0166] In some implementations, q first-type algorithm processing circuits are housed within n1 algorithm processing units, and p first-type algorithm processing circuits are housed within m1 algorithm processing units, where m1 and n1 are both positive integers. The m1 algorithm processing units comprise the n1 algorithm processing units. The p first-type algorithm processing circuits can be algorithm processing circuits in an FEC decoder, and the m1 algorithm processing units can be an FEC decoder.

[0167] In some implementations, the second data frame includes flow indication information, which indicates at least one of the following required to parse the second data frame: the number q of the first-type algorithm processing circuits, or the number a of clock cycles. Further, S1740 can be refined as follows: based on the flow indication information, controlling q of the first-type algorithm processing circuits to perform FEC decoding on the second data frame to obtain the first data frame; or, based on the flow indication information, controlling the first-type algorithm processing circuits for a clock cycles to perform FEC decoding on the second data frame to obtain the first data frame.

[0168] In some implementations, the flow indication information is located at a first position in the second data frame. The first position is associated with a first processing unit or a first clock cycle. The first processing unit is an algorithm processing unit in the receiving device that includes an algorithm processing circuit that is kept on. The first clock cycle is a clock cycle in the receiving device that is kept on.

[0169] In some other implementations, Q and A can be 0, and q and a can also be 0. The flow indication information is located at the second position of the second data frame, which corresponds to the periodically activated algorithm processing unit or clock cycle in the receiving device.

[0170] In some implementations, before executing S1740, the receiving device further performs the following: receiving a sixth data frame; controlling t of the s second-type algorithm processing circuits to process the sixth data frame to obtain a second data frame, or controlling d of the c clock cycles of the second-type algorithm processing circuits to process the sixth data frame to obtain a second data frame; wherein the second-type algorithm processing circuits are used to perform at least one of the following processes: clock recovery, equalization, sequence detection, signal decision, phase tracking, scaling compensation, dispersion compensation, link length compensation, crosstalk compensation, and laser linewidth compensation.

[0171] For example, the second type of algorithm processing circuit can be the algorithm processing circuit in the DSP processor, and the sixth data frame can be data frame 4 or data frame 4' in method 600. The specific implementation of determining t second type of algorithm processing circuits or d clock cycles can be referred to the description in method 600, and will not be repeated here.

[0172] In some implementations, this method further includes: when it is determined from the flow indication information that r first-type algorithm processing circuits need to be turned on so that q first-type algorithm processing circuits can perform FEC decoding processing on the second data frame, the voltage of the control power supply is increased, the power supply is used to supply power to p first-type algorithm processing circuits, where r is a positive integer and r is less than or equal to q; and the r first-type algorithm processing circuits are turned on.

[0173] In some implementations, this method further includes: controlling the voltage of the power supply to decrease at a third time point; wherein the third time point is the time when the r first-type algorithm processing circuits have completed their activation, or the third time point is the time after the fourth time point when the r first-type algorithm processing circuits are activated, and the time interval between the third time point and the fourth time point is a first duration. It can be understood that the r first-type algorithm processing circuits are the algorithm processing circuits in the FEC decoder.

[0174] The control method provided in this application, when the traffic of service data is less than the maximum bandwidth of the optical module, controls a portion of the FEC algorithm processing circuit in the transmitting device to perform FEC encoding processing on the first data frame to obtain the second data frame, which helps reduce power consumption waste in the transmitting device. Simultaneously, when the receiving device receives the second data frame, it controls a portion of the FEC algorithm processing circuit to perform FEC decoding processing on the second data frame to obtain the first data frame, which also helps reduce power consumption waste in the receiving device.

[0175] The control method provided by the embodiments of this application has been described above with reference to Figures 1 to 17. In the various embodiments of this application, unless otherwise specified or logically conflicting, the terms and / or descriptions between the various embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0176] The control device provided in the embodiments of this application is described in detail below with reference to Figures 18 and 19. It should be understood that the description of the device embodiments corresponds to the description of the method embodiments. Therefore, for content not described in detail, please refer to the method embodiments above; for the sake of brevity, some content will not be repeated.

[0177] Figure 18 is a schematic block diagram of a control device 1000 provided in an embodiment of this application. The device 1000 can be disposed in the OTN device 101 shown in Figure 1, or it can also be disposed in the OTN device shown in Figure 2. The device 1000 includes a transceiver module 1001, which can be used to implement corresponding transceiver functions. The transceiver module 1001 can also be referred to as a transceiver unit.

[0178] The device 1000 also includes a processing module 1002 (or processing unit), which can be used to implement corresponding processing functions.

[0179] Optionally, the device 1000 further includes a storage unit, which can be used to store instructions and / or data. The processing module 1002 can read the instructions and / or data in the storage unit so that the device can perform the operation of the relevant devices in the foregoing method embodiments.

[0180] The device 1000 can be used to perform the actions performed by the transmitting or receiving devices in the above method embodiments. In this case, the device 1000 can be a component of the transmitting or receiving devices. The transceiver module 1001 is used to perform the transceiver-related operations of the transmitting or receiving devices in the above method embodiments, and the processing module 1002 is used to perform the processing-related operations of the transmitting or receiving devices in the above method embodiments.

[0181] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0182] Figure 19 shows a schematic diagram of an OTN device according to an embodiment of this application. As shown in Figure 13, the OTN device 1100 includes a processor 1101 and an optical transceiver 1102. This OTN device can be applied to both transmitting and receiving devices. The OTN device shown in Figure 13 may include any of the OTN devices 101 shown in Figure 1, or the OTN device shown in Figure 13 may also include the OTN device shown in Figure 2.

[0183] When applied to a transmitting device, processor 1101 implements S1720 of method 1700 shown in FIG. 17, and optical transceiver 1102 implements S1710 and S1730 of method 1700 shown in FIG. 17. When applied to a receiving device, processor 1101 implements S1740 of method 1700 shown in FIG. 17, and optical transceiver 1102 implements S1730 of method 1700 shown in FIG. 17. During implementation, each step of the processing flow can be completed by the integrated logic circuitry in the hardware of processor 1101 or by instructions in the form of software, thus fulfilling the method executed by the transmitting or receiving device.

[0184] In this application embodiment, the processor 1101 can be a general-purpose processor, digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in this application embodiment. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software units within the processor.

[0185] Furthermore, the OTN device 1100 may include one or more processors 1101.

[0186] Optionally, the OTN device may further include a memory 1103, wherein the program code executed by the processor 1101 to implement the above-described methods may be stored in the memory 1103. The OTN device 1100 may include one or more memories 1103.

[0187] Specifically, memory 1103 can be coupled to processor 1101. The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. Alternatively, processor 1101 can operate in conjunction with memory 1103. Memory 1103 can be non-volatile memory, such as a hard disk drive (HDD), or volatile memory, such as random-access memory (RAM). Memory 1103 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. It should be noted that the apparatus shown in FIG13 can also be used to perform the method steps involved in the aforementioned variations of the embodiments shown in the figures, which will not be repeated here.

[0188] Based on the above embodiments, this application also provides an optical module, which includes a signal processor and an optical transmitting component. The signal processor is used to: execute S1720 of method 1700 to obtain a second data frame; the optical transmitting component is used to: convert the second data frame into an optical signal and transmit the optical signal. Alternatively, the optical module includes a signal processor and an optical transmitting component. The optical receiving component is used to receive the optical signal and convert the optical signal into a second data frame; the signal processor is used to: execute S1740 of method 1700 to parse the second data frame.

[0189] Based on the above embodiments, this application also provides a computer-readable storage medium. This storage medium stores a software program, which, when read and executed by one or more processors, can implement the methods provided in any one or more of the above embodiments. The computer-readable storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, random access memory, magnetic disk, or optical disk.

[0190] Based on the above embodiments, this application provides a computer program product containing instructions. When this computer program product is run on a computer or processor, it can implement the methods provided in any one or more of the above embodiments.

[0191] Based on the above embodiments, this application also provides a chip. The chip includes a processor for implementing the functions involved in any one or more of the above embodiments, such as acquiring or processing OTN frames involved in the above methods. Optionally, the chip further includes a memory for storing necessary program instructions and data executed by the processor. The chip may be composed of a single chip or may include chips and other discrete devices.

[0192] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

[0193] It should be understood that the processor mentioned in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0194] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM). For example, RAM can be used as an external cache. By way of example and not limitation, RAM can include a variety of forms, such as: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0195] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0196] In the description of the embodiments of this application, unless otherwise stated, " / " means "or", for example, A / B can mean A or B; "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. In this application, "at least one" means one or more, and "more" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0197] The use of prefixes such as "first" and "second" in this application embodiment is solely for distinguishing different descriptive objects and does not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes to distinguish descriptive objects in this application embodiment does not constitute a limitation on the described objects. The description of the described objects is found in the claims or the context of the embodiments, and the use of such prefixes should not constitute unnecessary restrictions.

[0198] Those skilled in the art will recognize that the units and steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application; such implementations should not be considered beyond the scope of protection of this application.

[0199] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of apparatus or units may be electrical, mechanical, or other forms.

[0200] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs). For example, the aforementioned available media can include, but are not limited to, various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0201] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

Claims

1. A control method characterized by, The method is applied to a sending terminal device, and comprises the following steps: obtaining a first data frame; determining, according to traffic of service data carried by the first data frame or according to a number of time slots occupied by the service data in the first data frame, any one of the following: controlling Q first-type algorithm processing circuits in P first-type algorithm processing circuits to perform forward error correction (FEC) encoding processing on the first data frame to obtain a second data frame; or controlling the first-type algorithm processing circuits in A clock cycles in B clock cycles to perform the FEC encoding processing on the first data frame to obtain the second data frame; wherein P, Q, B and A are positive integers; sending the second data frame.

2. The method of claim 1, wherein, The second data frame comprises traffic indication information, and the traffic indication information indicates at least one of the following: a number q of first-type algorithm processing circuits or a number a of clock cycles, which are required for analyzing the second data frame; wherein q is greater than or equal to Q, and a is greater than or equal to A.

3. The method of claim 2, wherein, The traffic indication information is located at a first position of the second data frame, and the first position is associated with a first processing unit or a first clock cycle, the first processing unit being an algorithm processing unit in a receiving terminal device and comprising an algorithm processing circuit that is kept on, and the first clock cycle being a clock cycle that is kept on in the receiving terminal device.

4. The method according to any one of claims 1 to 3, characterized in that, The method further comprises the following steps: performing time slot rearrangement processing on the first data frame according to traffic of the service data or according to a number of time slots occupied by the service data in the first data frame to obtain a third data frame and a fourth data frame, the third data frame comprising a first overhead area and a first payload area, and part or all time slots of the first payload area carrying the service data, and all time slots of the fourth data frame carrying padding; determining the Q first-type algorithm processing circuits or the A clock cycles according to the first overhead area.

5. The method according to any one of claims 1 to 4, characterized in that, The Q first-type algorithm processing circuits are arranged in N algorithm processing units, the P first-type algorithm processing circuits are arranged in M algorithm processing units, M and N are positive integers, and the M algorithm processing units comprise the N algorithm processing units.

6. The method according to any one of claims 1 to 5, characterized in that, The step of obtaining the first data frame comprises the following steps: mapping valid data in the service data to a fifth data frame according to traffic of the service data; mapping the fifth data frame to the first data frame according to a bandwidth of the fifth data frame.

7. The method according to any one of claims 1 to 5, characterized in that, The method further comprises the following steps: obtaining time slot allocation information, the time slot allocation information indicating an occupation of time slots of the first data frame by the service data; determining traffic of the service data according to the time slot allocation information.

8. The method according to any one of claims 1 to 7, characterized in that, The method further comprises the following steps: when it is determined that R first-type algorithm processing circuits need to be turned on so that the Q first-type algorithm processing circuits perform the FEC encoding processing on the first data frame, controlling a voltage of a power supply to increase, the power supply being configured to supply power to the P first-type algorithm processing circuits, wherein R is a positive integer and R is less than or equal to Q; controlling the R first-type algorithm processing circuits to be turned on.

9. The method of claim 8, wherein, The method further comprises the following steps: controlling the voltage of the power supply to decrease at a first time point, wherein the first time point is a time point at which the R first-type algorithm processing circuits are turned on, or the first time point is a time point after a second time point at which the R first-type algorithm processing circuits are controlled to be turned on, and a time interval between the first time point and the second time point is a first time length.

10. A control method characterized by, The method applied to a receiving end device comprises: obtaining a second data frame; controlling q first-type algorithm processing circuits in p first-type algorithm processing circuits to perform forward error correction (FEC) decoding processing on the second data frame to obtain a first data frame; or controlling the first-type algorithm processing circuits in a time interval of a time length of a to perform the FEC decoding processing on the second data frame to obtain the first data frame; wherein p, q, b, and a are positive integers.

11. The method of claim 10, wherein, The method further comprises: receiving a sixth data frame; controlling t second-type algorithm processing circuits in s second-type algorithm processing circuits to process the sixth data frame to obtain the second data frame, or controlling the second-type algorithm processing circuits in a time interval of a time length of d to process the sixth data frame to obtain the second data frame; wherein the second-type algorithm processing circuits are configured to perform at least one of the following: clock recovery, equalizer, sequence detection, signal decision, phase tracking, proportion compensation, dispersion compensation, link equalization compensation, crosstalk compensation, and laser linewidth compensation.

12. The method according to claim 10 or 11, characterized in that, The second data frame comprises traffic indication information, and the traffic indication information indicates at least one of the following: the number q of the first-type algorithm processing circuits, or the number a of the clock cycles, which are required for analyzing the second data frame. The method further comprises: controlling the q first-type algorithm processing circuits to perform the FEC decoding processing on the second data frame to obtain the first data frame according to the traffic indication information; or controlling the first-type algorithm processing circuits in the time interval of the time length of a to perform the FEC decoding processing on the second data frame to obtain the first data frame according to the traffic indication information.

13. The method of claim 12, wherein, The traffic indication information is located at a first position of the second data frame, and the first position is associated with a first processing unit or a first clock cycle of the receiving end device. The first processing unit is an algorithm processing unit including algorithm processing circuits that are kept turned on. The first clock cycle is a clock cycle that is kept turned on in the receiving end device.

14. The method according to claim 12 or 13, characterized in that, The method further comprises: controlling the voltage of a power supply to increase when it is determined according to the traffic indication information that r first-type algorithm processing circuits need to be turned on so that the q first-type algorithm processing circuits perform the FEC decoding processing on the second data frame, wherein the power supply is configured to supply power to the p first-type algorithm processing circuits, and r is a positive integer and less than or equal to q; controlling the r first-type algorithm processing circuits to be turned on.

15. The method of claim 14, wherein, The method further comprises: controlling the voltage of the power supply to decrease at a third time; wherein the third time is a time at which the r first-type algorithm processing circuits are turned on, or the third time is a time after a fourth time at which the r first-type algorithm processing circuits are controlled to be turned on, and a time interval between the third time and the fourth time is a first time length.

16. The method according to any one of claims 10 to 15, characterized in that, The q first-type algorithm processing circuits are arranged in n1 algorithm processing units, and the p first-type algorithm processing circuits are arranged in m1 algorithm processing units, m1 and n1 are positive integers, and the m1 algorithm processing units include the n1 algorithm processing units.

17. A control device characterized by comprising: The apparatus comprises a transceiver module and a processing module, and is configured to perform the method of any one of claims 1 to 9, or perform the method of any one of claims 10 to 16.

18. A control device characterized by comprising: The apparatus comprises at least one processor configured to execute computer programs or instructions stored in at least one memory, so as to cause the apparatus to perform the method of any one of claims 1 to 9, or cause the apparatus to perform the method of any one of claims 10 to 16.

19. The apparatus of claim 18, wherein, The apparatus further comprises the at least one memory.

20. An optical module characterized by comprising: The optical module comprises a signal processor and an optical transmitting component, The signal processor is configured to perform the method of any one of claims 1 to 9. The optical transmitting component is configured to convert the second data frame into an optical signal and transmit the optical signal.

21. An optical module characterized by comprising: The optical module comprises a signal processor and an optical receiving component, The optical receiving component is configured to receive an optical signal and convert the optical signal into a second data frame. The signal processor is configured to perform the method of any one of claims 10 to 16.

22. A chip, characterized by The chip comprises a processor and a communication interface, the communication interface is configured to transceive a data frame, and the processor is configured to perform the method of any one of claims 1 to 9, or perform the method of any one of claims 10 to 16, so as to process the data frame.

23. An optical transport network (OTN) device, comprising: The OTN device comprises the control apparatus of any one of claims 17 to 19, or comprises the optical module of claim 20 or 21, or comprises the chip of claim 22.

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