CMOS device with heterostructures and corresponding manufacturing method

Abstract

An electrical device is provided, the device comprising: an n-channel metal–oxide– semiconductor, NMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of negative charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; and a p-channel metal–oxide–semiconductor, PMOS, transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of positive charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; wherein the bodies are arranged separated, in parallel and superimposed relative to each other. The NMOS transistor and the PMOS transistor of the electrical device are connected to form a circuit for a complementary metal–oxide– semiconductor, CMOS. A method of providing an electrical device and a CMOS are also provided.

Description

[0001] CMOS DEVICE WITH HETEROSTRUCTURES AND CORRESPONDING MANUFACTURING METHOD

[0002] Technical field

[0003] The present disclosure relates to an electrical device, a method of providing an electrical device and a complementary metal-oxide-semiconductor. More specifically, the disclosure relates to an electrical device, a method of providing an electrical device configured to form a circuit for a complementary metal-oxide-semiconductor and a complementary metal-oxide-semiconductor as defined in the introductory parts of the independent claims.

[0004] Background art

[0005] Complementary CMOS (Complementary Metal-Oxide-Semiconductor) refers to a technology used for constructing integrated circuits, including microprocessors, microcontrollers, static RAM, and other digital logic circuits. The term "complementary" in this context refers to the use of both p-type and n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) in a complementary and symmetrical arrangement. To this end, the MOSFET may be understood as a functional electronic component that acts as a switch or amplifier, using the MOS structure as its gate to control current flow.

[0006] CMOS transistors are commonly formed by silicon structures. However, other material structures such as GaN-based technologies have been advancing rapidly, and there are significant research and development focused on integrating such devices with traditional CMOS processes, primarily to leverage the superior properties of GaN for high-power and high-frequency applications. GaN transistors may therefore be used for electrical devices operating at high-power and / or high frequency. Due to the large bandgap of GaN, such transistors may further operate efficiently at higher temperatures than e.g. Si transistors. Integrating GaN structures with CMOS processes may, however, increase complexity and may require advanced fabrication techniques. There is therefore still room for further improvements, for example, in terms of a more efficient charge carrier transport, switching and / or lower power consumption. To this end, efficient p-type GaN-based transistors may moreover be challenging to fabricate compared to the n-type ones, complicating the creation of complementary GaN-based logic circuits. There is also within the semiconductor industry a need for increased density of logic functions on a chip, i.e. that more transistors can be packed into a smaller area, enabling the creation of complex integrated circuits.

[0007] It is an object of the present disclosure to mitigate, alleviate or eliminate one or more of the above-identified deficiencies and disadvantages in the prior art and solve at least the above-mentioned problems and short comings. It is an objective of the present inventive concept to enable new types of efficient transistors. It is a further objective of the present inventive concept to enable power efficient electrical devices. It is a further objective of the present inventive concept to enable power efficient electrical devices allowing for an and or more controlled transport of charge carriers. It is also an objective to provide electrical devices that may operate at higher power and / or higher frequency. These and other objectives of the inventive concept are at least partly met by the invention as defined in the independent claims. Preferred embodiments are set out in the dependent claims.

[0008] In this text abbreviations of the natural elements will be used in accordance with the periodic table. For example, Al means aluminum, Ga means gallium, N means nitride, Si means silicon, and Mg means magnesium.

[0009] According to a first aspect there is provided an electrical device comprising: an n- channel metal-oxide-semiconductor, NMOS, transistor, the NMOS transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of negative charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; and a p-channel metal-oxide-semiconductor, PMOS, transistor, the PMOS transistor comprising a source, a body and a drain, wherein the body is an elongated semiconductor heterostructure configured for conduction of positive charge carriers, wherein the source and the drain are arranged on opposite distal regions of the body; wherein the bodies are arranged separated, in parallel and superimposed relative to each other, wherein the NMOS transistor and the PMOS transistor of the electrical device are connected to form a circuit for a complementary metal-oxide-semiconductor, CMOS.

[0010] An advantage may be that an electrical device is provided having an increased charge carrier transport. Put differently, the mobility of charge carriers in the respective elongated semiconductor heterostructures may be increased. Another advantage may be that the NMOS transistor and the PMOS transistor may extend and be arranged at a smaller distance from each other. The foot print of the electronic device may further be reduced. A larger density of electronic devices may thereby be provided. The controlling of the current flow through the respective charge channels formed within the elongated semiconductor heterostructures may, moreover, be controlled in a more efficient manner.

[0011] The n-channel metal-oxide-semiconductor, NMOS, transistor may be understood to as an n-channel MOSFET (NMOS), wherein the channel is formed by electrons. The negative charges conducted may be electrons.

[0012] The p-channel metal-oxide-semiconductor, PMOS, transistor may be understood to as a p-channel MOSFET (PMOS), wherein the channel is formed by holes. The positive charges conducted may be holes.

[0013] To this end, the term MOSFET may refer to a transistor structure that utilizes a MOS structure to control current flow.

[0014] The elongated semiconductor heterostructure of the NMOS transistor comprises a heterojunction configured for the conduction of negative charge carriers, the heterojunction being formed by a top layer and a bottom layer, both extending from a first end to a second end of the body. The elongated semiconductor heterostructure of the PMOS transistor comprises a heterojunction configured for the conduction of positive charges, the heterojunction being formed by a top layer and a bottom layer, both extending from a first end to a second end of the body.

[0015] An advantage may be that an interface between the top layer and the bottom layer may be created with increased accuracy. A uniform interface along the extension of the respective elongated semiconductor heterostructures may be obtained.

[0016] The top layer may, according to some examples, be referred to as a first layer. The bottom layer may according to some examples be referred to as a second layer.

[0017] The heterojunction should be construed to be formed in the interface between the adjacent top and bottom layers.

[0018] It may be understood that the source, body, and drain of the transistor may be part of the same elongated semiconductor heterostructure. However, the elongated semiconductor heterostructure may comprise other parts than the top and bottom layers.

[0019] The extension of the elongated semiconductor heterostructure may be understood to be along an axial direction. The axial direction may be perpendicular to an interface surface between the top and bottom layer. According to some examples, the axial direction may be oriented perpendicular to grow direction of the elongated semiconductor heterostructure.

[0020] The top and bottom layers are made of AIGaN with an aluminum content of 0% or higher and wherein the content of aluminum in the top layers are different to the content of aluminum in the bottom layers for each of the elongated semiconductor heterostructures. An advantage may be that an increased transport of charge carriers may be provided at the interface between the top layer and the bottom layer. A further advantage may be that the AIGaN / GaN heterojunctions formed may allow for improved injection of charge carriers and room temperature ballistic transport for complementary metal-oxide-semiconductor devices. The AIGaN / GaN structures may moreover handle higher power densities, making them more suitable for power amplifiers and high-power applications.

[0021] The AIGaN-layer and the GaN-layer may be understood to together form a heterojunction within the respective heterostructures.

[0022] The elongated semiconductor heterostructure of the NMOS transistor may be formed by a heterostructure comprising one or more AIGaN / GaN layer structures. The heterostructure may comprise an undoped GaN layer and an AIGaN layer, the AIGaN layer may being arranged on top of the GaN layer. The GaN layer may be formed by Ga polar GaN.

[0023] The one or more AIGaN / GaN layer structures may allow for higher switching frequency, higher breakdown voltage and higher power generation. A 1-dimensional electron gas, 1DEG, may be formed at or adjacent to the interface of the one or more AIGaN / GaN layer structures. An advantage may be that an improved charge carrier transport is achieved.

[0024] The elongated semiconductor heterostructure of the PMOS transistor may be formed by a heterostructure comprising one or more GaN / AIGaN layers. The heterostructure may comprise an AIGaN layer and an undoped GaN layer, the undoped layer being arranged on the AIGaN layer. The GaN layer may be formed be Ga polar GaN.

[0025] According to some embodiments a hole gas is formed at the interface between the GaN / AIGaN in the elongated semiconductor heterostructures.

[0026] An advantage may be that an improved charge carrier transport is achieved.

[0027] According to some examples, the Al content in AIGaN layer may be between 20-40 %, preferably 23-30 % for the heterostructure on the NMOS transistor.

[0028] According to some examples, the Al content in AIGaN layer between 20-40 %, preferably 23-30 % for PMOS transistor.

[0029] Each of the elongated semiconductor heterostructures has an axial length in a range of 200 to 50 nm and a largest cross section being less than 10 nm, preferably less than 5 nm.

[0030] An advantage may be that the density of electronic devices may be increased. The number of channels for charge transfer on a single device may further be increased. An advantage of having elongated semiconductor heterostructures with these dimensions may be that an electron gas and a hole gas may respectively be formed in the NMOS and PMOS transistor allowing for improved charge carrier transport. The dimensions may, moreover, provide efficient injection and transport of charge carriers in 1-dimensional electron gas (1DEG) and 1-dimensional electron hole gas (1DHG) formed within the respective elongated semiconductor heterostructures.

[0031] The transport of charge carriers may comprise ballistic transport. Put differently, 1- dimensional charge transport for complementary field effect transistors (FETs) may be provided.

[0032] In more detail, GaN as a material has a lighter effective mass for charge carriers and its high band gap blocking voltage is also beneficial for ballistic transport at room temperature.

[0033] This is in contrast to conventional devices being based on 2-dimensional electron gas (2DEG) and 2-dimensional electron hole gas (2DHG) has a 2-dimensional density of states that ?n is constant n2D(E) = The density of states, DOS, is n1D(E) = that diverges as 7T / i

[0034] E - 0 .

[0035] Due to the higher effective mass of holes in the present electrical device a complementary CMOS may be provided with 1-dimensional semiconductors forming a 1DHG. In some examples, the amount of strain polarization may be set to provide light holes with lower effective mass for 1-dimensional semiconductors.

[0036] The NMOS transistor and / or the PMOS transistor may comprise additional elongated semiconductor heterostructures for electron and hole transport respectively.

[0037] An advantage may be that the mobility for charge carrier transport may be increased by the plurality of elongated semiconductor heterostructures.

[0038] According to some examples, the number of elongated semiconductor heterostructures may differ between the NMOS transistor and the PMOS transistor. By way of example, the number of elongated semiconductor heterostructures in the PMOS transistor may be larger than the number of elongated semiconductor heterostructures in the NMOS transistor. A relatively lower mobility for hole transport than for electron transport may thereby be compensated for. A more symmetric complementary CMOS may thereby be provided. The performance of the electronic device and thereby the performance of the CMOS may be increased.

[0039] Each of the elongated semiconductor heterostructures has a thickness in the range of 1-10 nm, preferably in the range 3-5 nm.

[0040] An advantage may be that the elongated semiconductor heterostructures may efficiently create electron or hole gases in the interfaces between the layers of the heterostructure, e.g. the top and bottom layers. Put differently, thin quantum confined layers, for example of AIGaN / GaN, may efficiently create a 1DEG at the interface due to the differences in polarization and band alignment i.e. substantially restricting electrons in two dimensions and being free in a third dimension. This 1DEG may provide a higher density of electrons or holes that may be transported along the elongated semiconductor heterostructure with increased mobility. An electronic device having higher charge carrier mobility, i.e. electrons or holes, may enable improved high-speed and high-frequency applications.

[0041] In other words, an advantage may be that a 1-dimensional channel for charge carriers is provided. A one-dimensional density of states, DOS, may thereby be provided. An increased mobility for the charge carriers along the length of the channel may thereby be provided. Put differently an improved transport of charge carriers along the respective elongated semiconductor heterostructures may be achieved.

[0042] A further advantage being that the thickness of the elongated semiconductor heterostructures may be controlled, e.g. by metalorganic vapor phase epitaxy (MOVPE), with increased precision, down to the atomic level and with abrupt interfaces. An improved control for forming the heterojunctions may be achieved. An increased charge carrier mobility may thereby be achieved.

[0043] In addition, the PMOS and NMOS can be balanced to enable GaN CMOS as the mobility of the 1DHG improves beyond 2DHG with high area efficiency per CMOS logic inverter. Hence, sub band physics of AIGaN / GaN heterostructures may be used. The gate can precisely control which sub bands are occupied. Because the carriers only populate a narrow energy band, a small gate voltage can lead to a large change in carrier concentration. Turning the gate ON / OFF moves the Fermi level across sub bands. This leads to digital gate behavior which is ideal for low-power logic and THz operation.

[0044] Some possible applications in which the present invention may be used are Al accelerators where cloud computing isn't feasible i.e. "edge Al" and integrated logic for GaN RF Front-End-Modules.

[0045] According to some examples, an insulating material is arranged in between the bodies of the NMOS transistor and the PMOS transistor.

[0046] An improved electrostatic control over the charge transport within the respective transistors may be provided. The insulating material may further allow for a gate to better modulate the channel conductivity effectively.

[0047] According to some examples, the insulating material is part of a cladding, the cladding enclosing the bodies.

[0048] The insulating material may efficiently passivate surfaces of the bodies. A reduction in surface states and traps that could increase the scattering of charge carriers transported within the bodies may be obtained. An increased mobility may be achieved. The insulating material may reduce leakage currents between the bodies of the elongated semiconductor heterostructures and the surroundings, e.g. the substrate, other components or between the two elongated semiconductor heterostructures. A lower power consumption and higher device reliability may be achieved. The cladding may further offer improved thermal management. The cladding may provide mechanical support to the elongated semiconductor heterostructures.

[0049] The cladding may be arranged to extend along the axial direction of the bodies.

[0050] The enclosing may be understood as circumferentially enclosing.

[0051] By way of example, the insulating material may comprise or be formed by hafnium oxide, HfO. The insulating material may comprise or be formed by hafnium oxynitride, HfO(x)N(y).

[0052] The insulating material may comprise or be formed by Gadolinium oxide, Gd2O3.

[0053] The NMOS transistor may be arranged in relation to the PMOS transistor such that the drain of the NMOS transistor is arranged superimposed with the source of the PMOS transistor.

[0054] An advantage may be that a more compact electrical device may be provided. The contacting of the source and drain may further be simplified. A higher density of electronic devise may moreover be provided within a given area.

[0055] The drain of the NMOS transistor may alternatively be arranged superimposed with the drain of the PMOS transistor.

[0056] According to some examples, the electrical device comprises a gate for controlling the charge carriers in the NMOS transistor and the PMOS transistor, wherein the gate comprises a gate cladding structure enclosing a central portion of the bodies.

[0057] A more efficient control of the transport of charge carriers within the elongated semiconductor heterostructures may be achieved. Put differently, the modulation of the conductance of the channel between the source and drain may be improved. An improved electrostatic control over the charge transfer may further reduce short-channel effects.

[0058] The wording "a gate cladding structure enclosing" may be understood to be circumferentially enclosing. The gate cladding structure may enclose a substantial portion of the bodies of the NMOS transistor and the PMOS transistor.

[0059] The gate may be understood as a gate contact forming a contact, wherein the insulating material is arranged between the gate contact and the body. An applied bias on the gate contact may create an electric field in the body, under the electrical insulator. The applied bias may thereby control the conduction of negative charge carriers between the source and the drain, via the body. According to some examples, the gate comprises a gate layer stack structure that comprises a first layer, the first layer comprises Ti and / or Ta, a second layer arranged on the first layer, the second layer the electrical comprises Al, a third layer arranged on the second layer, the third layer the electrical comprises one or more of Ni, Ti, Pt, Pd, Mo, Re, Ir, and a fourth layer arranged on the third layer, the fourth layer the electrical comprises Au.

[0060] An advantage being that the gate layer stack structure may allow for improved work function tuning, thermal stability, and / or compatibility with the insulating material. An improved tailoring of the work functions and / or threshold voltages for controlling the carrier transport in the NMOS and PMOS transistors may be achieved. The material may further offer an improved adhesion and compatibility with the adjacent materials. An improved tuning of the resistive properties of the gate may further be provided. The quality of the ohmic contact formed may be increased.

[0061] According to some examples, the electrical device may be arranged on a substrate and wherein the elongated semiconductor heterostructures of the NMOS transistor and the PMOS transistor are arranged such that the elongation extends is a direction being parallel to the surface of the substrate.

[0062] An advantage may be that a small foot print is provided. The robustness of the electrical device may, moreover, be improved.

[0063] According to some examples, the electrical device may be grown on and above the substrate. The substrate may be a silicon substrate. The silicon substrate may be a <111> substrate. The silicon substrate may comprise a GaN layer. The GaN layer may be arranged on the substrate. The substrate may comprise a strain relief layer on which the GaN is grown. The strain relief layer may be formed by AIGaN layers on and above an AIN nucleation layer. The strain relief layer and the AIN nucleation layer may form a buffer layer for a GaN layer. The AIGaN layer may be formed by a stack of AIGaN layers. The stack of AIGaN layers may form a graded buffer layer.

[0064] According to other examples the substrate may be e.g. a SiC, or sapphire substrate.

[0065] According to a second aspect there is provided a method of providing an electrical device configured to form a circuit for a complementary metal-oxide-semiconductor, CMOS, the method comprising: forming a first stack of layers on a substrate, the first stack of layers comprising a first semiconductor heterostructure comprising a top layer and a bottom layer, and sacrificial layers arranged above and below the first stack of layers; forming a second stack of layers on and above the first stack of layers, the second stack of layers comprising a second semiconductor heterostructure comprising a top layer and a bottom layer, and sacrificial layers arranged above and below the second stack of layers; etching the first and the second stack of layers substantially in the vertical direction relative to the substrate such that the semiconductor heterostructures form elongated semiconductor heterostructures; etching the sacrificial layers; forming an insulating material in the form of a cladding, the cladding enclosing the elongated semiconductor heterostructures.

[0066] An improved process for forming the electrical device may be obtained. An advantage may be that the formation of the elongated semiconductor heterostructures may be made efficiently. The thickness of the elongated semiconductor heterostructure may be controlled with improved efficiency.

[0067] The wording "substantially in a vertical direction" may be understood as in a direction being perpendicular to the substrate surface. The vertical direction may be parallel to the surface normal of the substrate.

[0068] The forming of the insulating material in the form of cladding should be understood as the cladding being arranged to enclose a substantial part of the elongated heterostructures is arranged to extend along the axial direction of the bodies.

[0069] According to some examples, further the method comprises: forming a gate substantially enclosing the insulating material and the first and the second stack of layers.

[0070] The enclosing may comprise enclosing a cladding of insulating material. The forming of the gate may further comprise forming a gate cladding structure enclosing a central portion of the bodies of the elongated semiconductor heterostructures.

[0071] According to some examples, the forming of the first stack of layers comprises forming the first and second semiconductor heterostructures such that the respective top layers and bottom layers, are made of AIGaN with an aluminum content of 0% or higher and wherein the content of aluminum in the top layers s are different to the bottom layers.

[0072] According to some examples, the first semiconductor heterostructure comprises a first undoped GaN layer and a first AIGaN layer arranged on the first undoped GaN layer and the second semiconductor heterostructure comprises second AIGaN layer and a second undoped GaN layer arranged on the second AIGaN layer.

[0073] The skilled person realizes the order of the arrangement of the first semiconductor heterostructure and the second semiconductor heterostructure may be reversed. To this end, the relative order of the n-channel metal-oxide-semiconductor, NMOS, transistor and the p- channel metal-oxide-semiconductor, PMOS, transistor, may be reversed within the electrical device.

[0074] The method may further comprise forming a gate layer stack structure.

[0075] The method may further comprise forming a source and the drain arranged on opposite distal regions of the body of the elongated semiconductor heterostructures. The method may further comprise forming elongated one or more vias in or on the substrate, the elongated vias extending in length parallel to the elongated semiconductor heterostructures and comprises GaN.

[0076] An advantage being that conductive pathways for electrical connections are provided. The electrical connections may serve as power rails. A more efficient contacting of the source and / or drain may thereby be achieved.

[0077] According to a third aspect there is provided a complementary metal-oxide- semiconductor, CMOS, comprising the electrical device according to the first aspect.

[0078] The complementary CMOS may further comprise a capacitive load arrange between an output connector from the complementary CMOS and ground. An advantage being that a more stable output may be achieved. An improved signal filtering may moreover be achieved.

[0079] Effects and features of the second and third aspects are to a large extent analogous to those described above in connection with the first aspect. Examples mentioned in relation to the first aspect are largely compatible with the second and third aspects.

[0080] The present disclosure will become apparent from the detailed description given below. The detailed description and specific examples disclose preferred examples of the disclosure by way of illustration only. Those skilled in the art understand from guidance in the detailed description that changes and modifications may be made within the scope of the disclosure.

[0081] Hence, it is to be understood that the herein disclosed disclosure is not limited to the particular component parts of the device described or steps of the methods described since such device and method may vary. It is also to be understood that the terminology used herein is for purpose of describing particular examples only, and is not intended to be limiting. It should be noted that, as used in the specification and the appended claim, the articles "a", "an", "the", and "said" are intended to mean that there are one or more of the elements unless the context explicitly dictates otherwise. Thus, for example, reference to "a unit" or "the unit" may include several devices, and the like. Furthermore, the words "comprising", "including", "containing" and similar wordings does not exclude other elements or steps.

[0082] Brief descriptions of the drawings

[0083] The above objects, as well as additional objects, features and advantages of the present disclosure, will be more fully appreciated by reference to the following illustrative and non-limiting detailed description of example examples of the present disclosure, when taken in conjunction with the accompanying drawings. Figures la to lc show schematically different views of an electrical device according to some examples.

[0084] Figure Id shows schematically a circuit diagram for a complementary metal-oxide- semiconductor, CMOS according to some examples.

[0085] Figure 2 shows a flowchart schematically illustrating a method of providing an electrical device configured to form a circuit for a complementary metal-oxide-semiconductor, CMOS according to some examples.

[0086] Figures 3 to 6 show schematically different intermediate steps in the providing an electrical device configured to form a circuit for a complementary metal-oxide- semiconductor, CMOS according to some examples.

[0087] Figure 7 shows schematically a side view of an electrical device according to some examples.

[0088] Figure 8 shows schematically a side view of an electrical device according to some examples.

[0089] Detailed description

[0090] The present disclosure will now be described with reference to the accompanying drawings, in which preferred example examples of the disclosure are shown. The disclosure may, however, be embodied in other forms and should not be construed as limited to the herein disclosed examples. The disclosed examples are provided to fully convey the scope of the disclosure to the skilled person.

[0091] Figures la to lc show schematically different views of an electrical device 100. The electrical device 100 comprises: an n-channel metal-oxide-semiconductor, NMOS, transistor 1. The NMOS transistor 1 comprises a source 10, a body 12 and a drain 14. The body 12 is an elongated semiconductor heterostructure 13 configured for conduction of negative charge carriers, i.e. for electron transport. The source 10 and the drain 14 are arranged on opposite distal regions 15,17 of the body 12.

[0092] The electrical device 100 further comprises a p-channel metal-oxide-semiconductor, PMOS, transistor. The PMOS transistor 1' comprises a source 10', a body 12' and a drain 14'. The body 12' is an elongated semiconductor heterostructure 13' configured for conduction of positive charge carriers, i.e. for hole transport. The source 10' and the drain 14' are arranged on opposite distal regions 15', 17' of the body 12'.

[0093] The bodies 12,12' of the NMOS and the PMOS transistors 1, 1' are arranged separated, in parallel and superimposed relative to each other. As illustrated in Figures la-lc the PMOS transistor 1' is arranged above the NMOS transistor 1. The order may be reversed. The NMOS transistor 1 and the PMOS transistor 1' of the electrical device 100 are connected to form a circuit 200 for a complementary metal-oxide-semiconductor, CMOS 300.

[0094] The electrical device 100 may be arranged on a substrate 36. The elongated semiconductor heterostructures 13, 13' of the NMOS transistor 1 and the PMOS transistor 1', may be arranged such that the elongation extends is a direction 37 a being parallel to the surface of the substrate 36, see Figure lc.

[0095] The NMOS transistor 1 may be arranged in relation to the PMOS transistor 1' such that the drain 14 of the NMOS transistor 1 is arranged superimposed with the source 12' of the PMOS transistor 1', see Figures la-lc.

[0096] A circuit diagram for a CMOS 300 is schematically illustrated in Figure Id. In the circuit diagram the NMOS and PMOS transistors 1,1' are illustrated for clarity. The complementary CMOS may further comprise a capacitive load 302. The capacitive load 302 may be arranged between an output connector 304 from the complementary CMOS and ground 306. Illustrated in Figure Id is further an input connector 308. It is further visible in Figure Id that the gate for both transistors 1,1' is connected to the input connector 308.

[0097] With further reference to Figures la-lc, the elongated semiconductor heterostructure 13 of the NMOS transistor 1 may comprise a heterojunction 11. The heterojunction 11 is configured to for conduction of negative charge carriers. Put differently, the heterojunction 11 may be arranged to enable electron transport when the electronic device 100 is in operation.

[0098] The heterojunction is formed by a top layer 18 and a bottom layer 20. The top layer 18 and the bottom layer 20 are both extending from a first end 22 to a second end 24 of the body 12. The side view in Figure 1 illustrates the first end 22,22'. The opposite side view in Figure lb illustrates the second end 24,24'. The elongated semiconductor heterostructure 13' of the PMOS transistor 1' comprises heterojunction 11' configured for the conduction of positive charges. Put differently, the heterojunction 11' may be arranged to enable hole transport when the electronic device 100 is in operation.

[0099] The heterostructure 11' is formed by a top layer 18' and a bottom layer 20', both extending from a first end 22' to a second end 24' of the body 12', see Figures la and lb.

[0100] Figure lc shows schematically a side view along the extension of the of the elongated semiconductor heterostructures 13, 13'. The extension of the elongated semiconductor heterostructure may be refereed to along an axial direction 37. The axial direction 37 may be a direction perpendicular to an interface surface between the top layer 18,18' and bottom layer 20.20'. According to some examples, the axial direction 37 may be oriented perpendicular to grow direction of the elongated semiconductor heterostructures 13,13'. The interface surface may be parallel to the surface of the substrate 36. An insulating material 26 may be arranged in between the bodies 12,12' of the NMOS transistor 1 and the PMOS transistor 1', see Figure lc. The insulating material 26 may form part of a cladding 27. The cladding 27 enclosing the bodies 12,12'. The cladding 27 may enclose the bodies 12, 12' fully or at a substantial part of them. The cladding 27 may at least enclose portion of the bodies 12, 12'.

[0101] The electrical device 100 may comprise a gate 28. The gate 28 is arranged to control the charge carriers in the NMOS transistor 1 and the PMOS transistor 1'. The gate 28 may comprise a gate cladding structure 30 enclosing a central portion 32 of the bodies 12,12'.

[0102] The gate 28 may further comprise a gate layer stack structure 34. The gate layer stack structure 34 may comprises a first layer the electrical comprises Ti and / or Ta, a second layer arranged on the first layer, the second layer the electrical comprises Al, a third layer arranged on the second layer, the third layer the electrical comprises one or more of Ni, Ti, Pt, Pd, Mo, Re, Ir, and a fourth layer arranged on the third layer, the fourth layer the electrical comprises Au. The gate layer stack structure 34 and the four layers are illustrated in Figure la and lb.

[0103] According to some examples, the top and bottom layers 18, 18', 20, 20' may be made of AIGaN with an aluminum content of 0% or higher and wherein the content of aluminum in the top layers 18,18' are different to the content of aluminum in the bottom layers 20,20' for each of the elongated semiconductor heterostructures 13,13'.

[0104] The heterojunction 11 configured to conduct negative charges, e.g. for enabling electron transport, may be formed by a top layer 18 of AIGaN formed on a bottom layer 20 of GaN.

[0105] The heterojunction 11' configured to conduct positive charges, e.g. for enabling hole transport, may be formed by a top layer 18' GaN formed on a bottom layer 20' of AIGaN.

[0106] Each of the elongated semiconductor heterostructures 13,13' may have an axial length in a range of 200 to 50 nm and a largest cross section being less than 10 nm, preferably less than 5 nm.

[0107] Each of the elongated semiconductor heterostructures 13,13' may have a thickness in the range of 1-10 nm, preferably in the range 3-5 nm.

[0108] With reference to Figures 2 and Figures 3 - 6, a method of providing an electrical device 100 configured to form a circuit 200 for a complementary metal-oxide-semiconductor, CMOS, 300, is be described.

[0109] The method 400 comprises forming S402 a first stack of layers 40 on a substrate 36, the first stack of layers 40 comprising a first semiconductor heterostructure 42, and sacrificial layers 44a, 44b. The first semiconductor heterostructure 42 comprises a top layer 18, and a bottom layer 20. The sacrificial layers 44a, 44b are arranged above and below the first stack of layers 40, see Figures 2 and 3a.

[0110] The method 400 also comprises forming S404 a second stack of layers 46 on and above the first stack of layers 40. The second stack of layers 46 comprises a second semiconductor heterostructure 48. The second semiconductor heterostructure 48 comprises a top layer 18' and a bottom layer 20'. The sacrificial layers 44a', 44b' are arranged above and below the second stack of layers 46, see Figures 2 and 3a. The sacrificial layers 44b and 44a' arranged between the top layer 20 of the first semiconductor heterostructure 42 and the bottom layer 18' of the second semiconductor heterostructure 48 may be a combined common layer.

[0111] The first and second semiconductor heterostructures 42, 48 and / or sacrificial layers 44a, 44a', 44b, 44b' may be epitaxially grown sequentially in the GaN growth direction e.g. C- direction of the crystal structure wurtzite, by metal organic vapor phase epitaxy, MOVPE. However, other epitaxial growth methods may alternatively be used, e.g. molecular beam epitaxy, MBE. The first and the second semiconductor heterostructures 42, 48 may be epitaxially grown in one growth session or in several sessions.

[0112] The sacrificial layers 44a, 44a', 44b, 44b' may be grown in the same or in additional growth sessions as the first and second semiconductor heterostructures 42, 48.

[0113] By way of example, dopants of n-type may be introduced in the gas phase of the MOVPE. Precursors such as e.g. trimethyl gallium (TMG), trimethyl aluminum (TMA), and NH3 may be used for the growth.

[0114] According to some examples, dopants of p-type, e.g. Mg, may be introduced in the gas phase of the MOVPE. The aluminum content may be changed by changing precursor flows during the epitaxial growth, e.g. by changing a TMG / TMA ratio.

[0115] According to some examples the source / body / drain of the NMOS transistor may be doped. The source may be n-doped (e.g. strongly n-doped, commonly denoted by n+), the body may be p-doped, and the drain may be n-doped. Put differently, the doping for the source / body / drain may be n / p / n or n+ / p / n+.

[0116] The source / body / drain of the PMOS may be doped. The source may be p-doped (e.g. strongly p-doped, commonly denoted by p+), the body may be n-doped, and the drain may be p-doped. Put differently the doping of the source / body / drain may be p / n / p, e.g. p+ / n / p+.

[0117] The p-doping may refer to doping by Mg from e.g. the precursor Bis(cyclopentadienyl)magnesium, Cp2Mg. However, the same enhancement mechanism may also apply to other p-dopant e.g. Boron The n-doping may refer to doping by Si from e.g. the precursor SiH4. However, GaN- based materials may, at least under some circumstances, be intrinsically n-type. Thus, a n- doped region may not necessarily be actively doped.

[0118] The forming S402 of the first stack of layers 40 may comprise forming the first and second semiconductor heterostructures 13, 13' such that the respective top layers 18, 18' and bottom layers 20, 20', are made of AIGaN with an aluminum content of 0% or higher and wherein the content of aluminum in the top layers 18, 18' s are different to the bottom layers 20, 20'.

[0119] The first semiconductor heterostructure 13 may comprise a first undoped GaN layer and a first AIGaN layer arranged on the first undoped GaN layer and the second semiconductor heterostructure 13' comprises second AIGaN layer and a second undoped GaN layer arranged on the second AIGaN layer.

[0120] The method comprises etching steps performed on the formed structures. The etching S406 comprises etching the first and the second stack of layers 40, 46 substantially in the vertical direction 39 relative to the substrate 36, compare Figures 3a and 3b.

[0121] As a result, the semiconductor heterostructures 42, 48 form elongated semiconductor heterostructures 13, 13'. The vertical etch direction 39 may be understood as being perpendicular to the surfaces of the respective heterostructure layers. The vertical direction 39 may be perpendicular to the surface of the substrate.

[0122] The etching S406 may be done by wet etching, e.g. using hydrofluoric acid, or by dry etching, e.g. by reactive ion etching. In more detail, the etching S406 of the first and second stack of layers 40, 46 may be performed by a physical etch. This etching may be referred to as a physical etch. The etching S406 may be by plasma etching. An advantage may be that the plasma etch etches substantially in a downward direction (towards the substrate 36) with reduced or no inclined sidewalls.

[0123] The physical etching may be achieved by use of one or more etch masks 47. The one or more etch masks 47 may be referred to as hard masks. The masking may be achieved by lithographical patterning, e.g. by nanoimprint lithography, NIL. The etching may be to exposed areas, i.e. areas not covered by the mask.

[0124] The method 400 further comprises etching S408 the sacrificial layers 44a, 44b, 44a', 44b', compare Figures 3b and 4a. Figure 4b further illustrates schematically the same structure as in Figure 4a, but from a different side view such that the extension of the elongated semiconductor heterostructures 13, 13' formed are illustrated. In Fig 4a the elongated semiconductor heterostructures 13, 13' have their main extension into the "paper". That is Fig 4a illustrated a cross section relative to Fig 4b as taken in the plane A-A indicated in Fig 4b. The etching S408 of the sacrificial layers may be performed by a chemical etch. This etching S408 may be referred to as a chemical etch. The chemical etch may be a directional etch. The etching may be performed by reactive ion etching.

[0125] The sacrificial layers may be formed by one or more InGaN or doped GaN alloys. The one or more InGaN alloys may be configured to form I nl 3 and lnBr3 etch products when etched. Alternatively, etch selectivity of GaN to AIGaN may be configured.

[0126] An etch selectivity of GaN and InGaN relative to AIGaN may be used for the etching S408.

[0127] The sacrificial layer of the first stack of layers and one sacrificial layer of the second stack of layers may be the same layer according to some embodiments.

[0128] With further reference to Figure 2 and Figures 5a and 5b, the method 400 may comprise forming S410 an insulating material 26 in the form of a cladding. The cladding enclosing the elongated semiconductor heterostructures 13, 13'. In Fig 5a the elongated semiconductor heterostructures 13, 13' have their main extension into the "paper". That is Fig 5a illustrated a cross section relative to Fig 5b as taken in the plane A-A indicated in Fig 5b.

[0129] With further reference to Figure 2 and Figures 6a and 6b the method 400 may comprise forming S412 a gate 28 substantially enclosing the insulating material 26 and the first and the second stack of layers 40, 46. In Fig 6a the elongated semiconductor heterostructures 13, 13' have their main extension into the "paper". That is Fig 6a illustrated a cross section relative to Fig 6b as taken in the plane A-A indicated in Fig 6b.

[0130] The enclosing may comprise enclosing a cladding of insulating material 26. The forming S412 of the gate 28 may further comprise forming a gate cladding structure 30 enclosing a central portion 32 of the bodies 12, 12' of the elongated semiconductor heterostructures 13, 13'.

[0131] An insulating material, e.g. an oxide, may be arranged to electrically insulate the respective elongated semiconductor heterostructures semiconductor structure from each other and from the gate. The electrical insulator may be e.g. AI203, HfO2, or Y203.

[0132] With reference to Figure 2 and Figure 6c, the method 400 may further comprise forming S414 one or more vias 33 in or on the substrate 36. The vias 33 may extend in length parallel to the elongated semiconductor heterostructures 13,13'. The vias 33 may be understood to form elongated structures. The vias 33 may comprise or be formed by GaN. An advantage being that conductive pathways for electrical connections are provided. The electrical connections may serve as power rails. A more efficient contacting of the source and / or drain may thereby be achieved. With reference to Figure 2 and Figure 6d, the method 400 may comprise forming S416 a gate layer stack structure 34.

[0133] With reference to Figure 2, 7, and la-lc, the method 400 may comprise forming S418 a source 10,10' and the drain 14,14' arranged on opposite distal regions 15,17 of the body 12,12' of the elongated semiconductor heterostructures 13,13'.

[0134] The method 400 of Figure 2 is here described to comprise a number of steps S402- S418. It should, however be understood that some of the steps are optional, as indicated in the Figure 2. It should also be understood that at least some of the steps may be performed in a different order than indicated in Figure 2, as readily understood by the skilled person.

[0135] Figure 8 illustrates schematically that the electrical device 100 may be arranged such that the NMOS transistor 1 and / or the PMOS transistor 1' comprises additional heterojunctions for electron and hole transport respectively. Put differently, the NMOS transistor and / or the PMOS transistor may comprise a plurality of elongated semiconductor heterostructures 13, 13'.

[0136] Each of the elongated semiconductor heterostructures 13, 13', may comprise a one or more pairs of top and bottom layers in the first and second stack of layers.

[0137] To this end, the number of elongated semiconductor heterostructures 13, 13' may differ between the NMOS transistor 1 and the PMOS transistor 1'. By way of example, the number of elongated semiconductor heterostructures 13' in the PMOS transistor 1' may be larger than the number of elongated semiconductor heterostructures 13 in the NMOS transistor 1. This is illustrated by way of example by the three elongated semiconductor heterostructures 13' in the PMOS transistor 1' and the two elongated semiconductor heterostructures 13 in the NMOS transistor 1 in Figure 8.

[0138] The relatively lower mobility for hole transport than for electron transport may thereby be compensated for. A more symmetric complementary CMOS may thereby be provided. The performance of the electronic device and thereby the performance of the CMOS may be increased. An advantage may be that the mobility for charge carrier transport may be increased by the plurality of heterojunctions.

[0139] The person skilled in the art realizes that the present disclosure is not limited to the preferred examples described above. The person skilled in the art further realizes that modifications and variations are possible within the scope of the appended claims. Additionally, variations to the disclosed examples can be understood and effected by the skilled person in practicing the claimed disclosure, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. CLAIMS1. An electrical device comprising: an n-channel metal-oxide-semiconductor, NMOS, transistor (1), the NMOS transistor (1) comprising a source (10), a body (12) and a drain (14), wherein the body (12) is an elongated semiconductor heterostructure (13) configured for conduction of negative charge carriers, wherein the source (10) and the drain (14) are arranged on opposite distal regions (15,17) of the body (12), wherein the elongated semiconductor heterostructure (13) of the NMOS transistor (1) comprises a heterojunction (11) configured for the conduction of negative charge carriers, the heterojunction (11) being formed by a top layer (18) and a bottom layer (20), both extending from a first end (22) to a second end (24) of the body (12); and a p-channel metal-oxide-semiconductor, PMOS, transistor, the PMOS transistor (1') comprising a source (10'), a body (12') and a drain (14'), wherein the body (12') is an elongated semiconductor heterostructure (13') configured for conduction of positive charge carriers, wherein the source (10') and the drain (14') are arranged on opposite distal regions (15', 17') of the body (12'), wherein the elongated semiconductor heterostructure (13') of the PMOS transistor (1') comprises a heterojunction (11') configured for the conduction of positive charges, the heterojunction (11') being formed by a top layer (18') and a bottom layer (20'), both extending from a first end (22') to a second end (24') of the body (12'); wherein the top and bottom layers (18, 18', 20, 20') are made of AIGaN with an aluminum content of 0% or higher and wherein the content of aluminum in the top layers (18,18') are different to the content of aluminum in the bottom layers (20,20') for each of the elongated semiconductor heterostructures (13,13'), wherein each of the elongated semiconductor heterostructures (13,13') has an axial length in a range of 200 to 50 nm and a largest cross section being less than 10 nm, preferably less than 5 nm, wherein each of the elongated semiconductor heterostructures (13,13') has a thickness in the range of 1-10 nm, preferably in the range 3-5 nm, wherein the bodies (12,12') are arranged separated, in parallel and superimposed relative to each other, wherein the NMOS transistor (1) and the PMOS transistor (1') of the electrical device (100) are connected to form part of a circuit (200) for a complementary metal-oxide- semiconductor, CMOS (300).

2. The electrical device according to claim 1, wherein an insulating material (26) is arranged in between the bodies (12,12') of the NMOS transistor (1) and the PMOS transistor (1').

3. The electrical device according to claim 2, wherein the insulating material (26) is part of a cladding, the cladding enclosing the bodies (12,12').

4. The electrical device according to any one of claims 1-3, further comprising a gate (28) for controlling the charge carriers in the NMOS transistor (1) and the PMOS transistor (1'), wherein the gate (28) comprises a gate cladding structure (30) enclosing a central portion (32) of the bodies (12,12').

5. The electrical device according to claim 4, wherein the gate (28) comprises a gate layer stack structure (34) comprising a first layer comprising Ti and / or Ta, a second layer arranged on the first layer, the second layer comprising Al, a third layer arranged on the second layer, the third layer comprising one or more of Ni, Ti, Pt, Pd, Mo, Re, Ir, and a fourth layer arranged on the third layer, the fourth layer comprising Au.

6. The electrical device according to any one of claims 1-5, wherein the electrical device (100) is arranged on a substrate (36) and wherein the elongated semiconductor heterostructures (13,13') of the NMOS transistor (1) and the PMOS transistor (1'), are arranged such that the elongation extends is a direction (a) being parallel to the surface of the substrate (36).

7. The electrical device according to any one of claims 1-6, wherein one or both of the NMOS transistor (1) and the PMOS transistor (1') comprises a plurality of elongated semiconductor heterostructures (13, 13').

8. The electrical device according to claim 7, wherein a number elongated semiconductor heterostructures (13, 13') differ between the NMOS transistor (1) and the PMOS transistor (1').

9. The electrical device according to claim 7, wherein the number of elongated semiconductor heterostructures (13') in the PMOS transistor (1') is larger than the number of elongated semiconductor heterostructures (13) in the NMOS transistor (1).

10. A method of providing an electrical device configured to form part of a circuit (200) for a complementary metal-oxide-semiconductor, CMOS, (300), the method (400) comprising: forming (402) a first stack of layers (40) on a substrate (36), the first stack of layers (40) comprising a first semiconductor heterostructure (42) comprising a top layer (18) and a bottom layer (20) wherein the top and bottom layers (18, 20) are made of AIGaN with an aluminum content of 0% or higher and wherein the content of aluminum in the top layer (18) is different to the bottom layers (20), and sacrificial layers (44a, 44b) arranged above and below the first stack of layers (40); forming (404) a second stack of layers (46) on and above the first stack of layers (40), the second stack of layers (46) comprising a second semiconductor heterostructure (48) comprising a top layer (18') and a bottom layer (20') wherein the top and bottom layers (18', 20') are made of AIGaN with an aluminum content of 0% or higher and wherein the content of aluminum in the top layer (18') is different to the bottom layers (20'), and sacrificial layers (44a', 44b') arranged above and below the second stack of layers (46); etching (406) the first and the second stack of layers (40,46) substantially in the vertical direction relative to the substrate (36) such that the semiconductor heterostructures (42,48) form elongated semiconductor heterostructures (13,13') having an axial length in a range of 200 to 50 nm, a largest cross section being less than 10 nm, preferably less than 5 nm, and a thickness in the range of 1-10 nm, preferably in the range 3-5 nm; etching (408) the sacrificial layers (44a, 44b, 44a', 44b'); forming (410) an insulating material (26) in the form of a cladding, the cladding enclosing the elongated semiconductor heterostructures (13,13').

11. The method according to claim 10, further comprising: forming (412) a gate (28) substantially enclosing the insulating material (26) and the first and the second stack of layers (40,46).

12. The method according to claim 10 or 11, wherein the first semiconductor heterostructure (13) comprises a first undoped GaN layer and a first AIGaN layer arranged on the first undoped GaN layer and the second semiconductor heterostructure (13') comprises second AIGaN layer and a second undoped GaN layer arranged on the second AIGaN layer.

13. A complementary metal-oxide-semiconductor, CMOS, (300) comprising:an electrical device (100) according to claim 1, the electrical device (100) forming part of the circuit (200) of the CMOS (300); and a capacitive load (302) arranged between an output connector (304) from the CMOS (300) and ground (306).

14. The CMOS, (300) according to claim 13, wherein the electrical device (100) further comprises a gate (28) for controlling the charge carriers in the NMOS transistor (1) and the PMOS transistor (1'), wherein the gate (28) comprises a gate cladding structure (30) enclosing a central portion (32) of the bodies (12,12'), wherein the CMOS (300) further comprises an input connector (308) connected to the gate (28) for both transistors (1,1').

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