Electronic control device, method for utilizing memory, and program for utilizing memory

Abstract

An electronic control device (1) comprises: a first control unit (2) that executes software; a first storage unit (3) capable of storing software that is executed by the first control unit; a second control unit (4) that executes software; and a second storage unit (5) capable of storing software that is executed by the second control unit. The second storage unit has a memory area that functions as a reprogramming surface or an operating surface for the software of the first control unit. The first control unit performs data communication with the second control unit, and accesses the reprogramming surface or the operating surface of the second storage unit using a virtual address.

Description

Electronic control device, memory utilization method, and memory utilization program CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2024-97459, filed on June 17, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to an electronic control device, a memory utilization method, and a memory utilization program.

[0003] Vehicles are equipped with numerous systems. For example, with the diversification of vehicle control, such as driving assistance functions and autonomous driving functions, over-the-air (OTA) repro technology has been provided for wirelessly updating software installed in electronic control units (hereinafter referred to as ECUs (Electronic Control Units)), which are components of the systems (see, for example, Patent Document 1).

[0004] JP 2018-86849 A

[0005] When performing OTA reprogramming, in specifications where the storage unit that stores the software has a two-sided configuration, the memory area of ​​the storage unit is divided into a memory area on the operational side used at startup and a memory area on the reprogramming side that is the target of software updates. Meanwhile, with the increasing multi-functionality and distribution of processing, configurations that perform multi-control using multiple control units have been realized. In ECUs with multiple control units, software executed by a first control unit is stored in a first storage unit, and the memory area of ​​the first storage unit is divided into a memory area for the software of the first control unit and a reprogramming side, while software executed by a second control unit is stored in a second storage unit, and the memory area of ​​the second storage unit is divided into a memory area for the software of the second control unit and a reprogramming side.

[0006] However, for example, if the first and second control units are in a main-sub relationship and the first storage unit has a small capacity due to the specifications of the main first control unit prioritizing high-speed startup, there may be cases where it is not possible to secure a memory area for the repro side in the first storage unit. As a result, it is not possible to secure a memory area for the repro side of the first control unit, and a problem occurs in which it becomes impossible to update the software of the first control unit.

[0007] The present disclosure aims to, in a configuration having a first control unit and a second control unit, appropriately secure memory space on the reproduction side of the first control unit and appropriately update the software of the first control unit, even if the first memory unit capable of storing software executed by the first control unit has a small capacity.

[0008] According to one aspect of the present disclosure, a computer system includes a first control unit that executes software, a first storage unit capable of storing the software executed by the first control unit, a second control unit that executes software, and a second storage unit capable of storing the software executed by the second control unit. The second storage unit has a memory area that functions as a reproduction surface or an operation surface of the software of the first control unit. The first control unit performs data communication with the second control unit and accesses the reproduction surface or the operation surface of the second storage unit using a virtual address.

[0009] A memory area that functions as a reproduction surface or an operation surface of the software of the first control unit is provided in the second storage unit that can store the software executed by the second control unit, and the first control unit performs data communication with the second control unit and accesses the reproduction surface or the operation surface of the second storage unit using a virtual address. By allowing the first control unit to virtually access the memory area of ​​the second storage unit, even if the first storage unit has a small capacity, it is possible to appropriately secure the memory area of ​​the reproduction surface of the first control unit and appropriately update the software of the first control unit.

[0010] According to one aspect of the present disclosure, there is provided a method of utilizing memory in an electronic control device that includes a first control unit that executes software, a first memory unit that can store the software executed by the first control unit, a second control unit that executes software, and a second memory unit that can store the software executed by the second control unit, wherein a memory area that functions as a reproduction surface or operating surface of the software of the first control unit is provided in the second memory unit, and the first control unit communicates data with the second control unit and accesses the reproduction surface or operating surface of the second memory unit using a virtual address.

[0011] By virtually allowing the first control unit to access the memory area of ​​the second memory unit, even if the first memory unit has a small capacity, the memory area of ​​the reproduction side of the first control unit can be appropriately secured, and the software of the first control unit can be appropriately updated.

[0012] According to one aspect of the present disclosure, in an electronic control device comprising a first control unit that executes software, a first memory unit that can store the software executed by the first control unit, a second control unit that executes software, and a second memory unit that can store the software executed by the second control unit, the first control unit performs data communication with the second control unit and executes a procedure to access the reproduction surface or operation surface of the second memory unit using a virtual address.

[0013] By virtually allowing the first control unit to access the memory area of ​​the second memory unit, even if the first memory unit has a small capacity, the memory area of ​​the reproduction side of the first control unit can be appropriately secured, and the software of the first control unit can be appropriately updated.

[0014] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is a functional block diagram showing the overall configuration of a first embodiment, Fig. 2 is a diagram showing a state in which the reproduction surface and the working surface are switched, Fig. 3 is a diagram showing the processing flow, Fig. 4 is a diagram showing the processing flow, Fig. 5 is a functional block diagram showing the overall configuration of a second embodiment, and Fig. 6 is a diagram showing a state in which the reproduction surface and the working surface are switched.

[0015] Hereinafter, several embodiments will be described with reference to the drawings. In the following embodiments, the description of the same parts as in the preceding embodiments may be omitted. (First Embodiment)

[0016] A first embodiment will be described with reference to Figures 1 to 4. The ECU 1 shown in Figure 1 is a component of a cockpit system that performs control related to a vehicle cockpit, for example. The ECU 1 has a multi-CPU configuration including multiple CPUs. That is, the ECU 1 includes a first CPU 2 (corresponding to a first control unit), a first memory 3 (corresponding to a first storage unit) capable of storing software executed by the first CPU 2, a second CPU 4 (corresponding to a second control unit), and a second memory 5 (corresponding to a second storage unit) capable of storing software executed by the second CPU 4.

[0017] The first CPU 2 and the second CPU 4 have a main-sub relationship. The first CPU 2, which functions as the main CPU, is connected to a communication bus (not shown) and is designed to prioritize fast startup due to its nature of performing main processing such as power supply control. The first memory 3 has a relatively small capacity because the first CPU 2 is designed to prioritize fast startup as described above. The second memory 5 has a relatively large capacity because the second CPU 4 is designed not to require as fast startup as the first CPU 2. The first memory 3 functions as a local memory from the perspective of the first CPU 2 and as a remote memory from the perspective of the second CPU 4. The second memory 5 functions as a local memory from the perspective of the second CPU 4 and as a remote memory from the perspective of the first CPU 2.

[0018] The software stored in the first memory 3 and the software stored in the second memory 5 are updated as needed, for example, by wirelessly connecting the ECU 1 to an OTA center via a data communication device such as a DCM (Data Communication Module). The software stored in the first memory 3 and the software stored in the second memory 5 can also be updated as needed, for example, by wiredly connecting the ECU 1 to a diagnostic tool via a diagnostic connector. Software updated as needed via a wireless connection is called wireless repro, and software updated as needed via a wired connection is called wired repro. Software includes programs, data, libraries, etc. for operating the ECU.

[0019] The first CPU 2 includes a first data communication unit 2a (corresponding to a first communication unit) and a first memory management unit 2b (corresponding to a first storage management unit). The first data communication unit 2a performs inter-CPU communication with a second data communication unit 4a (described later) of the second CPU 4. The first memory management unit 2b manages the first memory 3 and also manages the second memory 5 via inter-CPU communication.

[0020] That is, when the first memory management unit 2b receives a software write instruction from an application, it determines whether the software is to be written to the first memory 3 or the second memory 5. If the first memory management unit 2b determines that the software is to be written to the first memory 3, it writes the data that constitutes the software to the first memory 3. If the first memory management unit 2b determines that the software is to be written to the second memory 5, it writes the data that constitutes the software to the second memory 5.

[0021] Furthermore, when the first memory management unit 2b receives an instruction to load software from an application, it determines whether the destination for loading the software is the first memory 3 or the second memory 5. If the first memory management unit 2b determines that the destination for loading the software is the first memory 3, it reads the data that constitutes the software into the first memory 3. If the first memory management unit 2b determines that the destination for loading the software is the second memory 5, it writes the data that constitutes the software into the second memory 5.

[0022] The second CPU 4 includes a second data communication unit 4a (corresponding to a second communication unit) and a second memory management unit 4b (corresponding to a second storage management unit). The second data communication unit 4a performs inter-CPU communication with the first data communication unit 2a of the first CPU 2. The second memory management unit 4b manages the second memory 5 and also manages the first memory 3 via inter-CPU communication.

[0023] As described above, since the first memory 3 has a relatively small capacity and the second memory 5 has a large capacity, the first CPU 2 manages physically existing addresses in the first memory 3 as well as physically non-existent addresses in the first memory 3. Specifically, for example, if the physically existing addresses in the first memory 3 are "0x000-0x200," the first CPU 2 accesses the first memory 3 when it receives data access from an application to the physically existing addresses "0x000-0x200." On the other hand, when it receives data access from an application to the physically non-existent addresses "0x200-0x400," it accesses the second memory 5 via inter-CPU communication.

[0024] The second memory 5 has a memory area divided into an operational area and a reproduction area for the software of the second CPU 4, and both the operational area and the reproduction area are allocated. Therefore, when the second CPU 4 updates its own software, it writes the data that constitutes the software to the memory area divided as the reproduction area for the second CPU in the second memory 5. After completing the writing, the second CPU 4 switches between the reproduction area and the operational area, for example, when the device power is reset.

[0025] On the other hand, the memory area of ​​the first memory 3 is not divided into an operating surface and a repro surface for the software of the first CPU 2, but is assigned either an operating surface or a repro surface. When the operating surface for the first CPU is assigned to the first memory 3, the repro surface for the first CPU is virtually assigned to the second memory 5. When the repro surface for the first CPU is assigned to the first memory 3, the operating surface for the first CPU is virtually assigned to the second memory 5. Therefore, when the first CPU 2 updates its own software, if the repro surface for the first CPU is not assigned to the first memory 3, it accesses the second memory 5 via inter-CPU communication and writes the data that constitutes the software to the memory area of ​​the second memory 5 that is divided into the repro surface for the first CPU. That is, as shown in FIG. 1, the first CPU 2 reserves "0x000-0x200" which is physically present in the first memory 3 as the working surface for the first CPU in the first memory 3, and reserves "0x200-0x400" which is not physically present in the first memory 3 in the second memory 5 as the reproduction surface for the first CPU.

[0026] When the first CPU 2 completes writing the data, it switches between the repro plane and the active plane, for example, when the device power is reset. That is, as shown in Figure 2, the first CPU 2 reserves "0x000-0x200" that physically exists in the first memory 3 as the repro plane for the first CPU in the first memory 3, and reserves "0x200-0x400" that does not physically exist in the first memory 3 in the second memory 5 as the active plane for the first CPU.

[0027] Next, the operation of the above-described configuration will be described with reference to Figures 3 and 4. In this case, the operation will be described in order when a write instruction is received from an application and when a read instruction is received from an application.

[0028] (1) When a write instruction is received from an application (see FIG. 3) In the first CPU 2, the first memory management unit 2b receives a write instruction from an application (S11), and when a data transfer instruction is received from the application (S12), it determines the write destination of the data. When the first memory management unit 2b determines that the data write destination is the second memory 5, it prepares the data transfer and waits for reference to the write destination of the data from the first data communication unit 2a. The first data communication unit 2a references the write destination of the data to the first memory management unit 2b (S13), and when it determines that the write destination of the data is the second memory 5, it transmits the data to the second CPU 4 (S14, S16, S18).

[0029] In the second CPU 4, when the second data communication unit 4a receives the data transmitted from the first CPU 2, the second data communication unit 4a transfers the received data to the second memory management unit 4b (S15, S17, S19). When the second memory management unit 4b receives the data from the second data communication unit 4a, the second memory management unit 4b writes the transferred data to the second memory 5.

[0030] (2) When a read instruction is received from an application (see FIG. 4) In the first CPU 2, when the first memory management unit 2b receives a read instruction from an application (S21), it determines the read destination of the data. If the first memory management unit 2b determines that the read destination of the data is the second memory 5, it waits for reference to the read destination of the data from the first data communication unit 2a. The first data communication unit 2a references the read destination of the data to the first memory management unit 2b (S22), and if it determines that the read destination of the data is the second memory 5, it sends a read instruction to the second CPU 4 (S23).

[0031] In the second CPU 4, when the second data communication unit 4a receives the read instruction transmitted from the first CPU 2, it transfers the received read instruction to the second memory management unit 4b (S24). When the read instruction is transferred from the second data communication unit 4a, the second memory management unit 4b prepares the data transfer and waits for the second data communication unit 4a to refer to the data write destination. The second data communication unit 4a refers to the second memory management unit 4b for the data write destination (S25), and when it identifies that the data write destination is the first memory 3, it transmits the data to the first CPU 2 (S26, S29, S32).

[0032] In the first CPU 2, when the first data communication unit 2a receives the data transmitted from the second CPU 4, the first data communication unit 2a transfers the received data to the first memory management unit 2b (S27, S30, S33). When the first memory management unit 2b receives the data from the first data communication unit 2a, the first memory management unit 2b transfers the transferred data to the application that requested the read instruction (S28, S31, S34).

[0033] As described above, the first embodiment provides the following advantageous effects. In the ECU 1, the second memory 5, which can store software executed by the second CPU 4, is provided with a memory area that functions as a reproduction surface or operation surface of the software of the first CPU 2, and the first CPU 2 accesses the reproduction surface or operation surface of the second memory 5 by performing data communication with the second CPU 4. By virtually enabling the first CPU 2 to access the memory area of ​​the second memory 5, even if the first memory 3 has a small capacity, it is possible to appropriately secure a memory area for the reproduction surface of the first CPU 2, and to appropriately update the software of the first CPU 2.

[0034] Second Embodiment A second embodiment will be described with reference to Fig. 5. In the first embodiment, the first CPU 2 functioning as the first control unit and the second CPU 4 functioning as the second control unit have a one-to-one relationship, but in the second embodiment, the CPU functioning as the first control unit and the CPU 4 functioning as the second control unit have a one-to-multiple relationship.

[0035] The ECU 11 includes a third CPU 12 (corresponding to the first control unit), a third memory 13 (corresponding to the first storage unit) capable of storing software executed by the third CPU 12, a fourth CPU 14 (corresponding to the second control unit), a fourth memory 15 (corresponding to the second storage unit) capable of storing software executed by the fourth CPU 14, a fifth CPU 16 (corresponding to the second control unit), and a fifth memory 117 (corresponding to the second storage unit) capable of storing software executed by the fifth CPU 16.

[0036] The third CPU 12 includes a third data communication unit 12a (corresponding to the first communication unit) and a third memory management unit 12b (corresponding to the first storage management unit). The fourth CPU 14 includes a fourth data communication unit 14a (corresponding to the second communication unit) and a fourth memory management unit 14b (corresponding to the second storage management unit). The fifth CPU 16 includes a fifth data communication unit 16a (corresponding to the second communication unit) and a fifth memory management unit 16b (corresponding to the second storage management unit). The third data communication unit 12a performs inter-CPU communication between the fourth data communication unit 14a and the fifth data communication unit 16a.

[0037] In this case, the third CPU 12 reserves "0x000-0x200" which is physically present in the third memory 13 as the working surface for the third CPU in the third memory 13, and divides and reserves "0x200-0x400" which is not physically present in the third memory 13 as the repro surface for the third CPU between the fourth memory 15 and the fifth memory 17. That is, the third CPU 12 reserves "0x200-0x300" which is not physically present in the third memory 13 in the fourth memory 15 as the repro surface for the third CPU, and reserves "0x300-0x400" which is not physically present in the third memory 13 in the fifth memory 17 as the repro surface for the third CPU.

[0038] 6, the third CPU 12 reserves "0x000-0x200" which is physically present in the third memory 13 in the first memory 3 as a repro plane for the third CPU, reserves "0x200-0x300" which is not physically present in the third memory 13 in the fourth memory 15 as a plane for the third CPU, and reserves "0x300-0x400" which is not physically present in the third memory 13 in the fifth memory 17 as a plane for the third CPU.

[0039] As described above, the second embodiment provides the following advantageous effects. In the ECU 11, the fourth memory 15 and the fifth memory 17 are provided with memory areas that function as a reproduction surface or an operation surface for the software of the third CPU 12, and the third CPU 12 accesses the reproduction surface or the operation surface of the fourth memory 15 and the fifth memory 17 by performing data communication between the fourth CPU 14 and the fifth CPU 16. By virtually enabling the third CPU 12 to access the memory areas of the fourth memory 15 and the fifth memory 17, even if the third memory 13 has a small capacity, it is possible to appropriately secure a memory area for the reproduction surface of the third CPU 12, and to appropriately update the software of the third CPU 12.

[0040] (Other Embodiments) While the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to those examples or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0041] The control unit and the method described herein may be implemented by a special-purpose computer configured by configuring a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control unit and the method described herein may be implemented by a special-purpose computer configured by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method described herein may be implemented by one or more special-purpose computers configured by combining a processor and memory programmed to perform one or more functions with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory tangible storage medium.

Claims

1. An electronic control device (1, 11) comprising a first control unit (2, 12) that executes software, a first memory unit (3, 13) that can store the software executed by the first control unit, a second control unit (4, 14, 16) that executes software, and a second memory unit (5, 15, 17) that can store the software executed by the second control unit, wherein the second memory unit has a memory area that functions as a reproduction surface or an operation surface of the software of the first control unit, and the first control unit performs data communication with the second control unit and accesses the reproduction surface or the operation surface of the second memory unit using a virtual address.

2. The electronic control device described in claim 1, wherein the first control unit comprises: a first memory management unit (2b, 12b) that determines the write destination of the data that constitutes the software when it receives an instruction to write the data that constitutes the software from an app; and a first communication unit (2a, 12a) that refers to the write destination of the data in the first memory management unit and, when it determines that the write destination of the data is the second memory unit, transmits the data to the second control unit.

3. The electronic control device described in claim 1, wherein the first control unit comprises: a first memory management unit (2b, 12b) that determines the destination from which the data constituting the software is to be read when it receives an instruction to read the data constituting the software from an app; and a first communication unit (2a, 12a) that refers to the destination from which the data is to be read in the first memory management unit and, when it determines that the destination from which the data is to be read is the second memory unit, transmits the read instruction to the second control unit.

4. An electronic control device as described in claim 3, wherein the second control unit is provided with a second communication unit (4a, 14a, 16a) that, when the read instruction is received from the first control unit, refers to the second memory management unit as to the data write destination and transmits the data to the first control unit.

5. An electronic control device as described in any one of claims 1 to 4, wherein a plurality of second control units are provided for one first control unit, and a plurality of second storage units are provided for one first storage unit.

6. A method of utilizing memory in an electronic control device (1, 11) comprising a first control unit (2, 12) that executes software, a first storage unit (3, 13) capable of storing the software executed by the first control unit, a second control unit (4, 14, 16) that executes software, and a second storage unit (5, 15, 17) capable of storing the software executed by the second control unit, wherein a memory area that functions as a reproduction surface or operation surface of the software of the first control unit is provided in the second storage unit, and the first control unit performs data communication with the second control unit and accesses the reproduction surface or operation surface of the second storage unit using a virtual address.

7. In an electronic control device (1, 11) comprising a first control unit (2, 12) that executes software, a first memory unit (3, 13) capable of storing the software executed by the first control unit, a second control unit (4, 14, 16) that executes software, and a second memory unit (5, 15, 17) capable of storing the software executed by the second control unit, a memory utilization program that causes the first control unit to perform data communication with the second control unit and execute a procedure to access the reproduction surface or operation surface of the second memory unit using a virtual address.

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