Dynamic logarithmic read-out circuits

Abstract

Described herein are techniques to enable dynamic logarithmic read-out circuits. One embodiment provides an apparatus including a plurality of bit lines intersecting with a plurality of word lines; a plurality of cross-point devices, wherein each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines; and a read-out circuit selectively connected to at least one of the bit lines, wherein the read-out circuit comprises a voltage-to-current conversion circuit and a logarithmic circuit, wherein the logarithmic circuit is configured to convert a current into a logarithmic voltage response.

Description

DYNAMIC LOGARITHMIC READ-OUT CIRCUITS CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefits of U.S. Provisional Application No.63 / 661,702, entitled “DYNAMIC LOGARITHMIC READ-OUT CIRCUITS,” filed June 19, 2024, which is incorporated herein in its entirety. BACKGROUND

[0002] A crossbar circuit may refer to a circuit structure with interconnecting electrically conductive lines sandwiching a memory element, such as a resistive switching material, at their intersections. Crossbar circuits may be used to implement in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding.

[0004] FIG.1 is a diagram illustrating an example of a crossbar circuit in accordance with some embodiments of the present disclosure.

[0005] FIGS.2A and 2B are schematic diagrams illustrating example cross-point devices and in accordance with some embodiments of the present disclosure

[0006] FIGS.3A, 3B, and 3C are circuit diagrams illustrating read-out circuit and schemes. Attorney Docket No. TEM-200520.0082-PCT

[0007] FIGS.4A, 4B, 4C, and 4D depict example read-out circuits in accordance with one implementation of the present disclosure.

[0008] FIG.5 is a flowchart illustrating an example process for performing in-memory computing using a crossbar circuit. DETAILED DESCRIPTION

[0009] The implementations of the disclosure relate generally to electronic circuits and, more specifically, to dynamic logarithmic read-out circuits. The read-out circuit described herein may be incorporated into crossbar circuits for in-memory computing.

[0010] A crossbar circuit may refer to a circuit structure with interconnecting electrically conductive lines sandwiching a memory element, such as a resistive switching material, at their intersections. The resistive switching material may include, for example, a memristor (also referred to as resistive random-access memory (RRAM or ReRAM)). Crossbar circuits may be used to implement in-memory computing applications, non- volatile solid-state memory, image processing applications, neural networks, etc.

[0011] Aspects of the disclosure provide read-out circuits utilizing logarithmic circuits. The read-out circuits may be used to implement crossbar circuits including intersecting electrically conductive wires (e.g., row lines, column lines, etc.) and cross-point devices arranged in one or more arrays. Each of the cross-point devices may be connected to a word line, a bit line, and a select line. The cross-point devices may include, for example, a phase-change memory (PCM) device, a floating gate device, a spintronic device, a ferroelectric device, a resistive random-access memory (RRAM) device, etc. The crossbar circuits may be used for multi-level memory (MLM) circuits and in-memory computing (IMC) circuits. Attorney Docket No. TEM-200520.0082-PCT

[0012] The present disclosure provides a logarithmic readout circuit that utilizes the charge-based scheme but realizes the linear relationship between input / weights and output. This circuit eliminates the DC current consumption for the memory array, which often accounts for the majority of the IMC macro's power usage. Because it preserves the linearity of the VMM operation, digital post-processing is no longer required.

[0013] FIG.1 is a diagram illustrating an example 100 of a crossbar circuit in accordance with some embodiments of the present disclosure. As shown, crossbar circuit 100 may include a plurality of interconnecting electrically conductive wires, such as one or more row wires 111a, 111b, ..., 111i, ..., 111n, and column wires 113a, 113b, ..., 113j, ..., 113m for an n-row by m-column crossbar array. The crossbar circuit 100 may further include cross-point devices 120a, 120b, ..., 120z, etc. Each of the cross-point devices may connect a row wire and a column wire. For example, the cross-point device 120ij may connect the row wire 111i and the column wire 113j. The number of the column wires 113a-m and the number of the row wires 111a-n may or may not be the same. Crossbar circuit 100 may further include a word line (WL) logic 105 that is connected to the cross-point devices via the row wires 111a-n. The WL logic 105 may include any suitable component for applying input signals to selected cross-point devices via row wires 111a-n, such as one or more digital-to-analog converters (DACs), amplifiers, etc. Each of the input signals may be a voltage signal, a current signal, etc.

[0014] Row wires 111a-n may include a first row wire 111a, a second row wire 111b, .. ., 111i, ..., and an n-th row wire 111n. Each of row wires 111a, ..., 111n may be and / or include any suitable electrically conductive material. In some embodiments, each row wire 111a-n may be a metal wire. Attorney Docket No. TEM-200520.0082-PCT

[0015] Column wires 113a-113m may include a first column wire 113a, a second column wire 113b, ..., and an m-th column wire 113m. Each column wire 113a-m may be and / or include any suitable electrically conductive material. In some embodiments, each column wire 113a-m may be a metal wire. In some embodiments, each row wire 111a-n may be a word line, and each column wire 113a-m may be a bit line.

[0016] Each cross-point device 120a-120z may be and / or include any suitable device with tunable resistance, such as a memristor, phase-change memory (PCM) devices, floating gates, spintronic devices, ferroelectric devices, RRAM devices, etc.

[0017] Each row wire 111a-111n may be connected to one or more row switches 131 (e.g., row switches 131a, 131b, ..., 131n). Each row switch 131 may include any suitable circuit structure that may control the current flowing through row wires 111a- 111n. For example, row switches 131 may be and / or include a CMOS switch circuit.

[0018] Each column wire 113a-m may be connected to one or more column switches 133 (e.g., switches 133a, ..., 133m). Each column switch 133a-133m may include any suitable circuit structure that may control current passing through column wires 113a-m. For example, column switches 133a-m may be and / or include a CMOS switch circuit. In some embodiments, one or more of switches 131a-n and 133a-m may further provide fault protection, electrostatic discharge (ESD) protection, noise reduction, and / or any other suitable function for one or more portions of crossbar circuit 100.

[0019] Output sensor(s) 140 may include one or more read-out circuits 141 and analog- to-digital converters (ADCs) 143 that may convert output voltages of read-out circuits 141 into digital outputs. Read-out circuit 141 may include a voltage-to-current (V-to-I) converter that may convert a bit line voltage VBLon a given bit line to a bit line currentIBLand a logarithmic circuit configured to convert the current passing through it into aAttorney Docket No. TEM-200520.0082-PCTlogarithmic voltage response. The logarithmic circuit may convert the BL current to an output voltage VOUT. The logarithmic circuit may include one or more diodes, BJT, etc. Voutis linearly proportional to the total conductance GTOTALof the cross-point devices that are connected to the bit line. Read-out circuit 141 may further include one or more resistors, op-amps, transistors, etc. Read-out circuit 141 may include read-out circuits 400a, 400b, 400c, and 400d as described in connection with FIGS.4A-4D below.

[0020] Programming circuit 160 may program the cross-point devices 120a-z selected by switches 131 and / or 133 to suitable conductance values. For example, programming a cross-point device may involve applying a suitable voltage signal or current signal across the cross-point device. The resistance of each cross-point device may be electrically changed between high-resistance and low-resistance. Setting a cross-point device may involve changing the resistance of the cross-point from high-resistance to low-resistance. Resetting the cross-point device may involve changing the resistance of the cross-point from low-resistance to high-resistance.

[0021] Crossbar circuit 100 may perform parallel weighted voltage multiplication. For example, an input voltage signal may be applied to one or more rows of crossbar circuit 100 (e.g., one or more selected rows). The input signal may flow through the cross-point devices of the rows of the crossbar circuit 100. The conductance of the cross-point device may be tuned to a specific value (also referred to as a “weight”). By Ohm’s law, the input voltage multiplies the cross-point conductance and generates a current from the cross-point device. By Kirchhoff’s law, the sum of the currents passes through the activated cross-point devices on a respective column (also referred to as the “bit line current”), which may be read from the column. According to Ohm’s law and Kirchhoff’s current law, the input-output relationship of the crossbar array can be represented as Attorney Docket No. TEM-200520.0082-PCTI=VG, wherein I represents the output signal matrix as current; V represents the input signal matrix as voltage; and G represents the conductance matrix of the cross-point devices. As such, the input signal is weighted at each of the cross-point devices by its conductance according to Ohm’s law. The weighted current (the “bit line current”) is output via each column wire and may be accumulated according to Kirchhoff’s current law. This may enable in-memory computing (IMC) via parallel multiplications and summations performed in the crossbar arrays.

[0022] Crossbar circuit 100 may be configured to perform vector-matrix multiplication (VMM). A VMM operation may be represented as Y=XA, wherein each of Y, X, A represents a respective matrix. More particularly, for example, input vector X may be mapped to the input voltage V of crossbar circuit 100. Matrix A may be mapped to conductance values G. The output current I may be read and mapped back to output results Y. In some embodiments, crossbar circuit 100 may be configured to implement a portion of a neural network by performing VMMs.

[0023] To perform a VMM operation, one or more cross-point devices of crossbar circuit 100 may be programmed to predetermined conductance values. The bit line(s) connected to the cross-point devices may be connected to a voltage source to be charged to a read voltage. The BLs may then be disconnected from the voltage source and discharged through the cross-point devices. The discharging time may be controlled by a pulse applied on the WL(s) connected to the selected cross-point devices. After the discharge of the BLs, a read-out circuit 141 may sense out the remaining BL voltage on a bit line and convert it back to a voltage signal Vout. For example, the V-to-I conversion circuit of the read-out circuit 141 may convert the remaining BL voltage into a current signal. Attorney Docket No. TEM-200520.0082-PCTThe logarithmic circuit may convert the current signal back to the voltage signal Vout. An ADC may then convert the voltage signal Vout into a digital signal.

[0024] In some embodiments, crossbar circuit 100 may perform convolution operations. For example, performing 2D convolution on input data may involve applying a single convolution kernel to the input signals. Performing a depthwise convolution on the input data may involve convolving each channel of the input data with a respective kernel corresponding to the channel and stacking the convolved outputs together. The convolution kernel may have a particular size defined by multiple dimensions (e.g., a width, a height, a channel, etc.). The convolution kernel may be applied to a portion of the input data having the same size to produce an output. The output may be mapped to an element of the convolution result that is located at a position corresponding to the position of the portion of the input data.

[0025] FIGS.2A and 2B are schematic diagrams illustrating example cross-point devices 1220a and 1220b in accordance with some embodiments of the present disclosure. Cross-point device 1220a and cross-point device 1220b may be referred to as a 1-transistor-1-resistor (1T1R) configuration.

[0026] As shown in FIGS.2A and 2B, a cross-point device 1220a or 1220b may include an RRAM device 1201 and a transistor 1203 that are connected in series. A transistor may include four terminals that may be marked as gate (G), source (S), drain (D), and bulk (B) (not shown in FIGS.2A and 2B), respectively. Referring to FIG.2A, the first terminal of RRAM device 1201 may be connected to the drain of transistor 1203. A second terminal of RRAM device 1201 may be connected to a bit line 1211. The source of the transistor 1203 may be connected to a word line 1215. The gate of transistor 1203 may be connected to a select line 1213. Attorney Docket No. TEM-200520.0082-PCT

[0027] As shown in FIG.2B, the second terminal of RRAM device 1201 may be connected to the word line 1215, and the source of the transistor 1203 may be connected to a bit line 1211 in some embodiments. Word line 1215 may correspond to a row wire 111a-n of FIG.1. Bit line 1211 may correspond to a column wire 123a-m of FIG.1.

[0028] Transistor 1203 may function as a selector as well as a current controller and may set the current compliance to RRAM device 1201 during programming. The gate voltage on transistor 1203 can set current compliances to cross-point device 1220a-b during programming and can thus control the conductance and analog behavior of cross-point device 1220a-b. For example, when cross-point device 1220a-b is set from a high- resistance state to a low-resistance state, a set signal (e.g., a voltage signal, a current signal) may be provided via bit line (BL) 1211 or word line (WL) 1215. Another voltage, also referred to as a select voltage or gate voltage, may be applied via select line (SEL) 1213 to the transistor gate to open the gate and set the current compliance, while word line (WL) 1215 or bit line (BL) 1211 may be grounded. When cross-point device 1220a- b is reset from the low-resistance state to the high-resistance state, a gate voltage may be applied to the gate of transistor 1203 via select line 1213 to open the transistor gate. Meanwhile, a reset signal may be sent to RRAM device 1201 via word line 1215 or bit line 1211, while bit line 1211 or word line 1215 may be grounded.

[0029] FIGS.3A, 3B, and 3C are circuit diagrams illustrating prior art read-out circuit and schemes.

[0030] As shown in FIG.3A, word lines (WL), bit line (BL) and select lines (SL) are connected to supply voltages all the time during a VMM operation. Multi-bit weight stored in memristor cells as conductance. Memristor cells consume constant current during the VMM operation. Cell current in the same column is accumulated on BL. BL Attorney Docket No. TEM-200520.0082-PCTcurrent is converted into a voltage usually by TIA or integrator or other I to V conversion circuits. The output voltage of TIA or integrator is converted into digital output by an ADC.

[0031] FIG.3B illustrates a first charge-based scheme for implementing a read-out circuit. In this scheme, the bit line (BL) is pre-charged to a read voltage. The word line (WL) turns on for a short period of time, during which the BL voltage is discharged based on the RC time constant. The voltage VBL(t) is given by the following formula:

[0032] VBL(t)=VRead x e^(-t x Gtotal / CBL).

[0033] A readout circuit may be used to linearly convert VBL to VOUT to achieve programmable gain. Memristor cells do not consume DC current during VMM operation. However, the output voltage is not linear to the memristor conductance.

[0034] The plot in FIG.3B shows the output voltage (Vout) as a function of time (in seconds) on a nanosecond scale. The plot illustrates an exponential decay of the voltage over time for different initial values. A red vertical line marks a specific time point on the graph, highlighting a particular moment during the decay process. This indicates the point at which the BL voltage is sampled for readout purposes. The various curves demonstrate how the output voltage decreases exponentially, influenced by different RC time constants.

[0035] FIG.3C illustrates a second charge-based scheme for implementing a read-out circuit. In this scheme, the bit line (BL) is pre-charged to read voltage. The word line (WL) turns on for a short period, during which the BL voltage is discharged based on the RC time constant. Instead of sensing the BL voltage, the scheme senses the discharging time when the BL voltage drops below a reference voltage. The timing information is then converted to digital output through an ADC. Similar to the current-based scheme Attorney Docket No. TEM-200520.0082-PCTand the first charge-based scheme described above, the discharge time is also not linear to the memristor conductance.

[0036] The plot in FIG.3C shows the output voltage (Vout) as a function of time (in seconds) on a nanosecond scale. It illustrates the exponential decay of voltage over time for various initial conditions. A horizontal red line represents a reference voltage level. The plot indicates the point in time where each voltage curve crosses the reference voltage, demonstrating the time at which the bit line (BL) voltage drops below the reference voltage. This time is used for sensing and converting to digital output.

[0037] FIGS.4A, 4B, 4C, and 4D depict example read-out circuits in accordance with one implementation of the present disclosure.

[0038] In some embodiments, as shown in FIG.4A, each bit line (BL) may be connected to a respective logarithmic read-out circuit as described herein. For example, a first read- out circuit 410 is connected to a first bit line BL<0>. A second read-out circuit 420 may be connected to a second bit line Bl<1>. The nth read-out circuit may be connected to the nth bit line. The output voltage of the logarithmic read-out circuit is linearly proportional to the total conductance of the cross-point devices that are connected to the respective BL and selected for programming / in-memory computing. The output voltage of the logarithmic read-out circuit is provided to an ADC to generate a respective digital output (e.g., output <0>, output <1>, ..., output <n>). A first ADC may connect the output voltage of the first read-out circuit to a first digital output (Output <0>). A second ADC may convert the output voltage of the second read-out circuit to a second digital output (Output <1>). Each of the read-out circuits may include a read-out circuit 400a, 400b, 400c, and / or 400d. Attorney Docket No. TEM-200520.0082-PCT

[0039] Read-out circuit 400a may include a voltage-to-current converter that may convert a bit line voltage VBLto a bit line current IBL. Read-out circuit 400a may further include a logarithmic circuit that may convert the BL current IBLto an output voltage VOUT. The logarithmic circuit may include one or more diodes, BJT, etc. Vout is linearly proportional to the total conductance GTOTAL. Read-out circuit 400a may further include one or more resistors, op-amps, transistors, etc. VDD-VOUT(t) = VTx log(IBL(t) / IS) = VTx log(VBL(t) / RL / IS) = x Gtotal / CBLx t

[0040] As shown in FIG.4B, read-out circuit 400b may include a voltage-to-current conversion circuit that includes one or more op-amps. The op-amp based activity circuit may provide drivability to the loading capacitor.

[0041] In some embodiments, the diode and the voltage to current conversion circuit may be combined. For example, read-out circuit 400c depicts an example of such implementation.

[0042] As shown in FIG.4D, the diode may be combined with the voltage-to-current converter. Use op-amp based active circuit to implement the programmable gain as follows: VOUT= VBLx (1+R2 / R1) - VDIODEx (R2 / R1)

[0043] FIG.5 is a flowchart illustrating an example process for performing in-memory computing using a crossbar circuit.

[0044] At 510, a plurality of cross-point devices of the crossbar circuit may be programmed to predetermined conductance values. Each of the cross-point devices may be connected to a bit line and a word line of the crossbar circuit.

[0045] At 520, each bit line connected to the cross-point devices may be connected to a voltage source to be charged to a read voltage. Attorney Docket No. TEM-200520.0082-PCT

[0046] At 530, the bit line(s) may be disconnected from the voltage source and discharged through the cross-point devices. The discharging time may be controlled by a pulse applied on the WL(s) connected to the selected cross-point devices.

[0047] At 540, one or more read-out circuits may sense out the remaining BL voltage on each bit line and generate an output voltage. For example, a V-to-I conversion circuit of the first read-out circuit may convert the remaining BL voltage on the first bit line into a first current signal. A logarithmic circuit of the first read-out circuit may convert the first current signal into the voltage signal Vout.

[0048] At 550, one or more ADCs may convert the output voltages into digital outputs.

[0049] The terms “approximately,” “about,” and “substantially” as used herein may mean within a range of normal tolerance in the art, such as within 2 standard deviations of the mean, within ±20% of a target dimension in some embodiments, within ±10% of a target dimension in some embodiments, within ±5% of a target dimension in some embodiments, within ±2% of a target dimension in some embodiments, within ±1% of a target dimension in some embodiments, and yet within ±0.1% of a target dimension in some embodiments. The terms “approximately” and “about” may include the target dimension. Unless specifically stated or obvious from context, all numerical values described herein are modified by the term “about.”

[0050] As used herein, a range includes all the values within the range. For example, a range of 1 to 10 may include any number, combination of numbers, sub-range from the numbers of 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10 and fractions thereof.

[0051] In the foregoing description, numerous details are set forth. It will be apparent, however, that the disclosure may be practiced without these specific details. In some Attorney Docket No. TEM-200520.0082-PCTinstances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the disclosure.

[0052] The terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation.

[0053] The words "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Reference throughout this specification to "an implementation" or "one implementation" means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrase "an implementation" or "one implementation" in various places throughout this specification are not necessarily all referring to the same implementation.

[0054] As used herein, when an element or layer is referred to as being “on” another element or layer, the element or layer may be directly on the other element or layer, or Attorney Docket No. TEM-200520.0082-PCTintervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” another element or layer, there are no intervening elements or layers present.

[0055] Whereas many alterations and modifications of the disclosure will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as the disclosure. Attorney Docket No. TEM-200520.0082-PCT

Claims

WHAT IS CLAIMED IS:

1. An apparatus, comprising: a plurality of bit lines intersecting with a plurality of word lines; a plurality of cross-point devices, wherein each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines; and a read-out circuit selectively connected to at least one of the bit lines, wherein the read-out circuit comprises a voltage-to-current conversion circuit and a logarithmic circuit, wherein the logarithmic circuit is configured to convert a current into a logarithmic voltage response.

2. The apparatus of claim 1, wherein the logarithmic circuit comprises a diode.

3. The apparatus of claim 1, wherein the logarithmic circuit comprises a Bipolar Junction Transistor (BJT).

4. The apparatus of claim 1, wherein the voltage-to-current converter comprises an op-amp.

5. The apparatus of claim 1, wherein the voltage-to-current converter comprises a plurality of op-amps.

6. The apparatus of claim 1, wherein an output voltage of the read-out circuit is linearly proportional to the total conductance of a plurality of cross-point devices Attorney Docket No. TEM-200520.0082-PCTconnected to the first-bit line, wherein the output voltage of the read-out circuit corresponds to the logarithmic voltage response.

7. The apparatus of claim 1, wherein the cross-point devices comprise at least one of a memristor, a phase-change memory (PCM) device, a floating gate device, a spintronic device, a ferroelectric device, or a resistive random-access memory (RRAM) device.

8. A method, comprising: programming a plurality of cross-point devices of a crossbar circuit to predetermined conductance values, wherein each of the cross-point devices is connected to a bit line and a word line of the crossbar circuit; charging each bit line connected to the cross-point devices to a read voltage; discharging the bit lines through the cross-point devices; after the discharging, converting, using one or more read-out circuits, bit lines voltages on the bit lines into a plurality of output voltages; and generating one or more digital outputs based on the plurality of output voltages.

9. The method of claim 8, wherein converting, using the one or more read-out circuits, the bit lines voltages on the bit lines into the plurality of output voltages comprises: converting, using a first read-out circuit, a first bit line voltage on a first bit line into a first current signal after the discharging of the first bit line; and Attorney Docket No. TEM-200520.0082-PCTconverting, using a logarithmic circuit of the first read-out circuit, the first current signal into a first output voltage.

10. The method of claim 9, wherein generating the one or more digital outputs based on the plurality of output voltages comprises converting, using a first ADC, the first output voltage into a first digital output.

11. The method of claim 8, wherein charging each bit line connected to the cross- point devices to the read voltage comprises connecting each bit line to a voltage source, and wherein discharging the bit lines through the cross-point devices comprises disconnecting the bit lines from the voltage source.

12. The method of claim 11, further comprising applying a pulse on the word lines connected to the cross-point devices to control the discharging time of the bit lines. Attorney Docket No. TEM-200520.0082-PCT

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