Three-dimensional memory array and preparation method therefor, and electronic device

Abstract

A three-dimensional memory array and a preparation method therefor, and an electronic device. The three-dimensional memory array comprises a first memory cell array, which comprises a plurality of memory cells stacked in a vertical direction, a plurality of word lines, and at least one bit line. Each memory cell comprises a transistor and a storage node which are coupled in a horizontal direction and are connected in parallel to each other, wherein the transistors in the plurality of memory cells in the vertical direction are connected to each other in series, and / or the storage nodes in the plurality of memory cells in the vertical direction are connected to each other in series. The plurality of word lines are arranged at intervals in the vertical direction and are respectively connected to the transistors in the plurality of memory cells in the vertical direction. The bit line extends in the vertical direction and is connected to the transistors in the plurality of memory cells in the vertical direction. The three-dimensional memory array can at least achieve a high-density memory array and improve the problem of crosstalk.

Description

Three-dimensional memory array, method of manufacturing the same, and electronic device

[0001] This application claims priority from the Chinese patent application No. 202410831274.9 filed on June 25, 2024, and entitled "Three-dimensional memory array, method of manufacturing the same, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a three-dimensional memory array, a method of manufacturing the same, and an electronic device. BACKGROUND

[0003] The development of memory pursues performance indicators such as high speed, high integration density, and low power consumption. With the miniaturization of semiconductor device structures, the technical barriers encountered by existing structures become more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers.

[0004] The emergence of three-dimensional memory meets the above-mentioned needs. However, three-dimensional memory has a serious crosstalk between adjacent storage bits, significantly increases power consumption and reduces read-write window and read-write speed, and has complex wiring, occupies a large area, reduces the effective storage array area, and affects the performance of the device.

[0005] SUMMARY

[0006] According to a first aspect of embodiments of the present disclosure, a three-dimensional memory array is provided, comprising a first storage cell array, comprising: a plurality of storage cells stacked in a vertical direction, each storage cell comprising a transistor and a storage node coupled in a horizontal direction, and connected in parallel with each other, wherein the transistors in the plurality of storage cells in the vertical direction are connected in series with each other, and / or the storage nodes in the plurality of storage cells in the vertical direction are connected in series with each other; a plurality of word lines arranged at intervals in the vertical direction and connected to the transistors in the plurality of storage cells in the vertical direction, respectively; and at least one bit line extending in the vertical direction and connected to the transistors in the plurality of storage cells in the vertical direction.

[0007] In some embodiments, the storage nodes in the plurality of storage cells in the vertical direction are connected in series with each other comprises: a plurality of electrodes and a plurality of storage media arranged alternately in the vertical direction, wherein adjacent storage nodes in the plurality of storage cells in the vertical direction share an electrode.

[0008] In some embodiments, the storage medium is selected from any one of a capacitive storage medium, a ferroelectric storage medium, a magnetic storage medium, a phase change storage medium, and a resistive switching storage medium.

[0009] In some embodiments, the transistors in the plurality of memory cells in the vertical direction are connected in series with each other, comprising: a semiconductor layer extending in the vertical direction and located on one side of the memory node in the horizontal direction, the semiconductor layer being coupled to the memory node in the horizontal direction, the semiconductor layer being connected to the bit line; a dielectric layer extending in the vertical direction and located on the surface of the semiconductor layer; a plurality of gates arranged in the vertical direction at intervals and located on the surface of the dielectric layer, the gates being connected to the word line; wherein the semiconductor layer comprises a plurality of source / drain regions and a plurality of channel regions arranged alternately, and the source / drain regions are shared by adjacent transistors in the plurality of memory cells in the vertical direction.

[0010] In some embodiments, the semiconductor layer is selected from at least one of single crystal silicon, polycrystalline silicon, molybdenum disulfide, indium tin oxide, indium gallium zinc oxide, zinc indium oxide, and gallium indium oxide.

[0011] In some embodiments, the semiconductor layer is conformally located on the surface of the plurality of electrodes of the memory node and the plurality of storage media, wherein the plurality of source / drain regions in the semiconductor layer are connected to the plurality of electrodes, and the plurality of channel regions in the semiconductor layer are connected to the plurality of storage media, so that the transistors and the memory node are coupled in the horizontal direction and connected in parallel with each other.

[0012] In some embodiments, the semiconductor layer has a plurality of recesses protruding towards the plurality of storage media, and the plurality of gates are located in the plurality of recesses, respectively.

[0013] In some embodiments, the semiconductor layer and the dielectric layer extend in the vertical direction and have a vertical surface, and the gate is located on one side of the dielectric layer and connected to the word line.

[0014] In some embodiments, the semiconductor layer and the storage media further comprise an insulating dielectric layer.

[0015] In some embodiments, the bit line is shared by the semiconductor layers of the plurality of transistors in the vertical direction.

[0016] In some embodiments, the material between the electrodes in the memory node and the gates in the transistors is different.

[0017] In some embodiments, the three-dimensional memory array further comprises a second memory cell array, and the second memory cell array and the first memory cell array are mirror symmetric to each other.

[0018] According to a second aspect of embodiments of the present disclosure, a method for manufacturing a three-dimensional memory array is provided. The method includes forming a first memory cell array, which includes: forming a plurality of memory cells stacked along a vertical direction, each memory cell including a transistor and a storage node coupled in a horizontal direction, and connected in parallel with each other, wherein the transistors in the plurality of memory cells in the vertical direction are connected in series with each other, and / or the storage nodes in the plurality of memory cells in the vertical direction are connected in series with each other; forming a plurality of word lines spaced apart along the vertical direction, the plurality of word lines being connected to the transistors in the plurality of memory cells in the vertical direction, respectively; and forming at least one bit line extending along the vertical direction, the at least one bit line being connected to the transistors in the plurality of memory cells in the vertical direction.

[0019] In some embodiments, the method further includes forming a second memory cell array that is mirror-symmetrical to the first memory cell array.

[0020] In some embodiments, the method includes: providing a substrate, and a stack of a plurality of electrode materials and a plurality of storage medium materials arranged alternately on the substrate; forming at least one first trench extending along a second horizontal direction through the stack, the stack being divided into at least a first memory cell array and a second memory cell array; forming at least two second trenches extending along a first horizontal direction through the stack, the at least two second trenches being spaced apart along the first horizontal direction, and each second trench extending along the second horizontal direction, the first horizontal direction being perpendicular to the second horizontal direction; etching part of the storage medium materials along the second trenches to form a plurality of side cavities spaced apart along the vertical direction, and the remaining plurality of electrode materials and plurality of storage medium materials being formed into electrodes and storage medium, respectively; forming a semiconductor layer conformally on surfaces of the plurality of electrodes exposed along the second trenches and surfaces of the plurality of storage medium exposed along the plurality of side cavities; forming a dielectric layer on surfaces of the semiconductor layer exposed along the second trenches and the plurality of side cavities; and forming a plurality of gates on surfaces of the dielectric layer exposed along the plurality of side cavities.

[0021] In some embodiments, the method further includes: etching the electrodes and the storage medium, and the dielectric layer and the semiconductor layer in the stack along the first horizontal direction downward to form a plurality of memory cells spaced apart along the second horizontal direction, wherein the word lines are reserved and extend along the second horizontal direction, and each word line is connected to the transistors in the plurality of memory cells along the second horizontal direction.

[0022] In some embodiments, before forming the semiconductor layer, the method further includes: forming a plurality of insulating dielectric layers respectively on surfaces of the plurality of storage medium within the plurality of side cavities.

[0023] In some embodiments, the bit line is formed simultaneously with the semiconductor layer.

[0024] In some embodiments, the storage medium is selected from any one of a capacitive storage medium, a ferroelectric storage medium, a magnetic storage medium, a phase change storage medium, and a resistive switching storage medium.

[0025] According to a third aspect of the embodiments of the present disclosure, an electronic device is provided, comprising: a processing device; and a memory device electrically connected to the processing device, the memory device comprising the three-dimensional storage array described above, and a controller configured to control reading and writing of the three-dimensional storage array.

[0026] In the embodiments of the present disclosure, a three-dimensional storage array is provided, by providing a plurality of storage units stacked in a vertical direction, each storage unit comprising a transistor and a storage node coupled in a horizontal direction, and by connecting the transistor and the storage node in parallel with each other, connecting the transistors in the plurality of storage units in the vertical direction in series with each other, and / or connecting the storage nodes in the plurality of storage units in the vertical direction in series with each other, the wiring is simple, the maximum vertical stacking density is achieved, and the adjacent storage bits are controlled to be selected by the parallel transistors, effectively avoiding the crosstalk problem of the existing three-dimensional memory structure, and improving the device performance. BRIEF DESCRIPTION OF DRAWINGS

[0027] FIG. 1 is a circuit schematic diagram of a three-dimensional storage array according to an example embodiment;

[0028] FIG. 2 is a perspective view of a three-dimensional storage array according to an example embodiment;

[0029] FIG. 3 is a plan view of the three-dimensional storage array in FIG. 2;

[0030] FIG. 4 is a perspective view of a three-dimensional storage array according to another example embodiment;

[0031] FIGS. 5 to 18 are cross-sectional views of a semiconductor device manufacturing process according to example embodiments;

[0032] FIG. 19 is a structural schematic diagram of an electronic device according to an example embodiment. DETAILED DESCRIPTION

[0033] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the example implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] The present disclosure is described more by way of example with reference to the following drawings. The advantages and features of the disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understand that the drawings depict only very simplified examples and are not intended to be precise in scale or proportion, but merely to aid in the explanation of the embodiments of the present disclosure.

[0035] It can be understood that the meaning of "on", "above" and "upper" in the present disclosure should be interpreted in the broadest way, so that "on" not only means the meaning of "on" something and there is no intervening feature or layer between them (i.e. directly on something), but also includes the meaning of "on" something and there is an intervening feature or layer between them.

[0036] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0037] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0038] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0039] FIG. 1 is a circuit schematic diagram of a three-dimensional memory array according to an example embodiment. FIG. 2 is a perspective view of a three-dimensional memory array according to an example embodiment. FIG. 3 is a plan schematic diagram of the three-dimensional memory array in FIG. 2.

[0040] Referring to FIGS. 1-3, the three-dimensional memory array in the embodiments of the present disclosure includes a substrate 100 and a plurality of memory cell arrays, such as a first memory cell array MA and a second memory cell array MB, disposed on the substrate 100. The first memory cell array MA and the second memory cell array MB are alternately and spacedly arranged on the substrate 100 to form a three-dimensional memory array, such as MA, MB, MA, MB, and so on. The memory cell arrays are isolated from each other by an isolation structure, which can include at least one of silicon oxide, silicon nitride, or silicon oxynitride (FIG. 2 shows a perspective view of the three-dimensional memory array, and thus some of the isolation structures are omitted). The first memory cell array MA and the second memory cell array MB are mirror-symmetrical to each other. Each memory cell array, such as the first memory cell array MA, includes a plurality of memory cells 201, a plurality of word lines 202, and at least one bit line 203. The plurality of memory cells 201 in the embodiments of the present disclosure are stacked in a vertical direction Z. Each memory cell 201 includes a transistor 220 and a storage node 210, which are coupled to each other in a horizontal direction, such as a first horizontal direction X, and are connected in parallel to each other. The transistors 220 in the plurality of memory cells 201 in the vertical direction Z are connected in series to each other. The storage nodes 210 in the plurality of memory cells 201 in the vertical direction Z are connected in series to each other.

[0041] In the embodiments of the present disclosure, the first memory cell array MA and the second memory cell array MB are described as an example of forming mirror-symmetrical memory cell arrays. It can be understood that a three-dimensional memory array with higher storage density can be obtained by arranging the first memory cell array MA and the second memory cell array MB as described above.

[0042] Referring to FIGS. 2-3, the substrate 100 can include silicon, such as single-crystal silicon, polycrystalline silicon, or amorphous silicon, and can also be selected from at least one of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0043] Please refer to FIG. 1 and FIG. 2, the storage node (SN) 210 and the transistor (TR) 220 of each storage unit 201 in the embodiment of the present disclosure are coupled in the horizontal direction, for example, the first horizontal direction X, and are connected in parallel with each other. Each storage node 210 includes an upper electrode, a storage medium, and a lower electrode. Each transistor 220 includes a source, a drain, and a gate. The two electrodes of the storage node 220 are respectively connected to the source and the drain of the transistor 220, thereby realizing the parallel connection between the transistor 220 and the storage node 210. By connecting the transistor 220 and the storage node 210 in parallel in the storage unit 201, the storage units 201 can be controlled to be selected by the parallel transistor when forming a three-dimensional storage array, thereby effectively avoiding the crosstalk problem of the 3D structure, for example, the X-POINT structure.

[0044] Please continue to refer to FIG. 1, the gate of the transistor 220 is connected to the word line (WL) 202. The source and the drain of the adjacent transistors 220 in the upper and lower layers are shared, that is, the source of the transistor 201 in the lower layer is connected to the drain of the transistor 201 in the upper layer, and is commonly connected to the same bit line (BL) 203. The bit line 203 is connected in series to the plurality of storage units 201 along the vertical direction Z, that is, all the transistors 220 of the same bit line 203 are connected in series, and / or all the storage nodes 210 of the same bit line 203 are connected in series. When performing a read / write operation, the target transistor TRx corresponding to the target storage node SNx is turned off, while all the other transistors TR are turned on. The upper and lower ends of the bit line 203, the BL end and the BL' end, are biased with different voltages according to the write 0 or write 1 requirement. The BL end can be electrically connected to an external circuit through a contact plug for power supply, and the BL' end is connected to the substrate 100, and the power supply can be realized by the lower logic circuit or the hybrid bonding.

[0045] It is worth noting that in one embodiment of the present disclosure, if the channel of the transistor 220 is a conductive material (for example, the ITO material shown later) or a negative Vt semiconductor material (for example, the transistor 220 is a P-type transistor), when performing a read / write operation, the WL of the target transistor TRx corresponding to the target storage node SNx is biased with a negative voltage to turn off the target transistor TRx, and the BL end and the BL' end are biased with different voltages according to the write 0 or write 1 requirement. In another embodiment of the present disclosure, if the channel of the transistor 220 is a positive Vt semiconductor material (for example, the transistor 220 is an N-type transistor), when performing a read / write operation, the WL of all the transistors TR except the target transistor TRx corresponding to the target storage node SNx is biased with a positive voltage to turn on (only the target transistor TRx is turned off), and the BL end and the BL' end are biased with different voltages according to the write 0 or write 1 requirement.

[0046] Please continue to refer to FIG. 1 to FIG. 3, the plurality of storage nodes 210 are stacked along the vertical direction Z and connected to each other in series, for example. As an example, the plurality of storage nodes 210 stacked along the vertical direction Z include a plurality of electrodes 211 and a plurality of storage media 212, the electrodes 211 and the storage media 212 are arranged alternately along the vertical direction Z, and the electrodes are shared between adjacent storage nodes 210 in the plurality of storage units 201 along the vertical direction Z. That is, between adjacent storage nodes 210, the upper electrode of the lower storage node is also the lower electrode of the upper storage node, so that through the structure of the embodiment of the present disclosure, the electrodes are shared between adjacent storage units of upper and lower layers, the process is simple, the plurality of storage nodes 210 are stacked along the vertical direction Z and connected to each other in series, and the maximum vertical stacking density can be achieved.

[0047] Please refer to FIG. 2 and FIG. 3, the plurality of electrodes 211 and the plurality of storage media 212 are arranged alternately along the vertical direction Z, and the electrodes 211 and the storage media 212 can extend along the horizontal direction, for example, the first horizontal direction X, for example, to form a horizontal capacitor in the form of a plate. In the embodiment of the present disclosure, the storage node capacitor is placed horizontally, which not only has a simple structure, but also can increase the area as needed to improve the capacitance. The material of the electrode 211 can be at least one of metal, metal nitride or metal oxide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), titanium oxide (TiO).

[0048] It is worth noting that the storage node 210 in the storage unit 201 can be selected from any one of a capacitive storage medium (such as DRAM), a ferroelectric storage medium (such as FeRAM, FTJ), a magnetic storage medium (such as MRAM), a phase change storage medium (such as PCRAM), and a resistive random access memory (such as RRAM), and the storage node in the embodiment of the present disclosure has excellent scalability and can be applied to various types of memories. The storage medium in the embodiment of the present disclosure takes a ferroelectric storage medium as an example to form a FeRAM, a non-volatile memory. The material of the ferroelectric storage medium can be selected from at least one of lead zirconium titanate (PZT), strontium bismuth titanate (SBT), bismuth lanthanum titanate (BLT), barium strontium titanate (BST), hafnium oxide with ferroelectricity (HfO2), zirconium oxide with ferroelectricity (ZrO), and hafnium zirconium oxide with ferroelectricity (HfZrO2), and further, a variety of doping elements such as lanthanum (La), yttrium (Y), titanium (Ti), and aluminum (Al) can also be used in the ferroelectric storage medium.

[0049] Referring back to FIGS. 1-3, the plurality of transistors 220 are stacked along the vertical direction Z and connected to each other, for example, in series. The plurality of transistors 220 include a plurality of gates 221, a plurality of dielectric layers 222, and a plurality of semiconductor layers 223. The plurality of semiconductor layers 223, the plurality of dielectric layers 222, and the plurality of gates 221 are located on one side of the plurality of storage nodes 210 along a horizontal direction, for example, the first horizontal direction X, and are coupled to the plurality of storage nodes 210 along a horizontal direction, for example, the first horizontal direction X. The plurality of semiconductor layers 223 and the plurality of dielectric layers 222 extend along the vertical direction Z, so that the transistors mainly extend along the vertical direction Z and have a small footprint in the horizontal direction, which not only provides a space for forming a storage node with a larger capacitance, but also facilitates forming a maximum stacking density in the vertical direction Z.

[0050] Referring back to FIGS. 2-3, the plurality of gates 221 are arranged at intervals along the vertical direction Z, and the gates 221 are connected to the word lines 202, for example, the gates 221 are part of the word lines 202. The material of the gates 221 can be at least one of doped polysilicon, metal, metal nitride, or metal carbide, for example, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), aluminum tantalum carbonitride (TaAlCN), and silicon tantalum carbonitride (TaSiCN). Notably, in the embodiments of the present disclosure, the material between the gates 221 and the electrodes 211 is different, so as to satisfy different etching selectivity ratios in the manufacturing process, and form a three-dimensional storage array with the expected structure.

[0051] Referring back to FIGS. 2-3, the plurality of dielectric layers 222 are located between the plurality of storage nodes 210 and the plurality of gates 221, and the plurality of dielectric layers 222 are a continuous whole extending along the vertical direction Z and shared by the plurality of dielectric layers 222 of the plurality of transistors 220 along the vertical direction Z. The plurality of dielectric layers 222 can be selected from at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric film with a dielectric constant higher than that of silicon oxide, for example, hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al2O3), tantalum oxide (Ta2O3), and lead scandium tantalum oxide (PbScTaO).

[0052] Please continue to refer to FIG. 2 and FIG. 3, the semiconductor layer 223 is located between the storage node 210 and the medium layer 222, two opposite surfaces of the semiconductor layer 223, one surface contacts the storage node 210, and is coupled with the storage node 210 in the horizontal direction, and the other surface contacts the medium layer 222, and the medium layer 222 is located on the surface of the semiconductor layer 223. The semiconductor layer 223 is the same as the medium layer 222, and is also a continuous whole, extending along the vertical direction Z, and the semiconductor layer 223 is connected to the bit line 203, for example, the semiconductor layer 223 is part of the bit line 203, and the bit line 203 can be shared, so that the semiconductor layer 223 of the plurality of transistors 220 along the vertical direction Z is shared through the bit line 203, that is, the plurality of transistors 220 are connected in series.

[0053] Please continue to refer to FIG. 2, the semiconductor layer 223 includes a plurality of source / drain regions 223a and a plurality of channel regions 223b, and the source / drain regions 223a and the channel regions 223b are arranged alternately in the semiconductor layer 223, wherein the source / drain regions 223a are shared between adjacent transistors 220 in the plurality of storage units 201 in the vertical direction Z. That is, between adjacent transistors 220, the source / drain region of the lower transistor is also the drain / source region of the upper transistor, so that through the structure of the embodiment of the present disclosure, the source / drain region is shared between adjacent storage units in the upper and lower layers, without a complex source / drain structure, and the process is simple, and the maximum vertical stacking density can be realized. The semiconductor layer 223 in the embodiment of the present disclosure can be a single crystal silicon, a polycrystalline silicon, a molybdenum disulfide (MoS2) or other two-dimensional material, or an oxide semiconductor material, such as at least one of indium tin oxide (ITO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and indium gallium oxide (IGO).

[0054] Please continue to refer to FIG. 2, the semiconductor layer 223 is conformally located on the surfaces of the plurality of electrodes 211 and the plurality of storage medium layers 212 stacked in the vertical direction Z, the plurality of source / drain regions 223a in the semiconductor layer 223 are connected with the plurality of electrodes 211, and the plurality of channel regions 223b in the semiconductor layer are connected with the plurality of storage medium layers 212, so that the transistor 210 and the storage node 220 are coupled in the horizontal direction, for example, the first horizontal direction X, and are connected in parallel with each other.

[0055] Please continue to refer to FIG. 2 to FIG. 3, in one embodiment of the present disclosure, the semiconductor layer 223 has a plurality of recesses, for example, protruding recesses formed at the channel region 223b towards the storage medium 212, for example, ferroelectric layer. Specifically, the storage medium 212 has a size in the horizontal direction, for example, the first horizontal direction X, which is smaller than the size of the electrode 211, so that when the semiconductor layer 223 is conformally located on the surface of the plurality of electrodes 211 and the surface of the plurality of storage media 212 from the side of the first horizontal direction X, the semiconductor layer 223 forms the plurality of recesses. The dielectric layer 222 is conformally located on the surface of the semiconductor layer 223, and also has corresponding recesses where the gate 221 is located, corresponding to the channel region 223b and the storage medium 212. In this embodiment, the gate 221 or the word line 202 is flush with one side of the dielectric layer 222, and does not protrude from the side of the dielectric layer 222. The recess is beneficial to form a stable gate 221, of course, it is not limited to this, in some other embodiments, for example, FIG. 4 shown later, shows other topography of the transistor 220. The semiconductor layer 230 extends along the vertical direction Z, and has a flush surface, and the semiconductor layer 230 is conformally located on the surface of the plurality of electrodes 211 and the surface of the plurality of storage media 212, for example, ferroelectric layer, from the side of the first horizontal direction X. The dielectric layer 222 also has a flush surface and is located on the surface of the semiconductor layer 223. The gate 221 is located on the surface of the dielectric layer 222, corresponding to the channel region 223b of the semiconductor layer 223. It can be understood that any scheme or topography that couples the transistor and the storage node in the horizontal direction and connects them in parallel with each other should be covered within the scope claimed by the present disclosure.

[0056] Please continue to refer to FIG. 3, the storage medium 212 and the channel region 223b of the semiconductor layer 223 can also include an insulating dielectric layer 224, for example, at least one selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), aluminum oxide (AlOx), aerogel, or air gap. The insulating dielectric layer 224 can reduce the capacitive coupling between the channel region 223b of the transistor 220 and the upper and lower electrodes 211 in the storage node 210, for example, a material with low dielectric constant can be selected.

[0057] Referring back to FIGS. 1-3, the first memory cell array MA in the three-dimensional memory array further includes a plurality of word lines 202 and at least one bit line 203. The plurality of word lines 202 are spaced apart along the vertical direction Z and are connected to the transistors 220, e.g., the gates 221, in the plurality of memory cells 201 along the vertical direction Z, respectively. Each of the word lines 202 extends along a horizontal direction, e.g., the second horizontal direction Y (e.g., perpendicular to the first horizontal direction X), so as to connect the transistors in the plurality of memory cells 201 along the second horizontal direction Y, e.g., when the plurality of memory cells 201 in the first memory cell array MA are spaced apart along the second horizontal direction Y. The bit line 203 extends along the vertical direction Z and is connected to the transistors 220, e.g., the semiconductor layer 223, in the plurality of memory cells 201 along the vertical direction Z. In some embodiments, the bit line 203 and the semiconductor layer 223 are shared, i.e., the semiconductor layer 223 also functions as the bit line 203 to carry signals out of the transistor 202. The transistors in the plurality of memory cells 201 along the second horizontal direction Y are connected by the plurality of bit lines, respectively.

[0058] FIG. 4 shows a cross-sectional view of another embodiment of a three-dimensional memory array. In this embodiment, the semiconductor layer 223 and the dielectric layer 222 do not include a recess and have vertical surfaces, and the gate 221 or the word line 202 is located aside the dielectric layer 222, e.g., on one side of the dielectric layer 222 along the first horizontal direction X and extends along the second horizontal direction Y. The three-dimensional memory array in FIG. 4 is substantially the same as the three-dimensional memory array described with reference to FIGS. 1-3. In this embodiment, the transistors 220 have a more regular shape and a simpler structure, which is beneficial to improve the performance of the device.

[0059] In some embodiments, a method of fabricating a three-dimensional memory array is provided. The method includes forming a first memory cell array, which includes: forming a plurality of memory cells stacked along a vertical direction, each of the memory cells including a transistor and a storage node coupled in a horizontal direction and connected in parallel to each other, wherein the transistors in the plurality of memory cells along the vertical direction are connected in series to each other and / or the storage nodes in the plurality of memory cells along the vertical direction are connected in series to each other; forming a plurality of word lines spaced apart along the vertical direction, the plurality of word lines being connected to the transistors in the plurality of memory cells along the vertical direction, respectively; and forming at least one bit line extending along the vertical direction, the bit line being connected to the transistors in the plurality of memory cells along the vertical direction.

[0060] FIGS. 5-18 are cross-sectional views of various stages in a method of fabricating a three-dimensional memory array according to embodiments of the present disclosure. Embodiments of the present disclosure are described by way of example with respect to forming mirror-symmetrical first memory cell array MA and second memory cell array MB. It is to be understood that more memory cell arrays can be formed simultaneously, spaced apart from each other on substrate 100, and isolated from each other by isolation layers (not all shown) to protect the three-dimensional memory array. The method of fabricating a three-dimensional memory array according to embodiments of the present disclosure will be described in detail below with respect to FIGS. 5-18.

[0061] Referring to FIG. 5, a substrate 100 is provided and a plurality of electrode materials 211' and a plurality of memory media materials, such as ferroelectric materials 212', are deposited in an alternating stack on the substrate 100. The electrode materials 211' are deposited first, covering the surface of the substrate 100, and then the memory media materials 212' are deposited, with the deposition of the electrode materials 211' and the memory media materials 212' being repeated alternately.

[0062] Referring to FIGS. 6-7, a first mask layer 110 is formed on the surface of the stack and patterned to form at least one first opening exposing the surface of the stack, and the stack is etched down along the first opening to form at least one first trench 110a extending through the stack. The at least one first trench 110a extends in a horizontal direction, such as a second horizontal direction Y, and divides the stack into a plurality of memory cell arrays spaced apart in a first horizontal direction X, such as a first memory cell array region MA and a second memory cell array region MB. Thereafter, referring to FIG. 7, an isolation material, such as silicon oxide, is deposited and planarized to form a first isolation layer 120a flush with the surface of the stack, such that the first isolation layer 120a isolates the plurality of memory cell array regions.

[0063] Referring to FIG. 8, a second mask layer 130 is formed on the surface of the stack and the first isolation layer 120a and patterned to form at least two second openings exposing the surface of the stack, and the stack is etched down along the second openings to form at least two second trenches 130a extending through the stack. The at least two second trenches 130a are spaced apart in the first horizontal direction X and each extends in the second horizontal direction Y, parallel to the first trench 110a. The at least two second trenches 130a are located on a side of the first memory cell array MA distal from the second memory cell array MB and on a side of the second memory cell array MB distal from the first memory cell array MA to facilitate forming transistors on opposite sides of the first memory cell array MA and the second memory cell array MB simultaneously.

[0064] Afterwards, referring to FIG. 9, the portion of the storage medium material 212’ in the stack is laterally etched, for example, by a dry etching process, to form a plurality of side cavities 130b spaced along the vertical direction z, which provides reserved locations for the subsequent formation of the gate 221. At this time, the remaining electrode material 211’ and the remaining storage medium material 212’ in the stack are formed into the electrode 211 and the storage medium 212, respectively. The plurality of electrodes 211 and the plurality of storage media 212 are arranged alternately along the vertical direction z to form a plurality of storage nodes 210 connected in series along the vertical direction z.

[0065] Referring to FIGS. 10-11, the plurality of side cavities 130b and the second trench 130a are communicated to form a comb-shaped open space, along which an insulating medium material 224’ is deposited, for example. After planarizing the insulating medium material 224’, a portion of the insulating medium material 224’ is removed again along the second trench 130a and the plurality of side cavities 130b, leaving the insulating medium material 224’ on the surface of the storage medium 212 in the plurality of side cavities 130b. At this time, the remaining insulating medium material 224’ is formed into a plurality of insulating medium layers 224. It can be understood that the insulating medium layer 224 can not be formed and the subsequent semiconductor layer 223 is directly formed. At this time, the semiconductor layer 223 will conformally be located on the surface of the plurality of electrodes 211 and the surface of the plurality of storage media 212.

[0066] Afterwards, referring to FIG. 12, the surface of the plurality of electrodes 211 exposed along the second trench 130a and the surface of the plurality of insulating medium layers 224 exposed along the plurality of side cavities 130b are conformally formed with a semiconductor layer 223, which extends along the vertical direction z. The space of the remaining plurality of side cavities 130b is formed into a plurality of recesses of the semiconductor layer 223. The semiconductor layer 223 is located on one side of the storage node 210 along the first horizontal direction X and is coupled with the storage node 210 in the horizontal direction, for example, the first horizontal direction X. The portion of the semiconductor layer 223 in contact with the electrode 211 is formed into a source / drain region 223a, and the portion of the semiconductor 223 in contact with the storage medium 212 or the insulating layer 212 on the surface of the storage medium 212 is formed into a channel region 223b. In addition, it is worth noting that in one embodiment of the present disclosure, the semiconductor layer 223 is shared with the bit line 203, so that the bit line 203 is formed at the same time as the semiconductor layer 223.

[0067] Referring to FIG. 13, a medium layer 222 is further formed on the surface of the semiconductor layer 223 exposed along the second trench 130a and the plurality of side cavities 130b. The medium layer 222 extends along the vertical direction z and is located on the surface of the semiconductor layer 223.

[0068] Referring to FIG. 14 and FIG. 15, the gate material 221’ is deposited in the remaining space of the second trench 130a and the remaining space of the plurality of side cavities 130b, and then referring to FIG. 15, the gate material 221’ is etched back to remove the gate material 221’ in the remaining space of the second trench 130a and retain the gate material 221’ in the remaining space of the plurality of side cavities 130b, at this time, the remaining gate material 221’ is located on the surface of the dielectric layer 222 and is spaced apart in the vertical direction Z to form a plurality of gates 221. The plurality of gates 221 are respectively located in the remaining space of the plurality of side cavities 130b, that is, in the plurality of recesses of the semiconductor layer 223, and correspond to the channel regions 230b of the semiconductor layer 223. It is worth noting that the gate material 221’ and the electrode material 211’ are different in the embodiment of the present disclosure to ensure that the etching selectivity of the two is different in the etching process to adapt to various patterning processes. In the embodiment of the present disclosure, the gate 221 is part of the word line 202, so a plurality of word lines 202 are also formed at this time. At this time, the transistors 220 in the plurality of memory cells 201 in the vertical direction are connected in series with each other, and the transistors 220 and the storage nodes 210 are coupled in the horizontal direction and connected in parallel with each other.

[0069] Please continue to refer to FIG. 15, the second isolation layer 120b, such as silicon oxide, is backfilled in the remaining space of the second trench 130a. The second isolation layer 120b is similar to the first isolation layer 120a and also extends along the second horizontal direction Y and penetrates through the stack to isolate the plurality of memory cell arrays.

[0070] Referring to FIGS. 16-18, a third mask layer 140 is formed over the entire structure and patterned to form at least one third opening 140a extending in the first horizontal direction X for etching the stack to form a plurality of memory cells 201 spaced apart in the second horizontal direction Y. Referring to FIG. 17, the electrodes 211 and the storage medium 212 in the stack are etched down through the third opening 140a to form a third trench 140b separating the layers in the second horizontal direction Y, leaving the gate 221 or word line 202 extending in the second horizontal direction Y to connect the transistors of the plurality of memory cells 201 in the second horizontal direction Y. Referring to FIG. 18, the third trench 140b is filled with an insulating material such as silicon oxide and planarized to form a third insulating layer 120c extending in the first horizontal direction X through the stack and through the dielectric layer 222, the semiconductor layer 223, and the region between adjacent word lines 202. The third insulating layer 120c separates the plurality of memory cells 201 spaced apart in the second horizontal direction Y in the first memory cell array MA and the second memory cell array MB. The first, second, and third insulating layers 120a, 120b, and 120c are collectively referred to as the insulating layer 120 separating the three-dimensional memory array on the substrate 100.

[0071] In embodiments of the present disclosure, a three-dimensional memory array is provided by stacking a plurality of memory cells in a vertical direction, each memory cell including a transistor and a storage node coupled in a horizontal direction, the transistor and the storage node being connected in parallel with each other, the transistors in the plurality of memory cells in the vertical direction being connected in series with each other, and / or the storage nodes in the plurality of memory cells in the vertical direction being connected in series with each other, which simplifies the wiring, achieves the maximum vertical stacking density, and effectively avoids the crosstalk problem of existing three-dimensional memory structures by selecting adjacent memory bits through the parallel transistor, thereby improving the device performance. Embodiments of the present disclosure can be applied to high-performance, high-bandwidth, and high-density non-volatile dual in-line memory modules (NVDIMM) or storage class memory (SCM).

[0072] Referring to FIG. 19, the present disclosure further provides an electronic device 1 having a storage function, which includes a processing device 2 and a memory device 3 electrically connected to the processing device 2. The memory device 3 includes the three-dimensional memory array 4 described in FIGS. 1-18 and the controller 5 for controlling the read / write of the three-dimensional memory array 4. The electronic device can be a terminal device, such as a personal computer, a mobile phone, a pad, a consumer electronics, such as a smart home appliance, an automotive, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, a server, a data center, etc. The memory device 3 can be, for example, a high-performance, high-bandwidth, high-density non-volatile dual in-line memory module (NVDIMM) or a storage class memory (SCM). The storage function in the electronic device 1 can be implemented by the memory device 3.

[0073] In some embodiments, the processing device 2 and the memory device 3 can be two independent chips to form a stand-alone memory. In other embodiments, the memory device 3 and the processing device 2 can be integrated into the same chip to form an embedded memory. The electronic device 1 and the three-dimensional memory array 4 described in FIGS. 1-18 can solve the same technical problem and achieve the same intended effect.

[0074] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A three-dimensional storage array, characterized in that, include: The first memory cell array (MA) includes: Multiple memory cells (201) stacked along a vertical direction (Z), each of the memory cells (201) including a horizontally coupled transistor (220) and a memory node (210) connected in parallel to each other, wherein the transistors (220) in the multiple memory cells (201) in the vertical direction (Z) are connected in series to each other, and / or the memory nodes (210) in the multiple memory cells (201) in the vertical direction (Z) are connected in series to each other; Multiple word lines (202) are arranged at intervals along the vertical direction (Z) and are respectively connected to transistors (220) in multiple memory cells (201) in the vertical direction (Z); And at least one bit line (203) extends along the vertical direction (Z) and connects transistors (220) in a plurality of memory cells (201) in the vertical direction (Z).

2. The three-dimensional storage array according to claim 1, characterized in that, The interconnection of storage nodes (210) in the multiple storage cells (201) in the vertical direction (Z) includes: Multiple electrodes (211) and multiple storage media (212) are arranged alternately along the vertical direction (Z), wherein adjacent storage nodes (210) in the multiple storage cells (201) in the vertical direction share the electrodes (211).

3. The three-dimensional storage array according to claim 2, characterized in that, The storage medium (212) is selected from any one of capacitive storage medium, ferroelectric storage medium, magnetic storage medium, phase change storage medium, and resistive switching storage medium.

4. The three-dimensional storage array according to any one of claims 1-3, characterized in that, The transistors (220) in the plurality of memory cells (201) in the vertical direction (Z) are connected in series with each other, including: A semiconductor layer (223) extends along the vertical direction (Z) and is located on one side of the storage node (210) in the horizontal direction (X), and is coupled to the storage node (210) in the horizontal direction (X). The semiconductor layer (223) is connected to the bit line (203). A dielectric layer (222) extends along the vertical direction (Z) and is located on the surface of the semiconductor layer (223); Multiple gates (221) are arranged at intervals along the vertical direction (Z) and located on the surface of the dielectric layer (222), and the gates (221) are connected to the word lines (202); The semiconductor layer (223) includes multiple source / drain regions (223a) and multiple channel regions (223b) arranged alternately, and the source / drain regions (223a) are shared between adjacent transistors (220) in the multiple memory cells (201) in the vertical direction (Z).

5. The three-dimensional storage array according to claim 4, characterized in that, The semiconductor layer (223) is selected from at least one of monocrystalline silicon, polycrystalline silicon, molybdenum disulfide, indium tin oxide, zinc indium gallium oxide, zinc indium oxide, and indium gallium oxide.

6. The three-dimensional storage array according to claim 4, characterized in that, The semiconductor layer (223) is conformally located on the surface of a plurality of electrodes (211) and a plurality of storage media (212) of the memory node (210), wherein a plurality of source / drain regions (223a) in the semiconductor layer (223) are connected to the plurality of electrodes (212), and a plurality of channel regions (223b) in the semiconductor layer (223) are connected to the plurality of storage media (212), so that the transistor (220) and the memory node (210) are coupled in the horizontal direction (X) and connected in parallel to each other.

7. The three-dimensional storage array according to claim 6, characterized in that, The semiconductor layer (223) has a plurality of recesses protruding toward the plurality of storage media (212), wherein the plurality of gates (221) are respectively located in the plurality of recesses.

8. The three-dimensional storage array according to claim 6, characterized in that, The semiconductor layer (223) and the dielectric layer (222) extend in a vertical direction (Z) and have vertical surfaces. The gate (221) is located on one side of the dielectric layer (222) and is connected to the word line (202).

9. The three-dimensional storage array according to any one of claims 6 to 8, characterized in that, An insulating dielectric layer (224) is also included between the semiconductor layer (223) and the storage medium (212).

10. The three-dimensional storage array according to any one of claims 4-9, characterized in that, The bit line (203) is shared with the semiconductor layer (223) of the plurality of transistors (220) along the vertical direction (Z).

11. The three-dimensional storage array according to any one of claims 1-10, characterized in that, The electrodes (211) in the storage node (210) and the gate (221) in the transistor (220) are made of different materials.

12. The three-dimensional storage array according to any one of claims 1-11, characterized in that, The three-dimensional storage array further includes a second storage cell array (MB), which is mirror-symmetric to the first storage cell array (MB).

13. A method for fabricating a three-dimensional storage array, characterized in that, The method includes forming a first memory cell array (MA), which includes: A plurality of memory cells (201) are formed stacked along a vertical direction (Z), each of the memory cells (201) including a transistor (220) and a memory node (210) coupled in a horizontal direction (X) and connected in parallel to each other, wherein the vertical direction (Z) is... The transistors (220) in the multiple memory cells (201) on the vertical direction (Z) are connected in series with each other, and / or the memory nodes (210) in the multiple memory cells (201) on the vertical direction (Z) are connected in series with each other; Multiple word lines (202) are formed and spaced apart along the vertical direction (Z), and the multiple word lines (202) are respectively connected to transistors (220) in multiple memory cells (201) in the vertical direction (Z); At least one bit line (203) is formed extending along the vertical direction (Z), the bit line (203) connecting transistors (220) in a plurality of memory cells (201) in the vertical direction (Z).

14. The preparation method according to claim 13, characterized in that, The method further includes forming a second memory cell array (MB) that is mirror-symmetric to the first memory cell array (MA).

15. The preparation method according to claim 14, characterized in that, The method includes: A substrate (100) is provided, and a stack of multiple electrode materials (211') and multiple storage medium materials (212') are alternately arranged on the substrate (100); At least one first trench (110a) is formed through the stack, the first trench (110a) extending along a second horizontal direction (Y), dividing the stack into at least a first memory cell array (MA) and a second memory cell array (MB); At least two second trenches (130a) are formed through the stack, the at least two second trenches (130a) are spaced apart along a first horizontal direction (X), and each second trench (130a) extends along a second horizontal direction (Y), the first horizontal direction (X) and the second horizontal direction (Y) are perpendicular; A portion of the storage medium material (212') is etched laterally along the second trench (130a) to form a plurality of side cavities (130b) spaced apart in the vertical direction (Y). The remaining plurality of electrode materials (211') and plurality of storage medium materials (212') are respectively formed as the electrode (211) and the storage medium (211). A semiconductor layer (223) is conformally formed on the surfaces of the plurality of electrodes (211) exposed along the second trench (130a) and the surfaces of the plurality of storage media (212) exposed along the plurality of side cavities (130b); A dielectric layer (212) is formed on the surface of the semiconductor layer (223) exposed along the second trench (130a) and the plurality of side cavities (130b); A plurality of gates (221) are formed on the surface of the dielectric layer (212) exposed in the plurality of side cavities (130b).

16. The preparation method according to claim 15, characterized in that, The method further includes: The electrodes (211) and the storage medium (212), as well as the dielectric layer (222) and the semiconductor layer (223) in the stack are etched downward along the first horizontal direction (X) to form a plurality of memory cells (201) spaced apart in the second horizontal direction (Y), wherein the word lines (202) are retained and extend along the second horizontal direction (Y), and each word line (202) connects to the transistors (220) in the plurality of memory cells (201) in the second horizontal direction (Y).

17. The preparation method according to claim 15 or 16, characterized in that, Before forming the semiconductor layer (223), the method further includes: Multiple insulating dielectric layers (224) are formed in the multiple side cavities (130b) respectively on the surface of the multiple storage media (212).

18. The preparation method according to any one of claims 15 to 17, characterized in that, The bit line (203) is formed simultaneously with the formation of the semiconductor layer (223).

19. The preparation method according to any one of claims 13-18, characterized in that, The storage medium (212) in the storage node (210) is selected from any one of capacitive storage medium, ferroelectric storage medium, magnetic storage medium, phase change storage medium, and resistive switching storage medium.

20. An electronic device (1), characterized in that, include: Processing device (2); as well as The storage device (3) is electrically connected to the processing device (2), the storage device (3) including a three-dimensional storage array (4) as described in any one of claims 1-12, and a controller (5) for controlling the reading and writing of the three-dimensional storage array (4).

Images