Heat treatment method and preparation method for topcon cell

Abstract

The present disclosure belongs to the technical field of solar cell preparation, and relates to a heat treatment method and preparation method for a TOPCon cell. The heat treatment method comprises: placing a TOPCon cell semi-finished product in a furnace at not higher than 830°C for a cooling and annealing treatment, wherein the TOPCon cell semi-finished product comprises a silicon wafer, an emitter layer located on the front side of the silicon wafer, a tunneling oxide layer located on the back side of the silicon wafer, and a doped polysilicon layer. The heat treatment method of the present disclosure is simple to operate, and the process conditions are easy to regulate and control; and the heat treatment method can improve the short-circuit current, fill factor, open-circuit voltage and conversion efficiency of a TOPCon cell.

Description

A heat treatment method and preparation method of a TOPCon cell

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to Chinese Patent Application No. 202410861688.6, filed on June 28, 2024, entitled "A heat treatment method and preparation method of a TOPCon cell", the disclosure of which is hereby incorporated by reference in its entirety as part or all of the present application. TECHNICAL FIELD

[0003] The present disclosure relates to a heat treatment method and preparation method of a TOPCon cell, belonging to the technical field of solar cell preparation. BACKGROUND

[0004] TOPCon cell, also known as tunnel oxide passivated contact solar cell, is a N-type silicon wafer cell technology proposed in 2013, aiming to improve the efficiency of solar cells by solving the problem of carrier selection passivation contact. TOPCon cell can greatly reduce the surface recombination of back n emitter and metal contact recombination by setting a tunnel contact structure on the back, thereby improving the efficiency of the cell.

[0005] The front side of the TOPCon cell is the same as the structure of the conventional N-type solar cell, and the main difference is that a tunnel oxide layer is prepared on the back of the cell. The layer is an ultra-thin high-quality silicon dioxide layer. There are two methods to prepare doped polysilicon on the tunnel oxide layer: one is the intrinsic method, which first deposits an intrinsic polysilicon layer, and then performs phosphorus diffusion doping; the other is the in-situ method, which introduces phosphorus element when depositing amorphous silicon, and forms doped polysilicon by annealing and crystallization. In order to improve the passivation performance of TOPCon cell, phosphorus gettering is an effective solution. The conventional phosphorus gettering solution adopts phosphorus diffusion before texturing, and then performs polishing and texturing process. The whole process is relatively complicated, and the cell thickness is further thinned, which is not conducive to mass production. In addition, the poor long-wave response of TOPCon cell has always been a difficult problem in the industry, and reducing the doping concentration of back polysilicon is an effective solution. The traditional solution is to reduce the phosphorus source or lower the doping temperature during phosphorus diffusion, but the low-doped polysilicon passivation obtained by this method will have certain loss.

[0006] SUMMARY

[0007] In view of the problems existing in the preparation process of the TOPCon cell, the present disclosure provides a heat treatment method and a preparation method of a TOPCon cell. By additionally adding a cooling annealing process after the crystallization of the doped polysilicon, the metal impurities in the silicon substrate can be absorbed into the polysilicon, effectively reducing the metal impurities in the silicon substrate, effectively improving the lifetime of the silicon substrate, and at the same time, a part of the phosphorus atoms in the doped polysilicon grains can be transferred to the grain boundaries, reducing the phosphorus atom doping concentration on the back surface, greatly enhancing the long-wave response of the TOPCon cell, and the phosphorus atoms in the grain boundaries can still ensure good contact performance on the back surface of the cell. The state of hydrogen in the polysilicon can also be changed, so that the passivation performance of the back surface of the cell is better. Based on the heat treatment method, the short-circuit current, the fill factor, the open-circuit voltage and the conversion efficiency of the TOPCon cell can be improved.

[0008] The purpose of the present disclosure is achieved by the following technical solutions.

[0009] A heat treatment method of a TOPCon cell, which is to place a TOPCon cell semi-product in a furnace with an initial temperature not higher than 830℃ for cooling annealing treatment.

[0010] The TOPCon cell semi-product includes a silicon wafer, an emitter layer on the front surface of the silicon wafer, and a tunnel oxide layer and a doped polysilicon layer on the back surface of the silicon wafer.

[0011] According to one or more embodiments of the present disclosure, the initial temperature of the cooling annealing treatment is 700-830℃, more preferably 730-800℃.

[0012] According to one or more embodiments of the present disclosure, when the TOPCon cell semi-product is placed in a furnace that meets the initial temperature requirement of the cooling annealing treatment, it is kept for 10-20min before cooling.

[0013] According to one or more embodiments of the present disclosure, the cooling rate of the cooling annealing treatment is 1.0-2.0℃ / min, more preferably 1.3-1.7℃ / min.

[0014] According to one or more embodiments of the present disclosure, gradient cooling is adopted during the cooling annealing treatment, and each time the temperature is lowered by 80-120℃. The cooling is stopped, and after keeping at this temperature for 10-20min, the cooling is continued.

[0015] According to one or more embodiments of the present disclosure, the cooling annealing treatment is carried out under normal pressure or low pressure, and the process pressure range is 10-1013mbar.

[0016] According to one or more embodiments of the present disclosure, during the cooling annealing process, nitrogen or inert gas is filled into the furnace as a protective atmosphere, which can effectively ensure that the silicon wafer is heated more uniformly in the furnace tube; more preferably, the gas flow of the protective atmosphere is 1000-20000sccm, wherein the gas flow of the protective atmosphere under low pressure is preferably 1000-5000sccm, and the gas flow of the protective atmosphere under normal pressure is preferably 5000-20000sccm.

[0017] According to one or more embodiments of the present disclosure, during the cooling annealing process, when the temperature drops to 400-550 DEG C, the silicon wafer is taken out for air cooling.

[0018] A preparation method of a TOPCon cell, comprising the following steps:

[0019] (1) cleaning and texturing the silicon wafer;

[0020] (2) diffusing boron on the front surface of the silicon wafer after step (1) to form an emitter layer;

[0021] (3) removing the back surface of the silicon wafer after step (2) around the PN junction, and then polishing or forming a tower base structure on the back surface of the silicon wafer;

[0022] (4) growing a through-oxide layer on the back surface of the silicon wafer after step (3), and then growing a doped polysilicon layer;

[0023] (5) performing cooling annealing treatment on the silicon wafer after step (4) by using the heat treatment method according to the present disclosure;

[0024] (6) removing the excess polysilicon layer and borosilicate glass layer on the front surface of the silicon wafer after step (5), and removing the phosphosilicate glass layer on the back surface of the silicon wafer, and then preparing a passivation and anti-reflection layer on the front surface and the back surface of the silicon wafer, respectively;

[0025] (7) preparing electrodes on the front surface and the back surface of the silicon wafer after step (6), thereby completing the preparation of the TOPCon cell.

[0026] According to one or more embodiments of the present disclosure, step (1) forms a pyramidal textured structure on the surface of the silicon wafer by texturing, which is beneficial to reduce the reflectivity of the front surface of the silicon wafer and increase the utilization rate of light.

[0027] According to one or more embodiments of the present disclosure, in step (4), the doped polysilicon layer is prepared by first preparing a polysilicon layer and then forming a doped polysilicon layer by phosphorus diffusion; or, a doped amorphous silicon layer is first prepared, and then a doped polysilicon layer is formed by annealing treatment. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a comparison of ECV before and after heat treatment of the silicon wafer in step (5) of Example 1.

[0029] Figure 2 is a comparison of ECV before and after heat treatment of the silicon wafer in step (5) of Example 2. DETAILED DESCRIPTION

[0030] The present disclosure will be further described in conjunction with specific embodiments, wherein the methods are conventional methods unless otherwise specified, and the raw materials are commercially available unless otherwise specified.

[0031] The preparation method of the TOPCon cell in the following examples includes the following steps:

[0032] (1) Use N-type monocrystalline silicon wafers with a resistivity of 1.0 Ω and a thickness of 130 μm as the substrate, clean and texturize the silicon wafers to form a pyramidal textured structure on the surface of the silicon wafers, with a reflectivity of 9-15% and a pyramid base size of 1-8 μm;

[0033] (2) Perform boron diffusion on the front side of the silicon wafer treated in step (1) to form a PN junction, wherein the doping sheet resistance is 100-500 Ω, the surface doping concentration is 1E+18-1E+20 atoms / cm 3 , and the junction depth is 1-3 μm, i.e., an emitter layer is formed on the front side of the silicon wafer;

[0034] (3) Use KOH or NaOH or other alkaline solutions to etch and remove the back side of the silicon wafer treated in step (2) around the PN junction, and then polish or form a pyramid base structure on the back side of the silicon wafer, wherein the pyramid base size is 1-10 μm;

[0035] (4) Grow a tunneling oxide layer on the back side of the silicon wafer treated in step (3), and then grow a doped polysilicon layer;

[0036] Use a tube-type LPCVD device to prepare the tunneling oxide layer, with a process temperature of 580-630 ℃, an oxygen flow rate of 1000-10000 sccm, and a thickness of the grown tunneling oxide layer of 1-2 nm;

[0037] Use a tube-type LPCVD device to prepare the polysilicon layer, with a temperature of 580-650 ℃, an N2 flow rate of 500-10000 sccm, a SiH4 flow rate of 100-5000 sccm, and a thickness of the grown polysilicon layer of 50-300 nm; then perform phosphorus diffusion on the polysilicon layer to form a crystallized doped polysilicon;

[0038] The temperature of the phosphorus source is 750-890℃, the flow rate of the phosphorus source is 200-3000sccm, the flow rate of oxygen is 100-2000sccm, the process time of the phosphorus source is 10-50min, the temperature of the non-source push is 850-930℃, the push time is 10-90min, the thickness of the deposited PSG is 10-50nm, the sheet resistance of the back surface is 30-150Ω, and the phosphorus doping concentration is 2E+20-6E+20atoms / cm 3 ;

[0039] (5) The silicon wafer treated in step (4) is placed in an annealing furnace with an initial temperature of 700-830℃, and after heat preservation for 10-20min, a cooling annealing treatment is performed, and the silicon wafer is taken out of the annealing furnace when the temperature is cooled to 400-550℃ and is air-cooled;

[0040] The nitrogen gas with a flow rate of 1000-20000sccm is introduced into the annealing furnace as a protective gas, the process pressure in the annealing furnace is 10-1013mbar, and the cooling rate is 1.0-2.0℃ / min; the gradient cooling mode is to stop cooling every time the temperature is decreased by 80-120℃, and after heat preservation for 10-20min at the temperature, the cooling is continued;

[0041] (6) The front surface of the silicon wafer treated in step (5) is etched by using an HF solution to remove the excess PSG layer, and then the front surface of the silicon wafer is cleaned by using an alkaline solution such as KOH or NaOH to remove the excess polysilicon, and finally the remaining BSG and PSG layers on the front and back surfaces of the silicon wafer are removed by using a tank-type HF solution; then the front surface of the silicon wafer is sequentially deposited with an AlOx passivation layer with a thickness of 1-15nm by using an ALD device and a SiONx or SiNx anti-reflection layer with a thickness of 50-100nm by using a PECVD device; finally, the back surface of the silicon wafer is deposited with a SiONx or SiNx anti-reflection layer with a thickness of 50-80nm by using a PECVD device;

[0042] (7) Electrodes are prepared on the front and back surfaces of the silicon wafer treated in step (6), and the preparation of the TOPCon cell is completed.

[0043] Example 1

[0044] A method for preparing a TOPCon cell, comprising the following steps:

[0045] (1) An N-type monocrystalline silicon wafer with a resistivity of 1.0Ω and a thickness of 130μm is used as a substrate, and the silicon wafer is cleaned and textured to form a pyramid-shaped textured structure on the surface of the silicon wafer, the reflectivity is 10-13%, and the size of the pyramid base is 5-7μm;

[0046] (2) the front surface of the silicon wafer treated in step (1) is subjected to boron diffusion to form a PN junction, wherein the sheet resistance of the doped layer is 350-400 Ω, the surface doping concentration is 2E+18-3E+18 atoms / cm 3 , the junction depth is 1.4-1.6 um, i.e. an emitter layer is formed on the front surface of the silicon wafer;

[0047] (3) the back surface of the silicon wafer treated in step (2) is subjected to etching to remove the PN junction around the back surface, and then the back surface of the silicon wafer is polished or a tower base structure is formed, wherein the size of the tower base is 5-10 um;

[0048] (4) a tunneling oxide layer is grown on the back surface of the silicon wafer treated in step (3), and then a doped polysilicon layer is grown;

[0049] The tunneling oxide layer is prepared by using a tube-type LPCVD device, the process temperature is 580-620 ℃, the oxygen flow rate is 10000 sccm, and the thickness of the grown tunneling oxide layer is 1-2 nm;

[0050] The intrinsic polysilicon layer is prepared by using a tube-type LPCVD device, the temperature is 590-620 ℃, the N2 flow rate is 1000-1200 sccm, the SiH4 flow rate is 800-1200 sccm, and the thickness of the grown polysilicon layer is 100-200 nm; then the polysilicon layer is subjected to phosphorus diffusion to form a crystallized doped polysilicon layer;

[0051] The temperature of the source during phosphorus diffusion is 780-850 ℃, the source flow rate is 800-1200 sccm, the oxygen flow rate is 400-600 sccm, the source time is 15-20 min, the temperature after the source is pushed is 880-910 ℃, the pushing time is 10-20 min, the thickness of the deposited PSG is 30-40 nm, the sheet resistance of the back surface is 35-45 Ω, and the phosphorus doping concentration is 5E+20-6E+20 atoms / cm 3 ;

[0052] (5) the silicon wafer treated in step (4) is placed in an annealing furnace with an initial temperature of 750 ℃, and after being kept at the temperature for 10 min, the annealing treatment is performed by using a gradient cooling method, and the silicon wafer is taken out from the annealing furnace when the temperature is lowered to 450 ℃ and then is subjected to air cooling;

[0053] The nitrogen gas with a flow rate of 20000sccm is introduced into the annealing furnace as a protective gas, the process pressure in the annealing furnace is 1013mbar, and the cooling rate is 1.6℃ / min; the gradient cooling method is to stop cooling at every 100℃ of temperature drop, and keep the temperature for 10min, and then continue to cool down; the specific gradient cooling method is: from 750℃ to 650℃, keep the temperature for 10min after cooling to 650℃, then continue to cool to 550℃, keep the temperature for 10min after cooling to 550℃, and then continue to cool to 450℃;

[0054] (6) The front surface of the silicon wafer treated in step (5) is etched with an HF solution to remove the excess PSG layer, and then the front surface of the silicon wafer is cleaned with a KOH alkaline solution to remove the excess polysilicon, and finally the excess PSG layer and BSG layer on the front and back surfaces of the silicon wafer are removed; then the front surface of the silicon wafer is sequentially deposited with an ALD device to form an AlOx passivation layer with a thickness of 3-5nm, and a PECVD device to form a SiONx anti-reflection layer with a thickness of 70-80nm; finally, the back surface of the silicon wafer is deposited with a PECVD device to form a SiONx anti-reflection layer with a thickness of 65-75nm;

[0055] (7) Electrodes are prepared on the front and back surfaces of the silicon wafer treated in step (6), and the preparation of the TOPCon cell is completed.

[0056] Figure 1 is an ECV comparison chart of the silicon wafer before and after heat treatment in step (5), the vertical axis is the doping concentration, and the horizontal axis is the doping depth. As can be seen from Figure 1, the doping concentration of the polysilicon after heat treatment is reduced from 6.51E+20 atoms / cm 3 to 4.11E+20 atoms / cm 3 .

[0057] The TOPCon cell obtained in step (7) of the embodiment is tested for performance, and the short-circuit current of the cell is measured to be 41.36A / cm 2 , the open-circuit voltage is 0.7384V, the fill factor is 84.24%, and the conversion efficiency is 25.73%.

[0058] Example 2

[0059] Based on Example 1, except that the process conditions of step (5) are different from those of Example 1, the other steps and process conditions are the same as those of Example 1. The specific process conditions of step (5) in this embodiment are as follows: the silicon wafer treated in step (4) is placed in an annealing furnace with an initial temperature of 780℃, and kept for 20min, then annealed by gradient cooling, and taken out from the annealing furnace when the temperature is reduced to 480℃ for air cooling;

[0060] Nitrogen gas with a flow rate of 1000 sccm is introduced into the annealing furnace as a protective gas. The process pressure in the annealing furnace is 10 mbar, and the cooling rate is 1.5℃ / min. The gradient cooling method is to stop cooling every 120℃, hold at that temperature for 20 minutes, and then continue cooling.

[0061] Figure 2 is a comparison of the ECV of the silicon wafer before and after heat treatment in step (5). The vertical axis represents the doping concentration, and the horizontal axis represents the doping junction depth. As can be seen from Figure 2, the doping concentration of the polycrystalline silicon after heat treatment is 6.82E+20 atoms / cm². 3 Reduced to 4.45E+20 atoms / cm 3 .

[0062] The TOPCon battery obtained in this embodiment was subjected to performance testing, and the short-circuit current of the battery was measured to be 41.32 A / cm. 2 The open-circuit voltage is 0.7372V, the fill factor is 84.44%, and the conversion efficiency is 25.72%.

[0063] Example 3

[0064] Based on Example 1, except that the temperature of the cooling annealing treatment in step (5) is 810°C, which is different from Example 1, all other steps and process conditions are the same as in Example 1.

[0065] The TOPCon battery obtained in Example 3 was subjected to performance testing, and the short-circuit current of the battery was measured to be 41.35 A / cm. 2 The open-circuit voltage is 0.7372V, the fill factor is 84.19%, and the conversion efficiency is 25.66%.

[0066] Example 4

[0067] Based on Example 1, except that the temperature of the cooling annealing treatment in step (5) is 680°C, which is different from Example 1, all other steps and process conditions are the same as in Example 1.

[0068] The TOPCon battery obtained in Example 4 was subjected to performance testing, and the short-circuit current of the battery was measured to be 41.33 A / cm. 2 The open-circuit voltage is 0.7370V, the fill factor is 84.14%, and the conversion efficiency is 25.61%.

[0069] Example 5

[0070] Based on Example 1, except that the cooling rate of the cooling annealing process in step (5) is 2.0℃ / min, which is different from Example 1, all other steps and process conditions are the same as in Example 1.

[0071] The performance of the TOPCon battery obtained in Comparative Example 3 was tested, and the short-circuit current of the battery was measured to be 41.29 A / cm. 2 The open-circuit voltage is 0.7377V, the fill factor is 84.11%, and the conversion efficiency is 25.62%.

[0072] Example 6

[0073] Based on Example 1, except that the cooling rate of the cooling annealing process in step (5) is 1.0℃ / min, which is different from Example 1, all other steps and process conditions are the same as in Example 1.

[0074] The TOPCon battery obtained in Example 6 was subjected to performance testing, and the short-circuit current of the battery was measured to be 41.37 A / cm. 2 The open-circuit voltage is 0.7365V, the fill factor is 84.13%, and the conversion efficiency is 25.63%.

[0075] Example 7

[0076] Based on Example 1, except that the temperature of the sample taken out of the annealing furnace in step (5) is 550°C, which is different from Example 1, all other steps and process conditions are the same as in Example 1.

[0077] The TOPCon battery obtained in Example 7 was subjected to performance testing, and the short-circuit current of the battery was measured to be 41.28 A / cm. 2 The open-circuit voltage is 0.7377V, the fill factor is 84.21%, and the conversion efficiency is 25.64%.

[0078] Comparative Example 1

[0079] Based on Example 1, except for step (5) cooling annealing treatment, all other steps and process conditions are the same as in Example 1.

[0080] The performance of the TOPCon battery obtained in Comparative Example 1 was tested, and the short-circuit current of the battery was measured to be 41.28 A / cm. 2 The open-circuit voltage is 0.7369V, the fill factor is 84.11%, and the conversion efficiency is 25.58%. Beneficial effects:

[0081] (1) This disclosure adds an extra cooling annealing process after the crystallization of the doped polycrystalline silicon layer. Since the polycrystalline silicon contains a large amount of phosphorus at this time, it can effectively get rid of the silicon wafer substrate to reduce the content of metal impurities in the silicon wafer substrate and draw the impurities in the silicon wafer substrate into the polycrystalline silicon, thereby effectively improving the bulk lifetime of the silicon wafer substrate. At the same time, taking advantage of the higher solid concentration of phosphorus in the polycrystalline silicon grain boundary at low temperature, some phosphorus atoms in the polycrystalline silicon grain are transferred to the grain boundary, thereby reducing the phosphorus atom doping concentration on the back side, greatly enhancing the long-wavelength response of the TOPCon cell, increasing the short-circuit current of the cell, and the phosphorus atoms in the grain boundary can still provide good contact for the back side of the cell, so that the contact performance of the cell is not affected. The low doping on the back side of the conventional TOPCon cell leads to the passivation loss on the back side of the cell, but the low doping formed by this heat treatment will not have such a problem, because the state of hydrogen in the polycrystalline silicon is also effectively changed during the heat treatment process, so that the silicon wafer is further passivated by hydrogen.

[0082] (2) The initial temperature of the cooling annealing process used in this disclosure should not be too high. On the one hand, opening the tube furnace door at an excessively high temperature will damage the equipment's sealing performance. On the other hand, an excessively high initial temperature will cause the phosphorus dopant in the polycrystalline silicon to diffuse further into the silicon wafer substrate, thereby damaging the tunneling oxide layer on the back side and causing passivation loss. In addition, since the phosphorus gettering temperature is theoretically better the higher it is, the higher the initial temperature of the cooling annealing process should be, the better, provided that the tunneling oxide layer on the back side is not affected.

[0083] (3) The heat treatment method adopted in this disclosure is to cool down. The cooling rate of this cooling process should not be too fast. Too fast cooling will cause phosphorus elements to fail to precipitate in time in the polycrystalline silicon grain boundary, thus failing to achieve the effect of reducing the doping concentration. At the same time, the cooling rate should not be too slow, as too long a process time will also cause passivation loss to the silicon wafer.

[0084] (4) The present invention can adopt a gradient cooling method during the cooling process, mainly because the cooling rate of each temperature zone of the furnace tube is not consistent, so as to avoid the temperature difference between each temperature zone being too large during the long-term continuous cooling process, which would not achieve a good effect. By adopting a gradient cooling method, the temperature can be reduced to a certain level and then held for a certain period of time, so that the temperature of different temperature zones tends to be the same, and the temperature difference between different temperature zones can be minimized.

[0085] (5) The heat treatment method described in this disclosure is simple to operate and the process conditions are easy to control. Based on this heat treatment method, the short-circuit current, fill factor, open-circuit voltage and conversion efficiency of TOPCon battery can be improved.

[0086] In summary, the above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A heat treatment method for TOPCon batteries, wherein the heat treatment method involves placing a TOPCon battery semi-finished product in a furnace with an initial temperature not exceeding 830°C for cooling and annealing treatment. The TOPCon battery semi-finished product includes a silicon wafer, an emitter layer on the front side of the silicon wafer, and a tunnel oxide layer and a doped polycrystalline silicon layer on the back side of the silicon wafer.

2. The heat treatment method for a TOPCon battery according to claim 1, wherein, The initial temperature for cooling annealing is 700-830℃.

3. The heat treatment method for a TOPCon battery according to claim 1, wherein, The initial temperature for cooling annealing is 730-800℃.

4. The heat treatment method for a TOPCon battery according to claim 1, wherein, When TOPCon battery semi-finished products are placed in a furnace that meets the initial temperature requirements for cooling annealing, they are kept at that temperature for 10-20 minutes before being cooled down.

5. The heat treatment method for a TOPCon battery according to claim 1, wherein, The cooling rate of the cooling annealing treatment is 1.0-2.0℃ / min.

6. The heat treatment method for a TOPCon battery according to claim 1, wherein, The cooling rate of the cooling annealing treatment is 1.3-1.7℃ / min.

7. A heat treatment method for a TOPCon battery according to any one of claims 1 to 6, wherein, During the cooling annealing process, a gradient cooling method is used, reducing the temperature by 80-120℃ each time, stopping the cooling, holding at that temperature for 10-20 minutes, and then continuing to cool down.

8. A heat treatment method for a TOPCon battery according to any one of claims 1 to 6, wherein, The process pressure inside the furnace during the cooling annealing process is 10-1013 mbar.

9. A heat treatment method for a TOPCon battery according to claim 8, wherein, During the cooling annealing process, nitrogen or inert gas is introduced into the furnace as a protective atmosphere, with a gas flow rate of 1000-20000 sccm.

10. A heat treatment method for a TOPCon battery according to any one of claims 1 to 6, wherein, When the temperature drops to 400-550℃ during the cooling annealing process, the furnace is removed and air-cooled.

11. A method for preparing a TOPCon battery, comprising the following steps: (1) Clean and texturize the silicon wafer; (2) Boron diffusion is performed on the front side of the silicon wafer after the treatment in step (1) to form an emitter layer; (3) Remove the PN junction on the back side of the silicon wafer after step (2), and then polish or form a tower base structure on the back side of the silicon wafer. (4) First, a tunnel oxide layer is grown on the back side of the silicon wafer after the treatment in step (3), and then a doped polycrystalline silicon layer is grown. (5) The silicon wafer processed in step (4) is subjected to cooling annealing treatment using the heat treatment method described in any one of claims 1-10; (6) Remove the excess polysilicon layer and borosilicate glass layer on the front side of the silicon wafer after step (5) and the phosphosilicate glass layer on the back side of the silicon wafer, and then prepare passivation antireflection layers on the front and back sides of the silicon wafer respectively. (7) Electrodes are prepared on the front and back sides of the silicon wafer after the process in step (6) to complete the preparation of the TOPCon cell.

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