Pixel driving circuit, driving method therefor, and display apparatus

Abstract

A pixel driving circuit, a driving method therefor, and a display apparatus. Under the control of a signal of at least one of a reset signal line and a second scanning signal line, a first control sub-circuit provides a signal of a first initial signal line to a first node, and stores a voltage difference between signals of the first node and a first power line. Under the control of signals of a first scanning signal line and a control signal line, a second control sub-circuit provides a signal of a third node to the first node. Under the control of signals of the first scanning signal line and a second light-emitting signal line, a third control sub-circuit provides a signal of a data signal line to a second node and provides a signal of a second initial signal line to a fourth node. Under the control of signals of the first node and the second node, a driving sub-circuit provides a driving signal to the third node. Under the control of a signal of a first light-emitting signal line, a light-emitting control sub-circuit provides the signal of the first power line to the second node and provides a signal of the fourth node to the third node.

Description

Pixel driving circuit, driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410833999.1, filed on June 25, 2024, and entitled "Pixel driving circuit, driving method thereof and display device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but not limited to, display technology, in particular to a pixel driving circuit, a driving method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a pixel driving circuit, comprising: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a light-emitting control sub-circuit.

[0006] The first control sub-circuit is electrically connected with at least one of a first node, a reset signal line and a second scan signal line, a first power supply line and a first initial signal line, and is configured to provide a signal of the first initial signal line to the first node under the control of a signal of the at least one of the reset signal line and the second scan signal line, and store a voltage difference between signals of the first node and the first power supply line.

[0007] The second control sub-circuit is electrically connected with the first node, a third node, a first scan signal line and a control signal line, and is configured to provide a signal of the third node to the first node under the control of signals of the first scan signal line and the control signal line.

[0008] The third control sub-circuit is electrically connected with the second node, the first scan signal line, the data signal line, the fourth node, the second light-emitting signal line and the second initial signal line respectively, and is configured to provide the signal of the data signal line to the second node and provide the signal of the second initial signal line to the fourth node under the control of the signals of the first scan signal line and the second light-emitting signal line.

[0009] The driving sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide the driving signal to the third node under the control of the signals of the first node and the second node.

[0010] The light-emitting control sub-circuit is electrically connected with the first power supply line, the first light-emitting signal line, the second node, the third node and the fourth node respectively, and is configured to provide the signal of the first power supply line to the second node and provide the signal of the fourth node to the third node under the control of the signal of the first light-emitting signal line.

[0011] In some possible implementation manners, the first control sub-circuit is electrically connected with the first node, the reset signal line, the second scan signal line, the first power supply line, the first initial signal line and the fifth node respectively, and is configured to provide the signal of the first initial signal line to the fifth node and provide the signal of the fifth node to the first node under the control of the signals of the reset signal line and the second scan signal line.

[0012] In some possible implementation manners, the first control sub-circuit includes a first transistor, an eighth transistor, a first capacitor and a second capacitor.

[0013] The control electrode of the first transistor is electrically connected with the reset signal line, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the first initial signal line.

[0014] The control electrode of the eighth transistor is electrically connected with the second scan signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fifth node.

[0015] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply line, and the second plate of the first capacitor is electrically connected with the first node.

[0016] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first initial signal line, and the second plate of the second capacitor is electrically connected with the fifth node.

[0017] In some possible implementation manners, the first control sub-circuit is electrically connected with the first node, the reset signal line, the first power supply line, the first initial signal line and the fifth node respectively, and is configured to provide the signal of the first initial signal line to the fifth node and provide the signal of the fifth node to the first node under the control of the signal of the reset signal line.

[0018] In some possible implementation manners, the first control sub-circuit includes a first transistor, an eighth transistor and a first capacitor.

[0019] The control electrode of the first transistor is electrically connected with the reset signal line, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the first initial signal line.

[0020] The control electrode of the eighth transistor is electrically connected with the reset signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fifth node.

[0021] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply line, and the second plate of the first capacitor is electrically connected with the first node.

[0022] In some possible implementation manners, the control signal line includes a second light-emitting signal line, the second control sub-circuit is electrically connected with the first node, the third node, the first scan signal line, the second light-emitting control signal line and the fifth node respectively, and is configured to provide the signal of the third node or the fifth node to the first node under the control of the signals of the first scan signal line and the second light-emitting control signal line.

[0023] In some possible implementation manners, the second control sub-circuit includes a tenth transistor and two second transistors.

[0024] The control electrode of one of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, and the second electrode is electrically connected with the sixth node; the control electrode of the other of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the sixth node, and the second electrode is electrically connected with the third node; the control electrode of the tenth transistor is electrically connected with the second light-emitting signal line, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the sixth node.

[0025] Or,

[0026] The second control sub-circuit includes a tenth transistor and a second transistor, and the second transistor is a double-gate transistor.

[0027] The first control electrode and the second control electrode of the second transistor are electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, the second electrode is electrically connected with the third node, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node; the control electrode of the tenth transistor is electrically connected with the second emitting signal line, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the sixth node.

[0028] In some possible implementation manners, the control signal line includes a third power supply line, and the second control sub-circuit is electrically connected with the first node, the third node, the first scan signal line, the first initial signal line and the third power supply line respectively, and is configured to provide the signal of the third node or the first initial signal line to the first node under the control of the signals of the first scan signal line and the third power supply line.

[0029] In some possible implementation manners, the second control sub-circuit includes: a tenth transistor and two second transistors.

[0030] The control electrode of one of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, and the second electrode is electrically connected with the sixth node.

[0031] The control electrode of the other of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the sixth node, and the second electrode is electrically connected with the third node.

[0032] The control electrode of the tenth transistor is electrically connected with the third power supply line, the first electrode of the tenth transistor is electrically connected with the first initial signal line, and the second electrode of the tenth transistor is electrically connected with the sixth node.

[0033] In some possible implementation manners, the driving sub-circuit includes: a third transistor.

[0034] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node.

[0035] In some possible implementation manners, the emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0036] The control electrode of the fifth transistor is electrically connected with the first emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node respectively.

[0037] The control electrode of the sixth transistor is electrically connected with the first emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0038] In some possible implementation manners, the third control sub-circuit comprises a fourth transistor and a seventh transistor.

[0039] The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the data signal line.

[0040] The control electrode of the seventh transistor is electrically connected with the second emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the second initial signal line.

[0041] In some possible implementation manners, the pixel driving circuit further comprises a fourth control sub-circuit.

[0042] The fourth control sub-circuit is electrically connected with the second node, the second emitting signal line and the third initial signal line respectively, and is configured to provide the signal of the third initial signal line to the second node under the control of the signal of the second emitting signal line.

[0043] In some possible implementation manners, the fourth control sub-circuit comprises a ninth transistor.

[0044] The control electrode of the ninth transistor is electrically connected with the second emitting signal line, the first electrode of the ninth transistor is electrically connected with the third initial signal line, and the second electrode of the ninth transistor is electrically connected with the second node.

[0045] In some possible implementation manners, the first control sub-circuit comprises a first transistor, an eighth transistor, a first capacitor and a second capacitor, the second control sub-circuit comprises a tenth transistor and one or two second transistors, the driving sub-circuit comprises a third transistor, the emitting control sub-circuit comprises a fifth transistor and a sixth transistor, and the third control sub-circuit comprises a fourth transistor and a seventh transistor.

[0046] The control electrode of the first transistor is electrically connected with the reset signal line, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the first initial signal line.

[0047] The second transistor is two, the control electrode of one of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, and the second electrode is electrically connected with the sixth node, the control electrode of the other of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the sixth node, and the second electrode is electrically connected with the third node; or the second transistor is one, the second transistor is a double-gate transistor, the first control electrode and the second control electrode of the second transistor are electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, the second electrode is electrically connected with the third node, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node.

[0048] a control electrode of the third transistor is electrically connected with the first node, a first electrode of the third transistor is electrically connected with the second node, and a second electrode of the third transistor is electrically connected with the third node;

[0049] a control electrode of the fourth transistor is electrically connected with the first scan signal line, a first electrode of the fourth transistor is electrically connected with the second node, and a second electrode of the fourth transistor is electrically connected with the data signal line;

[0050] a control electrode of the fifth transistor is electrically connected with the first emitting signal line of the second capacitor, a first electrode of the fifth transistor is electrically connected with the first power supply line, and a second electrode of the fifth transistor is electrically connected with the second node respectively;

[0051] a control electrode of the sixth transistor is electrically connected with the first emitting signal line, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the fourth node;

[0052] a control electrode of the seventh transistor is electrically connected with the second emitting signal line, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the second initial signal line;

[0053] a control electrode of the eighth transistor is electrically connected with the second scan signal line, a first electrode of the eighth transistor is electrically connected with the first node, and a second electrode of the eighth transistor is electrically connected with the fifth node;

[0054] a control electrode of the tenth transistor is electrically connected with the second emitting signal line, a first electrode of the tenth transistor is electrically connected with the fifth node, and a second electrode of the tenth transistor is electrically connected with the sixth node;

[0055] the first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply line, and the second plate of the first capacitor is electrically connected with the first node;

[0056] the second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first initial signal line, and the second plate of the second capacitor is electrically connected with the fifth node.

[0057] In some possible implementation manners, the first control sub-circuit comprises a first transistor, an eighth transistor, a first capacitor and a second capacitor, the second control sub-circuit comprises a tenth transistor and one or two second transistors, the driving sub-circuit comprises a third transistor, the emitting control sub-circuit comprises a fifth transistor and a sixth transistor, and the third control sub-circuit comprises a fourth transistor and a seventh transistor;

[0058] a control electrode of the first transistor is electrically connected with the reset signal line, a first electrode of the first transistor is electrically connected with the fifth node, and a second electrode of the first transistor is electrically connected with the first initial signal line.

[0059] The second transistor is two, one of the two second transistors has a control electrode electrically connected with the first scan signal line, a first electrode electrically connected with the first node, and a second electrode electrically connected with the sixth node, and the other of the two second transistors has a control electrode electrically connected with the first scan signal line, a first electrode electrically connected with the sixth node, and a second electrode electrically connected with the third node; or the second transistor is one, the second transistor is a double-gate transistor, the first control electrode and the second control electrode of the second transistor are electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, the second electrode is electrically connected with the third node, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node;

[0060] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node;

[0061] The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the data signal line;

[0062] The control electrode of the fifth transistor is electrically connected with the first emitting signal line of the second capacitor, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node respectively;

[0063] The control electrode of the sixth transistor is electrically connected with the first emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node;

[0064] The control electrode of the seventh transistor is electrically connected with the second emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the second initial signal line;

[0065] The control electrode of the eighth transistor is electrically connected with the second scan signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fifth node;

[0066] The control electrode of the tenth transistor is electrically connected with the third power supply line, the first electrode of the tenth transistor is electrically connected with the first initial signal line, and the second electrode of the tenth transistor is electrically connected with the sixth node;

[0067] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply line, and the second plate of the first capacitor is electrically connected with the first node;

[0068] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first initial signal line, and the second plate of the second capacitor is electrically connected with the fifth node.

[0069] In some possible implementation manners, the first control sub-circuit includes a first transistor, an eighth transistor and a first capacitor, the second control sub-circuit includes a tenth transistor and one or two second transistors, the driving sub-circuit includes a third transistor, the light-emitting control sub-circuit includes a fifth transistor and a sixth transistor, and the third control sub-circuit includes a fourth transistor and a seventh transistor.

[0070] The control electrode of the first transistor is electrically connected with a reset signal line, the first electrode of the first transistor is electrically connected with a fifth node, and the second electrode of the first transistor is electrically connected with a first initial signal line.

[0071] The second transistor is two, one of the two second transistors has a control electrode electrically connected with a first scan signal line, a first electrode electrically connected with a first node and a second electrode electrically connected with a sixth node, and the other of the two second transistors has a control electrode electrically connected with the first scan signal line, a first electrode electrically connected with the sixth node and a second electrode electrically connected with a third node; or, the second transistor is one, the second transistor is a double-gate transistor, the first control electrode and the second control electrode of the second transistor are electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, the second electrode is electrically connected with the third node, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node.

[0072] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with a second node, and the second electrode of the third transistor is electrically connected with the third node.

[0073] The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with a data signal line.

[0074] The control electrode of the fifth transistor is electrically connected with a first light-emitting signal line of the second capacitor, the first electrode of the fifth transistor is electrically connected with a first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0075] The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with a fourth node.

[0076] The control electrode of the seventh transistor is electrically connected with a second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with a second initial signal line.

[0077] The control electrode of the eighth transistor is electrically connected with the reset signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fifth node.

[0078] The control electrode of the tenth transistor is electrically connected with the second light-emitting signal line, the first electrode of the tenth transistor is electrically connected with the fifth node, and the second electrode of the tenth transistor is electrically connected with the sixth node.

[0079] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply line, and the second plate of the first capacitor is electrically connected with the first node.

[0080] In some possible implementation manners, the first control sub-circuit includes a first transistor, an eighth transistor and a first capacitor, the second control sub-circuit includes a tenth transistor and one or two second transistors, the driving sub-circuit includes a third transistor, the light-emitting control sub-circuit includes a fifth transistor and a sixth transistor, and the third control sub-circuit includes a fourth transistor and a seventh transistor.

[0081] The control electrode of the first transistor is electrically connected with the reset signal line, the first electrode of the first transistor is electrically connected with the fifth node, and the second electrode of the first transistor is electrically connected with the first initial signal line.

[0082] The second transistor is two, the control electrode of one of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, and the second electrode is electrically connected with the sixth node, the control electrode of the other of the two second transistors is electrically connected with the first scan signal line, the first electrode is electrically connected with the sixth node, and the second electrode is electrically connected with the third node; or, the second transistor is one, the second transistor is a double-gate transistor, the first control electrode and the second control electrode of the second transistor are electrically connected with the first scan signal line, the first electrode is electrically connected with the first node, the second electrode is electrically connected with the third node, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node.

[0083] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node.

[0084] The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the data signal line.

[0085] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line of the second capacitor, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0086] The control electrode of the sixth transistor is electrically connected with the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0087] The control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the second initial signal line;

[0088] The control electrode of the eighth transistor is electrically connected with the reset signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fifth node;

[0089] The control electrode of the tenth transistor is electrically connected with the third power supply line, the first electrode of the tenth transistor is electrically connected with the first initial signal line, and the second electrode of the tenth transistor is electrically connected with the sixth node;

[0090] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply line, and the second plate of the first capacitor is electrically connected with the first node.

[0091] In some possible implementation manners, the pixel driving circuit further includes a ninth transistor.

[0092] The control electrode of the ninth transistor is electrically connected with the second light-emitting signal line, the first electrode of the ninth transistor is electrically connected with the third initial signal line, and the second electrode of the ninth transistor is electrically connected with the second node.

[0093] In some possible implementation manners, at least one of the first transistor to the tenth transistor is a P-type transistor.

[0094] In a second aspect, the embodiments of the present disclosure provide a display device, including the pixel driving circuit according to any one of the embodiments of the first aspect.

[0095] In a third aspect, the embodiments of the present disclosure provide a driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of the embodiments of the first aspect, and the method includes:

[0096] The first control sub-circuit provides the signal of the first initial signal line to the first node and stores a voltage difference between the signals of the first node and the first power supply line under the control of the signal of at least one of the reset signal line and the second scan signal line;

[0097] The second control sub-circuit provides the signal of the third node to the first node under the control of the signals of the first scan signal line and the control signal line;

[0098] The third control sub-circuit provides the signal of the data signal line to the second node and provides the signal of the second initial signal line to the fourth node under the control of the signals of the first scan signal line and the second light-emitting signal line;

[0099] The driving sub-circuit provides a driving signal to the third node under the control of signals of the first node and the second node;

[0100] The light emitting control sub-circuit provides a signal of the first power supply line to the second node and a signal of the fourth node to the third node under the control of a signal of the first light emitting signal line.

[0101] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0102] SUMMARY

[0103] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0104] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an example embodiment of the present disclosure;

[0105] FIG. 2 is an equivalent circuit diagram of a driving sub-circuit provided by an example embodiment;

[0106] FIG. 3 is an equivalent circuit diagram of a first control sub-circuit provided by an example embodiment;

[0107] FIG. 4 is an equivalent circuit diagram of a first control sub-circuit provided by an example embodiment;

[0108] FIG. 5 is an equivalent circuit diagram of a second control sub-circuit provided by an example embodiment;

[0109] FIG. 6 is an equivalent circuit diagram of a second control sub-circuit provided by an example embodiment;

[0110] FIG. 7 is an equivalent circuit diagram of a light emitting control sub-circuit provided by an example embodiment;

[0111] FIG. 8 is a structural schematic diagram of a third control sub-circuit provided by an example embodiment of the present disclosure;

[0112] FIG. 9 is a structural schematic diagram of a pixel driving circuit provided by an example embodiment of the present disclosure;

[0113] FIG. 10 is an equivalent circuit diagram of a fourth control sub-circuit provided by an example embodiment;

[0114] FIG. 11 is an equivalent circuit schematic diagram of a pixel driving circuit;

[0115] FIG. 12 is a working timing diagram of the pixel driving circuit provided by FIG. 11;

[0116] FIG. 13 is a simulation timing diagram of the pixel driving circuit provided by FIG. 11;

[0117] Fig. 14 is an equivalent circuit schematic of a pixel drive circuit;

[0118] Fig. 15 is a timing diagram of the pixel drive circuit provided in Fig. 14;

[0119] Fig. 16 is a simulated timing diagram of the pixel drive circuit provided in Fig. 14;

[0120] Fig. 17 is an equivalent circuit schematic of a pixel drive circuit;

[0121] Fig. 18 is a timing diagram of the pixel drive circuit provided in Fig. 17;

[0122] Fig. 19 is an equivalent circuit schematic of a pixel drive circuit;

[0123] Fig. 20 is a timing diagram of the pixel drive circuit provided in Fig. 19;

[0124] Fig. 21A is an equivalent circuit schematic of a pixel drive circuit;

[0125] Fig. 21B is an equivalent circuit schematic of a pixel drive circuit;

[0126] Fig. 21C is an equivalent circuit schematic of a pixel drive circuit;

[0127] Fig. 21D is an equivalent circuit schematic of a pixel drive circuit.

[0128] DETAILED DESCRIPTION

[0129] To make the objects, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. One of ordinary skill in the art can easily understand that the manners and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0130] The scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in this disclosure are only schematic diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the drawings.

[0131] In this specification, ordinal terms such as "first", "second", and "third" are used to avoid confusion among components, and are not intended to limit in terms of numbers.

[0132] In this specification, for the convenience of explanation, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the components with reference to the drawings, and are only for the convenience of describing this specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on this disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0133] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0134] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0135] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0136] In the present specification, "electrically connected" includes a case where components are connected through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0137] In the present specification, "parallel" means a state where two straight lines form an angle of -10° or more and 10° or less, and thus, a state where the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where two straight lines form an angle of 80° or more and 100° or less, and thus, a state where the angle is 85° or more and 95° or less is also included.

[0138] In the present specification, "film" and "layer" can be replaced with each other. For example, "conductive layer" can be replaced with "conductive film". Similarly, "insulating film" can be replaced with "insulating layer".

[0139] In the present specification, "co-deposition" means that two (or more) structures are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of the precursors for forming the two (or more) structures by co-deposition are the same, and the materials of the final structures can be the same or different.

[0140] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, and deformation, and the like.

[0141] In the present disclosure, "about" means not strictly limited to the boundary, and allows values within a range of process and measurement errors.

[0142] The display panel of the OLED or QLED includes a substrate and a plurality of sub-pixels disposed on the substrate, and at least one of the sub-pixels includes a pixel driving circuit. A driving sub-circuit in the pixel driving circuit is configured to provide a driving signal to drive a transistor OLED or QLED to emit light. The driving sub-circuit generally includes a driving transistor. When displaying at a low frequency, there is a leakage of the control voltage (such as the gate voltage of the driving transistor) of the driving sub-circuit, which can cause a more obvious human eye flicker in low-frequency display.

[0143] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an example embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit can include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light-emitting control sub-circuit.

[0144] The first control sub-circuit is electrically connected with the first node N1, at least one of the reset signal line Reset and the second scan signal line Gate2, the first power supply line ELVDD and the first initial signal line Vint1 respectively, and is configured to provide the signal of the first initial signal line Vint1 to the first node N1 under the control of the signal of at least one of the reset signal line Reset and the second scan signal line Gate2, and store the voltage difference of the signals of the first node N1 and the first power supply line ELVDD.

[0145] The second control sub-circuit is electrically connected with the first node N1, the third node N3, the first scan signal line Gate1 and the control signal line CK respectively, and is configured to provide the signal of the third node N3 to the first node N1 under the control of the signals of the first scan signal line Gate1 and the control signal line CK.

[0146] The third control sub-circuit is electrically connected with the second node N2, the first scan signal line Gate1, the data signal line Data, the fourth node N4, the second emitting signal line EM2 and the second initial signal line Vint2 respectively, and is configured to provide the signal of the data signal line Data to the second node N2 under the control of the signals of the first scan signal line Gate1 and the second emitting signal line EM2, and provide the signal of the second initial signal line Vint2 to the fourth node N4.

[0147] The driving sub-circuit is electrically connected with the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide the driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0148] The emitting control sub-circuit is electrically connected with the first power supply line ELVDD, the first emitting signal line EM1, the second node N2, the third node N3 and the fourth node N4 respectively, and is configured to provide the signal of the first power supply line ELVDD to the second node N2 under the control of the signal of the first emitting signal line EM1, and provide the signal of the fourth node N4 to the third node N3.

[0149] In an example embodiment, the signal of the first power supply line ELVDD is a high-level signal.

[0150] In the embodiment of the present disclosure, the first control sub-circuit provides the signal of the first initial signal line to the first node under the control of the signal of at least one of the reset signal line and the second scan signal line, and stores the voltage difference between the signal of the first node and the signal of the first power supply line, the second control sub-circuit provides the signal of the third node to the first node under the control of the signals of the first scan signal line and the control signal line, and the driving sub-circuit provides the driving signal to the third node under the control of the signals of the first node and the second node. Through the control of the signals of at least one of the reset signal line and the second scan signal line, the first scan signal line and the control signal line by the first control sub-circuit and the second control sub-circuit, the control voltage (that is, the voltage of the first node) of the driving sub-circuit can be stabilized, the leakage of the control voltage of the driving sub-circuit can be reduced, the problem of obvious human eye flicker in low-frequency display can be improved, and the display effect can be improved.

[0151] FIG. 2 is an equivalent circuit diagram of the driving sub-circuit provided by an example embodiment. As shown in FIG. 2, in an example embodiment, the driving sub-circuit can include a third transistor T3.

[0152] In an example embodiment, as shown in FIG. 2, the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3.

[0153] In an example embodiment, the third transistor T3 is a single-gate transistor.

[0154] In an example embodiment, the third transistor T3 can be referred to as a driving transistor, and the driving current flowing between the second node N2 and the third node N3 is determined according to the potential difference between the gate electrode (also the first node N1) and the first electrode (also the second node N2) of the third transistor T3.

[0155] An example structure of the driving sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the driving sub-circuit is not limited to this.

[0156] In an example embodiment, the first control sub-circuit is electrically connected with the first node N1, the reset signal line Reset, the second scan signal line Gate2, the first power supply line ELVDD, the first initial signal line Vinit1 and the fifth node N5 respectively, and is configured to provide the signal of the first initial signal line Vinit1 to the fifth node N5 under the control of the signals of the reset signal line Reset and the second scan signal line Gate2, and provide the signal of the fifth node N5 to the first node N1.

[0157] FIG. 3 is an equivalent circuit diagram of the first control sub-circuit according to an example embodiment. As shown in FIG. 3, in an example embodiment, the first control sub-circuit can include a first transistor T1, an eighth transistor T8, a first capacitor C1, and a second capacitor C2.

[0158] In an example embodiment, as shown in FIG. 3, a control electrode of the first transistor T1 is electrically connected with the reset signal line Reset, a first electrode of the first transistor T1 is electrically connected with the fifth node N5, and a second electrode of the first transistor T1 is electrically connected with the first initial signal line Vinit1; a control electrode of the eighth transistor T8 is electrically connected with the second scan signal line Gate2, a first electrode of the eighth transistor T8 is electrically connected with the first node N1, and a second electrode of the eighth transistor T8 is electrically connected with the fifth node N5; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power supply line ELVDD, and the second plate C12 of the first capacitor is electrically connected with the first node N1; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first initial signal line Vinit1, and the second plate C22 of the second capacitor is electrically connected with the fifth node N5.

[0159] In the embodiments of the present disclosure, by adding the second capacitor C2 between the first transistor T1 and the eighth transistor T8, the voltage change (leakage) of the first node N1 can be reduced, the leakage path of the first node N1 can be improved, and the display effect can be improved.

[0160] An example structure of the first control sub-circuit is shown in FIG. 3. It is easy for those skilled in the art to understand that the implementation of the first control sub-circuit is not limited thereto.

[0161] In an example embodiment, the first control sub-circuit is electrically connected with the first node N1, the reset signal line Reset, the first power supply line ELVDD, the first initial signal line Vinit1, and the fifth node N5, respectively, and is configured to provide the signal of the first initial signal line Vinit1 to the fifth node N5 and provide the signal of the fifth node N5 to the first node N1 under the control of the signal of the reset signal line Reset.

[0162] FIG. 4 is an equivalent circuit diagram of the first control sub-circuit according to an example embodiment. As shown in FIG. 4, in an example embodiment, the first control sub-circuit can include a first transistor T1, an eighth transistor T8, and a first capacitor C1.

[0163] In an example embodiment, as shown in FIG. 4, the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the fifth node N5, and the second electrode of the first transistor T1 is electrically connected to the first initial signal line Vinit1; the control electrode of the eighth transistor T8 is electrically connected to the reset signal line Reset, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first power supply line ELVDD, and the second plate C12 of the first capacitor is electrically connected to the first node N1.

[0164] An example structure of the first control sub-circuit is shown in FIG. 4. It is easy for those skilled in the art to understand that the implementation of the first control sub-circuit is not limited thereto.

[0165] In an example embodiment, the control signal line CK can include a second light-emitting signal line EM2, and the second control sub-circuit is electrically connected to the first node N1, the third node N3, the first scan signal line Gate1, the second light-emitting control signal line EM2, and the fifth node N5, respectively, and is configured to provide the signal of the third node N3 or the fifth node N5 to the first node N1 under the control of the signals of the first scan signal line Gate1 and the second light-emitting control signal line EM2.

[0166] FIG. 5 is an equivalent circuit diagram of the second control sub-circuit provided by an example embodiment. As shown in FIG. 5, in an example embodiment, the second control sub-circuit can include a tenth transistor T10 and two second transistors T2.

[0167] In an example embodiment, as shown in FIG. 5, the control electrode of one of the two second transistors T2 is electrically connected to the first scan signal line Gate1, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the sixth node N6; the control electrode of the other of the two second transistors T2 is electrically connected to the first scan signal line Gate1, the first electrode is electrically connected to the sixth node N6, and the second electrode is electrically connected to the third node N3; the control electrode of the tenth transistor T10 is electrically connected to the second light-emitting signal line EM2, the first electrode of the tenth transistor T10 is electrically connected to the fifth node N5, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6.

[0168] In an alternative embodiment, the second control sub-circuit can include a tenth transistor T10 and a second transistor T2, and the second transistor T2 is a double-gate transistor.

[0169] The first control electrode and the second control electrode of the second transistor T2 are electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, the second electrode is electrically connected with the third node N3, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node N6; the control electrode of the tenth transistor 10 is electrically connected with the second emitting signal line EM2, the first electrode of the tenth transistor 10 is electrically connected with the fifth node N5, and the second electrode of the tenth transistor 10 is electrically connected with the sixth node N6.

[0170] An exemplary structure of the second control sub-circuit is shown in FIG. 5. It is easy for those skilled in the art to understand that the implementation of the second control sub-circuit is not limited to this.

[0171] In an exemplary embodiment, the control signal line CK can include a third power line VGH, and the second control sub-circuit is electrically connected with the first node N1, the third node N3, the first scan signal line Gate1, the first initial signal line Vinit1 and the third power line VGH respectively, and is configured to provide the signal of the third node N3 or the first initial signal line Vinit1 to the first node N1 under the control of the signals of the first scan signal line Gate1 and the third power line VGH.

[0172] In an exemplary embodiment, the signal of the third power line VGH is a high-level signal.

[0173] FIG. 6 is an equivalent circuit diagram of the second control sub-circuit provided by an exemplary embodiment. As shown in FIG. 6, in an exemplary embodiment, the second control sub-circuit can include: a tenth transistor T10 and two second transistors T2.

[0174] In an exemplary embodiment, as shown in FIG. 6, the control electrode of one of the two second transistors T2 is electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, and the second electrode is electrically connected with the sixth node N6; the control electrode of the other of the two second transistors T2 is electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the sixth node N6, and the second electrode is electrically connected with the third node N3; the control electrode of the tenth transistor T10 is electrically connected with the third power line VGH, the first electrode of the tenth transistor T10 is electrically connected with the first initial signal line Vinit1, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6.

[0175] In an alternative embodiment, the second control sub-circuit can include: a tenth transistor T10 and a second transistor T2, and the second transistor T2 is a double-gate transistor.

[0176] The first control electrode and the second control electrode of the second transistor T2 are electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, the second electrode is electrically connected with the third node N3, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected with the third power supply line VGH, the first electrode of the tenth transistor T10 is electrically connected with the first initial signal line Vinit1, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6.

[0177] In the embodiment of the present disclosure, the control electrode of the tenth transistor T10 is electrically connected with the third power supply line VGH, the third power supply line VGH continuously provides a stable high-level signal, and the tenth transistor T10 is always turned off. Through the tenth transistor T10 which is always turned off, the voltage change (leakage) of the first node N1 can be reduced, the leakage path of the first node N1 is improved, and the display effect is improved.

[0178] An example structure of the second control sub-circuit is shown in FIG. 6. It is easy for those skilled in the art to understand that the implementation of the second control sub-circuit is not limited to this.

[0179] FIG. 7 is an equivalent circuit diagram of a light emitting control sub-circuit provided by an example embodiment. As shown in FIG. 7, in an example embodiment, the light emitting control sub-circuit can include a fifth transistor T5 and a sixth transistor T6.

[0180] In an example embodiment, as shown in FIG. 7, the control electrode of the fifth transistor T5 is electrically connected with the first light emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line ELVDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2 respectively; the control electrode of the sixth transistor T6 is electrically connected with the first light emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fourth node N4.

[0181] In an example embodiment, as shown in FIG. 7, the fourth node N4 can also be connected with a light emitting device L, the first electrode of the light emitting device L is electrically connected with the fourth node N4, and the second electrode of the light emitting device L is electrically connected with the second power supply line ELVSS.

[0182] In an example embodiment, the light emitting device L can be an organic electroluminescence diode (OLED) or a quantum dot light emitting diode (QLED). The OLED can include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) which are stacked.

[0183] In an example embodiment, the signal of the second power supply line ELVSS is a low-level signal.

[0184] In an example embodiment, the fifth transistor T5 can be referred to as a first light emitting transistor, and the sixth transistor T6 can be referred to as a second light emitting transistor. When the first light emitting signal line EM1 inputs a valid level signal, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device L to emit light by forming a driving current path between the first power supply line ELVDD and the second power supply line ELVSS.

[0185] An example structure of the light emitting control sub-circuit is shown in FIG. 7. It is easily understood by those skilled in the art that the implementation of the light emitting control sub-circuit is not limited thereto.

[0186] FIG. 8 is a structural schematic diagram of a third control sub-circuit according to an example embodiment of the present disclosure. As shown in FIG. 8, the third control sub-circuit can include a fourth transistor T4 and a seventh transistor T7.

[0187] In an example embodiment, as shown in FIG. 8, a control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, a first electrode of the fourth transistor T4 is electrically connected with the second node N2, and a second electrode of the fourth transistor T4 is electrically connected with the data signal line Data; a control electrode of the seventh transistor T7 is electrically connected with the second light emitting signal line EM2, a first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and a second electrode of the seventh transistor T7 is electrically connected with the second initial signal line Vint2.

[0188] An example structure of the third control sub-circuit is shown in FIG. 8. It is easily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited thereto.

[0189] FIG. 9 is a structural schematic diagram of a pixel driving circuit according to an example embodiment of the present disclosure. As shown in FIG. 9, the pixel driving circuit can further include a fourth control sub-circuit.

[0190] In an example embodiment, as shown in FIG. 9, the fourth control sub-circuit is electrically connected with the second node N2, the second light emitting signal line EM2 and the third initial signal line Vinit3 respectively, and is configured to provide the signal of the third initial signal line Vinit3 to the second node N2 under the control of the signal of the second light emitting signal line EM2.

[0191] FIG. 10 is an equivalent circuit diagram of the fourth control sub-circuit according to an example embodiment. As shown in FIG. 10, in an example embodiment, the fourth control sub-circuit can include a ninth transistor T9.

[0192] In an example embodiment, as shown in FIG. 10, a control electrode of the ninth transistor T9 is electrically connected with the second light emitting signal line EM2, a first electrode of the ninth transistor T9 is electrically connected with the third initial signal line Vinit3, and a second electrode of the ninth transistor T9 is electrically connected with the second node N2.

[0193] An exemplary structure of the fourth control sub-circuit is shown in FIG. 10. It is easy for those skilled in the art to understand that the implementation of the fourth control sub-circuit is not limited to this.

[0194] FIG. 11 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 11, the first control sub-circuit can include a first transistor T1, an eighth transistor T8, a first capacitor C1 and a second capacitor C2, the second control sub-circuit can include a tenth transistor T10 and two second transistors T2, the driving sub-circuit can include a third transistor T3, the light-emitting control sub-circuit can include a fifth transistor T5 and a sixth transistor T6, and the third control sub-circuit can include a fourth transistor T4 and a seventh transistor T7.

[0195] In an example embodiment, as shown in FIG. 11, the control electrode of the first transistor T1 is electrically connected with the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected with the fifth node N5, and the second electrode of the first transistor T1 is electrically connected with the first initial signal line Vinit1; the control electrode of one of the two second transistors T2 is electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, and the second electrode is electrically connected with the sixth node N6; the control electrode of the other of the two second transistors T2 is electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the sixth node N6, and the second electrode is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the data signal line Data; the control electrode of the fifth transistor T5 is electrically connected with the first emission signal line EM1 of the second capacitor, the first electrode of the fifth transistor T5 is electrically connected with the first power line ELVDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the first emission signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected with the second emission signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the second initial signal line Vinit2; the control electrode of the eighth transistor T8 is electrically connected with the second scan signal line Gate2, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fifth node N5; the control electrode of the tenth transistor T10 is electrically connected with the second emission signal line EM2, the first electrode of the tenth transistor T10 is electrically connected with the fifth node N5, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power line ELVDD, and the second plate C12 of the first capacitor is electrically connected with the first node N1; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first initial signal line Vinit1, and the second plate C22 of the second capacitor is electrically connected with the fifth node N5.

[0196] In an alternative embodiment, the second transistor T2 can be one, the second transistor T2 is a double-gate transistor, the first control electrode and the second control electrode of the second transistor T2 are electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, the second electrode is electrically connected with the third node N3, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node N6.

[0197] In an example embodiment, the types of the first transistor T1 to the eighth transistor T8 and the tenth transistor are P-type transistors.

[0198] In the embodiments of the present disclosure, the third transistor T3 can be a single-gate transistor. By arranging the second capacitor C2 between the first transistor T1 and the eighth transistor T8, the voltage signal of the sixth node N6 at the initial moment of light emission can be reduced, so that the voltage of the sixth node N6 is closer to the voltage of the first node N1, the leakage current of the first node N1 in a frame is reduced, the problem of high-brightness decay in low-frequency display is improved, and the display effect is improved.

[0199] An example structure of the pixel driving circuit is shown in FIG. 11. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0200] FIG. 12 is a timing diagram of the pixel driving circuit provided in FIG. 11. The working process of the pixel driving circuit shown in FIG. 11 is described below to illustrate the example embodiments of the present disclosure. The working process of the pixel driving circuit can include:

[0201] The first stage S1 is called the initial stage. The signals of the first scan signal line Gate1, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high-level signals, and the signals of the reset signal line Reset and the second scan signal line Gate2 are all low-level signals. The signal of the reset signal line Reset is a low-level signal, the first transistor T1 is turned on, the signal of the second scan signal line Gate2 is a low-level signal, the eighth transistor T8 is turned on, and the signal of the first initial signal line Vinit1 is provided to the first node N1 through the fifth node N5, so as to initialize the fifth node N5 and the gate electrode of the third transistor T3 (that is, the first node N1), for example, to empty the pre-stored voltage in the internal thereof, and complete the initialization. The second transistor T2 to the seventh transistor T7 and the tenth transistor T10 are disconnected. In this stage, the light-emitting device L does not emit light.

[0202] The second stage S2 is called a compensation stage, and the signals of the reset signal line Reset, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high-level signals, and the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are all low-level signals. In this stage, since the first node N1 is a low-level signal, the third transistor T3 is turned on. The signal of the first scan signal line Gate1 is a low-level signal, the second transistor T2 is turned on, the fourth transistor T4 is turned on, the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the first capacitor C1 until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3; and the data voltage output by the data signal line Data is provided to the fifth node N5 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2 and the turned-on eighth transistor T8. The signal of the reset signal line Reset is a high-level signal, and the first transistor T1 is turned off. Among them, the first transistor T1, the fifth transistor T5 to the seventh transistor T7 and the tenth transistor T10 are turned off. In this stage, the light-emitting device L does not emit light.

[0203] The third stage S3 is called a writing stage, and the signals of the reset signal line Reset, the first scan signal line Gate1, the second scan signal line Gate2 and the first light-emitting signal line EM1 are all high-level signals, and the signal of the second light-emitting signal line EM2 is a low-level signal. The signal of the second light-emitting signal line EM2 is a low-level signal, the tenth transistor T10 is turned on, and the signal of the fifth node is written to the sixth node N6 through the tenth transistor T10; the seventh transistor T7 is turned on, and the signal of the second initial signal line Vinit2 is written to the fourth node N4 to initialize (reset) the first electrode of the light-emitting device L, for example: empty the pre-stored voltage in the internal thereof, and complete the initialization. The signal of the first scan signal line Gate1 is a high-level signal, and the second transistor T2 and the fourth transistor T4 are turned off; the signal of the second scan signal line Gate2 is a high-level signal, and the eighth transistor T8 is turned off. Among them, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting device L does not emit light.

[0204] The fourth stage S4 is called a light emitting stage, the signal of the first light emitting signal line EM1 is a low level signal, the signals of the reset signal line Reset, the first scan signal line Gate1, the second scan signal line Gate2 and the second light emitting signal line EM2 are all high level signals. The signal of the second light emitting signal line EM2 is a high level signal, the seventh transistor T7 and the tenth transistor T10 are turned off. The signal of the first light emitting signal line EM1 is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the driving voltage output by the first power supply line ELVDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor M5, the turned-on third transistor M3 and the turned-on sixth transistor M6, and the light emitting device L is driven to emit light.

[0205] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0206] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power voltage output by the first power supply line ELVDD.

[0207] FIG. 13 is a simulation timing diagram of the pixel driving circuit provided in FIG. 11. As shown in FIG. 13, the output signals of the first scan signal line Gate1 and the reset signal line Reset can be one pulse signal shown in FIG. 12, or can be three pulse signals shown in FIG. 13. In FIG. 13, the horizontal axis represents time, and the vertical axis represents voltage. Based on the simulation timing diagram shown in FIG. 13, the simulation values of the simulation effect of the pixel driving circuit shown in Table 1 can be obtained.

[0208] Table 1

[0209] Time Voltage of the first node N1 / V Light emitting device current / nA

[0210] Before improvement After improvement Before improvement After improvement

[0211] In one frame, the beginning is 0.73936 0.78266 64.435 59.567

[0212] Intra-frame end 0.76559 0.78425 61.352 59.386

[0213] Retention rate 103.55% 100.20% 95.22% 99.69%

[0214] As shown in Table 1, the pixel driving circuit provided by the embodiment of the present disclosure can improve the voltage retention rate of the first node N1 in a low-frequency driving mode. Before improvement, the voltage retention rate of the first node N1 in a frame is 103.55%. After using the pixel driving circuit provided by the embodiment of the present disclosure, the voltage retention rate of the first node N1 can be reduced to 100.20%, and the improvement amount (or reduction amount) is 3.35%. Correspondingly, before improvement, the current retention rate of the light emitting device in a frame is 95.22%. After using the pixel driving circuit provided by the embodiment of the present disclosure, the current retention rate of the light emitting device can be improved to 99.69%, and the improvement amount (or reduction amount) is 4.47%.

[0215] FIG. 14 is a schematic equivalent circuit diagram of a pixel driving circuit. As shown in FIG. 14, the first control sub-circuit includes a first transistor T1, an eighth transistor T8 and a first capacitor C1, the second control sub-circuit includes a tenth transistor T10 and two second transistors T2, the driving sub-circuit includes a third transistor T3, the light emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, and the third control sub-circuit includes a fourth transistor T4 and a seventh transistor T7.

[0216] In an example embodiment, as shown in FIG. 14, the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the fifth node N5, and the second electrode of the first transistor T1 is electrically connected to the first initial signal line Vinit1; the control electrode of one of the two second transistors T2 is electrically connected to the first scan signal line Gate1, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the sixth node N6; the control electrode of the other of the two second transistors T2 is electrically connected to the first scan signal line Gate1, the first electrode is electrically connected to the sixth node N6, and the second electrode is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the data signal line Data; the control electrode of the fifth transistor T5 is electrically connected to the first emission signal line EM1 of the second capacitor, the first electrode of the fifth transistor T5 is electrically connected to the first power line ELVDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first emission signal line EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the second emission signal line EM2, the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected to the second initial signal line Vinit2; the control electrode of the eighth transistor T8 is electrically connected to the reset signal line Reset, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the control electrode of the tenth transistor T10 is electrically connected to the third power line VGH, the first electrode of the tenth transistor T10 is electrically connected to the first initial signal line Vinit1, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first power line ELVDD, and the second plate C12 of the first capacitor is electrically connected to the first node N1.

[0217] In an alternative embodiment, the second transistor T2 can be one, and the second transistor T2 is a double-gate transistor, the first control electrode and the second control electrode of the second transistor T2 are electrically connected to the first scan signal line Gate1, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the third node N3, and the connection point of the first control electrode and the second control electrode is electrically connected to the sixth node N6.

[0218] In an example embodiment, the first transistor T1 to the eighth transistor T8 and at least one of the tenth transistor are P-type transistors.

[0219] In the example embodiment of the present disclosure, the tenth transistor T10 is electrically connected with the third power supply line VGH, and the third power supply line VGH continuously provides a stable high-level signal, and the tenth transistor T10 is always off. In the light-emitting stage, the high potential of the sixth node N6 can be consumed by the tenth transistor T10 which is always off, thereby reducing the leakage current between the sixth node N6 and the first node N1, and improving the voltage retention rate of the first node N1 in a low-frequency driving mode.

[0220] An example structure of the pixel driving circuit is shown in FIG. 14. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0221] FIG. 15 is a timing diagram of the pixel driving circuit provided in FIG. 14. The working process of the pixel driving circuit illustrated by FIG. 15 is used to explain the example embodiment of the present disclosure, and the working process of the pixel driving circuit can include:

[0222] The first stage S1 is referred to as an initial stage, and the signals of the first scan signal line Gate1, the third power supply line VGH, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high-level signals, and the signal of the reset signal line Reset is a low-level signal. The signal of the reset signal line Reset is a low-level signal, the first transistor T1 is turned on, the eighth transistor T8 is turned on, and the signal of the first initial signal line Vinit1 is provided to the first node N1 to initialize the gate electrode (i.e., the first node N1) of the third transistor T3, for example, to empty the internal pre-stored voltage, and the initialization is completed. The signal of the third power supply line VGH is a high-level signal, and the tenth transistor T10 is always off. Among them, the second transistor T2 to the seventh transistor T7 are off. In this stage, the light-emitting device L does not emit light.

[0223] The second stage S2 is called a compensation stage, the signals of the reset signal line Reset, the third power supply line VGH, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high-level signals, and the signal of the first scan signal line Gate1 is a low-level signal. In this stage, since the first node N1 is a low-level signal, the third transistor T3 is turned on. The signal of the first scan signal line Gate1 is a low-level signal, the second transistor T2 is turned on, the fourth transistor T4 is turned on, the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the first capacitor C1, until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3. The signal of the reset signal line Reset is a high-level signal, and the first transistor T1 is turned off. The first transistor T1, the fifth transistor T5 to the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0224] The third stage S3 is called a writing stage, the signals of the reset signal line Reset, the third power supply line VGH, the first scan signal line Gate1 and the first light-emitting signal line EM1 are all high-level signals, and the signal of the second light-emitting signal line EM2 is a low-level signal. The signal of the second light-emitting signal line EM2 is a low-level signal, the seventh transistor T7 is turned on, the signal of the second initial signal line Vinit2 is written into the fourth node N4, and the first electrode of the light-emitting device L is initialized (reset), for example, the internal pre-stored voltage is emptied, and the initialization is completed. The signal of the first scan signal line Gate1 is a high-level signal, and the second transistor T2 and the fourth transistor T4 are turned off. The first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting device L does not emit light.

[0225] The fourth stage S4 is called a light-emitting stage, the signal of the first light-emitting signal line EM1 is a low-level signal, and the signals of the reset signal line Reset, the third power supply line VGH, the first scan signal line Gate1 and the second light-emitting signal line EM2 are all high-level signals. The signal of the second light-emitting signal line EM2 is a high-level signal, and the seventh transistor T7 is turned off. The signal of the first light-emitting signal line EM1 is a low-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output by the first power supply line ELVDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the turned-on third transistor M3 and the turned-on sixth transistor M6, and drives the light-emitting device L to emit light.

[0226] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0227] wherein I is the driving current flowing through the third transistor T3, that is, the driving current of the light emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power voltage output by the first power supply line ELVDD.

[0228] FIG. 16 is a simulation timing diagram of the pixel driving circuit provided in FIG. 14, as shown in FIG. 16, curve L1 represents the voltage of the first node N1 before improvement, curve L2 represents the voltage of the first node N1 after improvement by using the pixel driving circuit according to the embodiment of the present disclosure, curve Q1 represents the current of the light emitting device before improvement, and curve Q2 represents the current of the light emitting device after improvement by using the pixel driving circuit according to the embodiment of the present disclosure, wherein NV in FIG. 16 represents the voltage of the first node N1, and LI represents the current of the light emitting device, the horizontal axis in FIG. 16 represents time, and the vertical axis represents voltage or current. Since the tenth transistor T10 newly added in the embodiment of the present disclosure is always off, the leakage of the first node N1 in one frame at a low frequency can be balanced, so that the current of the light emitting device does not monotonically decrease. Based on the simulation timing diagram shown in FIG. 16, the simulation values of the simulation effect of the pixel driving circuit shown in Table 2 can be obtained.

[0229] Table 2

[0230] Time Voltage of the first node N1 / V Current of the light emitting device / nA

[0231] Before improvement After improvement Before improvement After improvement

[0232] Start of one frame 0.73982 0.76174 64.372 61.861

[0233] End of one frame 0.76554 0.75755 61.357 62.456

[0234] Retention rate 103.48% 99.45% 95.32% 100.79%

[0235] As shown in Table 2, the pixel driving circuit provided by the embodiment of the present disclosure can improve the voltage retention rate of the first node N1 within a frame under low-frequency driving. Before improvement, the voltage retention rate of the first node N1 within a frame is 103485%, and after the pixel driving circuit provided by the embodiment of the present disclosure is used, the voltage retention rate of the first node N1 can be reduced to 99.45%, and the improvement amount (or reduction amount) is 4.03%. Correspondingly, before improvement, the current retention rate of the light emitting device within a frame is 95.32%, and after the pixel driving circuit provided by the embodiment of the present disclosure is used, the current retention rate of the light emitting device can be improved to 100.79%, and the improvement amount is 5.47%.

[0236] FIG. 17 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 17, the first control sub-circuit includes a first transistor T1, an eighth transistor T8, a first capacitor C1 and a second capacitor C2, the second control sub-circuit can include a tenth transistor T10 and two second transistors T2, the driving sub-circuit can include a third transistor T3, the light emitting control sub-circuit can include a fifth transistor T5 and a sixth transistor T6, and the third control sub-circuit can include a fourth transistor T4 and a seventh transistor T7.

[0237] In an example embodiment, as shown in FIG. 17, the control electrode of the first transistor T1 is electrically connected with the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected with the fifth node N5, and the second electrode of the first transistor T1 is electrically connected with the first initial signal line Vinit1; the control electrode of one of the two second transistors T2 is electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, and the second electrode is electrically connected with the sixth node N6; the control electrode of the other of the two second transistors T2 is electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the sixth node N6, and the second electrode is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the data signal line Data; the control electrode of the fifth transistor T5 is electrically connected with the first emission signal line EM1 of the second capacitor, the first electrode of the fifth transistor T5 is electrically connected with the first power line ELVDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the first emission signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected with the second emission signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with the second initial signal line Vinit2; the control electrode of the eighth transistor T8 is electrically connected with the second scan signal line Gate2, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fifth node N5; the control electrode of the tenth transistor T10 is electrically connected with the third power line VGH, the first electrode of the tenth transistor is electrically connected with the first initial signal line Vinit1, and the second electrode of the tenth transistor is electrically connected with the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power line ELVDD, and the second plate C12 of the first capacitor is electrically connected with the first node N1; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first initial signal line Vinit1, and the second plate C22 of the second capacitor is electrically connected with the fifth node N5.

[0238] In an alternative embodiment, the second transistor T2 can be one, the second transistor T2 is a double-gate transistor, the first control electrode and the second control electrode of the second transistor T2 are electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, the second electrode is electrically connected with the third node N3, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node N6.

[0239] In an exemplary embodiment, the types of the first transistor T1 to the eighth transistor T8 and the tenth transistor are P-type transistors.

[0240] In the embodiments of the present disclosure, the third transistor T3 can be a single-gate transistor. By arranging the second capacitor C2 between the first transistor T1 and the eighth transistor T8, the voltage signal of the sixth node N6 at the initial moment of light emission can be reduced, so that the voltage of the sixth node N6 is closer to the voltage of the first node N1, the leakage amount of the first node N1 in a frame is reduced, the problem of high-brightness decay in low-frequency display is improved, and the display effect is improved. In addition, the tenth transistor T10 is electrically connected with the third power line VGH, the third power line VGH continuously provides a stable high-level signal, and the tenth transistor T10 is always disconnected. In the light-emitting stage, the high potential of the sixth node N6 can consume a part through the always disconnected tenth transistor T10, reducing the leakage amount of the sixth node N6 and the first node N1, which can improve the voltage retention rate of the first node N1 in a frame under low-frequency driving, and improve the display effect.

[0241] An exemplary structure of the pixel driving circuit is shown in FIG. 17. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0242] FIG. 18 is a timing diagram of the pixel driving circuit provided in FIG. 17. The working process of the pixel driving circuit shown in FIG. 17 is described below to illustrate the exemplary embodiments of the present disclosure. The working process of the pixel driving circuit can include:

[0243] The first stage S1 is called an initial stage. The signals of the first scan signal line Gate1, the first light-emitting signal line EM1, the second light-emitting signal line EM2 and the third power supply line VGH are all high-level signals, and the signals of the reset signal line Reset and the second scan signal line Gate2 are all low-level signals. The signal of the reset signal line Reset is a low-level signal, the first transistor T1 is turned on, the signal of the second scan signal line Gate2 is a low-level signal, the eighth transistor T8 is turned on, the signal of the first initial signal line Vinit1 is provided to the first node N1 through the fifth node N5, the fifth node N5 and the gate electrode of the third transistor T3 (i.e., the first node N1) are initialized, for example, the internal pre-stored voltage is emptied, and the initialization is completed. The signal of the third power supply line VGH is a high-level signal, and the tenth transistor T10 is always disconnected. The second transistor T2 to the seventh transistor T7 are disconnected. In this stage, the light-emitting device L does not emit light.

[0244] The second stage S2 is called a compensation stage. The signals of the reset signal line Reset, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high-level signals, and the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are all low-level signals. In this stage, since the first node N1 is a low-level signal, the third transistor T3 is turned on. The signal of the first scan signal line Gate1 is a low-level signal, the second transistor T2 is turned on, the fourth transistor T4 is turned on, the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the first capacitor C1, until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3; and the data voltage output by the data signal line Data is provided to the fifth node N5 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2 and the turned-on eighth transistor T8. The signal of the reset signal line Reset is a high-level signal, and the first transistor T1 is disconnected. The first transistor T1, the fifth transistor T5 to the seventh transistor T7 are disconnected. In this stage, the light-emitting device L does not emit light.

[0245] The third stage S3 is called a writing stage, the signals of the reset signal line Reset, the first scan signal line Gate 1, the second scan signal line Gate 2 and the first emitting signal line EM 1 are high level signals, and the signal of the second emitting signal line EM 2 is a low level signal. The signal of the second emitting signal line EM 2 is a low level signal, the seventh transistor T7 is turned on, the signal of the second initial signal line Vinit 2 is written to the fourth node N4, the first electrode of the light emitting device L is initialized (reset), for example, the internal pre-stored voltage is emptied, and the initialization is completed. The signal of the first scan signal line Gate 1 is a high level signal, the second transistor T2 and the fourth transistor T4 are disconnected; the signal of the second scan signal line Gate 2 is a high level signal, and the eighth transistor T8 is disconnected. Among them, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are disconnected. In this stage, the light emitting device L does not emit light.

[0246] The fourth stage S4 is called an emitting stage, the signal of the first emitting signal line EM 1 is a low level signal, and the signals of the reset signal line Reset, the first scan signal line Gate 1, the second scan signal line Gate 2 and the second emitting signal line EM 2 are high level signals. The signal of the second emitting signal line EM 2 is a high level signal, and the seventh transistor T7 is disconnected. The signal of the first emitting signal line EM 1 is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving voltage is provided to the first electrode of the light emitting device L from the first power supply line ELVDD through the turned-on fifth transistor M5, the turned-on third transistor M3 and the turned-on sixth transistor M6, so that the light emitting device L emits light.

[0247] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0248] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line ELVDD.

[0249] Fig. 19 is a schematic view of an equivalent circuit of a pixel driving circuit. As shown in Fig. 19, the first control sub-circuit includes a first transistor T1, an eighth transistor T8 and a first capacitor C1, the second control sub-circuit includes a tenth transistor T10 and two second transistors T2, the driving sub-circuit includes a third transistor T3, the light emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, and the third control sub-circuit includes a fourth transistor T4 and a seventh transistor T7.

[0250] In an example embodiment, as shown in Fig. 19, the control electrode of the first transistor T1 is electrically connected with a reset signal line Reset, the first electrode of the first transistor T1 is electrically connected with a fifth node N5, and the second electrode of the first transistor T1 is electrically connected with a first initial signal line Vinit1; the control electrode of one of the two second transistors T2 is electrically connected with a first scan signal line Gate1, the first electrode is electrically connected with a first node N1, and the second electrode is electrically connected with a sixth node N6; the control electrode of the other of the two second transistors T2 is electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the sixth node N6, and the second electrode is electrically connected with a third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with a second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with a data signal line Data; the control electrode of the fifth transistor T5 is electrically connected with a first emitting signal line EM1 of a second capacitor, the first electrode of the fifth transistor T5 is electrically connected with a first power line ELVDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the first emitting signal line EM1, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with a fourth node N4; the control electrode of the seventh transistor T7 is electrically connected with a second emitting signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected with a second initial signal line Vinit2; the control electrode of the eighth transistor T8 is electrically connected with the reset signal line Reset, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fifth node N5; the control electrode of the tenth transistor T10 is electrically connected with the second emitting signal line EM2, the first electrode of the tenth transistor T10 is electrically connected with the fifth node N5, and the second electrode of the tenth transistor T10 is electrically connected with the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power line ELVDD, and the second plate C12 of the first capacitor is electrically connected with the first node N1.

[0251] In an alternative embodiment, the second transistor T2 can be one, the second transistor T2 is a double-gate transistor, the first control electrode and the second control electrode of the second transistor T2 are electrically connected with the first scan signal line Gate1, the first electrode is electrically connected with the first node N1, the second electrode is electrically connected with the third node N3, and the connection point of the first control electrode and the second control electrode is electrically connected with the sixth node N6.

[0252] In an exemplary embodiment, the types of the first transistor T1 to the eighth transistor T8 and the tenth transistor are P-type transistors.

[0253] An exemplary structure of the pixel driving circuit is shown in FIG. 19. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0254] FIG. 20 is a timing diagram of the pixel driving circuit provided in FIG. 19. The working process of the pixel driving circuit exemplified by FIG. 19 is described below to illustrate the exemplary embodiments of the present disclosure. The working process of the pixel driving circuit can include:

[0255] The first stage S1 is called the initial stage. The signals of the first scan signal line Gate1, the first emission signal line EM1 and the second emission signal line EM2 are all high-level signals, and the signal of the reset signal line Reset is a low-level signal. The signal of the reset signal line Reset is a low-level signal, the first transistor T1 is turned on, the eighth transistor T8 is turned on, the signal of the first initial signal line Vinit1 is provided to the first node N1, the gate electrode (i.e. the first node N1) of the third transistor T3 is initialized, for example, the internal pre-stored voltage is emptied, and the initialization is completed. Among them, the second transistor T2 to the seventh transistor T7 and the tenth transistor T10 are turned off. In this stage, the light emitting device L does not emit light.

[0256] The second stage S2 is called a compensation stage, the signals of the reset signal line Reset, the first emitting signal line EM1 and the second emitting signal line EM2 are all high level signals, and the signal of the first scanning signal line Gate1 is a low level signal. In this stage, the first node N1 is a low level signal, so the third transistor T3 is turned on. The signal of the first scanning signal line Gate1 is a low level signal, the second transistor T2 is turned on, the fourth transistor T4 is turned on, the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the first capacitor C1, until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3. The signal of the reset signal line Reset is a high level signal, and the first transistor T1 is turned off. The first transistor T1, the fifth transistor T5 to the seventh transistor T7 and the tenth transistor T10 are turned off. In this stage, the light emitting device L does not emit light.

[0257] The third stage S3 is called a writing stage, the signals of the reset signal line Reset, the first scanning signal line Gate1 and the first emitting signal line EM1 are all high level signals, and the signal of the second emitting signal line EM2 is a low level signal. The signal of the second emitting signal line EM2 is a low level signal, the tenth transistor T10 is turned on, and the signal of the fifth node is written into the sixth node N6 through the tenth transistor T10; the seventh transistor T7 is turned on, and the signal of the second initial signal line Vinit2 is written into the fourth node N4 to initialize (reset) the first electrode of the light emitting device L, for example, to empty the pre-stored voltage in the first electrode, and the initialization is completed. The signal of the first scanning signal line Gate1 is a high level signal, and the second transistor T2 and the fourth transistor T4 are turned off. The first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0258] The fourth stage S4 is called an emitting stage, the signal of the first emitting signal line EM1 is a low level signal, and the signals of the reset signal line Reset, the third power supply line VGH, the first scanning signal line Gate1 and the second emitting signal line EM2 are all high level signals. The signal of the second emitting signal line EM2 is a high level signal, and the seventh transistor T7 and the tenth transistor T10 are turned off. The signal of the first emitting signal line EM1 is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output by the first power supply line ELVDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor M5, the turned-on third transistor M3 and the turned-on sixth transistor M6, and drives the light emitting device L to emit light.

[0259] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0260] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power voltage output by the first power supply line ELVDD.

[0261] FIG. 21A is a schematic diagram of an equivalent circuit of a pixel driving circuit, FIG. 21B is a schematic diagram of an equivalent circuit of a pixel driving circuit, FIG. 21C is a schematic diagram of an equivalent circuit of a pixel driving circuit, and FIG. 21D is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIGS. 21A-21D, the pixel driving circuit can further include a ninth transistor T9.

[0262] In an example embodiment, as shown in FIGS. 21A-21D, the control electrode of the ninth transistor T9 is electrically connected with the second light emitting signal line EM2, the first electrode of the ninth transistor T9 is electrically connected with the third initial signal line Vinit3, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2.

[0263] In an example embodiment, at least one of the first transistor T1 to the tenth transistor T10 is a P-type transistor.

[0264] An example structure of the pixel driving circuit is shown in FIGS. 21A-21D. It is easily understood by those skilled in the art that the implementation of the pixel driving circuit is not limited thereto.

[0265] The display device provided by the embodiments of the present disclosure includes the pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here.

[0266] The embodiments of the present disclosure further provide a driving method of a pixel driving circuit configured to drive the pixel driving circuit. The driving method of the pixel driving circuit can include:

[0267] The first control sub-circuit provides a signal of the first initial signal line to the first node under control of a signal of at least one of the reset signal line and the second scan signal line, and stores a voltage difference between signals of the first node and the first power supply line;

[0268] The second control sub-circuit provides a signal of the third node to the first node under control of signals of the first scan signal line and the control signal line;

[0269] The third control sub-circuit provides a signal of the data signal line to the second node and a signal of the second initial signal line to the fourth node under control of signals of the first scan signal line and the second emission signal line;

[0270] The driving sub-circuit provides a driving signal to the third node under control of signals of the first node and the second node;

[0271] The emission control sub-circuit provides a signal of the first power supply line to the second node and a signal of the fourth node to the third node under control of a signal of the first emission signal line.

[0272] The pixel driving circuit is similar to the pixel driving circuit provided by any one of the foregoing embodiments in principle and effect, and thus will not be described again.

[0273] The drawings in the disclosure only relate to structures involved in the embodiments of the disclosure, and other structures can be referred to general design.

[0274] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe the embodiments of the disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0275] Although the embodiments disclosed in the disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating understanding of the disclosure, and is not intended to limit the disclosure. Any person skilled in the art of the disclosure can make any modification and change in the form and details without departing from the spirit and scope of the disclosure disclosed, but the patent protection scope of the disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit, comprising: The circuit includes a driver sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light-emitting control sub-circuit. The first control sub-circuit is electrically connected to the first node, at least one of the reset signal line and the second scan signal line, the first power supply line, and the first initial signal line, respectively. It is configured to provide the signal of the first initial signal line to the first node under the control of the signal of at least one of the reset signal line and the second scan signal line, and to store the voltage difference between the signals of the first node and the first power supply line. The second control sub-circuit is electrically connected to the first node, the third node, the first scan signal line, and the control signal line, respectively, and is configured to provide the signal of the third node to the first node under the control of the signals of the first scan signal line and the control signal line; The third control sub-circuit is electrically connected to the second node, the first scan signal line, the data signal line, the fourth node, the second light emission signal line, and the second initial signal line, respectively. It is configured to provide the data signal line to the second node and the second initial signal line to the fourth node under the control of the signals of the first scan signal line and the second light emission signal line. The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The light-emitting control sub-circuit is electrically connected to the first power line, the first light-emitting signal line, the second node, the third node, and the fourth node, respectively. It is configured to provide the first power line signal to the second node and the fourth node signal to the third node under the control of the first light-emitting signal line signal.

2. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit is electrically connected to the first node, the reset signal line, the second scan signal line, the first power supply line, the first initial signal line, and the fifth node, respectively, and is configured to provide the signal of the first initial signal line to the fifth node and the signal of the fifth node to the first node under the control of the signals of the reset signal line and the second scan signal line.

3. The pixel driving circuit according to claim 2, wherein, The first control sub-circuit includes: a first transistor, an eighth transistor, a first capacitor, and a second capacitor; The control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the first initial signal line. The control electrode of the eighth transistor is electrically connected to the second scan signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fifth node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to a first power line, and the second plate of the first capacitor is electrically connected to a first node. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first initial signal line, and the second plate of the second capacitor is electrically connected to the fifth node.

4. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit is electrically connected to the first node, the reset signal line, the first power supply line, the first initial signal line, and the fifth node, respectively, and is configured to provide the signal of the first initial signal line to the fifth node and the signal of the fifth node to the first node under the control of the signal of the reset signal line.

5. The pixel driving circuit according to claim 4, wherein, The first control sub-circuit includes: a first transistor, an eighth transistor, and a first capacitor; The control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the first initial signal line. The control electrode of the eighth transistor is electrically connected to the reset signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fifth node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to a first power line, and the second plate of the first capacitor is electrically connected to a first node.

6. The pixel driving circuit according to claim 1, wherein, The control signal line includes a second light-emitting signal line. The second control sub-circuit is electrically connected to the first node, the third node, the first scan signal line, the second light-emitting control signal line, and the fifth node, respectively. It is configured to provide the first node with the signal of the third node or the fifth node under the control of the signals of the first scan signal line and the second light-emitting control signal line.

7. The pixel driving circuit according to claim 6, wherein, The second control sub-circuit includes: a tenth transistor and two second transistors; The control electrode of one of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the sixth node; the control electrode of the other of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the sixth node, and the second electrode is electrically connected to the third node; the control electrode of the tenth transistor is electrically connected to the second light emission signal line, the first electrode of the tenth transistor is electrically connected to the fifth node, and the second electrode of the tenth transistor is electrically connected to the sixth node. or, The second control sub-circuit includes: a tenth transistor and a second transistor, wherein the second transistor is a dual-gate transistor; The first and second control electrodes of the second transistor are electrically connected to the first scan signal line. The first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node. The connection point of the first and second control electrodes is electrically connected to the sixth node. The control electrode of the tenth transistor is electrically connected to the second light-emitting signal line. The first electrode of the tenth transistor is electrically connected to the fifth node, and the second electrode of the tenth transistor is electrically connected to the sixth node.

8. The pixel driving circuit according to claim 1, wherein, The control signal line includes a third power line. The second control sub-circuit is electrically connected to the first node, the third node, the first scan signal line, the first initial signal line, and the third power line, respectively, and is configured to provide the first node with the signal of the third node or the first initial signal line under the control of the signals of the first scan signal line and the third power line.

9. The pixel driving circuit according to claim 8, wherein, The second control sub-circuit includes: a tenth transistor and two second transistors; The control electrode of one of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the sixth node; the control electrode of the other of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the sixth node, and the second electrode is electrically connected to the third node; the control electrode of the tenth transistor is electrically connected to the third power supply line, the first electrode of the tenth transistor is electrically connected to the first initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node. or, The second control sub-circuit includes: a tenth transistor and a second transistor, wherein the second transistor is a dual-gate transistor; The first and second control electrodes of the second transistor are electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, the second electrode is electrically connected to the third node, and the connection point of the first and second control electrodes is electrically connected to the sixth node; the control electrode of the tenth transistor is electrically connected to the third power line, the first electrode of the tenth transistor is electrically connected to the first initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node.

10. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit further includes: a fourth control sub-circuit; The fourth control sub-circuit is electrically connected to the second node, the second light-emitting signal line, and the third initial signal line, respectively, and is configured to provide the signal of the third initial signal line to the second node under the control of the signal of the second light-emitting signal line.

11. The pixel driving circuit according to claim 10, wherein, The fourth control sub-circuit includes: a ninth transistor; The control electrode of the ninth transistor is electrically connected to the second light-emitting signal line, the first electrode of the ninth transistor is electrically connected to the third initial signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

12. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a first transistor, an eighth transistor, a first capacitor, and a second capacitor; the second control sub-circuit includes: a tenth transistor and one or two second transistors; the driving sub-circuit includes: a third transistor; the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; and the third control sub-circuit includes: a fourth transistor and a seventh transistor. The control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the first initial signal line. There are two second transistors. The control electrode of one of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the sixth node. The control electrode of the other two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the sixth node, and the second electrode is electrically connected to the third node. Alternatively, there is one second transistor, which is a dual-gate transistor. The first and second control electrodes of the second transistor are electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node. The connection point of the first and second control electrodes is electrically connected to the sixth node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the data signal line. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line of the second capacitor, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second initial signal line. The control electrode of the eighth transistor is electrically connected to the second scan signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fifth node. The control electrode of the tenth transistor is electrically connected to the second light-emitting signal line, the first electrode of the tenth transistor is electrically connected to the fifth node, and the second electrode of the tenth transistor is electrically connected to the sixth node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to a first power line, and the second plate of the first capacitor is electrically connected to a first node. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first initial signal line, and the second plate of the second capacitor is electrically connected to the fifth node.

13. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a first transistor, an eighth transistor, a first capacitor, and a second capacitor; the second control sub-circuit includes: a tenth transistor and one or two second transistors; the driving sub-circuit includes: a third transistor; the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; and the third control sub-circuit includes: a fourth transistor and a seventh transistor. The control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the first initial signal line. There are two second transistors. The control electrode of one of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the sixth node. The control electrode of the other two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the sixth node, and the second electrode is electrically connected to the third node. Alternatively, there is one second transistor, which is a dual-gate transistor. The first and second control electrodes of the second transistor are electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node. The connection point of the first and second control electrodes is electrically connected to the sixth node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the data signal line. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line of the second capacitor, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second initial signal line. The control electrode of the eighth transistor is electrically connected to the second scan signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fifth node. The control electrode of the tenth transistor is electrically connected to the third power supply line, the first electrode of the tenth transistor is electrically connected to the first initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to a first power line, and the second plate of the first capacitor is electrically connected to a first node. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first initial signal line, and the second plate of the second capacitor is electrically connected to the fifth node.

14. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a first transistor, an eighth transistor, and a first capacitor; the second control sub-circuit includes: a tenth transistor and one or two second transistors; the driving sub-circuit includes: a third transistor; the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; and the third control sub-circuit includes: a fourth transistor and a seventh transistor. The control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the first initial signal line. There are two second transistors. The control electrode of one of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the sixth node. The control electrode of the other two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the sixth node, and the second electrode is electrically connected to the third node. Alternatively, there is one second transistor, which is a dual-gate transistor. The first and second control electrodes of the second transistor are electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node. The connection point of the first and second control electrodes is electrically connected to the sixth node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the data signal line. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line of the second capacitor, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second initial signal line. The control electrode of the eighth transistor is electrically connected to the reset signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fifth node. The control electrode of the tenth transistor is electrically connected to the second light-emitting signal line, the first electrode of the tenth transistor is electrically connected to the fifth node, and the second electrode of the tenth transistor is electrically connected to the sixth node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to a first power line, and the second plate of the first capacitor is electrically connected to a first node.

15. The pixel driving circuit according to claim 1, wherein, The first control sub-circuit includes: a first transistor, an eighth transistor, and a first capacitor; the second control sub-circuit includes: a tenth transistor and one or two second transistors; the driving sub-circuit includes: a third transistor; the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; and the third control sub-circuit includes: a fourth transistor and a seventh transistor. The control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the first initial signal line. There are two second transistors. The control electrode of one of the two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the sixth node. The control electrode of the other two second transistors is electrically connected to the first scan signal line, the first electrode is electrically connected to the sixth node, and the second electrode is electrically connected to the third node. Alternatively, there is one second transistor, which is a dual-gate transistor. The first and second control electrodes of the second transistor are electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node. The connection point of the first and second control electrodes is electrically connected to the sixth node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the data signal line. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line of the second capacitor, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the first light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second initial signal line. The control electrode of the eighth transistor is electrically connected to the reset signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fifth node. The control electrode of the tenth transistor is electrically connected to the third power supply line, the first electrode of the tenth transistor is electrically connected to the first initial signal line, and the second electrode of the tenth transistor is electrically connected to the sixth node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to a first power line, and the second plate of the first capacitor is electrically connected to a first node.

16. The pixel driving circuit according to any one of claims 12 to 15, wherein, The pixel driving circuit further includes: a ninth transistor; The control electrode of the ninth transistor is electrically connected to the second light-emitting signal line, the first electrode of the ninth transistor is electrically connected to the third initial signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

17. A display device, comprising: The pixel driving circuit as described in any one of claims 1 to 16.

18. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 16, the method comprising: Under the control of at least one of the reset signal line and the second scan signal line, the first control sub-circuit provides the signal of the first initial signal line to the first node and stores the voltage difference between the signals of the first node and the first power line. The second control sub-circuit provides the third node signal to the first node under the control of the first scan signal line and the control signal line; The third control sub-circuit, under the control of the signals of the first scanning signal line and the second light emission signal line, provides the data signal line signal to the second node and the second initial signal line signal to the fourth node; The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes; Under the control of the first light-emitting signal line, the light-emitting control sub-circuit provides the first power line signal to the second node and the fourth node signal to the third node.

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