Pixel driving circuit and driving method therefor, and display device

Abstract

A pixel driving circuit and a driving method therefor, and a display device. The pixel driving circuit comprises: a driving sub-circuit which provides a driving current to a fourth node (N4) under the control of signals of a first node (N1) and a third node (N3); a first control sub-circuit which, under the control of signals of a reset signal line (RE) and a first scan signal line (Gate1), provides a signal of a reference signal line (Ref) or the fourth node (N4) to the first node (N1), and provides the signal of the first node (N1) to the second node (N2); a second control sub-circuit which provides a signal of a data signal line (Data) or a first power supply line (VSS) to the second node (N2) under the control of signals of a second scan signal line (Gate2) and at least one control signal line (CK); a third control sub-circuit which provides the signal of the reference signal line (Ref) to a fifth node (N5) under the control of the signal of the reset signal line (RE); and a light-emitting control sub-circuit which, under the control of signals of a first light-emitting signal line (EM1) and a second light-emitting signal line (EM2), provides the signal of the first power supply line (VSS) to the third node (N3), and provides the signal of the fourth node (N4) to the fifth node (N5), wherein the signal of the first power supply line (VSS) is a negative voltage signal.

Description

Pixel driving circuit, driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410833839.7, filed on June 25, 2024, and entitled “Pixel driving circuit, driving method thereof and display device”, the content of which is to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but not limited to, display technology, in particular to a pixel driving circuit, a driving method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a pixel driving circuit, comprising: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a light-emitting control sub-circuit.

[0006] The driving sub-circuit is electrically connected with a first node, a third node and a fourth node respectively, and is configured to provide a driving current to the fourth node under the control of signals of the first node and the third node.

[0007] The first control sub-circuit is electrically connected with a reset signal line, a reference signal line, a first scan signal line, the first node, a second node and the fourth node respectively, and is configured to provide a signal of the reference signal line or the fourth node to the first node, and provide a signal of the first node to the second node under the control of signals of the reset signal line and the first scan signal line.

[0008] The second control sub-circuit is electrically connected with the second scan signal line, the second node, at least one control signal line, the data signal line and the first power supply line respectively, and is configured to provide the signal of the data signal line or the first power supply line to the second node under the control of the signals of the second scan signal line and the at least one control signal line.

[0009] The third control sub-circuit is electrically connected with the reset signal line, the reference signal line and the fifth node respectively, and is configured to provide the signal of the reference signal line to the fifth node under the control of the signal of the reset signal line.

[0010] The light emitting control sub-circuit is electrically connected with the first power supply line, the first light emitting signal line, the second light emitting signal line, the third node, the fourth node and the fifth node respectively, and is configured to provide the signal of the first power supply line to the third node and provide the signal of the fourth node to the fifth node under the control of the signals of the first light emitting signal line and the second light emitting signal line.

[0011] The signal of the first power supply line is a negative voltage signal.

[0012] In some possible implementation manners, the fifth node is electrically connected with the second electrode of the light emitting device, the first electrode of the light emitting device is electrically connected with the second power supply line, and the signal of the second power supply line is a positive voltage signal.

[0013] In some possible implementation manners, the at least one control signal line includes a third scan signal line.

[0014] The second control sub-circuit is electrically connected with the second scan signal line, the second node, the third scan signal line, the data signal line and the first power supply line respectively, and is configured to provide the signal of the data signal line or the first power supply line to the second node under the control of the signals of the second scan signal line and the third scan signal line.

[0015] In some possible implementation manners, the first scan signal line and the third scan signal line are the same signal line.

[0016] In some possible implementation manners, the second control sub-circuit includes a fourth transistor, an eighth transistor and a first capacitor.

[0017] The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node.

[0018] The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the second node, and the second electrode of the eighth transistor is electrically connected with the first power supply line.

[0019] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power line.

[0020] In some possible implementation manners, the at least one control signal line comprises a first scan signal line;

[0021] The second control sub-circuit is electrically connected with the second scan signal line, the second node, the third node, the first scan signal line, the data signal line and the first power line respectively, and is configured to provide a signal of the data signal line or the first power line or the third node to the second node under control of signals of the second scan signal line and the first scan signal line.

[0022] In some possible implementation manners, the second control sub-circuit comprises a fourth transistor, an eighth transistor and a first capacitor.

[0023] The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node.

[0024] The control electrode of the eighth transistor is electrically connected with the first scan signal line, the first electrode of the eighth transistor is electrically connected with the second node, and the second electrode of the eighth transistor is electrically connected with the third node.

[0025] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power line.

[0026] In some possible implementation manners, the first control sub-circuit comprises a second transistor, a third transistor and a second capacitor.

[0027] The control electrode of the second transistor is electrically connected with the reset signal line, the first electrode of the second transistor is electrically connected with the reference signal line, and the second electrode of the second transistor is electrically connected with the first node.

[0028] The control electrode of the third transistor is electrically connected with the first scan signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the fourth node.

[0029] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the second node.

[0030] In some possible implementation manners, the third control sub-circuit comprises a seventh transistor.

[0031] The control electrode of the seventh transistor is electrically connected with a reset signal line, the first electrode of the seventh transistor is electrically connected with the fifth node, and the second electrode of the seventh transistor is electrically connected with a reference signal line.

[0032] In some possible implementation manners, the driving sub-circuit comprises a first transistor.

[0033] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the third node.

[0034] In some possible implementation manners, the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor.

[0035] The control electrode of the fifth transistor is electrically connected with a first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the fifth node, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0036] The control electrode of the sixth transistor is electrically connected with a second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with a first power supply line.

[0037] In some possible implementation manners, the driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor and a second capacitor, the second control sub-circuit comprises a fourth transistor, an eighth transistor and a first capacitor, the third control sub-circuit comprises a seventh transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor.

[0038] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the third node.

[0039] The control electrode of the second transistor is electrically connected with a reset signal line, the first electrode of the second transistor is electrically connected with a reference signal line, and the second electrode of the second transistor is electrically connected with the first node.

[0040] The control electrode of the third transistor is electrically connected with a first scan signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the fourth node.

[0041] The control electrode of the fourth transistor is electrically connected with a second scan signal line, the first electrode of the fourth transistor is electrically connected with a data signal line, and the second electrode of the fourth transistor is electrically connected with the second node.

[0042] The control electrode of the fifth transistor is electrically connected with a first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the fifth node, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0043] The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the first power supply line;

[0044] The control electrode of the seventh transistor is electrically connected with the reset signal line, the first electrode of the seventh transistor is electrically connected with the fifth node, and the second electrode of the seventh transistor is electrically connected with the reference signal line;

[0045] The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the second node, and the second electrode of the eighth transistor is electrically connected with the first power supply line;

[0046] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power supply line;

[0047] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the second node.

[0048] In some possible implementation manners, the driving sub-circuit includes a first transistor, the first control sub-circuit includes a second transistor, a third transistor and a second capacitor, the second control sub-circuit includes a fourth transistor, an eighth transistor and a first capacitor, the third control sub-circuit includes a seventh transistor, and the light-emitting control sub-circuit includes a fifth transistor and a sixth transistor;

[0049] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the third node;

[0050] The control electrode of the second transistor is electrically connected with the reset signal line, the first electrode of the second transistor is electrically connected with the reference signal line, and the second electrode of the second transistor is electrically connected with the first node;

[0051] The control electrode of the third transistor is electrically connected with the first scan signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the fourth node;

[0052] The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node;

[0053] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the fifth node, and the second electrode of the fifth transistor is electrically connected with the fourth node;

[0054] A control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the first power supply line;

[0055] A control electrode of the seventh transistor is electrically connected with the reset signal line, a first electrode of the seventh transistor is electrically connected with the fifth node, and a second electrode of the seventh transistor is electrically connected with the reference signal line;

[0056] A control electrode of the eighth transistor is electrically connected with the first scan signal line, a first electrode of the eighth transistor is electrically connected with the second node, and a second electrode of the eighth transistor is electrically connected with the third node;

[0057] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power supply line;

[0058] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the second node.

[0059] In some possible implementation manners, the type of at least one of the first transistor to the eighth transistor is an N-type transistor.

[0060] In some possible implementation manners, the difference between the voltage value of the second power supply line and the voltage value of the reference signal line is less than the set light-emitting starting threshold value.

[0061] In some possible implementation manners, the set light-emitting starting threshold value is in a range of [1V, 2V].

[0062] In a second aspect, the embodiments of the present disclosure provide a display device, including the pixel driving circuit according to any one of the embodiments of the first aspect.

[0063] In a third aspect, the embodiments of the present disclosure provide a driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of the embodiments of the first aspect, and the method includes:

[0064] The driving sub-circuit determines a driving current flowing between the third node and the fourth node under the control of the signal of the first node;

[0065] The first control sub-circuit provides the signal of the reference signal line or the fourth node to the first node and provides the signal of the first node to the second node under the control of the signals of the reset signal line and the first scan signal line;

[0066] The second control sub-circuit provides the signal of the data signal line or the first power supply line to the second node under the control of the signals of the second scan signal line and at least one control signal line;

[0067] The third control sub-circuit provides a signal of a fifth node with a signal of a reference signal line under control of a signal of a reset signal line;

[0068] The light emitting control sub-circuit provides a signal of the third node with a signal of a first power supply line and provides a signal of the fifth node with a signal of the fourth node under control of signals of a first light emitting signal line and a second light emitting signal line;

[0069] The signal of the first power supply line is a negative voltage signal.

[0070] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings.

[0071] SUMMARY

[0072] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and should not be considered limiting of the present disclosure's scope.

[0073] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an example embodiment of the present disclosure;

[0074] FIG. 2 is an equivalent circuit diagram of a driving sub-circuit according to an example embodiment;

[0075] FIG. 3 is an equivalent circuit diagram of a first control sub-circuit according to an example embodiment;

[0076] FIG. 4A is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment;

[0077] FIG. 4B is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment;

[0078] FIG. 5 is an equivalent circuit diagram of a third control sub-circuit according to an example embodiment;

[0079] FIG. 6 is an equivalent circuit diagram of a light emitting control sub-circuit according to an example embodiment;

[0080] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0081] FIG. 8 is a working timing diagram of the pixel driving circuit according to FIG. 7;

[0082] FIG. 9A is an equivalent circuit diagram of a working process one of the pixel driving circuit;

[0083] FIG. 9B is an equivalent circuit diagram of a working process two of the pixel driving circuit;

[0084] FIG. 9C is an equivalent circuit diagram of a working process three of the pixel driving circuit;

[0085] FIG. 9D is an equivalent circuit diagram of the pixel driving circuit in a fourth operation process;

[0086] FIG. 10 is an equivalent circuit diagram of the pixel driving circuit according to an example embodiment;

[0087] FIG. 11 is a timing chart of the pixel driving circuit according to FIG. 10;

[0088] FIG. 12A is an equivalent circuit diagram of the pixel driving circuit in a first operation process;

[0089] FIG. 12B is an equivalent circuit diagram of the pixel driving circuit in a second operation process;

[0090] FIG. 12C is an equivalent circuit diagram of the pixel driving circuit in a third operation process;

[0091] FIG. 12D is an equivalent circuit diagram of the pixel driving circuit in a fourth operation process.

[0092] DETAILED DESCRIPTION

[0093] In order to make the objects, technical solutions, and advantages of the present disclosure clearer, below will be a detailed description of the embodiments of the present disclosure in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. One of ordinary skill in the art can easily understand that the manner and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0094] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams of the structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0095] The ordinal numbers "first", "second", "third", and the like in the present specification are set to avoid confusion of the components, and are not intended to be limiting in terms of number.

[0096] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0097] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0098] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0099] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0100] In this specification, "electrically connected" includes the case where the components are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0101] In the present specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus, a state in which the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus, a state in which the angle is 85° or more and 95° or less is also included.

[0102] In the present specification, "film" and "layer" can be exchanged with each other. For example, "conductive layer" can be sometimes exchanged with "conductive film". Similarly, "insulating film" can be sometimes exchanged with "insulating layer".

[0103] In the present specification, "same layer" refers to structures of two (or more) kinds that are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of precursors for forming the structures of the same layer are the same, and the materials finally formed can be the same or different.

[0104] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly, and can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformations due to tolerances, and there can be rounded corners, arc edges, and deformations, etc.

[0105] In the present disclosure, "about" refers to not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0106] The display panel of the OLED or QLED includes a substrate and a plurality of sub-pixels disposed on the substrate, at least one sub-pixel includes a pixel driving circuit, and the node potential of the driving sub-circuit in the pixel driving circuit affects the reliability and uniformity of the display.

[0107] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an example embodiment of the present disclosure, as shown in FIG. 1, the pixel driving circuit can include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light-emitting control sub-circuit.

[0108] The driving sub-circuit is electrically connected with the first node N1, the third node N3, and the fourth node N4, respectively, and is configured to provide a driving current to the fourth node N4 under the control of signals of the first node N1 and the third node N3.

[0109] The first control sub-circuit is electrically connected with the reset signal line RE, the reference signal line Ref, the first scan signal line Gate1, the first node N1, the second node N2 and the fourth node N4 respectively, and is configured to provide the signal of the reference signal line Ref or the fourth node N4 to the first node N1 and provide the signal of the first node N1 to the second node N2 under the control of the signals of the reset signal line RE and the first scan signal line Gate1.

[0110] The second control sub-circuit is electrically connected with the second scan signal line Gate2, the second node N2, at least one control signal line CK, the data signal line Data and the first power supply line VSS respectively, and is configured to provide the signal of the data signal line Data or the first power supply line VSS to the second node N2 under the control of the signals of the second scan signal line Gate2 and the at least one control signal line CK.

[0111] The third control sub-circuit is electrically connected with the reset signal line RE, the reference signal line Ref and the fifth node N5 respectively, and is configured to provide the signal of the reference signal line Ref to the fifth node N5 under the control of the signal of the reset signal line RE.

[0112] The light-emitting control sub-circuit is electrically connected with the first power supply line VSS, the first light-emitting signal line EM1, the second light-emitting signal line EM2, the third node N3, the fourth node N4 and the fifth node N5 respectively, and is configured to provide the signal of the first power supply line VSS to the third node N3 and provide the signal of the fourth node N4 to the fifth node N5 under the control of the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2.

[0113] The signal of the first power supply line VSS is a negative voltage signal.

[0114] In the embodiments of the present disclosure, the driving sub-circuit provides a driving current to the fourth node N4 under the control of the signals of the first node N1 and the third node N3, the light-emitting control sub-circuit provides the signal of the first power supply line VSS to the third node N3 under the control of the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2, and the signal of the first power supply line VSS is a negative voltage signal. The node (the third node N3) of the driving sub-circuit is connected with the first power supply line VSS of the negative voltage signal through the light-emitting control sub-circuit, so that the node potential of the driving sub-circuit depends on the negative voltage signal of the first power supply line, and the problem that the anode potential of the light-emitting device is inconsistent due to the influence of factors such as non-uniform characteristics of the light-emitting device on the display panel, device aging or temperature change (such as temperature rise) when the node potential of the driving sub-circuit depends on the anode potential of the light-emitting device, which affects the uniformity of display, can be avoided.

[0115] In an example embodiment, the fifth node N5 is electrically connected with the second electrode (cathode) of the light emitting device L, and the first electrode (anode) of the light emitting device L is connected with the second power line VDD, and the signal of the second power line VDD is a positive voltage signal.

[0116] In an example embodiment, the light emitting device L can be an organic electroluminescence diode (OLED) or a quantum dot light emitting diode (QLED). The OLED can include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0117] In the embodiment of the present disclosure, the light emitting control sub-circuit provides the signal of the fourth node to the fifth node under the control of the signals of the first light emitting signal line and the second light emitting signal line, the fifth node is electrically connected with the second electrode of the light emitting device, and the first electrode of the light emitting device is electrically connected with the second power line of the positive voltage signal. By inverting the connection mode of the light emitting device, the power voltage output by the first power line VSS of the negative voltage signal is provided to the second electrode (cathode) of the light emitting device L through the driving sub-circuit and the light emitting control sub-circuit, and the light emitting device L is driven to emit light, which can avoid the influence of the potential of the first electrode (anode) of the light emitting device L on the node voltage of the driving transistor, and ensure the reliability and uniformity of the display.

[0118] FIG. 2 is an equivalent circuit diagram of the driving sub-circuit provided by an example embodiment. As shown in FIG. 2, in an example embodiment, the driving sub-circuit can include a first transistor T1.

[0119] In an example embodiment, as shown in FIG. 2, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth node N4, and the second electrode of the first transistor T1 is electrically connected with the third node N3.

[0120] In an example embodiment, the first transistor T1 can be referred to as a driving transistor, and the driving current flowing between the third node N3 and the fourth node N4 is determined according to the potential difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the first transistor T1.

[0121] The second electrode (also the third node N3) of the first transistor T1 is electrically connected with the first power line VSS of the negative voltage signal through the light emitting control sub-circuit, which can avoid the influence of the potential of the first electrode (anode) of the light emitting device L on the potential difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the first transistor T1, and ensure the reliability and uniformity of the display.

[0122] An example structure of the driving sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the driving sub-circuit is not limited thereto.

[0123] In an example embodiment, a difference between the voltage value VD of the second power supply line VDD and the voltage value Vref of the reference signal line Ref is less than a set light-emitting start threshold value.

[0124] In an example embodiment, the set light-emitting start threshold value can be in a range of [1V, 2V]. For example, VD-Vref < 2V, or VD-Vref < 1V.

[0125] In the embodiment of the present disclosure, the difference between the voltage value VD of the second power supply line VDD and the voltage value Vref of the reference signal line Ref is less than the set light-emitting start threshold value, which can ensure that the light-emitting device L does not emit light at an unexpected time when the pixel driving circuit is working, for example, can ensure that the light-emitting device L does not emit light in the sampling stage or the compensation stage of the threshold voltage Vth of the first transistor T1 when the pixel driving circuit is working.

[0126] FIG. 3 is an equivalent circuit diagram of the first control sub-circuit provided by an example embodiment. As shown in FIG. 3, in an example embodiment, the first control sub-circuit includes: a second transistor T2, a third transistor T3, and a second capacitor C2.

[0127] In an example embodiment, as shown in FIG. 3, the control electrode of the second transistor T2 is electrically connected with the reset signal line RE, the first electrode of the second transistor T2 is electrically connected with the reference signal line Ref, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first scan signal line Gate1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the second node N2.

[0128] An example structure of the first control sub-circuit is shown in FIG. 3. It is easy for those skilled in the art to understand that the implementation of the first control sub-circuit is not limited thereto.

[0129] In an example embodiment, the at least one control signal line CK can include: a third scan signal line Gate3; and a second control sub-circuit, which is electrically connected with the second scan signal line Gate2, the second node N2, the third scan signal line Gate3, the data signal line Data, and the first power supply line VSS respectively, and is configured to provide the signal of the data signal line Data or the first power supply line VSS to the second node N2 under the control of the signals of the second scan signal line Gate2 and the third scan signal line Gate3.

[0130] In an example embodiment, the first scan signal line Gate1 and the third scan signal line Gate3 can be the same signal line.

[0131] FIG. 4A is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment. As shown in FIG. 4A, in an example embodiment, the second control sub-circuit includes a fourth transistor T4, an eighth transistor T8, and a first capacitor C1.

[0132] In an example embodiment, as shown in FIG. 4A, a control electrode of the fourth transistor T4 is electrically connected with the second scan signal line Gate2, a first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and a second electrode of the fourth transistor T4 is electrically connected with the second node N2; a control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, a first electrode of the eighth transistor T8 is electrically connected with the second node N2, and a second electrode of the eighth transistor T8 is electrically connected with the first power supply line VSS; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first power supply line VSS.

[0133] An example structure of the second control sub-circuit is shown in FIG. 4A. It is easily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited thereto.

[0134] In an example embodiment, the at least one control signal line CK can include: a first scan signal line Gate1; a second control sub-circuit electrically connected with a second scan signal line Gate2, a second node N2, a third node N3, the first scan signal line Gate1, a data signal line Data, and a first power supply line VSS, respectively, and configured to provide a signal of the data signal line Data or the first power supply line VSS or the third node N3 to the second node N2 under control of signals of the second scan signal line Gate2 and the first scan signal line Gate1.

[0135] FIG. 4B is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment. As shown in FIG. 4B, in an example embodiment, the second control sub-circuit includes a fourth transistor T4, an eighth transistor T8, and a first capacitor C1.

[0136] In an example embodiment, as shown in FIG. 4B, the control electrode of the fourth transistor T4 is electrically connected with the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the eighth transistor T8 is electrically connected with the first scan signal line Gate1, the first electrode of the eighth transistor T8 is electrically connected with the second node N2, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first power supply line VSS.

[0137] An example structure of the second control sub-circuit is shown in FIG. 4B. It is easily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0138] FIG. 5 is an equivalent circuit diagram of a third control sub-circuit according to an example embodiment. As shown in FIG. 5, in an example embodiment, the third control sub-circuit includes a seventh transistor T7.

[0139] In an example embodiment, as shown in FIG. 5, the control electrode of the seventh transistor T7 is electrically connected with the reset signal line RE, the first electrode of the seventh transistor T7 is electrically connected with the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected with the reference signal line Ref.

[0140] An example structure of the third control sub-circuit is shown in FIG. 5. It is easily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0141] FIG. 6 is an equivalent circuit diagram of a light emitting control sub-circuit according to an example embodiment. As shown in FIG. 6, in an example embodiment, the light emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6.

[0142] In an example embodiment, as shown in FIG. 6, the control electrode of the fifth transistor T5 is electrically connected with the first light emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the second light emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply line VSS.

[0143] In an example embodiment, the fifth transistor T5 can be referred to as a first light emitting transistor, and the sixth transistor T6 can be referred to as a second light emitting transistor. When the first light emitting signal line EM1 and the second light emitting signal line EM2 input a valid level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output by the first power supply line VSS is provided to the second electrode of the light emitting device L through the turned-on sixth transistor T6, the turned-on first transistor T1, and the turned-on fifth transistor T5, to drive the light emitting device L to emit light.

[0144] An example structure of the light emitting control sub-circuit is shown in FIG. 6. It is easy for those skilled in the art to understand that the implementation of the light emitting control sub-circuit is not limited to this.

[0145] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment. As shown in FIG. 7, in an example embodiment, the pixel driving circuit can include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light emitting control sub-circuit, the driving sub-circuit includes a first transistor T1, the first control sub-circuit includes a second transistor T2, a third transistor T3, and a second capacitor C2, the second control sub-circuit includes a fourth transistor T4, an eighth transistor T8, and a first capacitor C1, the third control sub-circuit includes a seventh transistor T7, and the light emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6.

[0146] In an example embodiment, as shown in FIG. 7, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth node N4, and the second electrode of the first transistor T1 is electrically connected with the third node N3; the control electrode of the second transistor T2 is electrically connected with the reset signal line RE, the first electrode of the second transistor T2 is electrically connected with the reference signal line Ref, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first scan signal line Gate1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, the second electrode of the fourth transistor T4 is electrically connected with the second node N2, the control electrode of the fifth transistor T5 is electrically connected with the first emission signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the second emission signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply line VSS; the control electrode of the seventh transistor T7 is electrically connected with the reset signal line RE, the first electrode of the seventh transistor T7 is electrically connected with the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected with the reference signal line Ref; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the second node N2, and the second electrode of the eighth transistor T8 is electrically connected with the first power supply line VSS; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first power supply line VSS; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the second node N2.

[0147] In an example embodiment, the first scan signal line and the third scan signal line can be the same signal line. The control electrode of the third transistor T3 and the control electrode of the eighth transistor T8 can multiplex the same signal line.

[0148] In an example embodiment, as shown in FIG. 7, the type of at least one of the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0149] An example structure of the pixel driving circuit is shown in FIG. 7. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited thereto.

[0150] FIG. 8 is a timing diagram of the pixel driving circuit of FIG. 7, FIG. 9A is an equivalent circuit diagram of a first working process of the pixel driving circuit, FIG. 9B is an equivalent circuit diagram of a second working process of the pixel driving circuit, FIG. 9C is an equivalent circuit diagram of a third working process of the pixel driving circuit, and FIG. 9D is an equivalent circuit diagram of a fourth working process of the pixel driving circuit. The working processes of the pixel driving circuit of FIG. 7 are described below to illustrate the exemplary embodiments of the present disclosure, and the working processes of the pixel driving circuit can include:

[0151] The first stage P1 is referred to as an initialization stage (also referred to as a reset stage). The signal of the reset signal line RE is a high-level signal, and the signals of the first emission signal line EM1, the second emission signal line EM2, the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3 are all low-level signals. The signal of the reset signal line RE is a high-level signal, the second transistor T2 is turned on, and the signal of the reference signal line Ref is provided to the first node N1 to initialize the gate electrode (i.e., the first node N2) of the first transistor T1, for example, to clear the pre-stored voltage in the gate electrode, and to complete the initialization. The seventh transistor T7 is turned on, and the signal of the reference signal line Ref is provided to the fifth node N5. The third transistor T3 to the sixth transistor T6 and the eighth transistor T8 are turned off.

[0152] The fifth node N5 is electrically connected to the second electrode (cathode) of the light emitting device L. When the seventh transistor T7 is turned on, the fifth node N5 provides the initial voltage of the reference signal line Ref to the second electrode of the light emitting device L to initialize (reset) the second electrode of the light emitting device L, for example, to clear the pre-stored voltage in the second electrode, to complete the initialization, and to ensure that the light emitting device L does not emit light. In this stage, the light emitting device L does not emit light.

[0153] The second stage P2 is a compensation stage (also referred to as a first transistor T1 threshold voltage Vth sampling stage). The signals of the first scan signal line Gate1, the third scan signal line Gate3, and the second emitting signal line EM2 are all high level signals, and the signals of the reset signal line RE, the second scan signal line Gate2, and the first emitting signal line EM1 are all low level signals. The signal of the reset signal line RE is a low level signal, and the second transistor T2 and the seventh transistor T7 are turned off. The signal of the first scan signal line Gate1 is a high level signal, and the third transistor T3 is turned on. The signal of the second emitting signal line EM2 is a high level signal, and the sixth transistor T6 is turned on. The signal of the first node N1 flows through the turned-on third transistor T3, the turned-on first transistor T1, and the turned-on sixth transistor T6 to the first power supply line VSS. At this time, the voltage of the first node N1 is the sum of the power supply voltage Vs of the first power supply line VSS and the threshold voltage Vth of the first transistor T1, and the power supply voltage Vs of the first power supply line VSS is charged to the second capacitor C2. The signal of the third scan signal line Gate3 is a high level signal, and the eighth transistor T8 is turned on. The second node N2 writes the power supply voltage of the first power supply line VSS, that is, the voltage of the second node N2 is the power supply voltage Vs of the first power supply line VSS. The fourth transistor T4 and the fifth transistor T5 are disconnected. In this stage, the light emitting device L does not emit light.

[0154] In the P2 stage, the difference Vref between the voltage value VD of the second power supply line VDD and the voltage value of the reference signal line Ref is less than the set light emitting start threshold value. The value range of the set light emitting start threshold value can be [1V, 2V], which can ensure that the light emitting device L does not emit light when the pixel driving circuit works in the first transistor T1 threshold voltage Vth sampling stage or the compensation stage.

[0155] The third stage P3 is called a writing stage, the signal of the second scan signal line Gate2 is a high level signal, the signals of the reset signal line RE, the first scan signal line Gate1, the third scan signal line Gate3, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all low level signals. The signal of the first scan signal line Gate1 is a low level signal, and the third transistor T3 is turned off; the signal of the third scan signal line Gate3 is a low level signal, and the eighth transistor T8 is turned off; the signal of the second light-emitting signal line EM2 is a low level signal, and the sixth transistor T6 is turned off. The signal of the second scan signal line Gate2 is a high level signal, and the fourth transistor T4 is turned on, and the signal of the data signal line Data is written to the second node N2. At this time, the voltage value V2 of the signal of the second node N2 is the voltage value Vdata of the data signal line Data. Under the action of the second capacitor C2, the voltage value of the signal of the first node N1 in this stage jumps compared with the voltage value in the last stage. At this time, the voltage of the first node N1 jumps to Vdata+Vth. The second transistor T2, the fifth transistor T5 and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0156] In the P3 stage, the voltage value V2 of the signal of the second node N2 is the voltage value Vdata of the data signal line Data, and the voltage of the data signal line Data cannot be divided by the first capacitor C1 and the second capacitor C2, so that the cross voltage of the signal of the data signal line Data can be reduced.

[0157] The fourth stage P4 is called a light-emitting stage, the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are all high level signals, the signals of the reset signal line RE, the first scan signal line Gate1 to the third scan signal line Gate3 are all low level signals. The signal of the second scan signal line Gate2 is a low level signal, and the fourth transistor T4 is turned off. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high level signals respectively, the fifth transistor T5 and the sixth transistor T6 are turned on respectively, and the power supply voltage output by the first power supply line VSS provides a driving voltage to the second electrode of the light-emitting device L through the turned-on sixth transistor T6, the turned-on first transistor T1 and the turned-on fifth transistor T5, so as to drive the light-emitting device L to emit light.

[0158] In the driving process of the pixel circuit, the driving current flowing through the first transistor T1 (the driving transistor) is determined by the voltage difference Vgs between the gate electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the first node N1 is Vdata+Vth, and the voltage value of the third node N3 is the power supply voltage Vs of the first power supply line VSS, the driving current of the first transistor T1 is: I=K*(V gs -Vth) 2= K * (Vdata + Vth - Vs - Vth) 2＝ K * (Vdata - Vs) 2

[0159] wherein I is a driving current flowing through the first transistor T1, i.e., a driving current for driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the gate electrode and the second electrode of the first transistor T1.

[0160] FIG. 10 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment. As shown in FIG. 10, in an exemplary embodiment, the pixel driving circuit can include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light emitting control sub-circuit, the driving sub-circuit including a first transistor T1, the first control sub-circuit including a second transistor T2, a third transistor T3, and a second capacitor C2, the second control sub-circuit including a fourth transistor T4, an eighth transistor T8, and a first capacitor C1, the third control sub-circuit including a seventh transistor T7, and the light emitting control sub-circuit including a fifth transistor T5 and a sixth transistor T6.

[0161] In an example embodiment, as shown in FIG. 10, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth node N4, and the second electrode of the first transistor T1 is electrically connected with the third node N3; the control electrode of the second transistor T2 is electrically connected with the reset signal line RE, the first electrode of the second transistor T2 is electrically connected with the reference signal line Ref, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first scan signal line Gate1, the first electrode of the third transistor T3 is electrically connected with the first node N1, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the first emission signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the second emission signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply line VSS; the control electrode of the seventh transistor T7 is electrically connected with the reset signal line RE, the first electrode of the seventh transistor T7 is electrically connected with the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected with the reference signal line Ref; the control electrode of the eighth transistor T8 is electrically connected with the first scan signal line Gate1, the first electrode of the eighth transistor T8 is electrically connected with the second node N2, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the first power supply line VSS; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the second node N2.

[0162] In an example embodiment, as shown in FIG. 7, the type of at least one of the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0163] An example structure of the pixel driving circuit is shown in FIG. 10. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0164] Fig. 11 is a timing diagram of the pixel driving circuit provided in Fig. 10, Fig. 12A is an equivalent circuit diagram of a first working process of the pixel driving circuit, Fig. 12B is an equivalent circuit diagram of a second working process of the pixel driving circuit, Fig. 12C is an equivalent circuit diagram of a third working process of the pixel driving circuit, and Fig. 12D is an equivalent circuit diagram of a fourth working process of the pixel driving circuit. The working process of the pixel driving circuit exemplified by Fig. 10 can include:

[0165] The first stage P1 is called an initial stage (also referred to as a reset stage). The signal of the reset signal line RE is a high-level signal, and the signals of the first emission signal line EM1, the second emission signal line EM2, the first scan signal line Gate1, and the second scan signal line Gate2 are all low-level signals. The signal of the reset signal line RE is a high-level signal, the second transistor T2 is turned on, and the signal of the reference signal line Ref is provided to the first node N1 to initialize the gate electrode (i.e., the first node N2) of the first transistor T1, for example, to empty the pre-stored voltage in the gate electrode, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the reference signal line Ref is provided to the fifth node N5. The third transistor T3 to the sixth transistor T6 and the eighth transistor T8 are turned off.

[0166] The fifth node N5 is electrically connected to the second electrode (cathode) of the light emitting device L. When the seventh transistor T7 is turned on, the initial voltage of the reference signal line Ref is provided to the second electrode of the light emitting device L from the fifth node N5 to initialize (reset) the second electrode of the light emitting device L, for example, to empty the pre-stored voltage in the second electrode, and the initialization is completed to ensure that the light emitting device L does not emit light. In this stage, the light emitting device L does not emit light.

[0167] The second stage P2 is called a compensation stage (also referred to as a first transistor T1 threshold voltage Vth sampling stage). The signals of the first scan signal line Gate1 and the second emitting signal line EM2 are high level signals, and the signals of the reset signal line RE, the second scan signal line Gate2 and the first emitting signal line EM1 are low level signals. The signal of the reset signal line RE is a low level signal, and the second transistor T2 and the seventh transistor T7 are turned off. The signal of the first scan signal line Gate1 is a high level signal, and the third transistor T3 is turned on. The signal of the second emitting signal line EM2 is a high level signal, and the sixth transistor T6 is turned on. The signal of the first node N1 flows through the turned-on third transistor T3, the turned-on first transistor T1 and the turned-on sixth transistor T6 to the first power supply line VSS. At this time, the voltage of the first node N1 is the sum of the power supply voltage Vs of the first power supply line VSS and the threshold voltage Vth of the first transistor T1, and the power supply voltage Vs of the first power supply line VSS is charged to the second capacitor C2. The eighth transistor T8 is turned on, and the second node N2 and the third node N3 are connected. The second node N2 and the third node N3 write the power supply voltage of the first power supply line VSS, that is, the voltages of the second node N2 and the third node N3 are the power supply voltage Vs of the first power supply line VSS. The fourth transistor T4 and the fifth transistor T5 are disconnected. In this stage, the light emitting device L does not emit light.

[0168] In the P2 stage, the difference Vref between the voltage value VD of the second power supply line VDD and the voltage value of the reference signal line Ref is less than the set light emitting start threshold value. The value range of the set light emitting start threshold value can be [1V, 2V], which can ensure that the light emitting device L does not emit light when the pixel driving circuit works in the first transistor T1 threshold voltage Vth sampling stage or the compensation stage.

[0169] The third stage P3 is called a writing stage, the signal of the second scan signal line Gate2 is a high level signal, the signals of the reset signal line RE, the first scan signal line Gate1, the first emitting signal line EM1 and the second emitting signal line EM2 are all low level signals. The signal of the first scan signal line Gate1 is a low level signal, the third transistor T3 is disconnected, the eighth transistor T8 is disconnected; the signal of the second emitting signal line EM2 is a low level signal, the sixth transistor T6 is disconnected. The signal of the second scan signal line Gate2 is a high level signal, the fourth transistor T4 is turned on, the signal of the data signal line Data is written into the second node N2, at this time, the voltage value V2 of the signal of the second node N2 is the voltage value Vdata of the data signal line Data. Under the action of the second capacitor C2, the voltage value of the signal of the first node N1 in this stage jumps compared with the voltage value in the last stage, at this time, the voltage of the first node N1 jumps to Vdata+Vth. The second transistor T2, the fifth transistor T5 and the seventh transistor T7 are disconnected. In this stage, the light emitting device L does not emit light.

[0170] In the P3 stage, the voltage value V2 of the signal of the second node N2 is the voltage value Vdata of the data signal line Data, the voltage of the data signal line Data cannot be divided by the first capacitor C1 and the second capacitor C2, and the voltage across the data signal line Data can be reduced.

[0171] The fourth stage P4 is called an emitting stage, the signals of the first emitting signal line EM1 and the second emitting signal line EM2 are all high level signals, the signals of the reset signal line RE, the first scan signal line Gate1 and the second scan signal line Gate2 are all low level signals. The signal of the second scan signal line Gate2 is a low level signal, the fourth transistor T4 is disconnected. The signals of the first emitting signal line EM1 and the second emitting signal line EM2 are high level signals respectively, the fifth transistor T5 and the sixth transistor T6 are turned on respectively, the power supply voltage output by the first power supply line VSS is provided to the second electrode of the light emitting device L through the turned-on sixth transistor T6, the turned-on first transistor T1 and the turned-on fifth transistor T5, and the light emitting device L is driven to emit light.

[0172] In the driving process of the pixel circuit, the driving current flowing through the first transistor T1 (the driving transistor) is determined by the voltage difference Vgs between the gate electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the first node N1 is Vdata+Vth, and the voltage value of the third node N3 is the power supply voltage Vs of the first power supply line VSS, the driving current of the first transistor T1 is: I=K*(Vgs-Vth) 2 =K*(Vdata+Vth-Vs-Vth) 2 =K*(Vdata-Vs)2

[0173] Wherein, I is the driving current flowing through the first transistor T1, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the second electrode of the first transistor T1.

[0174] The display device provided in the embodiments of the present disclosure comprises a pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided in any one of the foregoing embodiments, and has similar principles and effects, which will not be described here again.

[0175] The display device provided in the embodiments of the present disclosure comprises a pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided in any one of the foregoing embodiments, and has similar principles and effects, which will not be described here again.

[0176] The driving sub-circuit determines the driving current flowing between the third node and the fourth node under the control of the signal of the first node;

[0177] The first control sub-circuit provides the signal of the reference signal line or the fourth node to the first node and provides the signal of the first node to the second node under the control of the signals of the reset signal line and the first scan signal line;

[0178] The second control sub-circuit provides the signal of the data signal line or the first power supply line to the second node under the control of the signals of the second scan signal line and at least one control signal line;

[0179] The third control sub-circuit provides the signal of the reference signal line to the fifth node under the control of the signal of the reset signal line;

[0180] The light emitting control sub-circuit provides the signal of the first power supply line to the third node and provides the signal of the fourth node to the fifth node under the control of the signals of the first light emitting signal line and the second light emitting signal line;

[0181] Wherein, the signal of the first power supply line is a negative voltage signal.

[0182] The pixel driving circuit is the pixel driving circuit provided in any one of the foregoing embodiments, and has similar principles and effects, which will not be described here again.

[0183] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0184] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of a layer or microstructure are exaggerated. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0185] Although the embodiments of the present disclosure are disclosed as above, the above-described content is merely an embodiment adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art to which the present disclosure belongs can make any modification and change in the form and details thereof without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

A pixel driving circuit, comprising: The circuit includes a driver sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light-emitting control sub-circuit. The driving sub-circuit is electrically connected to the first node, the third node and the fourth node respectively, and is configured to provide driving current to the fourth node under the control of the signals of the first node and the third node. The first control sub-circuit is electrically connected to the reset signal line, the reference signal line, the first scan signal line, the first node, the second node, and the fourth node, respectively, and is configured to provide the reference signal line or the fourth node to the first node and the first node with the signal of the first node under the control of the signals of the reset signal line and the first scan signal line; The second control sub-circuit is electrically connected to the second scan signal line, the second node, at least one control signal line, a data signal line, and the first power line, respectively, and is configured to provide the data signal line or the first power line signal to the second node under the control of the signals of the second scan signal line and at least one control signal line. The third control sub-circuit is electrically connected to the reset signal line, the reference signal line and the fifth node respectively, and is configured to provide the reference signal line signal to the fifth node under the control of the reset signal line signal; The light-emitting control sub-circuit is electrically connected to the first power line, the first light-emitting signal line, the second light-emitting signal line, the third node, the fourth node, and the fifth node, respectively. It is configured to provide the signal of the first power line to the third node and the signal of the fourth node to the fifth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line. The signal of the first power line is a negative voltage signal. According to the pixel driving circuit of claim 1, wherein, The fifth node is electrically connected to the second electrode of the light-emitting device, and the first electrode of the light-emitting device is electrically connected to the second power line. The signal of the second power line is a positive voltage signal. According to the pixel driving circuit of claim 1, wherein, At least one control signal line includes: a third scan signal line; The second control sub-circuit is electrically connected to the second scan signal line, the second node, the third scan signal line, the data signal line, and the first power line, respectively, and is configured to provide the data signal line or the first power line signal to the second node under the control of the signals of the second scan signal line and the third scan signal line. According to the pixel driving circuit of claim 3, wherein, The first scan signal line and the third scan signal line are the same signal line. According to the pixel driving circuit of claim 3, wherein, The second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor; The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first power supply line. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line. According to the pixel driving circuit of claim 1, wherein, At least one control signal line includes: a first scan signal line; The second control sub-circuit is electrically connected to the second scan signal line, the second node, the third node, the first scan signal line, the data signal line, and the first power line, respectively, and is configured to provide the data signal line or the first power line or the third node signal to the second node under the control of the signals of the second scan signal line and the first scan signal line. According to the pixel driving circuit of claim 6, wherein, The second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor; The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the third node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line. According to the pixel driving circuit of claim 1, wherein, The first control sub-circuit includes: a second transistor, a third transistor, and a second capacitor; The control electrode of the second transistor is electrically connected to the reset signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the first scan signal line, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the fourth node. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second node. According to the pixel driving circuit of claim 1, wherein, The third control sub-circuit includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the reference signal line. According to the pixel driving circuit of claim 1, wherein, The driving sub-circuit includes: a first transistor; The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node. According to the pixel driving circuit of claim 1, wherein, The light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first power supply line. According to the pixel driving circuit of claim 1, wherein, The driving sub-circuit includes: a first transistor; the first control sub-circuit includes: a second transistor, a third transistor, and a second capacitor; the second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor; the third control sub-circuit includes: a seventh transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor. The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the reset signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the first scan signal line, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first power supply line. The control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the reference signal line. The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first power supply line. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second node. According to the pixel driving circuit of claim 1, wherein, The driving sub-circuit includes: a first transistor; the first control sub-circuit includes: a second transistor, a third transistor, and a second capacitor; the second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor; the third control sub-circuit includes: a seventh transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor. The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the reset signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the first scan signal line, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node. The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first power supply line. The control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the reference signal line. The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the third node. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second node. The pixel driving circuit according to claim 12 or 13, wherein, At least one of the first to eighth transistors is an N-type transistor. According to the pixel driving circuit of claim 2, wherein, The difference between the voltage value of the second power line and the voltage value of the reference signal line is less than the set light-up threshold. According to the pixel driving circuit of claim 15, wherein, The threshold value for light emission is set to [1V, 2V]. A display device, comprising: The pixel driving circuit as described in any one of claims 1 to 16. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in any one of claims 1 to 16, the method comprising: The driving sub-circuit, under the control of the signal from the first node, determines the driving current flowing between the third and fourth nodes; Under the control of the reset signal line and the first scan signal line, the first control sub-circuit provides the reference signal line or the signal of the fourth node to the first node, and provides the signal of the first node to the second node; The second control sub-circuit provides a data signal line or a first power line signal to the second node under the control of the second scan signal line and at least one control signal line. The third control sub-circuit provides the reference signal line signal to the fifth node under the control of the reset signal line signal; Under the control of the signals from the first and second light-emitting signal lines, the light-emitting control sub-circuit provides the signal from the first power line to the third node and the signal from the fourth node to the fifth node; The signal of the first power line is a negative voltage signal.

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