Communication method, communication apparatus and communication system

Abstract

A communication method, a communication apparatus, and a communication system. In the method, a terminal and an access network device each simply needs to store one sequence, that is, a first sequence, and do not need to store a plurality of sequences, such that storage overheads of the terminal and the access network device can be reduced.

Description

A communication method, a communication apparatus, and a communication system

[0001] Cross Reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410840554.6, filed on June 26, 2024, and entitled “A communication method, a communication apparatus, and a communication system”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of wireless communication, and in particular to a communication method, a communication apparatus, and a communication system. BACKGROUND

[0004] In wireless communication, an access network device determines a sequence from a plurality of stored sequences, generates a primary synchronization signal (PSS) carrying synchronization information based on the sequence, and transmits the primary synchronization signal. The sequence used to generate the primary synchronization signal is mapped on a plurality of consecutive subcarriers in the frequency domain. The form of the sequence mapped on the plurality of consecutive subcarriers in the frequency domain is as follows: d PSS (n) = 1 - 2x(m);

[0005] wherein d PSS (n) represents a complex value of a subcarrier with a frequency domain index n, 0 ≤ n < 127, represents synchronization information and x(i+7) = (x(i+4) + x(i)) mod 2, x(6) = 1, x(5) = 1, x(4) = 1, x(3) = 0, x(2) = 1, x(1) = 1, x(0) = 0, mod represents a modulo operation.

[0006] Different sequences correspond to different synchronization information. Specifically, when the value of is 0, the corresponding sequence is 1; when the value of is 1, the corresponding sequence is 2; and when the value of is 2, the corresponding sequence is 3.

[0007] A terminal receives a signal and performs primary synchronization signal detection on the received signal using a plurality of stored sequences to obtain synchronization information.

[0008] In the above method, the terminal and / or the access network device need to store a plurality of sequences, which has a large storage overhead. SUMMARY

[0009] Embodiments of the present application provide a communication method, a communication device and a communication system to reduce the storage overhead of a terminal and / or an access network device.

[0010] In a first aspect, embodiments of the present application provide a communication method, which can be applied to a terminal side, for example, a terminal or a communication module in the terminal, or a circuit or chip responsible for communication function in the terminal (for example, a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or a system in package (SIP) chip containing a modem core). The method comprises: obtaining a first sequence; and detecting first synchronization information and / or second synchronization information according to the first sequence, wherein the first synchronization information is different from the second synchronization information.

[0011] In the above solution, the first sequence can be obtained from a storage medium (for example, a memory) of the terminal.

[0012] Based on the above solution, the terminal only needs to store one sequence, that is, the first sequence, without storing multiple sequences, so that the storage overhead of the terminal can be reduced.

[0013] In a possible design, the first synchronization information and the second synchronization information are used to indicate different values of a first cell identifier.

[0014] In a possible design, the first synchronization information and the second synchronization information are both information carried by a primary synchronization signal, and the first cell identifier and a physical layer cell identifier satisfy the following relationship:

[0015] wherein, is the physical layer cell identifier, the value of is indicated by the first synchronization information or the second synchronization information, A is a positive integer, is another value used to determine the physical layer cell identifier.

[0016] In a possible design, the value of A is 1. The value set of includes 3 or 4 elements. For example, When the value set of includes 3 elements, the value set of is {0, 1, 2}; When the value set of includes 4 elements, the value set of is {0, 1, 2, 3}.

[0017] In a possible design, the value set of includes 3 or 4 elements, and A is The number of elements included in the value set of A is 3. The number of elements included in the value set of A is 4. The number of elements included in the value set of A is 4.

[0018] In a possible design, the first synchronization information is carried in a first primary synchronization signal, a sequence of the first primary synchronization signal is the first sequence; and the second synchronization information is carried in a second primary synchronization signal, a sequence of the second primary synchronization signal is a second sequence, and the second sequence is obtained based on the first sequence.

[0019] Based on the above scheme, the terminal only needs to store the first sequence, and generates the second sequence based on the first sequence when detecting the second synchronization information, which can reduce the storage cost of the terminal.

[0020] In a possible design, the detecting the second synchronization information based on the first sequence includes: generating the second sequence based on the first sequence; and detecting the second synchronization information based on the second sequence.

[0021] Based on the above scheme, the terminal only needs to store the first sequence, and generates the second sequence based on the first sequence when detecting the second synchronization information, which can reduce the storage cost of the terminal.

[0022] In a possible design, a sequence of real parts of each element in the second sequence and a sequence of real parts of each element in the first sequence are inverse sequences of each other, and a sequence of imaginary parts of each element in the second sequence and a sequence of imaginary parts of each element in the first sequence are inverse sequences of each other.

[0023] Based on the above scheme, the complexity of generating the second sequence based on the first sequence is relatively low, and the calculation cost can be reduced.

[0024] In a possible design, the first synchronization information is carried in a first primary synchronization signal, a sequence of the first primary synchronization signal is a third sequence, the third sequence is obtained based on the first sequence; and the second synchronization information is carried in a second primary synchronization signal, a sequence of the second primary synchronization signal is a second sequence, and the second sequence is obtained based on the first sequence.

[0025] Based on the above scheme, the terminal only needs to store the first sequence, and generates the second sequence and / or the third sequence based on the first sequence when detecting the first synchronization information and / or the second synchronization information, which can reduce the storage cost of the terminal.

[0026] In a possible design, the detecting the first synchronization information and / or the second synchronization information according to the first sequence includes: generating the third sequence according to the first sequence, and detecting the first synchronization information according to the third sequence; and / or, generating the second sequence according to the first sequence, and detecting the second synchronization information according to the second sequence.

[0027] Based on the above scheme, the terminal only needs to store the first sequence, and generates the second sequence and / or the third sequence based on the first sequence when it is necessary to detect the first synchronization information and / or the second synchronization information, which can reduce the storage overhead of the terminal.

[0028] In a possible design, the sequence of real parts of elements in the second sequence is the inverse sequence of the sequence of real parts of elements in the third sequence, and the sequence of imaginary parts of elements in the second sequence is the inverse sequence of the sequence of imaginary parts of elements in the third sequence.

[0029] In a possible design, the second sequence is obtained by cyclically shifting elements in the first sequence.

[0030] Based on the above scheme, the complexity of generating the second sequence based on the first sequence is relatively low, which can reduce the calculation overhead.

[0031] In a possible design, the first sequence is {A(0), A(1), …, A(N-1)}.

[0032] wherein A(n) = c(n) + jd(n); n ∈ {0, 1, …, N-1}, N is a positive integer power of 2, and N is the length of the first sequence; c(n) = a n (2 n -1); d(n) = b n (2 n -1).

[0033] a(n) and b(n) satisfy the following recursive relationship: a0(i) = δ(i); b0(i) = δ(i); a n (i) = a n-1 (i) + q·b n-1 (i-2 n-1 ); b n (i) = a n-1 (i) - q·b n-1 (i-2 n-1 ).

[0034] wherein i ∈ {0, 1, …, N-1}; δ(i) = 1 if and only if i = 0; δ(i) = 0 if and only if i ≠ 0, and q ∈ {-1, 1}.

[0035] In a possible design, the length of the first sequence is 64, 128 or 256.

[0036] In a second aspect, the method can be applied to a network side, for example, an access network device at the network side, a module (for example, a circuit, a chip or a chip system, etc.) in the access network device, or a logic node, a logic module or software capable of implementing all or part of the function of the access network device. The method includes: generating a first primary synchronization signal or a second primary synchronization signal according to a first sequence, the first primary synchronization signal carrying first synchronization information, and the second primary synchronization signal carrying second synchronization information, the first synchronization information being different from the second synchronization information; and sending the first primary synchronization signal or the second primary synchronization signal.

[0037] Based on the above scheme, the access network device only needs to store one sequence, that is, the first sequence, and does not need to store multiple sequences, thereby reducing the storage overhead of the access network device.

[0038] In a possible design, the first synchronization information and the second synchronization information are used to indicate different values of a first cell identifier.

[0039] In a possible design, the first cell identifier and a physical layer cell identifier satisfy the following relationship:

[0040] wherein, is the physical layer cell identifier, the value of is indicated by the first synchronization information or the second synchronization information, and A is a positive integer, is another value used to determine the physical layer cell identifier.

[0041] In a possible design, the value set of includes 3 or 4 elements. For example, when the value set of includes 3 elements, the value set of is {0, 1, 2}; when the value set of includes 4 elements, the value set of is {0, 1, 2, 3}.

[0042] In a possible design, the value set of includes 3 or 4 elements, and A is the number of elements included in the value set of. For example, when the value set of includes 3 elements, A=3; when the value set of includes 4 elements, A=4.

[0043] In a possible design, the sequence of the first primary synchronization signal is the first sequence; and the sequence of the second primary synchronization signal is a second sequence, which is derived from the first sequence.

[0044] Based on the above scheme, the access network device only needs to store the first sequence, and generates the second sequence based on the first sequence when the second primary synchronization signal needs to be generated, and generates the second primary synchronization signal based on the second sequence, which can reduce the storage overhead of the access network device.

[0045] In a possible design, the generating the second primary synchronization signal based on the first sequence includes: generating the second sequence based on the first sequence; and generating the second primary synchronization signal based on the second sequence.

[0046] Based on the above scheme, the access network device only needs to store the first sequence, and generates the second sequence based on the first sequence when the second primary synchronization signal needs to be generated, and generates the second primary synchronization signal based on the second sequence, which can reduce the storage overhead of the access network device.

[0047] In a possible design, the sequence of real parts of elements in the second sequence is the inverse of the sequence of real parts of elements in the first sequence, and the sequence of imaginary parts of elements in the second sequence is the inverse of the sequence of imaginary parts of elements in the first sequence.

[0048] Based on the above scheme, the complexity of generating the second sequence based on the first sequence is relatively low, which can reduce the computation overhead.

[0049] In a possible design, the sequence of the first primary synchronization signal is a third sequence, which is derived from the first sequence; and the sequence of the second primary synchronization signal is a second sequence, which is derived from the first sequence.

[0050] Based on the above scheme, the access network device only needs to store the first sequence, and generates the third sequence based on the first sequence when the first primary synchronization signal needs to be generated, and generates the first primary synchronization signal based on the third sequence, or generates the second sequence based on the first sequence when the second primary synchronization signal needs to be generated, and generates the second primary synchronization signal based on the second sequence, which can reduce the storage overhead of the access network device.

[0051] In a possible design, the generating the first primary synchronization signal or the second primary synchronization signal based on the first sequence includes: generating the third sequence based on the first sequence, and generating the first primary synchronization signal based on the third sequence; or generating the second sequence based on the first sequence, and generating the second primary synchronization signal based on the second sequence.

[0052] Based on the scheme, the access network device only needs to store the first sequence, and generate the third sequence based on the first sequence and generate the first primary synchronization signal based on the third sequence when the first primary synchronization signal needs to be generated, or generate the second sequence based on the first sequence and generate the second primary synchronization signal based on the second sequence when the second primary synchronization signal needs to be generated, which can reduce the storage overhead of the access network device.

[0053] In a possible design, a sequence composed of real parts of elements in the second sequence is an inverse sequence of a sequence composed of real parts of elements in the third sequence, and a sequence composed of imaginary parts of elements in the second sequence is an inverse sequence of a sequence composed of imaginary parts of elements in the third sequence.

[0054] In a possible design, the second sequence is obtained by cyclically shifting elements in the first sequence.

[0055] Based on the scheme, the complexity of generating the second sequence based on the first sequence is relatively low, and the calculation overhead can be reduced.

[0056] In a possible design, the first sequence is {A(0), A(1), …, A(N-1)}.

[0057] wherein A(n) = c(n) + jd(n); n ∈ {0, 1, …, N-1}, N is a positive integer power of 2, and N is the length of the first sequence; c(n) = a n (2 n -1); d(n) = b n (2 n -1).

[0058] a(n) and b(n) satisfy the following recursive relationship: a0(i) = δ(i); b0(i) = δ(i); a n (i) = a n-1 (i) + q·b n-1 (i-2 n-1 ); b n (i) = a n-1 (i) - q·b n-1 (i-2 n-1 ).

[0059] wherein i ∈ {0, 1, …, N-1}; δ(i) = 1 if and only if i = 0; δ(i) = 0 if and only if i ≠ 0, and q ∈ {-1, 1}.

[0060] In a possible design, the length of the first sequence is 64, 128, or 256.

[0061] In a third aspect, the present application provides a communication apparatus, which has the functions of the first aspect. For example, the communication apparatus includes modules, units or means corresponding to the operations of the first aspect. These modules, units or means can be implemented in software, or in hardware, or in a combination of software and hardware.

[0062] In a fourth aspect, the present application provides a communication apparatus, which has the functions of the second aspect. For example, the communication apparatus includes modules, units or means corresponding to the operations of the second aspect. These modules, units or means can be implemented in software, or in hardware, or in a combination of software and hardware.

[0063] In a fifth aspect, the present application provides a communication apparatus, which includes an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory is used to store part or all of the necessary computer programs or instructions for implementing the functions of the first aspect. The one or more processors can execute the computer programs or instructions, which, when executed, cause the communication apparatus to implement the method in any possible design or implementation manner of the first aspect. The interface circuit is used to implement the communication function within the communication apparatus and / or the communication function of the communication apparatus with other apparatuses or components.

[0064] In a possible design, the processor is configured to communicate with other apparatuses or components through the interface circuit.

[0065] In a possible design, the communication apparatus can further include the memory.

[0066] The communication apparatus can be a terminal, or a communication module in a terminal, or a chip responsible for the communication function in a terminal, such as a modem chip (also referred to as a baseband chip) or an SoC or SIP chip including a modem module.

[0067] In a sixth aspect, the present application provides a communication apparatus, which includes an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory is used to store part or all of the necessary computer programs or instructions for implementing the functions of the second aspect. The one or more processors can execute the computer programs or instructions, which, when executed, cause the communication apparatus to implement the method in any possible design or implementation manner of the second aspect. The interface circuit is used to implement the communication function within the communication apparatus and / or the communication function of the communication apparatus with other apparatuses or components.

[0068] The communication device can be an access network device, a module (e.g., a circuit, a chip or a chip system, etc.) in the access network device, or a logic node, a logic module or software capable of implementing all or part of the functions of the access network device.

[0069] In a seventh aspect, the present application provides a communication system, which comprises a communication device for performing the method in any possible design of the first aspect, and a communication device for performing the method in any possible design of the second aspect.

[0070] In an eighth aspect, the present application provides a computer readable storage medium, which stores computer readable instructions, and when a computer reads and executes the computer readable instructions, the computer performs the method in any possible design of the first aspect to the second aspect.

[0071] In a ninth aspect, the present application provides a computer program product, and when a computer reads and executes the computer program product, the computer performs the method in any possible design of the first aspect to the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0072] FIG. 1 is a possible, non-limiting system schematic diagram;

[0073] FIG. 2 is a flow diagram of a communication method provided by an embodiment of the present application;

[0074] FIG. 3 is a possible exemplary block diagram of a communication device involved in an embodiment of the present application;

[0075] FIG. 4 is a structural schematic diagram of a terminal provided by an embodiment of the present application. DETAILED DESCRIPTION

[0076] Figure 1 is a schematic diagram of a possible, non-limiting system. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. Optionally, the communication system also includes the Internet 300. The RAN 100 includes at least one RAN node (e.g., 110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (e.g., 120a-120j in Figure 1, collectively referred to as 120). Other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1), can also be included in the RAN 100. The terminals 120 are wirelessly connected to the RAN nodes 110. The RAN nodes 110 are connected to the core network 200 by wireline or wireless means. The core network devices in the core network 200 and the RAN nodes 110 in the RAN 100 can be different physical devices, or they can be the same physical devices that integrate the core network logical functions and the radio access network logical functions.

[0077] The RAN 100 can be a 3rd generation partnership project (3GPP)-related cellular system, such as a 4th generation (4G), 5th generation (5G) mobile communication system, or a future-oriented evolved system (e.g., a 6th generation (6G) mobile communication system). The RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. The RAN 100 can also be a communication system that integrates two or more of the above systems.

[0078] The RAN node 110, which can also be referred to as an access network device, a RAN entity, or an access node, etc., forms part of the communication system, and is configured to facilitate the wireless access by the terminals. The RAN nodes 110 in the communication system 10 can be of the same type or different types. In some scenarios, the roles of the RAN node 110 and the terminal 120 are relative, e.g., the network element 120i in Figure 1 can be a helicopter or a drone, which can be configured to be a mobile base station, and for a terminal 120j accessing the RAN 100 via the network element 120i, the network element 120i is a base station; but for the base station 110a, the network element 120i is a terminal. Both the RAN node 110 and the terminal 120 are sometimes referred to as communication apparatuses, e.g., the network elements 110a and 110b in Figure 1 can be understood as communication apparatuses with base station functionalities, and the network elements 120a-120j can be understood as communication apparatuses with terminal functionalities.

[0079] In a possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a next generation base station in a 6G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc. The RAN node can be a macro base station (e.g., 110a in Figure 1), a micro base station or an indoor station (e.g., 110b in Figure 1), a relay node or a donor node, or a wireless controller in a CRAN scenario. Optionally, the RAN node can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU). All or part of the functions of the RAN node in this application can also be implemented by software functions running on hardware, or by virtualized functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be provided with a communication module, circuit or chip for performing corresponding communication functions, and program instructions for performing corresponding communication functions. The RAN node in this application can also be a logical node, a logical module or software that can implement all or part of the functions of the RAN node.

[0080] In another possible scenario, multiple RAN nodes cooperate to assist a terminal to implement wireless access, and different RAN nodes respectively implement part of functions of a base station. For example, a RAN node can be a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), etc. The CU and the DU can be separately arranged, or can also be included in the same network element, for example, in a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, for example, included in a remote radio unit (RRU), an active antenna processing unit (AAU), or a remote radio head (RRH).

[0081] In different systems, the CU (or CU-CP and CU-UP), DU or RU can also have different names, but those skilled in the art can understand their meanings. For example, in an ORAN system, the CU can also be referred to as an O-CU (open CU), the DU can also be referred to as an O-DU, the CU-CP can also be referred to as an O-CU-CP, the CU-UP can also be referred to as an O-CU-UP, and the RU can also be referred to as an O-RU. For the convenience of description, the CU, CU-CP, CU-UP, DU and RU are taken as examples for description in this application. Any one of the CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0082] A terminal can be a device or module with corresponding communication functions and can access the above-mentioned communication system. The terminal can also be referred to as a terminal device, user equipment (UE), mobile station, mobile terminal, etc. The terminal can be widely used in various scenarios, such as device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-type communication (MTC), internet of things (IOT), virtual reality, augmented reality, industrial control, autonomous driving, remote medical treatment, smart power grid, smart furniture, smart office, smart wear, smart transportation, smart city, etc. The terminal can be a mobile phone, tablet computer, computer with wireless transceiver function, wearable device, vehicle, unmanned aerial vehicle, helicopter, airplane, ship, robot, mechanical arm, smart home device, transport vehicle with wireless communication function, communication module, etc. Embodiments of the present application do not limit the device form of the terminal. The terminal is usually provided with a communication module, circuit or chip for executing corresponding communication functions. The terminal is also configured with program instructions for executing corresponding communication functions.

[0083] In wireless communication, a terminal receives a primary synchronization signal from an access network device, detects the received primary synchronization signal to obtain synchronization information, which includes, for example, downlink timing information, etc. The synchronization information is generated based on a sequence, one sequence can be used to generate one synchronization information, and different sequences can be used to generate different synchronization information.

[0084] The access network device selects a sequence from a plurality of stored sequences, generates corresponding synchronization information based on the sequence, and transmits a primary synchronization signal carrying the synchronization information. The terminal detects the synchronization information using a plurality of stored sequences.

[0085] The above method, terminal and access network device all need to store a plurality of sequences, which has a large storage overhead.

[0086] To solve this problem, the present application provides corresponding communication methods and devices.

[0087] The communication method and device are further described below with reference to the drawings. It can be understood that the access network device and the terminal are taken as an example to illustrate the execution subject of the interaction in the present application, but the present application is not limited to the execution subject of the interaction. For example, the method executed by the access network device in the present application can also be implemented by a module (such as a circuit, a chip or a chip system, etc.) in the access network device, or a logical node, a logical module or software capable of implementing all or part of the function of the access network device; the method executed by the terminal in the present application can also be implemented by a communication module in the terminal or a circuit or chip (such as a modem chip (also known as a baseband chip), or a SoC chip containing a modem core, or a SIP chip) responsible for the communication function in the terminal.

[0088] FIG. 2 is a flowchart of a communication method provided by an embodiment of the present application. The method includes the following steps:

[0089] In step 201, the access network device generates a first primary synchronization signal or a second primary synchronization signal according to a first sequence.

[0090] The first primary synchronization signal carries first synchronization information, and the second primary synchronization signal carries second synchronization information. The first synchronization information is different from the second synchronization information.

[0091] For example, the length of the first sequence is a positive integer power of 2, such as 2, 4, 8, 16, 32, 64, 128 or 256, etc.

[0092] For example, the first synchronization information and the second synchronization information are used to indicate different values of a first cell identifier.

[0093] For example, the first cell identifier and the physical layer cell identifier satisfy the following relationship:

[0094] wherein, is the physical layer cell identifier, the value of is indicated by the first synchronization information or the second synchronization information, and A is a positive integer, is another value used to determine the physical layer cell identifier.

[0095] For example, The value set of includes 3 or 4 elements. For example, When the value set of includes 3 elements, the value set of is {0, 1, 2}; When the value set of includes 4 elements, the value set of is {0, 1, 2, 3}.

[0096] For example, The set of values ​​for A contains 3 or 4 elements, and A is... The number of elements included in the set of possible values. For example, When the set of possible values ​​contains 3 elements, A = 3; When the set of possible values ​​includes 4 elements, A = 4.

[0097] in, The set of values ​​that can be used can be predefined.

[0098] For example, The value is indicated by the secondary synchronization signal sent by the access network device. For example, the terminal performs secondary synchronization signal detection on the received signal and obtains the indication information, and then determines the value based on the indication information. The value of .

[0099] The following describes two different implementation methods for step 201.

[0100] In one implementation method, the access network device generates a first primary synchronization signal based on the first sequence, or the access network device generates a second sequence based on the first sequence and generates a second primary synchronization signal based on the second sequence.

[0101] Based on this implementation method, the sequence of the first primary synchronization signal is a first sequence, and the access network device can generate the first primary synchronization signal according to the first sequence. The sequence of the second primary synchronization signal is a second sequence, and the access network device can first generate the second sequence according to the first sequence, and then generate the second primary synchronization signal according to the second sequence.

[0102] For example, the first sequence and the second sequence satisfy the following relationship: the first sequence includes N elements, each element being a complex number; the second sequence includes N elements, each element being a complex number, where N is an integer greater than 1. Furthermore, the sequence formed by the real parts of each element in the second sequence is the reverse of the sequence formed by the real parts of each element in the first sequence, and the sequence formed by the imaginary parts of each element in the second sequence is the reverse of the sequence formed by the imaginary parts of each element in the first sequence. For example, the elements in the first sequence sequentially include: a1+jb1, a2+jb2, ..., a N +jb N The elements in the second sequence include, in order: a N +jb N a N-1 +jb N-1 ,…,a1+jb1。

[0103] In the second implementation, the access network device generates a third sequence according to the first sequence and generates the first primary synchronization signal according to the third sequence, or generates a second sequence according to the first sequence and generates the second primary synchronization signal according to the second sequence. The second sequence is different from the third sequence.

[0104] According to the implementation, the sequence of the first primary synchronization signal is the third sequence, and the access network device can generate the third sequence according to the first sequence first, and then generate the first primary synchronization signal according to the third sequence. The sequence of the second primary synchronization signal is the second sequence, and the access network device can generate the second sequence according to the first sequence first, and then generate the second primary synchronization signal according to the second sequence.

[0105] For example, the second sequence and the third sequence satisfy the following relationship: the second sequence includes N elements, each element is a complex number, the third sequence includes N elements, each element is a complex number, N is an integer greater than 1. And the sequence of the real part of each element in the second sequence and the sequence of the real part of each element in the third sequence are inverse sequences of each other, and the sequence of the imaginary part of each element in the second sequence and the sequence of the imaginary part of each element in the third sequence are inverse sequences of each other. For example, the elements of the second sequence include c1+jd1, c2+jd2, …, cN-1+jdN-1, cN+jdN in turn, and the elements of the third sequence include cN+jdN, cN-1+jdN-1, …, c2+jd2, c1+jd1 in turn. N N N N N-1 N-1

[0106] In a possible design, the second sequence is obtained by cyclically shifting the elements in the first sequence. For example, the first sequence is c5+jd5, c6+jd6, …, cN-1+jdN-1, cN+jdN, and the second sequence is cN+jdN, c5+jd5, c6+jd6, …, cN-1+jdN-1, c1+jd1, c2+jd2, c3+jd3, c4+jd4. N N

[0107] In another possible design, the third sequence is obtained by cyclically shifting the elements in the first sequence. For example, the first sequence is c1+jd1, c2+jd2, c3+jd3, c4+jd4, c5+jd5, c6+jd6, …, cN-1+jdN-1, cN+jdN, and the third sequence is cN+jdN, cN-1+jdN-1, …, c6+jd6, c5+jd5, c4+jd4, c3+jd3, c2+jd2, c1+jd1. N-2 N-2 N-3 N-3 N N N-1 N-1

[0108] In step 202, the access network device sends the first primary synchronization signal or the second primary synchronization signal.

[0109] ​​​​​​​​​​​​​​​​In step 203, the terminal acquires the first sequence.

[0110] The terminal can acquire the first sequence from a local storage or from an external storage.

[0111] In step 204, the terminal detects the first synchronization information and / or the second synchronization information according to the first sequence.

[0112] That is, the terminal detects the received primary synchronization signal based on the first sequence, and thus detects the synchronization information carried in the primary synchronization signal. For example, if the access network device transmits the first primary synchronization signal, the terminal detects the first synchronization information; if the access network device transmits the second primary synchronization signal, the terminal can detect the second synchronization information.

[0113] Two different implementation methods of the step 204 are described below. The following implementation method A corresponds to the above implementation method one, and the following implementation method B corresponds to the above implementation method two.

[0114] In implementation method A, the terminal detects the first synchronization information according to the first sequence, and / or detects the second synchronization information according to the second sequence. The second sequence is generated by the terminal based on the first sequence.

[0115] In one implementation method, the terminal first detects the received primary synchronization signal according to the first sequence, and stops the detection if the first synchronization information is correctly detected. At this time, the terminal can not need to detect the received primary synchronization signal according to the second sequence. In this scenario, the access network device transmits the first primary synchronization signal. Based on this implementation method, the terminal can also not need to generate the second sequence based on the first sequence.

[0116] In another implementation method, the terminal first detects the received primary synchronization signal according to the first sequence, and then detects the received primary synchronization signal according to the second sequence if the first synchronization information is not correctly detected. The terminal stops the detection if the second synchronization information is correctly detected. In this scenario, the access network device transmits the second primary synchronization signal. Based on this implementation method, the terminal can generate the second sequence before detecting the received primary synchronization signal according to the first sequence, or can generate the second sequence after the detection of the received primary synchronization signal according to the first sequence fails.

[0117] In another implementation method, the terminal first generates the second sequence according to the first sequence, and detects the received primary synchronization signal according to the second sequence. The terminal stops the detection if the second synchronization information is correctly detected. At this time, the terminal can not need to detect the received primary synchronization signal according to the first sequence. In this scenario, the access network device transmits the second primary synchronization signal.

[0118] In another implementation method, the terminal first generates the second sequence according to the first sequence, and detects the received primary synchronization signal according to the second sequence. If the second synchronization information is not correctly detected, the terminal detects the received primary synchronization signal according to the first sequence again. If the first synchronization information is correctly detected, the detection is stopped. In this scenario, the primary synchronization signal sent by the access network device is the first primary synchronization signal.

[0119] In the implementation method B, the terminal detects the first synchronization information according to the third sequence, and / or detects the second synchronization information according to the second sequence. The second sequence and the third sequence are both generated by the terminal based on the first sequence, and the second sequence is different from the third sequence.

[0120] In one implementation method, the terminal first generates the third sequence according to the first sequence, and detects the received primary synchronization signal according to the third sequence. If the first synchronization information is correctly detected, the detection is stopped. At this time, the terminal can not need to detect the received primary synchronization signal according to the second sequence. In this scenario, the primary synchronization signal sent by the access network device is the first primary synchronization signal. Based on this implementation method, the terminal can also not need to generate the second sequence based on the first sequence.

[0121] In another implementation method, the terminal first generates the third sequence according to the first sequence, and detects the received primary synchronization signal according to the third sequence. If the first synchronization information is not correctly detected, the terminal detects the received primary synchronization signal according to the second sequence again. If the second synchronization information is correctly detected, the detection is stopped. In this scenario, the primary synchronization signal sent by the access network device is the second primary synchronization signal. Based on this implementation method, the terminal can generate the second sequence before detecting the received primary synchronization signal according to the third sequence, or generate the second sequence after the detection of the received primary synchronization signal according to the third sequence fails.

[0122] In another implementation method, the terminal first generates the second sequence according to the first sequence, and detects the received primary synchronization signal according to the second sequence. If the second synchronization information is correctly detected, the detection is stopped. At this time, the terminal can not need to detect the received primary synchronization signal according to the third sequence. In this scenario, the primary synchronization signal sent by the access network device is the second primary synchronization signal. Based on this implementation method, the terminal can also not need to generate the third sequence based on the first sequence.

[0123] In another implementation method, the terminal first generates the second sequence according to the first sequence, and detects the received primary synchronization signal according to the second sequence, if the second synchronization information is not correctly detected, the terminal detects the received primary synchronization signal according to the third sequence again, and if the first synchronization information is correctly detected, the detection is stopped. In this scenario, the primary synchronization signal sent by the access network device is the first primary synchronization signal. Based on this implementation method, the terminal can generate the third sequence before detecting the received primary synchronization signal according to the second sequence, or generate the third sequence after the detection of the received primary synchronization signal according to the second sequence fails.

[0124] In a possible design, the first sequence is {A(0), A(1), …, A(N-1)}. Wherein, A(n) is the nth element in the first sequence, n ∈ {0, 1, …, N-1}, N is a positive integer power of 2, and N is the length of the first sequence.

[0125] Exemplarily, A(n) = c(n) + jd(n).

[0126] Wherein, c(n) = a n (2 n -1), d(n) = b n (2 n -1).

[0127] a(n) and b(n) satisfy the following recursive relationship: a0(i) = δ(i). b0(i) = δ(i). a n (i) = a n-1 (i) + q·b n-1 (i-2 n-1 ). b n (i) = a n-1 (i) - q·b n-1 (i-2 n-1 ).

[0128] Wherein, i ∈ {0, 1, …, N-1}. δ(i) = 1 if and only if i = 0. δ(i) = 0 if and only if i ≠ 0, q ∈ {-1, 1}.

[0129] For example, when N = 2, A(0) = 1 + j, and A(1) = 1 - j.

[0130] Based on the above scheme, the terminal and the access network device only need to store one sequence, i.e., the first sequence, without the need to store multiple sequences, which can reduce the storage overhead of the terminal and the access network device. And when the second sequence and / or the third sequence is generated according to the first sequence, the generation complexity is low, which can save the computing resource overhead of the terminal and the access network device.

[0131] FIG. 3 shows a possible exemplary block diagram of a communication apparatus involved in embodiments of the present application. As shown in FIG. 3, the communication apparatus 300 can include modules or units for implementing the above-described method embodiments. In one possible design, the communication apparatus 300 includes a processing unit 302 and a communication unit 303. Optionally, the communication apparatus 300 can further include a storage unit 301, configured to store apparatus program code and / or data.

[0132] The communication apparatus 300 can be a terminal-side apparatus in the above-described embodiments, for example, a terminal or a communication module in a terminal, or a circuit or chip responsible for communication functions in a terminal.

[0133] For example, in one embodiment, the processing unit 302 is configured to acquire a first sequence; and detect first synchronization information and / or second synchronization information according to the first sequence, the first synchronization information being different from the second synchronization information.

[0134] In one possible design, the first synchronization information and the second synchronization information are both first cell identifiers.

[0135] In one possible design, the first synchronization information and the second synchronization information are both information carried in a primary synchronization signal, and the first cell identifier and a physical layer cell identifier satisfy the following relationship:

[0136] wherein, is the physical layer cell identifier, is the first synchronization information or the second synchronization information, and A is a positive integer, is other synchronization information used to determine the physical layer cell identifier.

[0137] In one possible design, the first synchronization information is carried in a first primary synchronization signal, a sequence of the first primary synchronization signal being the first sequence; and the second synchronization information is carried in a second primary synchronization signal, a sequence of the second primary synchronization signal being a second sequence, the second sequence being derived according to the first sequence.

[0138] In one possible design, the processing unit 302 is configured to detect the second synchronization information according to the first sequence, including: generating the second sequence according to the first sequence; and detecting the second synchronization information according to the second sequence.

[0139] In one possible design, a sequence of real parts of elements in the second sequence and a sequence of real parts of elements in the first sequence are inverse sequences of each other, and a sequence of imaginary parts of elements in the second sequence and a sequence of imaginary parts of elements in the first sequence are inverse sequences of each other.

[0140] In one possible design, the first synchronization information is carried in a first primary synchronization signal, a sequence of the first primary synchronization signal is a third sequence, and the third sequence is derived from the first sequence; and the second synchronization information is carried in a second primary synchronization signal, a sequence of the second primary synchronization signal is a second sequence, and the second sequence is derived from the first sequence.

[0141] In one possible design, the processing unit 302, configured to detect the first synchronization information and / or the second synchronization information according to the first sequence, can include a unit configured to generate the third sequence according to the first sequence, and detect the first synchronization information according to the third sequence; and / or, generate the second sequence according to the first sequence, and detect the second synchronization information according to the second sequence.

[0142] In one possible design, a sequence of real parts of elements in the second sequence and a sequence of real parts of elements in the third sequence are inverse sequences of each other, and a sequence of imaginary parts of elements in the second sequence and a sequence of imaginary parts of elements in the third sequence are inverse sequences of each other.

[0143] In one possible design, the second sequence is obtained by cyclically shifting elements in the first sequence.

[0144] In one possible design, the first sequence is {A(0), A(1), …, A(N-1)}; and the second sequence is {B(0), B(1), …, B(N-1)}.

[0145] where A(n) = c(n) + jd(n); n ∈ {0, 1, …, N-1}, N is a positive integer power of 2, and N is the length of the first sequence; c(n) = a n (2 n -1); and d(n) = b n (2 n -1).

[0146] a(n) and b(n) satisfy the following recursive relations: a0(i) = δ(i); b0(i) = δ(i); a n (i) = a n-1 (i) + q·b n-1 (i-2 n-1 ); and b n (i) = a n-1 (i) - q·b n-1 (i-2 n-1 ),

[0147] where i ∈ {0, 1, …, N-1}; δ(i) = 1 if and only if i = 0; δ(i) = 0 if and only if i ≠ 0, and q ∈ {-1, 1}.

[0148] In a possible design, the length of the first sequence is 64, 128 or 256.

[0149] In a possible design, when the communication apparatus 300 is a terminal or a communication module in a terminal, the function of the processing unit 302 can be implemented by one or more processors. Specifically, the processor can include a modem chip, or a system on chip (SoC) chip or a SIP chip including a modem core. The function of the communication unit 303 can be implemented by a transceiver circuit.

[0150] In a possible design, when the communication apparatus 300 is a circuit or chip responsible for communication functions in a terminal, such as a modem chip or a system on chip (SoC) chip or a SIP chip including a modem core, the function of the processing unit 302 can be implemented by circuitry including one or more processors or processor cores in the chip. The function of the communication unit 303 can be implemented by an interface circuit or a data transceiver circuit on the chip.

[0151] The communication apparatus 300 can also be a network-side device in the above-described embodiments, for example, an access network device on the network side, a module (for example, a circuit, a chip or a chip system, etc.) in the access network device, or a logic node, a logic module or software capable of implementing all or part of the functions of the access network device.

[0152] For example, in an embodiment, the processing unit 302 is configured to generate a first primary synchronization signal or a second primary synchronization signal according to a first sequence, the first primary synchronization signal carrying first synchronization information, and the second primary synchronization signal carrying second synchronization information, the first synchronization information being different from the second synchronization information; and the communication unit 303 is configured to send the first primary synchronization signal or the second primary synchronization signal.

[0153] In a possible design, the first synchronization information and the second synchronization information are both first cell identifiers.

[0154] In a possible design, the first cell identifier and a physical layer cell identifier satisfy the following relationship:

[0155] wherein, is the physical layer cell identifier, is the first synchronization information or the second synchronization information, and A is a positive integer, is other synchronization information used to determine the physical layer cell identifier.

[0156] In a possible design, the sequence of the first primary synchronization signal is the first sequence; and the sequence of the second primary synchronization signal is a second sequence, which is obtained from the first sequence.

[0157] In a possible design, the processing unit 302 is configured to generate the second primary synchronization signal according to the first sequence, including: generating the second sequence according to the first sequence; and generating the second primary synchronization signal according to the second sequence.

[0158] In a possible design, the sequence of real parts of elements in the second sequence is the inverse of the sequence of real parts of elements in the first sequence, and the sequence of imaginary parts of elements in the second sequence is the inverse of the sequence of imaginary parts of elements in the first sequence.

[0159] In a possible design, the sequence of the first primary synchronization signal is a third sequence, which is obtained from the first sequence; and the sequence of the second primary synchronization signal is a second sequence, which is obtained from the first sequence.

[0160] In a possible design, the processing unit 302 is configured to generate the first primary synchronization signal or the second primary synchronization signal according to the first sequence, including: generating the third sequence according to the first sequence, and generating the first primary synchronization signal according to the third sequence; or generating the second sequence according to the first sequence, and generating the second primary synchronization signal according to the second sequence.

[0161] In a possible design, the sequence of real parts of elements in the second sequence is the inverse of the sequence of real parts of elements in the third sequence, and the sequence of imaginary parts of elements in the second sequence is the inverse of the sequence of imaginary parts of elements in the third sequence.

[0162] In a possible design, the second sequence is obtained by cyclically shifting elements in the first sequence.

[0163] In a possible design, the first sequence is {A(0), A(1), …, A(N-1)}.

[0164] wherein A(n) = c(n) + jd(n); n ∈ {0, 1, …, N-1}, N is a positive integer power of 2, and N is the length of the first sequence; c(n) = a n (2 n -1); d(n) = b n (2 n -1);

[0165] The a(n) and b(n) satisfy the following recursive relations: a0(i) = δ(i); b0(i) = δ(i); a n (i) = a n-1 (i) + q.b n-1 (i-2 n-1 ); b n (i) = a n-1 (i) - q.b n-1 (i-2 n-1 );

[0166] where i ∈ {0, 1, …, N-1}; δ(i) = 1 if and only if i = 0; δ(i) = 0 if and only if i ≠ 0, q ∈ {-1, 1}.

[0167] In one possible design, the first sequence has a length of 64, 128, or 256.

[0168] It can be understood that the division of units in the above apparatus is merely a logical division of functions, and one function can correspond to one functional unit, or two or more functions can be integrated into one functional unit. In actual implementation, all or part of the units can be integrated into one physical entity, or can be distributed in different physical entities. In addition, the above functional units can be implemented in the form of hardware, or in the form of software, or in the form of hardware combined with software. Whether a certain function is implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for a specific application, but such implementation should not be considered beyond the scope of the present application.

[0169] In one example, the functional units in any of the above apparatuses can be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more central processing units (CPUs), one or more microcontroller Units (MCUs), one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0170] In one example, the storage unit 301 can include random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory and / or registers, etc.

[0171] FIG. 4 is a structural schematic diagram of a terminal 400 provided by an embodiment of the present application. The terminal 400 can correspond to the terminal shown in FIG. 1, and is used to implement the operation of the terminal in the above embodiments. As shown in FIG. 4, the terminal includes one or more antennas 410, a radio frequency processing system 420, and a processor system 430.

[0172] In the downlink or sidelink direction, the radio frequency processing system 420 receives radio frequency signals through the antenna 410, and sends the signals processed by radio frequency to the processor system 430 for further processing. In the uplink or sidelink direction, the processor system 430 performs signal processing on the information at the terminal side, and sends the signal to the radio frequency processing system 420, which performs radio frequency processing on the signal and transmits it through the antenna 410.

[0173] In one example, the radio frequency processing system 420, as a communication interface of the terminal for external communication, can include a radio frequency frontend 421 (RFFE) and a radio frequency transceiver 422 (RF transceiver). The RFFE 421 is mainly used for one or more of shaping, passband selection, or gain processing of RF signals received by the antenna or RF signals to be sent through the antenna, and can include one or more of radio frequency switches, duplexers, filters, power amplifiers, antenna tuning, and low-noise amplifiers. The RFFE 421 can be a circuit system composed of multiple discrete devices, or can be integrated and packaged in one or more chips. The radio frequency transceiver 422 is used to process the RF signals received by the RFFE into baseband / intermediate frequency signals for further processing by the processor system 430, and to process the baseband / intermediate frequency signals provided by the processor system 430 into RF signals for sending to the RFFE 421. The baseband / intermediate frequency signals transmitted between the radio frequency transceiver 422 and the processor system 430 can be digital signals or analog signals. The radio frequency transceiver 422 can be implemented by one or more chips, which are usually referred to as radio frequency chips (RFIC).

[0174] In one example, the processor system 430 can include one or more processors for processing signals and executing one or more communication protocols. Optionally, the processor system 430 can further include a memory 436. In one example, the one or more processors include at least one baseband processor 431 (also referred to as a modem processor). The memory 436 is used for storing data and / or computer program instructions. Optionally, the processor system 430 can further include one or more application processors 432 for implementing processing for an operating system of the terminal and for an application layer. Optionally, the processor system 430 can further include one or more of a voice subsystem 433, a multimedia subsystem 434, or an interface circuit 435. The voice subsystem 433 is used for processing voice signals, the multimedia subsystem 434 is used for processing multimedia related operations such as video codec, image processing, etc., and the interface circuit 435 is used for implementing communication with other terminal components such as the display 440, the input device 450, the memory 460, etc. The above components in the processor system 430 can communicate with each other through a bus or a communication interface circuit.

[0175] In one example, the processor system 430 can be packaged as a processor chip such as a SoC chip or a SIP chip. In one example, the processor system 430 can be a system of multiple chips, for example, the baseband processor 431 can be packaged as a separate chip or packaged with part or all of the circuitry of the radio frequency processing system as a chip.

[0176] In one example, the memory 436 can be an on-chip memory, i.e., located on the chip of the processor system 430. In one example, the memory 460 can be an off-chip memory, i.e., located off the chip of the processor system 430.

[0177] In one example, the baseband processor 431 can include one or more processor cores 4311 and an interface circuit 4314. The one or more processor cores 4311 are configured to process signals and perform one or more communication protocols. Optionally, the baseband processor 431 can further include a memory 4312 configured to store at least part of corresponding computer program instructions and / or data. In one example, the one or more processor cores 4311 implement the above-mentioned operations (e.g., performing the above-mentioned steps 203 and 204) in the above-mentioned method embodiments by executing the computer program instructions stored in the memory 4312. In the present disclosure, the memory 4312 configured to store corresponding computer program instructions and / or data can mean that the memory 4312 is configured to store all corresponding computer program instructions and / or data for execution by the processor core 4311; or can mean that the memory 4312 is configured to store part of corresponding computer program instructions and / or data, which includes computer program instructions and / or data currently required for execution by the processor core 4311, and the memory 4312 can store different parts of computer program instructions and / or data for execution by the processor core 4311 multiple times to implement the above-mentioned operations in the above-mentioned method embodiments. The interface circuit 4314 is configured as a communication interface to communicate with other components, such as transmitting signals with the radio frequency processing system 420, communicating with other subsystems and related components of the processor system 430 through a bus, such as transmitting data control signals with the application processor 432, and transmitting data or computer program instructions with the memory 436 or the memory 460. Optionally, in order to reduce the load of the processor core, a baseband signal processing circuit 4313 can be further provided to implement at least part of the processing work of the baseband signal, including one or more of demodulation, modulation, encoding or decoding of the signal.

[0178] In one example, the communication apparatus provided in the present application can be the terminal 400, the communication module including the processor system 430 and the radio frequency system 420, the processor system 430, or the baseband processor 431.

[0179] The processor, processor system, application processor, baseband processor, processor circuit, or processor core can be collectively referred to as a processor, which can include one or a combination of a central processing unit (CPU), a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0180] The above-mentioned memory can include one or more of the following storage media: random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), phase-change memory (PCM), resistive RAM (ReRAM), magneto resistive RAM (MRAM), ferroelectric RAM (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable ROM (EPROM), hard disk, etc. In one example, the computer program instructions for implementing the above-mentioned embodiments can be stored on a non-volatile memory, such as at least part of the above-mentioned memory 460 (e.g., one or more of ROM, flash memory, EPROM, or hard disk). During terminal operation, the corresponding computer program instructions can be partially or entirely loaded onto a memory with faster transmission speed to the processor, such as at least part of the above-mentioned memory 436 and / or memory 4312 (e.g., one or more of RAM, SRAM, DRAM, PCM, RERAM, MRAM, FRAM, cache, or register), for execution by the processor to implement the steps in the above-mentioned method embodiments.

[0181] In one example, the radio frequency transceiver 422 and the radio frequency front end 421 can also be packaged in one chip. In one example, the radio frequency transceiver 422, the radio frequency front end 421, and the baseband processor 431 can also be packaged in one chip.

[0182] The terms "system" and "network" in the embodiments of the present application can be used interchangeably. "At least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the cases of A alone, A and B together, and B alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC, and "at least one of A, B, and C" can also be understood to include A, B, C, AB, AC, BC, or ABC. In addition, unless otherwise specified, the ordinal numbers "first", "second", etc. mentioned in the embodiments of the present application are used to distinguish a plurality of objects, and are not used to limit the order, time sequence, priority or importance of the plurality of objects.

[0183] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0184] The present application is described with reference to flowcharts and / or block diagrams according to the methods, devices (systems), and computer program products of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0185] These computer program instructions can also be stored in a computer-readable storage medium that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable storage medium produce a product including instruction means, which implements the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0186] These computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are performed on the computer or other programmable devices to generate computer-implemented processes, so that the instructions executed on the computer or other programmable devices provide steps for implementing the functions specified in one or more flows in the flowchart and / or one or more blocks in the block diagram.

[0187] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the scope of the present application. Thus, it is intended that the present application embrace all such modifications and changes and, accordingly, the application is not to be limited by the above-described one or more embodiments.

Claims

1. A communication method, characterized in that, The method includes: Obtain the first sequence; Based on the first sequence, first synchronization information and / or second synchronization information are detected, wherein the first synchronization information is different from the second synchronization information.

2. The method as described in claim 1, characterized in that, Both the first synchronization information and the second synchronization information are the identifier of the first cell.

3. The method as described in claim 2, characterized in that, Both the first synchronization information and the second synchronization information are carried by the primary synchronization signal. The first cell identifier and the physical layer cell identifier satisfy the following relationship: in, This is the physical layer cell identifier. The first synchronization information or the second synchronization information, where A is a positive integer. Other synchronization information used to determine the physical layer cell identifier.

4. The method according to any one of claims 1 to 3, characterized in that, The first synchronization information is carried in the first master synchronization signal, and the sequence of the first master synchronization signal is the first sequence; The second synchronization information is carried in the second main synchronization signal, and the sequence of the second main synchronization signal is the second sequence, which is obtained based on the first sequence.

5. The method as described in claim 4, characterized in that, The step of detecting the second synchronization information based on the first sequence includes: Generate the second sequence based on the first sequence; The second synchronization information is detected based on the second sequence.

6. The method as described in claim 4 or 5, characterized in that, The sequence formed by the real parts of each element in the second sequence is the reverse of the sequence formed by the real parts of each element in the first sequence, and the sequence formed by the imaginary parts of each element in the second sequence is the reverse of the sequence formed by the imaginary parts of each element in the first sequence.

7. The method according to any one of claims 1 to 3, characterized in that, The first synchronization information is carried in the first main synchronization signal, and the sequence of the first main synchronization signal is a third sequence, which is obtained based on the first sequence; The second synchronization information is carried in the second main synchronization signal, and the sequence of the second main synchronization signal is the second sequence, which is obtained based on the first sequence.

8. The method as described in claim 7, characterized in that, The step of detecting the first synchronization information and / or the second synchronization information according to the first sequence includes: The third sequence is generated based on the first sequence, and the first synchronization information is detected based on the third sequence; and / or, The second sequence is generated based on the first sequence, and the second synchronization information is detected based on the second sequence.

9. The method as described in claim 7 or 8, characterized in that, The sequence formed by the real parts of each element in the second sequence is the reverse of the sequence formed by the real parts of each element in the third sequence, and the sequence formed by the imaginary parts of each element in the second sequence is the reverse of the sequence formed by the imaginary parts of each element in the third sequence.

10. The method as described in claim 9, characterized in that, The second sequence is obtained by cyclically shifting the elements in the first sequence.

11. The method according to any one of claims 1 to 10, characterized in that, The first sequence is {A(0),A(1),…,A(N-1)}; Where A(n) = c(n) + jd(n); n∈{0,1,…,N-1}, N is a positive integer power of 2, and N is the length of the first sequence; c(n)=a n (2 n -1); d(n)=b n (2 n -1); a(n) and b(n) satisfy the following recurrence relation: a0(i) = δ(i); b0(i) = δ(i); a n (i)=a n-1 (i)+q·b n-1 (i-2 n-1 ); b n (i)=a n-1 (i)-q·b n-1 (i-2 n-1 ); Where i∈{0,1,…,N-1}; δ(i)=1 if and only if i=0; δ(i)=0 if and only if i≠0, q∈{-1,1}.

12. The method according to any one of claims 1 to 11, characterized in that, The length of the first sequence is 64, 128, or 256.

13. A communication method, characterized in that, The method includes: Based on the first sequence, a first master synchronization signal or a second master synchronization signal is generated. The first master synchronization signal carries first synchronization information, and the second master synchronization signal carries second synchronization information. The first synchronization information and the second synchronization information are different. Send the first master synchronization signal or the second master synchronization signal.

14. The method as described in claim 13, characterized in that, Both the first synchronization information and the second synchronization information are the identifier of the first cell.

15. The method as described in claim 14, characterized in that, The first cell identifier and the physical layer cell identifier satisfy the following relationship: in, This is the physical layer cell identifier. The first synchronization information or the second synchronization information, where A is a positive integer. Other synchronization information used to determine the physical layer cell identifier.

16. The method according to any one of claims 13 to 15, characterized in that, The sequence of the first master synchronization signal is the first sequence; The sequence of the second master synchronization signal is a second sequence, which is obtained based on the first sequence.

17. The method as described in claim 16, characterized in that, The step of generating the second master synchronization signal based on the first sequence includes: Generate the second sequence based on the first sequence; The second master synchronization signal is generated based on the second sequence.

18. The method as described in claim 16 or 17, characterized in that, The sequence formed by the real parts of each element in the second sequence is the reverse of the sequence formed by the real parts of each element in the first sequence, and the sequence formed by the imaginary parts of each element in the second sequence is the reverse of the sequence formed by the imaginary parts of each element in the first sequence.

19. The method according to any one of claims 13 to 15, characterized in that, The sequence of the first master synchronization signal is a third sequence, which is obtained based on the first sequence; The sequence of the second master synchronization signal is a second sequence, which is obtained based on the first sequence.

20. The method as described in claim 19, characterized in that, The step of generating a first master synchronization signal or a second master synchronization signal according to the first sequence includes: The third sequence is generated based on the first sequence, and the first master synchronization signal is generated based on the third sequence; or, The second sequence is generated based on the first sequence, and the second master synchronization signal is generated based on the second sequence.

21. The method as described in claim 19 or 20, characterized in that, The sequence formed by the real parts of each element in the second sequence is the reverse of the sequence formed by the real parts of each element in the third sequence, and the sequence formed by the imaginary parts of each element in the second sequence is the reverse of the sequence formed by the imaginary parts of each element in the third sequence.

22. The method as described in claim 21, characterized in that, The second sequence is obtained by cyclically shifting the elements in the first sequence.

23. The method according to any one of claims 13 to 22, characterized in that, The first sequence is {A(0),A(1),…,A(N-1)}; Where A(n) = c(n) + jd(n); n∈{0,1,…,N-1}, N is a positive integer power of 2, and N is the length of the first sequence; c(n)=a n (2 n -1); d(n)=b n (2 n -1); a(n) and b(n) satisfy the following recurrence relation: a0(i) = δ(i); b0(i) = δ(i); a n (i)=a n-1 (i)+q·b n-1 (i-2 n-1 ); b n (i)=a n-1 (i)-q·b n-1 (i-2 n-1 ); Where i∈{0,1,…,N-1}; δ(i)=1 if and only if i=0; δ(i)=0 if and only if i≠0, q∈{-1,1}.

24. The method according to any one of claims 13 to 23, characterized in that, The length of the first sequence is 64, 128, or 256.

25. A communication device, characterized in that, Includes modules for performing the method of any one of claims 1 to 12, or the method of any one of claims 13 to 24.

26. A communication device, characterized in that, It includes a processor and an interface circuit, the processor being configured to communicate with other devices via the interface circuit to implement the method of any one of claims 1 to 12, or to implement the method of any one of claims 13 to 24.

27. A computer program product, characterized in that, The computer program product includes instructions that, when executed, implement the method of any one of claims 1 to 12, or the method of any one of claims 13 to 24.

28. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed, implement the method of any one of claims 1 to 12, or the method of any one of claims 13 to 24.

29. A communication system, characterized in that, include: A terminal for performing the method according to any one of claims 1 to 12; An access network device for performing the method described in any one of claims 13 to 24.

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